From 60d9d871f5ddc182a6cfbad171f4f562f44cc9c4 Mon Sep 17 00:00:00 2001 From: IOsetting Date: Sat, 18 Feb 2023 22:10:50 +0800 Subject: [PATCH] feat: ll iwdg example --- Examples/LL/IWDG/Basic/main.c | 73 +++++++++++++++++++++++++ Examples/LL/IWDG/Basic/main.h | 28 ++++++++++ Examples/LL/IWDG/Basic/py32f0xx_it.c | 42 ++++++++++++++ Examples/LL/IWDG/Basic/py32f0xx_it.h | 18 ++++++ Examples/LL/PWR/PVD/main.c | 2 + Libraries/BSP_LL/Inc/py32f0xx_bsp_led.h | 2 +- 6 files changed, 164 insertions(+), 1 deletion(-) create mode 100644 Examples/LL/IWDG/Basic/main.c create mode 100644 Examples/LL/IWDG/Basic/main.h create mode 100644 Examples/LL/IWDG/Basic/py32f0xx_it.c create mode 100644 Examples/LL/IWDG/Basic/py32f0xx_it.h diff --git a/Examples/LL/IWDG/Basic/main.c b/Examples/LL/IWDG/Basic/main.c new file mode 100644 index 0000000..811bb8a --- /dev/null +++ b/Examples/LL/IWDG/Basic/main.c @@ -0,0 +1,73 @@ +/** + * Independent Watchdog Demo +*/ +#include "main.h" +#include "py32f0xx_bsp_clock.h" +#include "py32f0xx_bsp_printf.h" + +static void APP_GPIO_Config(void); +static void APP_IWDG_Config(void); + +int main(void) +{ + uint8_t delay = 0; + // Set HSI 24MHz as system clock source + BSP_RCC_HSI_24MConfig(); + // Initialize UART on PA2:TX PA3:RX + BSP_USART_Config(115200); + printf("PY32F0 IWDG Demo\r\nClock: %ld\r\n", SystemCoreClock); + // Set PB5 for LED output + APP_GPIO_Config(); + + APP_IWDG_Config(); + + while (1) + { + /* + * Watchdog will be triggered when delay exceeds 1 second + */ + printf("Delay %d ... ", 900 + delay); + LL_mDelay(900 + delay); + LL_GPIO_TogglePin(GPIOB, LL_GPIO_PIN_5); + printf("reload counter\r\n"); + LL_IWDG_ReloadCounter(IWDG); + delay += 10; + } +} + +static void APP_GPIO_Config(void) +{ + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); + LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_5, LL_GPIO_MODE_OUTPUT); +} + +static void APP_IWDG_Config(void) +{ + // Enable LSI + LL_RCC_LSI_Enable(); + while (LL_RCC_LSI_IsReady() == 0U) {;} + // Enable IWDG + LL_IWDG_Enable(IWDG); + + LL_IWDG_EnableWriteAccess(IWDG); + // Set waiting period to around 1 ms + LL_IWDG_SetPrescaler(IWDG, LL_IWDG_PRESCALER_32); + // Set counter to 1000 -> around 1 seconds + LL_IWDG_SetReloadCounter(IWDG, 1000); + // Wait IWDG ready + while (LL_IWDG_IsReady(IWDG) == 0U); + // Reset counter + LL_IWDG_ReloadCounter(IWDG); +} + +void APP_ErrorHandler(void) +{ + while (1); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(uint8_t *file, uint32_t line) +{ + while (1); +} +#endif /* USE_FULL_ASSERT */ diff --git a/Examples/LL/IWDG/Basic/main.h b/Examples/LL/IWDG/Basic/main.h new file mode 100644 index 0000000..7ba0b4d --- /dev/null +++ b/Examples/LL/IWDG/Basic/main.h @@ -0,0 +1,28 @@ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "py32f0xx_ll_rtc.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_cortex.h" +#include "py32f0xx_ll_dma.h" +#include "py32f0xx_ll_exti.h" +#include "py32f0xx_ll_gpio.h" +#include "py32f0xx_ll_lptim.h" +#include "py32f0xx_ll_iwdg.h" +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_system.h" +#include "py32f0xx_ll_tim.h" +#include "py32f0xx_ll_utils.h" + + +void APP_ErrorHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Examples/LL/IWDG/Basic/py32f0xx_it.c b/Examples/LL/IWDG/Basic/py32f0xx_it.c new file mode 100644 index 0000000..458707c --- /dev/null +++ b/Examples/LL/IWDG/Basic/py32f0xx_it.c @@ -0,0 +1,42 @@ +#include "main.h" +#include "py32f0xx_it.h" + +extern void APP_TransferCompleteCallback(void); + +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ +} diff --git a/Examples/LL/IWDG/Basic/py32f0xx_it.h b/Examples/LL/IWDG/Basic/py32f0xx_it.h new file mode 100644 index 0000000..f1403ae --- /dev/null +++ b/Examples/LL/IWDG/Basic/py32f0xx_it.h @@ -0,0 +1,18 @@ +#ifndef __PY32F0XX_IT_H +#define __PY32F0XX_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_IT_H */ diff --git a/Examples/LL/PWR/PVD/main.c b/Examples/LL/PWR/PVD/main.c index dff92b7..a3283c7 100644 --- a/Examples/LL/PWR/PVD/main.c +++ b/Examples/LL/PWR/PVD/main.c @@ -1,5 +1,7 @@ /** * Power Voltage Detector(PVD) Demo + * + * - when input(PB7) voltage lower than 1.2V, PB5 output high */ #include "main.h" #include "py32f0xx_bsp_clock.h" diff --git a/Libraries/BSP_LL/Inc/py32f0xx_bsp_led.h b/Libraries/BSP_LL/Inc/py32f0xx_bsp_led.h index c22f7c1..4b18f75 100644 --- a/Libraries/BSP_LL/Inc/py32f0xx_bsp_led.h +++ b/Libraries/BSP_LL/Inc/py32f0xx_bsp_led.h @@ -42,7 +42,7 @@ typedef enum #define LED3_GPIO_CLK_DISABLE() LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOB) #define LEDx_GPIO_CLK_ENABLE(__INDEX__) do {LED3_GPIO_CLK_ENABLE(); } while(0U) -#define LEDx_GPIO_CLK_DISABLE(__INDEX__) LED3_GPIO_CLK_DISABLE()) +#define LEDx_GPIO_CLK_DISABLE(__INDEX__) LED3_GPIO_CLK_DISABLE() void BSP_LED_Init(Led_TypeDef Led);