diff --git a/Examples/LL/TIM/TIM1_DMA/main.c b/Examples/LL/TIM/TIM1_DMA/main.c new file mode 100644 index 0000000..a09d253 --- /dev/null +++ b/Examples/LL/TIM/TIM1_DMA/main.c @@ -0,0 +1,109 @@ +/*** + * Demo: TIM1 DMA + * + */ +#include "main.h" +#include "py32f0xx_bsp_printf.h" + +uint32_t TIM1ReloadCounter[9] = {900-1,800-1,700-1,600-1,500-1,400-1,300-1,200-1,100-1}; + + +static void APP_GPIOConfig(void); +static void APP_SystemClockConfig(void); +static void APP_TIM1Config(void); +static void APP_DMAConfig(void); + + +int main(void) +{ + APP_SystemClockConfig(); + APP_GPIOConfig(); + BSP_USART_Config(115200); + printf("TIM1 DMA Demo\r\nClock: %ld\r\n", SystemCoreClock); + + APP_TIM1Config(); + APP_DMAConfig(); + while (1); +} + +static void APP_TIM1Config(void) +{ + LL_TIM_InitTypeDef TIM1CountInit = {0}; + + LL_APB1_GRP2_EnableClock(RCC_APBENR2_TIM1EN); + + TIM1CountInit.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM1CountInit.CounterMode = LL_TIM_COUNTERMODE_UP; + /* Start with 1 second interval (at 8MHz) */ + TIM1CountInit.Prescaler = 8000-1; + TIM1CountInit.Autoreload = 1000-1; + TIM1CountInit.RepetitionCounter = 0; + LL_TIM_Init(TIM1,&TIM1CountInit); + + LL_TIM_EnableIT_UPDATE(TIM1); + LL_TIM_EnableDMAReq_UPDATE(TIM1); + LL_TIM_EnableCounter(TIM1); + + NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn,0); +} + +static void APP_DMAConfig(void) +{ + LL_DMA_InitTypeDef DMA_TIM1Reload ={0}; + + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1); + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG); + + DMA_TIM1Reload.PeriphOrM2MSrcAddress = (uint32_t)&(TIM1->ARR); + DMA_TIM1Reload.MemoryOrM2MDstAddress = (uint32_t)TIM1ReloadCounter; + DMA_TIM1Reload.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH; + DMA_TIM1Reload.Mode = LL_DMA_MODE_NORMAL; + DMA_TIM1Reload.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_TIM1Reload.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; + DMA_TIM1Reload.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD; + DMA_TIM1Reload.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD; + DMA_TIM1Reload.NbData = 9; + DMA_TIM1Reload.Priority = LL_DMA_PRIORITY_MEDIUM; + LL_DMA_Init(DMA1,LL_DMA_CHANNEL_1,&DMA_TIM1Reload); + + /* Remap TIM1 update to DMA channel 1 */ + LL_SYSCFG_SetDMARemap_CH1(LL_SYSCFG_DMA_MAP_TIM1_UP); + + LL_DMA_EnableIT_TC(DMA1,LL_DMA_CHANNEL_1); + LL_DMA_EnableChannel(DMA1,LL_DMA_CHANNEL_1); + + NVIC_EnableIRQ(DMA1_Channel1_IRQn); + NVIC_SetPriority(DMA1_Channel1_IRQn,0); +} + +static void APP_SystemClockConfig(void) +{ + LL_RCC_HSI_Enable(); + while(LL_RCC_HSI_IsReady() != 1); + + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSISYS); + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS); + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + + LL_Init1msTick(8000000); + LL_SetSystemCoreClock(8000000); +} + +static void APP_GPIOConfig(void) +{ + /* Set PB5 as GPIO output */ + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); + LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_5, LL_GPIO_MODE_OUTPUT); +} + +void APP_TIM1UpdateCallback(void) +{ + LL_GPIO_TogglePin(GPIOB, LL_GPIO_PIN_5); +} + +void APP_ErrorHandler(void) +{ + while (1); +} diff --git a/Examples/LL/TIM/TIM1_DMA/main.h b/Examples/LL/TIM/TIM1_DMA/main.h new file mode 100644 index 0000000..b23b6b5 --- /dev/null +++ b/Examples/LL/TIM/TIM1_DMA/main.h @@ -0,0 +1,28 @@ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "py32f0xx_ll_adc.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_cortex.h" +#include "py32f0xx_ll_dma.h" +#include "py32f0xx_ll_exti.h" +#include "py32f0xx_ll_gpio.h" +#include "py32f0xx_ll_pwr.h" +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_system.h" +#include "py32f0xx_ll_tim.h" +#include "py32f0xx_ll_utils.h" + + +void APP_ErrorHandler(void); +void APP_TIM1UpdateCallback(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Examples/LL/TIM/TIM1_DMA/py32f0xx_it.c b/Examples/LL/TIM/TIM1_DMA/py32f0xx_it.c new file mode 100644 index 0000000..e9f081d --- /dev/null +++ b/Examples/LL/TIM/TIM1_DMA/py32f0xx_it.c @@ -0,0 +1,59 @@ +#include "main.h" +#include "py32f0xx_it.h" + +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ +} + +void TIM1_BRK_UP_TRG_COM_IRQHandler(void) +{ + if (LL_TIM_IsActiveFlag_UPDATE(TIM1) && LL_TIM_IsEnabledIT_UPDATE(TIM1)) + { + LL_TIM_ClearFlag_UPDATE(TIM1); + APP_TIM1UpdateCallback(); + } +} + +void DMA1_Channel1_IRQHandler(void) +{ + if (LL_DMA_IsActiveFlag_TC1(DMA1) == 1) + { + LL_DMA_ClearFlag_TC1(DMA1); + /* Turn off DMA after transfer complete */ + LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1); + } +} \ No newline at end of file diff --git a/Examples/LL/TIM/TIM1_DMA/py32f0xx_it.h b/Examples/LL/TIM/TIM1_DMA/py32f0xx_it.h new file mode 100644 index 0000000..55ad33e --- /dev/null +++ b/Examples/LL/TIM/TIM1_DMA/py32f0xx_it.h @@ -0,0 +1,21 @@ +#ifndef __PY32F0XX_IT_H +#define __PY32F0XX_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void TIM1_BRK_UP_TRG_COM_IRQHandler(void); +void DMA1_Channel1_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_IT_H */ diff --git a/Examples/LL/TIM/TIM1_TimeBase/main.c b/Examples/LL/TIM/TIM1_TimeBase/main.c new file mode 100644 index 0000000..1385e4f --- /dev/null +++ b/Examples/LL/TIM/TIM1_TimeBase/main.c @@ -0,0 +1,72 @@ +/*** + * Demo: TIM1 Update Interrupt + */ +#include "main.h" +#include "py32f0xx_bsp_printf.h" + + +static void APP_GPIOConfig(void); +static void APP_SystemClockConfig(void); +static void APP_TIM1Config(void); + +int main(void) +{ + APP_SystemClockConfig(); + APP_GPIOConfig(); + BSP_USART_Config(115200); + printf("TIM1 Interrupt Demo\r\nClock: %ld\r\n", SystemCoreClock); + + APP_TIM1Config(); + while (1); +} + +static void APP_TIM1Config(void) +{ + LL_TIM_InitTypeDef TIM1CountInit = {0}; + + LL_APB1_GRP2_EnableClock(RCC_APBENR2_TIM1EN); + + TIM1CountInit.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM1CountInit.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM1CountInit.Prescaler = 8000-1; + TIM1CountInit.Autoreload = 1000-1; + TIM1CountInit.RepetitionCounter = 0; + LL_TIM_Init(TIM1,&TIM1CountInit); + + LL_TIM_EnableIT_UPDATE(TIM1); + LL_TIM_EnableCounter(TIM1); + + NVIC_EnableIRQ(TIM1_BRK_UP_TRG_COM_IRQn); + NVIC_SetPriority(TIM1_BRK_UP_TRG_COM_IRQn,0); +} + +static void APP_SystemClockConfig(void) +{ + LL_RCC_HSI_Enable(); + while(LL_RCC_HSI_IsReady() != 1); + + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSISYS); + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS); + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + + LL_Init1msTick(8000000); + LL_SetSystemCoreClock(8000000); +} + +static void APP_GPIOConfig(void) +{ + /* Set PB5 as GPIO output */ + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); + LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_5, LL_GPIO_MODE_OUTPUT); +} + +void APP_TIM1UpdateCallback(void) +{ + LL_GPIO_TogglePin(GPIOB, LL_GPIO_PIN_5); +} + +void APP_ErrorHandler(void) +{ + while (1); +} diff --git a/Examples/LL/TIM/TIM1_TimeBase/main.h b/Examples/LL/TIM/TIM1_TimeBase/main.h new file mode 100644 index 0000000..b23b6b5 --- /dev/null +++ b/Examples/LL/TIM/TIM1_TimeBase/main.h @@ -0,0 +1,28 @@ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "py32f0xx_ll_adc.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_cortex.h" +#include "py32f0xx_ll_dma.h" +#include "py32f0xx_ll_exti.h" +#include "py32f0xx_ll_gpio.h" +#include "py32f0xx_ll_pwr.h" +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_system.h" +#include "py32f0xx_ll_tim.h" +#include "py32f0xx_ll_utils.h" + + +void APP_ErrorHandler(void); +void APP_TIM1UpdateCallback(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Examples/LL/TIM/TIM1_TimeBase/py32f0xx_it.c b/Examples/LL/TIM/TIM1_TimeBase/py32f0xx_it.c new file mode 100644 index 0000000..c459e64 --- /dev/null +++ b/Examples/LL/TIM/TIM1_TimeBase/py32f0xx_it.c @@ -0,0 +1,47 @@ +#include "main.h" +#include "py32f0xx_it.h" + +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ +} + +void TIM1_BRK_UP_TRG_COM_IRQHandler(void) +{ + if(LL_TIM_IsActiveFlag_UPDATE(TIM1) && LL_TIM_IsEnabledIT_UPDATE(TIM1)) + { + LL_TIM_ClearFlag_UPDATE(TIM1); + APP_TIM1UpdateCallback(); + } +} \ No newline at end of file diff --git a/Examples/LL/TIM/TIM1_TimeBase/py32f0xx_it.h b/Examples/LL/TIM/TIM1_TimeBase/py32f0xx_it.h new file mode 100644 index 0000000..15fdc6b --- /dev/null +++ b/Examples/LL/TIM/TIM1_TimeBase/py32f0xx_it.h @@ -0,0 +1,20 @@ +#ifndef __PY32F0XX_IT_H +#define __PY32F0XX_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void TIM1_BRK_UP_TRG_COM_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_IT_H */ diff --git a/Examples/LL/TIM/TIM_PWM/main.c b/Examples/LL/TIM/TIM_PWM/main.c new file mode 100644 index 0000000..ce03dad --- /dev/null +++ b/Examples/LL/TIM/TIM_PWM/main.c @@ -0,0 +1,97 @@ +/*** + * Demo: TIM1 PWM output + * + */ +#include "main.h" +#include "py32f0xx_bsp_printf.h" + +uint32_t TIM1ReloadCounter[9] = {900-1,800-1,700-1,600-1,500-1,400-1,300-1,200-1,100-1}; + + +static void APP_SystemClockConfig(void); +static void APP_TIM1Config(void); +static void APP_PWMChannelConfig(void); + + +int main(void) +{ + APP_SystemClockConfig(); + BSP_USART_Config(115200); + printf("TIM1 DMA Demo\r\nClock: %ld\r\n", SystemCoreClock); + + APP_TIM1Config(); + APP_PWMChannelConfig(); + while (1); +} + +static void APP_PWMChannelConfig(void) +{ + LL_GPIO_InitTypeDef TIM1CH1MapInit = {0}; + LL_TIM_OC_InitTypeDef TIM_OC_Initstruct = {0}; + + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA); + + /* PA8/PA9/PA10 -> TIM1_CH1N/TIM1_CH1/TIM1_CH2/TIM1_CH3 */ + TIM1CH1MapInit.Pin = LL_GPIO_PIN_8 | LL_GPIO_PIN_9 | LL_GPIO_PIN_10; + TIM1CH1MapInit.Mode = LL_GPIO_MODE_ALTERNATE; + TIM1CH1MapInit.Alternate = LL_GPIO_AF_2; + LL_GPIO_Init(GPIOA, &TIM1CH1MapInit); + + TIM_OC_Initstruct.OCMode = LL_TIM_OCMODE_PWM2; + TIM_OC_Initstruct.OCState = LL_TIM_OCSTATE_ENABLE; + TIM_OC_Initstruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_Initstruct.OCIdleState = LL_TIM_OCIDLESTATE_LOW; + + /* Set channel compare values */ + TIM_OC_Initstruct.CompareValue = 250; + LL_TIM_OC_Init(TIM1, LL_TIM_CHANNEL_CH1, &TIM_OC_Initstruct); + TIM_OC_Initstruct.CompareValue = 500; + LL_TIM_OC_Init(TIM1, LL_TIM_CHANNEL_CH2, &TIM_OC_Initstruct); + TIM_OC_Initstruct.CompareValue = 750; + LL_TIM_OC_Init(TIM1, LL_TIM_CHANNEL_CH3, &TIM_OC_Initstruct); +} + +static void APP_TIM1Config(void) +{ + LL_TIM_InitTypeDef TIM1CountInit = {0}; + + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM1); + + TIM1CountInit.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM1CountInit.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM1CountInit.Prescaler = 2400-1; + /* PWM period = 1000 */ + TIM1CountInit.Autoreload = 1000-1; + TIM1CountInit.RepetitionCounter = 0; + LL_TIM_Init(TIM1,&TIM1CountInit); + + LL_TIM_EnableAllOutputs(TIM1); + LL_TIM_EnableCounter(TIM1); +} + + +static void APP_SystemClockConfig(void) +{ + LL_RCC_HSI_Enable(); + LL_RCC_HSI_SetCalibFreq(LL_RCC_HSICALIBRATION_24MHz); + while (LL_RCC_HSI_IsReady() != 1); + + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSISYS); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS); + + LL_Init1msTick(24000000); + LL_SetSystemCoreClock(24000000); +} + +void APP_TIM1UpdateCallback(void) +{ + LL_GPIO_TogglePin(GPIOB, LL_GPIO_PIN_5); +} + +void APP_ErrorHandler(void) +{ + while (1); +} diff --git a/Examples/LL/TIM/TIM_PWM/main.h b/Examples/LL/TIM/TIM_PWM/main.h new file mode 100644 index 0000000..4d57498 --- /dev/null +++ b/Examples/LL/TIM/TIM_PWM/main.h @@ -0,0 +1,25 @@ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "py32f0xx_ll_adc.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_cortex.h" +#include "py32f0xx_ll_dma.h" +#include "py32f0xx_ll_exti.h" +#include "py32f0xx_ll_gpio.h" +#include "py32f0xx_ll_pwr.h" +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_system.h" +#include "py32f0xx_ll_tim.h" +#include "py32f0xx_ll_utils.h" + + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Examples/LL/TIM/TIM_PWM/py32f0xx_it.c b/Examples/LL/TIM/TIM_PWM/py32f0xx_it.c new file mode 100644 index 0000000..3a10d14 --- /dev/null +++ b/Examples/LL/TIM/TIM_PWM/py32f0xx_it.c @@ -0,0 +1,40 @@ +#include "main.h" +#include "py32f0xx_it.h" + +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ +} diff --git a/Examples/LL/TIM/TIM_PWM/py32f0xx_it.h b/Examples/LL/TIM/TIM_PWM/py32f0xx_it.h new file mode 100644 index 0000000..f1403ae --- /dev/null +++ b/Examples/LL/TIM/TIM_PWM/py32f0xx_it.h @@ -0,0 +1,18 @@ +#ifndef __PY32F0XX_IT_H +#define __PY32F0XX_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_IT_H */