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refactor: update bsp for compatible with f002a

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This commit is contained in:
IOsetting 2023-03-12 13:32:13 +08:00
parent e4ace192b2
commit 7b640ce615
4 changed files with 57 additions and 61 deletions
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32
Examples/LL/GPIO/LED_Toggle/main.c
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@ -20,30 +20,27 @@
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "main.h"
#include "py32f0xx_bsp_led.h"
#include "py32f0xx_bsp_printf.h"
/* Private define ------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private user code ---------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
static void APP_SystemClockConfig(void);
static void APP_GpioConfig(void);
static void APP_GPIOConfig(void);
int main(void)
{
APP_SystemClockConfig();
APP_GPIOConfig();
APP_GpioConfig();
BSP_USART_Config(115200);
printf("PY32F0xx GPIO Example\r\nClock: %ld\r\n", SystemCoreClock);
while (1)
{
LL_GPIO_TogglePin(GPIOA, LL_GPIO_PIN_0);
printf("echo\r\n");
LL_mDelay(500);
LL_GPIO_TogglePin(GPIOB,LL_GPIO_PIN_5);
}
}
@ -61,15 +58,12 @@ static void APP_SystemClockConfig(void)
LL_SetSystemCoreClock(8000000);
}
/**
* @brief 配置GPIO
* @param 无
* @retval 无
*/
static void APP_GpioConfig(void)
static void APP_GPIOConfig(void)
{
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_5, LL_GPIO_MODE_OUTPUT);
// PA0
LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_0, LL_GPIO_MODE_OUTPUT);
}
void APP_ErrorHandler(void)
@ -83,5 +77,3 @@ void assert_failed(uint8_t *file, uint32_t line)
while (1);
}
#endif /* USE_FULL_ASSERT */
/************************ (C) COPYRIGHT Puya *****END OF FILE******************/

7
Libraries/BSP_LL/Inc/py32f0xx_bsp_clock.h
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@ -24,12 +24,15 @@ extern "C" {
#include "py32f0xx_ll_gpio.h"
#include "py32f0xx_ll_usart.h"
void BSP_RCC_HSI_PLL48MConfig(void);
void BSP_RCC_HSI_24MConfig(void);
void BSP_RCC_HSI_8MConfig(void);
void BSP_RCC_HSE_PLLConfig(void);
void BSP_RCC_HSE_Config(void);
#if defined(RCC_PLL_SUPPORT)
void BSP_RCC_HSI_PLL48MConfig(void);
void BSP_RCC_HSE_PLLConfig(void);
#endif
#ifdef __cplusplus
}
#endif

14
Libraries/BSP_LL/Inc/py32f0xx_bsp_printf.h
View File

@ -28,11 +28,9 @@ extern "C" {
#include "py32f0xx_ll_usart.h"
//debug printf redirect config
#define DEBUG_USART USART2
#define DEBUG_USART_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2)
#define DEBUG_USART USART1
#define DEBUG_USART_CLK_ENABLE() LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_USART1)
#define __GPIOA_CLK_ENABLE() do { \
__IO uint32_t tmpreg = 0x00U; \
@ -45,15 +43,15 @@ extern "C" {
#define DEBUG_USART_RX_GPIO_PORT GPIOA
#define DEBUG_USART_RX_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA)
#define DEBUG_USART_RX_PIN LL_GPIO_PIN_3
#define DEBUG_USART_RX_AF LL_GPIO_AF_4
#define DEBUG_USART_RX_AF LL_GPIO_AF_1
#define DEBUG_USART_TX_GPIO_PORT GPIOA
#define DEBUG_USART_TX_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA)
#define DEBUG_USART_TX_PIN LL_GPIO_PIN_2
#define DEBUG_USART_TX_AF LL_GPIO_AF_4
#define DEBUG_USART_TX_AF LL_GPIO_AF_1
#define DEBUG_USART_IRQHandler USART2_IRQHandler
#define DEBUG_USART_IRQ USART2_IRQn
#define DEBUG_USART_IRQHandler USART1_IRQHandler
#define DEBUG_USART_IRQ USART1_IRQn
/************************************************************/

65
Libraries/BSP_LL/Src/py32f0xx_bsp_clock.c
View File

@ -1,21 +1,5 @@
#include "py32f0xx_bsp_clock.h"
void BSP_RCC_HSI_PLL48MConfig(void)
{
LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct;
LL_RCC_HSI_Enable();
/* Change this value to adjust clock frequency, larger is faster */
LL_RCC_HSI_SetCalibFreq(LL_RCC_HSICALIBRATION_24MHz);
while (LL_RCC_HSI_IsReady() != 1);
UTILS_ClkInitStruct.AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
UTILS_ClkInitStruct.APB1CLKDivider = LL_RCC_APB1_DIV_1;
LL_PLL_ConfigSystemClock_HSI(&UTILS_ClkInitStruct);
/* Re-init frequency of SysTick source, reload = freq/ticks = 48000000/1000 = 48000 */
LL_Init1msTick(48000000);
}
void BSP_RCC_HSI_24MConfig(void)
{
@ -52,21 +36,6 @@ void BSP_RCC_HSI_8MConfig(void)
LL_Init1msTick(8000000);
}
void BSP_RCC_HSE_PLLConfig(void)
{
LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct;
LL_RCC_HSE_Enable();
LL_RCC_HSE_SetFreqRegion(LL_RCC_HSE_16_32MHz);
while(LL_RCC_HSE_IsReady() != 1);
UTILS_ClkInitStruct.AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
UTILS_ClkInitStruct.APB1CLKDivider = LL_RCC_APB1_DIV_1;
LL_PLL_ConfigSystemClock_HSE(HSE_VALUE, LL_UTILS_HSEBYPASS_OFF, &UTILS_ClkInitStruct);
/* Re-init frequency of SysTick source */
LL_Init1msTick(HSE_VALUE * 2);
}
void BSP_RCC_HSE_Config(void)
{
LL_RCC_HSE_Enable();
@ -84,3 +53,37 @@ void BSP_RCC_HSE_Config(void)
/* Re-init frequency of SysTick source */
LL_Init1msTick(HSE_VALUE);
}
#if defined(RCC_PLL_SUPPORT)
void BSP_RCC_HSI_PLL48MConfig(void)
{
LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct;
LL_RCC_HSI_Enable();
/* Change this value to adjust clock frequency, larger is faster */
LL_RCC_HSI_SetCalibFreq(LL_RCC_HSICALIBRATION_24MHz);
while (LL_RCC_HSI_IsReady() != 1);
UTILS_ClkInitStruct.AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
UTILS_ClkInitStruct.APB1CLKDivider = LL_RCC_APB1_DIV_1;
LL_PLL_ConfigSystemClock_HSI(&UTILS_ClkInitStruct);
/* Re-init frequency of SysTick source, reload = freq/ticks = 48000000/1000 = 48000 */
LL_Init1msTick(48000000);
}
void BSP_RCC_HSE_PLLConfig(void)
{
LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct;
LL_RCC_HSE_Enable();
LL_RCC_HSE_SetFreqRegion(LL_RCC_HSE_16_32MHz);
while(LL_RCC_HSE_IsReady() != 1);
UTILS_ClkInitStruct.AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
UTILS_ClkInitStruct.APB1CLKDivider = LL_RCC_APB1_DIV_1;
LL_PLL_ConfigSystemClock_HSE(HSE_VALUE, LL_UTILS_HSEBYPASS_OFF, &UTILS_ClkInitStruct);
/* Re-init frequency of SysTick source */
LL_Init1msTick(HSE_VALUE * 2);
}
#endif