From 8813b261fae8b2a6d0e6de1276e3702bcad52973 Mon Sep 17 00:00:00 2001 From: IOsetting Date: Sun, 12 Mar 2023 13:54:01 +0800 Subject: [PATCH] refactor: update bsp for compatible with f002a --- Libraries/BSP/Inc/py32f0xx_bsp_clock.h | 6 ++- Libraries/BSP/Inc/py32f0xx_bsp_printf.h | 36 -------------- Libraries/BSP/Src/py32f0xx_bsp_clock.c | 66 +++++++++++++------------ 3 files changed, 39 insertions(+), 69 deletions(-) diff --git a/Libraries/BSP/Inc/py32f0xx_bsp_clock.h b/Libraries/BSP/Inc/py32f0xx_bsp_clock.h index bd01491..cf9276f 100644 --- a/Libraries/BSP/Inc/py32f0xx_bsp_clock.h +++ b/Libraries/BSP/Inc/py32f0xx_bsp_clock.h @@ -18,10 +18,12 @@ extern "C" { #include "py32f0xx_hal_rcc.h" HAL_StatusTypeDef BSP_HSI_24MHzClockConfig(void); -HAL_StatusTypeDef BSP_HSI_PLL_48MHzClockConfig(void); - HAL_StatusTypeDef BSP_HSE_ClockConfig(void); + +#if defined(RCC_PLL_SUPPORT) +HAL_StatusTypeDef BSP_HSI_PLL_48MHzClockConfig(void); HAL_StatusTypeDef BSP_HSE_PLL_ClockConfig(void); +#endif #ifdef __cplusplus diff --git a/Libraries/BSP/Inc/py32f0xx_bsp_printf.h b/Libraries/BSP/Inc/py32f0xx_bsp_printf.h index 8e32499..3637806 100644 --- a/Libraries/BSP/Inc/py32f0xx_bsp_printf.h +++ b/Libraries/BSP/Inc/py32f0xx_bsp_printf.h @@ -24,40 +24,6 @@ extern "C" { //debug printf redirect config #define DEBUG_USART_BAUDRATE 115200 -#if (defined(PY32F003PRE)|| defined(PY32F030PRE) || defined(PY32F072PRE)) - -#define DEBUG_USART USART2 -#define DEBUG_USART_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->APBENR1, RCC_APBENR1_USART2EN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define __GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define DEBUG_USART_RX_GPIO_PORT GPIOA -#define DEBUG_USART_RX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define DEBUG_USART_RX_PIN GPIO_PIN_3 -#define DEBUG_USART_RX_AF GPIO_AF4_USART2 - -#define DEBUG_USART_TX_GPIO_PORT GPIOA -#define DEBUG_USART_TX_GPIO_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE() -#define DEBUG_USART_TX_PIN GPIO_PIN_2 -#define DEBUG_USART_TX_AF GPIO_AF4_USART2 - -#define DEBUG_USART_IRQHandler USART2_IRQHandler -#define DEBUG_USART_IRQ USART2_IRQn - -#else - #define DEBUG_USART USART1 #define DEBUG_USART_CLK_ENABLE() do { \ __IO uint32_t tmpreg = 0x00U; \ @@ -88,8 +54,6 @@ extern "C" { #define DEBUG_USART_IRQHandler USART1_IRQHandler #define DEBUG_USART_IRQ USART1_IRQn -#endif - extern UART_HandleTypeDef DebugUartHandle; #endif diff --git a/Libraries/BSP/Src/py32f0xx_bsp_clock.c b/Libraries/BSP/Src/py32f0xx_bsp_clock.c index 9ee3fc2..ac22e09 100644 --- a/Libraries/BSP/Src/py32f0xx_bsp_clock.c +++ b/Libraries/BSP/Src/py32f0xx_bsp_clock.c @@ -11,8 +11,12 @@ HAL_StatusTypeDef BSP_HSI_24MHzClockConfig(void) RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV1; /* No division */ RCC_OscInitStruct.HSEState = RCC_HSE_OFF; /* OFF */ RCC_OscInitStruct.LSIState = RCC_LSI_OFF; /* OFF */ + #if defined(RCC_LSE_SUPPORT) RCC_OscInitStruct.LSEState = RCC_LSE_OFF; /* OFF */ + #endif + #if defined(RCC_PLL_SUPPORT) RCC_OscInitStruct.PLL.PLLState = RCC_PLL_OFF; /* OFF */ + #endif if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { @@ -32,7 +36,36 @@ HAL_StatusTypeDef BSP_HSI_24MHzClockConfig(void) return HAL_OK; } +HAL_StatusTypeDef BSP_HSE_ClockConfig(void) +{ + RCC_OscInitTypeDef RCC_OscInitStruct = {0}; + RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* Turn on HSE */ + RCC_OscInitStruct.HSEFreq = (RCC_ECSCR_HSE_FREQ_0 | RCC_ECSCR_HSE_FREQ_1); /* HSE frequency range */ + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) + { + return HAL_ERROR; + } + + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1; + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; /* SYSCLK source */ + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; + /* + * Re-initialize RCC clock + * -- clock <= 24MHz: FLASH_LATENCY_0 + * -- clock > 24MHz: FLASH_LATENCY_1 + */ + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) + { + return HAL_ERROR; + } + return HAL_OK; +} + +#if defined(RCC_PLL_SUPPORT) HAL_StatusTypeDef BSP_HSI_PLL_48MHzClockConfig(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -65,36 +98,6 @@ HAL_StatusTypeDef BSP_HSI_PLL_48MHzClockConfig(void) return HAL_OK; } - -HAL_StatusTypeDef BSP_HSE_ClockConfig(void) -{ - RCC_OscInitTypeDef RCC_OscInitStruct = {0}; - RCC_ClkInitTypeDef RCC_ClkInitStruct = {0}; - - RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; - RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* Turn on HSE */ - RCC_OscInitStruct.HSEFreq = RCC_HSE_16_32MHz; /* HSE frequency range */ - if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) - { - return HAL_ERROR; - } - - RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_PCLK1; - RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_HSE; /* SYSCLK source */ - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - /* - * Re-initialize RCC clock - * -- clock <= 24MHz: FLASH_LATENCY_0 - * -- clock > 24MHz: FLASH_LATENCY_1 - */ - if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0) != HAL_OK) - { - return HAL_ERROR; - } - return HAL_OK; -} - HAL_StatusTypeDef BSP_HSE_PLL_ClockConfig(void) { RCC_OscInitTypeDef RCC_OscInitStruct = {0}; @@ -120,4 +123,5 @@ HAL_StatusTypeDef BSP_HSE_PLL_ClockConfig(void) return HAL_ERROR; } return HAL_OK; -} \ No newline at end of file +} +#endif