From a640594c648a3c240b64092c14bdcdb7b697cdab Mon Sep 17 00:00:00 2001 From: IOsetting Date: Mon, 23 Jan 2023 18:12:42 +0800 Subject: [PATCH] feat: ll tim1 pwm complementary, dma burst example --- Examples/LL/TIM/TIM1_DMA_Burst/main.c | 123 ++++++++++++++++++ Examples/LL/TIM/TIM1_DMA_Burst/main.h | 27 ++++ Examples/LL/TIM/TIM1_DMA_Burst/py32f0xx_it.c | 47 +++++++ Examples/LL/TIM/TIM1_DMA_Burst/py32f0xx_it.h | 20 +++ Examples/LL/TIM/{TIM_PWM => TIM1_PWM}/main.c | 0 Examples/LL/TIM/{TIM_PWM => TIM1_PWM}/main.h | 0 .../TIM/{TIM_PWM => TIM1_PWM}/py32f0xx_it.c | 0 .../TIM/{TIM_PWM => TIM1_PWM}/py32f0xx_it.h | 0 Examples/LL/TIM/TIM1_PWM_Complementary/main.c | 108 +++++++++++++++ Examples/LL/TIM/TIM1_PWM_Complementary/main.h | 27 ++++ .../TIM/TIM1_PWM_Complementary/py32f0xx_it.c | 40 ++++++ .../TIM/TIM1_PWM_Complementary/py32f0xx_it.h | 19 +++ 12 files changed, 411 insertions(+) create mode 100644 Examples/LL/TIM/TIM1_DMA_Burst/main.c create mode 100644 Examples/LL/TIM/TIM1_DMA_Burst/main.h create mode 100644 Examples/LL/TIM/TIM1_DMA_Burst/py32f0xx_it.c create mode 100644 Examples/LL/TIM/TIM1_DMA_Burst/py32f0xx_it.h rename Examples/LL/TIM/{TIM_PWM => TIM1_PWM}/main.c (100%) rename Examples/LL/TIM/{TIM_PWM => TIM1_PWM}/main.h (100%) rename Examples/LL/TIM/{TIM_PWM => TIM1_PWM}/py32f0xx_it.c (100%) rename Examples/LL/TIM/{TIM_PWM => TIM1_PWM}/py32f0xx_it.h (100%) create mode 100644 Examples/LL/TIM/TIM1_PWM_Complementary/main.c create mode 100644 Examples/LL/TIM/TIM1_PWM_Complementary/main.h create mode 100644 Examples/LL/TIM/TIM1_PWM_Complementary/py32f0xx_it.c create mode 100644 Examples/LL/TIM/TIM1_PWM_Complementary/py32f0xx_it.h diff --git a/Examples/LL/TIM/TIM1_DMA_Burst/main.c b/Examples/LL/TIM/TIM1_DMA_Burst/main.c new file mode 100644 index 0000000..43e801b --- /dev/null +++ b/Examples/LL/TIM/TIM1_DMA_Burst/main.c @@ -0,0 +1,123 @@ +/*** + * Demo: TIM1 DMA Burst + */ +#include "main.h" +#include "py32f0xx_bsp_printf.h" + +uint32_t TIM1DataBuff[] = {5,200,5,800,5,100,5,900,5,50,5,950}; + +static void APP_DMABurstConfig(void); +static void APP_PWMChannelConfig(void); +static void APP_SystemClockConfig(void); +static void APP_TIM1BaseConfig(void); + +int main(void) +{ + APP_SystemClockConfig(); + + BSP_USART_Config(115200); + printf("TIM1 DMA Burst Demo\r\nClock: %ld \r\n", SystemCoreClock); + + APP_TIM1BaseConfig(); + APP_PWMChannelConfig(); + APP_DMABurstConfig(); + + while (1); +} + +static void APP_PWMChannelConfig(void) +{ + LL_GPIO_InitTypeDef TIM1CH1MapInit = {0}; + LL_TIM_OC_InitTypeDef TIM_OC_Initstruct = {0}; + + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA); + + TIM1CH1MapInit.Pin = LL_GPIO_PIN_8; + TIM1CH1MapInit.Mode = LL_GPIO_MODE_ALTERNATE; + TIM1CH1MapInit.Alternate = LL_GPIO_AF_2; + LL_GPIO_Init(GPIOA, &TIM1CH1MapInit); + + TIM_OC_Initstruct.OCMode = LL_TIM_OCMODE_PWM1; + TIM_OC_Initstruct.OCState = LL_TIM_OCSTATE_ENABLE; + TIM_OC_Initstruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_Initstruct.OCIdleState = LL_TIM_OCIDLESTATE_LOW; + TIM_OC_Initstruct.CompareValue = 100; + LL_TIM_OC_Init(TIM1, LL_TIM_CHANNEL_CH1, &TIM_OC_Initstruct); +} + +static void APP_DMABurstConfig(void) +{ + LL_DMA_InitTypeDef DMA_TIM1DMABurst ={0}; + + LL_AHB1_GRP1_EnableClock(LL_AHB1_GRP1_PERIPH_DMA1); + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_SYSCFG); + + DMA_TIM1DMABurst.PeriphOrM2MSrcAddress = (uint32_t)&(TIM1->DMAR); + DMA_TIM1DMABurst.MemoryOrM2MDstAddress = (uint32_t)TIM1DataBuff; + DMA_TIM1DMABurst.Direction = LL_DMA_DIRECTION_MEMORY_TO_PERIPH; + DMA_TIM1DMABurst.Mode = LL_DMA_MODE_NORMAL; + DMA_TIM1DMABurst.PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_TIM1DMABurst.MemoryOrM2MDstIncMode = LL_DMA_MEMORY_INCREMENT; + DMA_TIM1DMABurst.PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_WORD; + DMA_TIM1DMABurst.MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_WORD; + DMA_TIM1DMABurst.Priority = LL_DMA_PRIORITY_MEDIUM; + DMA_TIM1DMABurst.NbData = 12; + LL_DMA_Init(DMA1, LL_DMA_CHANNEL_1, &DMA_TIM1DMABurst); + + LL_SYSCFG_SetDMARemap_CH1(LL_SYSCFG_DMA_MAP_TIM1_UP); + + LL_DMA_EnableIT_TC(DMA1, LL_DMA_CHANNEL_1); + LL_DMA_EnableChannel(DMA1, LL_DMA_CHANNEL_1); + + NVIC_EnableIRQ(DMA1_Channel1_IRQn); + NVIC_SetPriority(DMA1_Channel1_IRQn, 0); +} + +static void APP_TIM1BaseConfig(void) +{ + LL_TIM_InitTypeDef TIM1CountInit = {0}; + + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM1); + + TIM1CountInit.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM1CountInit.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM1CountInit.Prescaler = 4800 - 1; + TIM1CountInit.Autoreload = 1000 - 1; + TIM1CountInit.RepetitionCounter = 1; + LL_TIM_Init(TIM1, &TIM1CountInit); + + LL_TIM_EnableDMAReq_UPDATE(TIM1); + /* DMA burst mode, each time 2 registers starting from RCR */ + LL_TIM_ConfigDMABurst(TIM1, LL_TIM_DMABURST_BASEADDR_RCR, LL_TIM_DMABURST_LENGTH_2TRANSFERS); + LL_TIM_EnableAllOutputs(TIM1); + LL_TIM_EnableCounter(TIM1); +} + +static void APP_SystemClockConfig(void) +{ + LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct; + + LL_RCC_HSI_Enable(); + /* Change this value to adjust clock frequency, larger is faster */ + LL_RCC_HSI_SetCalibFreq(LL_RCC_HSICALIBRATION_24MHz + 15); + while (LL_RCC_HSI_IsReady() != 1); + + UTILS_ClkInitStruct.AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + UTILS_ClkInitStruct.APB1CLKDivider = LL_RCC_APB1_DIV_1; + LL_PLL_ConfigSystemClock_HSI(&UTILS_ClkInitStruct); + + /* Re-init frequency of SysTick source, reload = freq/ticks = 48000000/1000 = 48000 */ + LL_InitTick(48000000, 1000U); +} + +void APP_ErrorHandler(void) +{ + while (1); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(uint8_t *file, uint32_t line) +{ + while (1); +} +#endif /* USE_FULL_ASSERT */ diff --git a/Examples/LL/TIM/TIM1_DMA_Burst/main.h b/Examples/LL/TIM/TIM1_DMA_Burst/main.h new file mode 100644 index 0000000..fe3863f --- /dev/null +++ b/Examples/LL/TIM/TIM1_DMA_Burst/main.h @@ -0,0 +1,27 @@ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "py32f0xx_ll_adc.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_cortex.h" +#include "py32f0xx_ll_dma.h" +#include "py32f0xx_ll_exti.h" +#include "py32f0xx_ll_gpio.h" +#include "py32f0xx_ll_pwr.h" +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_system.h" +#include "py32f0xx_ll_tim.h" +#include "py32f0xx_ll_utils.h" + + +void APP_ErrorHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Examples/LL/TIM/TIM1_DMA_Burst/py32f0xx_it.c b/Examples/LL/TIM/TIM1_DMA_Burst/py32f0xx_it.c new file mode 100644 index 0000000..06a40fc --- /dev/null +++ b/Examples/LL/TIM/TIM1_DMA_Burst/py32f0xx_it.c @@ -0,0 +1,47 @@ +#include "main.h" +#include "py32f0xx_it.h" + +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + while (1); +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ +} + +void DMA1_Channel1_IRQHandler(void) +{ + if (LL_DMA_IsActiveFlag_TC1(DMA1) == 1) + { + LL_DMA_ClearFlag_TC1(DMA1); + LL_DMA_DisableChannel(DMA1, LL_DMA_CHANNEL_1); + } +} \ No newline at end of file diff --git a/Examples/LL/TIM/TIM1_DMA_Burst/py32f0xx_it.h b/Examples/LL/TIM/TIM1_DMA_Burst/py32f0xx_it.h new file mode 100644 index 0000000..430ad67 --- /dev/null +++ b/Examples/LL/TIM/TIM1_DMA_Burst/py32f0xx_it.h @@ -0,0 +1,20 @@ +#ifndef __PY32F0XX_IT_H +#define __PY32F0XX_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +void DMA1_Channel1_IRQHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_IT_H */ diff --git a/Examples/LL/TIM/TIM_PWM/main.c b/Examples/LL/TIM/TIM1_PWM/main.c similarity index 100% rename from Examples/LL/TIM/TIM_PWM/main.c rename to Examples/LL/TIM/TIM1_PWM/main.c diff --git a/Examples/LL/TIM/TIM_PWM/main.h b/Examples/LL/TIM/TIM1_PWM/main.h similarity index 100% rename from Examples/LL/TIM/TIM_PWM/main.h rename to Examples/LL/TIM/TIM1_PWM/main.h diff --git a/Examples/LL/TIM/TIM_PWM/py32f0xx_it.c b/Examples/LL/TIM/TIM1_PWM/py32f0xx_it.c similarity index 100% rename from Examples/LL/TIM/TIM_PWM/py32f0xx_it.c rename to Examples/LL/TIM/TIM1_PWM/py32f0xx_it.c diff --git a/Examples/LL/TIM/TIM_PWM/py32f0xx_it.h b/Examples/LL/TIM/TIM1_PWM/py32f0xx_it.h similarity index 100% rename from Examples/LL/TIM/TIM_PWM/py32f0xx_it.h rename to Examples/LL/TIM/TIM1_PWM/py32f0xx_it.h diff --git a/Examples/LL/TIM/TIM1_PWM_Complementary/main.c b/Examples/LL/TIM/TIM1_PWM_Complementary/main.c new file mode 100644 index 0000000..d7e29a9 --- /dev/null +++ b/Examples/LL/TIM/TIM1_PWM_Complementary/main.c @@ -0,0 +1,108 @@ +/*** + * Demo: TIM1 PWM Complementary + * + * CH1:PA8 -> CH1N:PA7 + * CH2:PA9 -> CH2N:PB0 + * CH3:PA10 -> CH3N:PB1 + */ +#include "main.h" +#include "py32f0xx_bsp_printf.h" + +static void APP_PWMChannelConfig(void); +static void APP_SystemClockConfig(void); +static void APP_TIM1BaseConfig(void); + +int main(void) +{ + APP_SystemClockConfig(); + + BSP_USART_Config(115200); + printf("TIM1 PWM Complementary Demo\r\nClock: %ld \r\n", SystemCoreClock); + + APP_TIM1BaseConfig(); + APP_PWMChannelConfig(); + + while (1); +} + +static void APP_PWMChannelConfig(void) +{ + LL_GPIO_InitTypeDef TIM1CH1MapInit= {0}; + LL_TIM_OC_InitTypeDef TIM_OC_Initstruct ={0}; + + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA|LL_IOP_GRP1_PERIPH_GPIOB); + + /* PA7/PA8/PA9/PA10 -> TIM1_CH1N/TIM1_CH1/TIM1_CH2/TIM1_CH3 */ + TIM1CH1MapInit.Pin = LL_GPIO_PIN_7|LL_GPIO_PIN_8|LL_GPIO_PIN_9|LL_GPIO_PIN_10; + TIM1CH1MapInit.Mode = LL_GPIO_MODE_ALTERNATE; + TIM1CH1MapInit.Alternate = LL_GPIO_AF_2; + LL_GPIO_Init(GPIOA, &TIM1CH1MapInit); + + /* PB0/PB1 -> TIM1_CH2N/TIM1_CH3N */ + TIM1CH1MapInit.Pin = LL_GPIO_PIN_0|LL_GPIO_PIN_1; + TIM1CH1MapInit.Mode = LL_GPIO_MODE_ALTERNATE; + TIM1CH1MapInit.Alternate = LL_GPIO_AF_2; + LL_GPIO_Init(GPIOB, &TIM1CH1MapInit); + + TIM_OC_Initstruct.OCMode = LL_TIM_OCMODE_PWM1; + TIM_OC_Initstruct.OCState = LL_TIM_OCSTATE_ENABLE; + TIM_OC_Initstruct.OCPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_Initstruct.OCIdleState = LL_TIM_OCIDLESTATE_LOW; + TIM_OC_Initstruct.OCNState = LL_TIM_OCSTATE_ENABLE; + TIM_OC_Initstruct.OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_Initstruct.OCNIdleState = LL_TIM_OCIDLESTATE_LOW; + + TIM_OC_Initstruct.CompareValue = 50; + LL_TIM_OC_Init(TIM1,LL_TIM_CHANNEL_CH1,&TIM_OC_Initstruct); + + TIM_OC_Initstruct.CompareValue = 500; + LL_TIM_OC_Init(TIM1,LL_TIM_CHANNEL_CH2,&TIM_OC_Initstruct); + + TIM_OC_Initstruct.CompareValue = 950; + LL_TIM_OC_Init(TIM1,LL_TIM_CHANNEL_CH3,&TIM_OC_Initstruct); +} + +static void APP_TIM1BaseConfig(void) +{ + LL_TIM_InitTypeDef TIM1CountInit = {0}; + + LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM1); + + TIM1CountInit.ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM1CountInit.CounterMode = LL_TIM_COUNTERMODE_UP; + TIM1CountInit.Prescaler = 2400-1; + TIM1CountInit.Autoreload = 1000-1; + TIM1CountInit.RepetitionCounter = 0; + LL_TIM_Init(TIM1,&TIM1CountInit); + LL_TIM_EnableAllOutputs(TIM1); + LL_TIM_EnableCounter(TIM1); +} + +static void APP_SystemClockConfig(void) +{ + LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct; + + LL_RCC_HSI_Enable(); + /* Change this value to adjust clock frequency, larger is faster */ + LL_RCC_HSI_SetCalibFreq(LL_RCC_HSICALIBRATION_24MHz + 15); + while (LL_RCC_HSI_IsReady() != 1); + + UTILS_ClkInitStruct.AHBCLKDivider = LL_RCC_SYSCLK_DIV_1; + UTILS_ClkInitStruct.APB1CLKDivider = LL_RCC_APB1_DIV_1; + LL_PLL_ConfigSystemClock_HSI(&UTILS_ClkInitStruct); + + /* Re-init frequency of SysTick source, reload = freq/ticks = 48000000/1000 = 48000 */ + LL_InitTick(48000000, 1000U); +} + +void APP_ErrorHandler(void) +{ + while (1); +} + +#ifdef USE_FULL_ASSERT +void assert_failed(uint8_t *file, uint32_t line) +{ + while (1); +} +#endif /* USE_FULL_ASSERT */ diff --git a/Examples/LL/TIM/TIM1_PWM_Complementary/main.h b/Examples/LL/TIM/TIM1_PWM_Complementary/main.h new file mode 100644 index 0000000..fe3863f --- /dev/null +++ b/Examples/LL/TIM/TIM1_PWM_Complementary/main.h @@ -0,0 +1,27 @@ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include "py32f0xx_ll_adc.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_cortex.h" +#include "py32f0xx_ll_dma.h" +#include "py32f0xx_ll_exti.h" +#include "py32f0xx_ll_gpio.h" +#include "py32f0xx_ll_pwr.h" +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_system.h" +#include "py32f0xx_ll_tim.h" +#include "py32f0xx_ll_utils.h" + + +void APP_ErrorHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ diff --git a/Examples/LL/TIM/TIM1_PWM_Complementary/py32f0xx_it.c b/Examples/LL/TIM/TIM1_PWM_Complementary/py32f0xx_it.c new file mode 100644 index 0000000..3a10d14 --- /dev/null +++ b/Examples/LL/TIM/TIM1_PWM_Complementary/py32f0xx_it.c @@ -0,0 +1,40 @@ +#include "main.h" +#include "py32f0xx_it.h" + +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ +} diff --git a/Examples/LL/TIM/TIM1_PWM_Complementary/py32f0xx_it.h b/Examples/LL/TIM/TIM1_PWM_Complementary/py32f0xx_it.h new file mode 100644 index 0000000..76b3dad --- /dev/null +++ b/Examples/LL/TIM/TIM1_PWM_Complementary/py32f0xx_it.h @@ -0,0 +1,19 @@ +#ifndef __PY32F0XX_IT_H +#define __PY32F0XX_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_IT_H */