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feat: startup files for 002 and 072
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Libraries/CMSIS/Device/PY32F0xx/Source/gcc/startup_py32f002.s
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221
Libraries/CMSIS/Device/PY32F0xx/Source/gcc/startup_py32f002.s
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/**
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******************************************************************************
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* @file startup_py32f002.s
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* @brief PY32F002 devices vector table for GCC toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually calls main()).
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* After Reset the Cortex-M0 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m0plus
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =_estack
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mov sp, r0 /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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ldr r0, =_sdata
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ldr r1, =_edata
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ldr r2, =_sidata
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movs r3, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r4, [r2, r3]
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str r4, [r0, r3]
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adds r3, r3, #4
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LoopCopyDataInit:
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adds r4, r0, r3
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cmp r4, r1
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bcc CopyDataInit
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/* Zero fill the bss segment. */
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ldr r2, =_sbss
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ldr r4, =_ebss
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movs r3, #0
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b LoopFillZerobss
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FillZerobss:
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZerobss:
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cmp r2, r4
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors. Remove this line if compile with `-nostartfiles` reports error */
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bl __libc_init_array
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/* Call the application's entry point.*/
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bl main
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LoopForever:
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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* unexpected interrupt. This simply enters an infinite loop, preserving
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* the system state for examination by a debugger.
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*
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* @param None
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* @retval : None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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*
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* The minimal vector table for a Cortex M0. Note that the proper constructs
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* must be placed on this to ensure that it ends up at physical address
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* 0x0000.0000.
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*
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******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler /* Reset Handler */
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.word NMI_Handler /* NMI Handler */
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.word HardFault_Handler /* Hard Fault Handler */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word SVC_Handler /* SVCall Handler */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word PendSV_Handler /* PendSV Handler */
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.word SysTick_Handler /* SysTick Handler */
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.word 0 /* 0Reserved */
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.word 0 /* 1Reserved */
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.word 0 /* 2Reserved */
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.word FLASH_IRQHandler /* 3FLASH */
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.word RCC_IRQHandler /* 4RCC */
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.word EXTI0_1_IRQHandler /* 5EXTI Line 0 and 1 */
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.word EXTI2_3_IRQHandler /* 6EXTI Line 2 and 3 */
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.word EXTI4_15_IRQHandler /* 7EXTI Line 4 to 15 */
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.word 0 /* 8Reserved */
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.word 0 /* 9Reserved */
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.word 0 /* 10Reserved */
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.word 0 /* 11Reserved */
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.word ADC_IRQHandler /* 12ADC */
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.word TIM1_BRK_UP_TRG_COM_IRQHandler /* 13TIM1 Break, Update, Trigger and Commutation */
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.word TIM1_CC_IRQHandler /* 14TIM1 Capture Compare */
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.word 0 /* 15Reserved */
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.word 0 /* 16Reserved */
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.word LPTIM1_IRQHandler /* 17LPTIM1 */
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.word 0 /* 18Reserved */
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.word 0 /* 19Reserved */
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.word 0 /* 20Reserved */
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.word TIM16_IRQHandler /* 21TIM16 */
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.word 0 /* 22Reserved */
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.word I2C1_IRQHandler /* 23I2C1 */
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.word 0 /* 24Reserved */
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.word SPI1_IRQHandler /* 25SPI1 */
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.word 0 /* 26Reserved */
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.word USART1_IRQHandler /* 27USART1 */
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.word 0 /* 28Reserved */
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.word 0 /* 29Reserved */
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.word 0 /* 30Reserved */
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.word 0 /* 31Reserved */
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/*******************************************************************************
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*
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* Provide weak aliases for each Exception handler to the Default_Handler.
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* As they are weak aliases, any function with the same name will override
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* this definition.
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*
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*******************************************************************************/
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.weak NMI_Handler
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.thumb_set NMI_Handler,Default_Handler
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.weak HardFault_Handler
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.thumb_set HardFault_Handler,Default_Handler
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.weak SVC_Handler
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.thumb_set SVC_Handler,Default_Handler
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.weak PendSV_Handler
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.thumb_set PendSV_Handler,Default_Handler
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.weak SysTick_Handler
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.thumb_set SysTick_Handler,Default_Handler
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.weak FLASH_IRQHandler
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.thumb_set FLASH_IRQHandler,Default_Handler
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.weak RCC_IRQHandler
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.thumb_set RCC_IRQHandler,Default_Handler
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.weak EXTI0_1_IRQHandler
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.thumb_set EXTI0_1_IRQHandler,Default_Handler
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.weak EXTI2_3_IRQHandler
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.thumb_set EXTI2_3_IRQHandler,Default_Handler
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.weak EXTI4_15_IRQHandler
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.thumb_set EXTI4_15_IRQHandler,Default_Handler
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.weak ADC_IRQHandler
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.thumb_set ADC_IRQHandler,Default_Handler
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.weak TIM1_BRK_UP_TRG_COM_IRQHandler
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.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
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.weak TIM1_CC_IRQHandler
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.thumb_set TIM1_CC_IRQHandler,Default_Handler
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.weak LPTIM1_IRQHandler
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.thumb_set LPTIM1_IRQHandler,Default_Handler
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.weak TIM16_IRQHandler
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.thumb_set TIM16_IRQHandler,Default_Handler
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.weak I2C1_IRQHandler
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.thumb_set I2C1_IRQHandler,Default_Handler
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.weak SPI1_IRQHandler
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.thumb_set SPI1_IRQHandler,Default_Handler
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.weak USART1_IRQHandler
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.thumb_set USART1_IRQHandler,Default_Handler
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@ -1,7 +1,7 @@
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/**
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/**
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******************************************************************************
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******************************************************************************
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* @file startup_py32f003x6.s
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* @file startup_py32f003.s
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* @brief PY32F003X6 devices vector table for GCC toolchain.
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* @brief PY32F003 devices vector table for GCC toolchain.
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* This module performs:
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* This module performs:
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* - Set the initial SP
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the initial PC == Reset_Handler,
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@ -1,7 +1,7 @@
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/**
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/**
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******************************************************************************
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******************************************************************************
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* @file startup_py32f030x6.s
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* @file startup_py32f030.s
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* @brief PY32F030X6 devices vector table for GCC toolchain.
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* @brief PY32F030 devices vector table for GCC toolchain.
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* This module performs:
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* This module performs:
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* - Set the initial SP
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the initial PC == Reset_Handler,
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272
Libraries/CMSIS/Device/PY32F0xx/Source/gcc/startup_py32f072.s
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272
Libraries/CMSIS/Device/PY32F0xx/Source/gcc/startup_py32f072.s
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/**
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******************************************************************************
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* @file startup_py32f072.s
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* @brief PY32F072 devices vector table for GCC toolchain.
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* This module performs:
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* - Set the initial SP
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* - Set the initial PC == Reset_Handler,
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* - Set the vector table entries with the exceptions ISR address
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* - Branches to main in the C library (which eventually calls main()).
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* After Reset the Cortex-M0 processor is in Thread mode,
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* priority is Privileged, and the Stack is set to Main.
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******************************************************************************
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*/
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.syntax unified
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.cpu cortex-m0plus
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.fpu softvfp
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.thumb
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.global g_pfnVectors
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.global Default_Handler
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/* start address for the initialization values of the .data section.
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defined in linker script */
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.word _sidata
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/* start address for the .data section. defined in linker script */
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.word _sdata
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/* end address for the .data section. defined in linker script */
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.word _edata
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/* start address for the .bss section. defined in linker script */
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.word _sbss
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/* end address for the .bss section. defined in linker script */
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.word _ebss
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.section .text.Reset_Handler
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.weak Reset_Handler
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.type Reset_Handler, %function
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Reset_Handler:
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ldr r0, =_estack
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mov sp, r0 /* set stack pointer */
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/* Copy the data segment initializers from flash to SRAM */
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ldr r0, =_sdata
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ldr r1, =_edata
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ldr r2, =_sidata
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movs r3, #0
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b LoopCopyDataInit
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CopyDataInit:
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ldr r4, [r2, r3]
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str r4, [r0, r3]
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adds r3, r3, #4
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LoopCopyDataInit:
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adds r4, r0, r3
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cmp r4, r1
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bcc CopyDataInit
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/* Zero fill the bss segment. */
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ldr r2, =_sbss
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ldr r4, =_ebss
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movs r3, #0
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b LoopFillZerobss
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FillZerobss:
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str r3, [r2]
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adds r2, r2, #4
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LoopFillZerobss:
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cmp r2, r4
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bcc FillZerobss
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/* Call the clock system intitialization function.*/
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bl SystemInit
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/* Call static constructors. Remove this line if compile with `-nostartfiles` reports error */
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bl __libc_init_array
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/* Call the application's entry point.*/
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bl main
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LoopForever:
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b LoopForever
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.size Reset_Handler, .-Reset_Handler
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/**
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* @brief This is the code that gets called when the processor receives an
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||||||
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* unexpected interrupt. This simply enters an infinite loop, preserving
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||||||
|
* the system state for examination by a debugger.
|
||||||
|
*
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* @param None
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|
* @retval : None
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*/
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.section .text.Default_Handler,"ax",%progbits
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Default_Handler:
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Infinite_Loop:
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b Infinite_Loop
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.size Default_Handler, .-Default_Handler
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/******************************************************************************
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||||||
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*
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|
* The minimal vector table for a Cortex M0. Note that the proper constructs
|
||||||
|
* must be placed on this to ensure that it ends up at physical address
|
||||||
|
* 0x0000.0000.
|
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|
*
|
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|
******************************************************************************/
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.section .isr_vector,"a",%progbits
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.type g_pfnVectors, %object
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.size g_pfnVectors, .-g_pfnVectors
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g_pfnVectors:
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.word _estack
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.word Reset_Handler /* Reset Handler */
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.word NMI_Handler /* NMI Handler */
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.word HardFault_Handler /* Hard Fault Handler */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word SVC_Handler /* SVCall Handler */
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.word 0 /* Reserved */
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.word 0 /* Reserved */
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.word PendSV_Handler /* PendSV Handler */
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.word SysTick_Handler /* SysTick Handler */
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.word WWDG_IRQHandler /* 0Window Watchdog */
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.word PVD_IRQHandler /* 1PVD through EXTI Line detect */
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.word RTC_IRQHandler /* 2RTC through EXTI Line */
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.word FLASH_IRQHandler /* 3FLASH */
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.word RCC_CTC_IRQHandler /* 4RCC, CTC */
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.word EXTI0_1_IRQHandler /* 5EXTI Line 0 and 1 */
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.word EXTI2_3_IRQHandler /* 6EXTI Line 2 and 3 */
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.word EXTI4_15_IRQHandler /* 7EXTI Line 4 to 15 */
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.word LCD_IRQHandler /* 8LCD */
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.word DMA1_Channel1_IRQHandler /* 9DMA1 Channel 1 */
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.word DMA1_Channel2_3_IRQHandler /* 10DMA1 Channel 2 and Channel 3 */
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.word 0 /* 11Reserved */
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.word ADC_COMP_IRQHandler /* 12ADC&COMP1 */
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.word TIM1_BRK_UP_TRG_COM_IRQHandler /* 13TIM1 Break, Update, Trigger and Commutation */
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.word TIM1_CC_IRQHandler /* 14TIM1 Capture Compare */
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.word TIM2_IRQHandler /* 15TIM2 */
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.word TIM3_IRQHandler /* 16TIM3 */
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||||||
|
.word TIM6_LPTIM1_DAC_IRQHandler /* 17TIM6, LPTIM1, DAC */
|
||||||
|
.word TIM7_IRQHandler /* 18TIM7 */
|
||||||
|
.word TIM14_IRQHandler /* 19TIM14 */
|
||||||
|
.word TIM15_IRQHandler /* 20TIM15 */
|
||||||
|
.word TIM16_IRQHandler /* 21TIM16 */
|
||||||
|
.word TIM17_IRQHandler /* 22TIM17 */
|
||||||
|
.word I2C1_IRQHandler /* 23I2C1 */
|
||||||
|
.word I2C2_IRQHandler /* 24I2C2 */
|
||||||
|
.word SPI1_IRQHandler /* 25SPI1 */
|
||||||
|
.word SPI2_IRQHandler /* 26SPI2 */
|
||||||
|
.word USART1_IRQHandler /* 27USART1 */
|
||||||
|
.word USART2_IRQHandler /* 28USART2 */
|
||||||
|
.word USART3_4_IRQHandler /* 29USART3, USART4 */
|
||||||
|
.word 0 /* 30Reserved */
|
||||||
|
.word USB_IRQHandler /* 31USB */
|
||||||
|
|
||||||
|
/*******************************************************************************
|
||||||
|
*
|
||||||
|
* Provide weak aliases for each Exception handler to the Default_Handler.
|
||||||
|
* As they are weak aliases, any function with the same name will override
|
||||||
|
* this definition.
|
||||||
|
*
|
||||||
|
*******************************************************************************/
|
||||||
|
|
||||||
|
.weak NMI_Handler
|
||||||
|
.thumb_set NMI_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak HardFault_Handler
|
||||||
|
.thumb_set HardFault_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SVC_Handler
|
||||||
|
.thumb_set SVC_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak PendSV_Handler
|
||||||
|
.thumb_set PendSV_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak SysTick_Handler
|
||||||
|
.thumb_set SysTick_Handler,Default_Handler
|
||||||
|
|
||||||
|
.weak WWDG_IRQHandler
|
||||||
|
.thumb_set WWDG_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak PVD_IRQHandler
|
||||||
|
.thumb_set PVD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RTC_IRQHandler
|
||||||
|
.thumb_set RTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak FLASH_IRQHandler
|
||||||
|
.thumb_set FLASH_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak RCC_CTC_IRQHandler
|
||||||
|
.thumb_set RCC_CTC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI0_1_IRQHandler
|
||||||
|
.thumb_set EXTI0_1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI2_3_IRQHandler
|
||||||
|
.thumb_set EXTI2_3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak EXTI4_15_IRQHandler
|
||||||
|
.thumb_set EXTI4_15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak LCD_IRQHandler
|
||||||
|
.thumb_set LCD_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel1_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak DMA1_Channel2_3_IRQHandler
|
||||||
|
.thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak ADC_COMP_IRQHandler
|
||||||
|
.thumb_set ADC_COMP_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_BRK_UP_TRG_COM_IRQHandler
|
||||||
|
.thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM1_CC_IRQHandler
|
||||||
|
.thumb_set TIM1_CC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM2_IRQHandler
|
||||||
|
.thumb_set TIM2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM3_IRQHandler
|
||||||
|
.thumb_set TIM3_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM6_LPTIM1_DAC_IRQHandler
|
||||||
|
.thumb_set TIM6_LPTIM1_DAC_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM7_IRQHandler
|
||||||
|
.thumb_set TIM7_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM14_IRQHandler
|
||||||
|
.thumb_set TIM14_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM15_IRQHandler
|
||||||
|
.thumb_set TIM15_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM16_IRQHandler
|
||||||
|
.thumb_set TIM16_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak TIM17_IRQHandler
|
||||||
|
.thumb_set TIM17_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C1_IRQHandler
|
||||||
|
.thumb_set I2C1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak I2C2_IRQHandler
|
||||||
|
.thumb_set I2C2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI1_IRQHandler
|
||||||
|
.thumb_set SPI1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak SPI2_IRQHandler
|
||||||
|
.thumb_set SPI2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART1_IRQHandler
|
||||||
|
.thumb_set USART1_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART2_IRQHandler
|
||||||
|
.thumb_set USART2_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USART3_4_IRQHandler
|
||||||
|
.thumb_set USART3_4_IRQHandler,Default_Handler
|
||||||
|
|
||||||
|
.weak USB_IRQHandler
|
||||||
|
.thumb_set USB_IRQHandler,Default_Handler
|
||||||
4
Makefile
4
Makefile
@ -24,7 +24,7 @@ ARM_TOOCHAIN ?= /opt/gcc-arm/arm-gnu-toolchain-12.2.rel1-x86_64-arm-none-eabi/bi
|
|||||||
|
|
||||||
# path to JLinkExe
|
# path to JLinkExe
|
||||||
JLINKEXE ?= /opt/SEGGER/JLink/JLinkExe
|
JLINKEXE ?= /opt/SEGGER/JLink/JLinkExe
|
||||||
# JLink device type, options: PY32F003X4, PY32F003X6, PY32F003X8, PY32F030X6, PY32F030X7, PY32F030X8
|
# JLink device type, options: PY32F003X4, PY32F003X6, PY32F003X8, PY32F030X4, PY32F030X6, PY32F030X7, PY32F030X8
|
||||||
JLINK_DEVICE ?= PY32F003X8
|
JLINK_DEVICE ?= PY32F003X8
|
||||||
# path to PyOCD,
|
# path to PyOCD,
|
||||||
PYOCD_EXE ?= pyocd
|
PYOCD_EXE ?= pyocd
|
||||||
@ -36,7 +36,7 @@ PYOCD_DEVICE ?= py32f003x8
|
|||||||
|
|
||||||
# Link descript file: py32f003x6.ld, py32f003x8.ld, py32f030x6.ld, py32f030x8.ld
|
# Link descript file: py32f003x6.ld, py32f003x8.ld, py32f030x6.ld, py32f030x8.ld
|
||||||
LDSCRIPT = Libraries/LDScripts/py32f003x8.ld
|
LDSCRIPT = Libraries/LDScripts/py32f003x8.ld
|
||||||
# Library build flags: PY32F030x3, PY32F030x4, PY32F030x6, PY32F030x7, PY32F030x8, PY32F003x4, PY32F003x6, PY32F003x8
|
# Library build flags: PY32F002x5, PY32F002Ax5, PY32F003x4, PY32F003x6, PY32F003x8, PY32F030x3, PY32F030x4, PY32F030x6, PY32F030x7, PY32F030x8, PY32F072xB
|
||||||
LIB_FLAGS = PY32F003x8
|
LIB_FLAGS = PY32F003x8
|
||||||
|
|
||||||
# C source folders
|
# C source folders
|
||||||
|
|||||||
Loading…
x
Reference in New Issue
Block a user