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feat: ll adc analog watchdog example
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IOsetting
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175
Examples/LL/ADC/ADC_SingleConversion_AnalogWatchdog/main.c
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175
Examples/LL/ADC/ADC_SingleConversion_AnalogWatchdog/main.c
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/***
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* Demo: Analog Watchdog
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*
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* - PA4 is set as ADC input pin
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* - Limit the input voltage to between [0v, 1.5v] when start
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* - Increase the input voltage
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* - The LED on PB5 will start blinking when the voltage exceeds around 1.66v
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*/
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#include "main.h"
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#include "py32f0xx_bsp_printf.h"
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#define ADC_CALIBRATION_TIMEOUT_MS ((uint32_t) 1)
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__IO uint8_t ubAnalogWatchdog1Status = 0;
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static void APP_AdcConfig(void);
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static void APP_AwdConfig(uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue);
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static void APP_AdcCalibrate(void);
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static void APP_GPIOConfig(void);
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static void APP_SystemClockConfig(void);
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static void APP_TimerInit(void);
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int main(void)
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{
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APP_SystemClockConfig();
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APP_GPIOConfig();
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BSP_USART_Config(115200);
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printf("ADC Watchdog Demo\r\nClock: %ld\r\n", SystemCoreClock);
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LL_ADC_Reset(ADC1);
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_ADC1);
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APP_AdcCalibrate();
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APP_AdcConfig();
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/* Set threshold range to [0V, 1.66V] */
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APP_AwdConfig(0x0FFF / 2, 0);
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LL_ADC_Enable(ADC1);
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/* Delay 1ms(>= 8 ADC Clock) to ensure ADC is stable */
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LL_mDelay(1);
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LL_ADC_REG_StartConversion(ADC1);
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APP_TimerInit();
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while (1)
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{
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if (ubAnalogWatchdog1Status == 1)
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{
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LL_GPIO_TogglePin(GPIOB, LL_GPIO_PIN_5);
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LL_mDelay(500);
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}
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}
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}
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static void APP_AdcCalibrate(void)
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{
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#if (USE_TIMEOUT == 1)
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uint32_t Timeout = 0;
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#endif
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if (LL_ADC_IsEnabled(ADC1) == 0)
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{
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LL_ADC_StartCalibration(ADC1);
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#if (USE_TIMEOUT == 1)
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Timeout = ADC_CALIBRATION_TIMEOUT_MS;
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#endif
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while (LL_ADC_IsCalibrationOnGoing(ADC1) != 0)
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{
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#if (USE_TIMEOUT == 1)
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/* 检测校准是否超时 */
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if (LL_SYSTICK_IsActiveCounterFlag())
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{
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if(Timeout-- == 0)
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{
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}
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}
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#endif
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}
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/* Delay 1ms(>= 4 ADC clocks) before re-enable ADC */
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LL_mDelay(1);
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}
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}
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static void APP_AdcConfig(void)
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{
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LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA);
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/* PA4 as ADC input */
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LL_GPIO_SetPinMode(GPIOA, LL_GPIO_PIN_4, LL_GPIO_MODE_ANALOG);
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/* Set ADC channel and clock source when ADEN=0, set other configurations when ADSTART=0 */
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LL_ADC_SetCommonPathInternalCh(__LL_ADC_COMMON_INSTANCE(ADC1), LL_ADC_PATH_INTERNAL_NONE);
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LL_ADC_SetClock(ADC1, LL_ADC_CLOCK_SYNC_PCLK_DIV2);
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LL_ADC_SetResolution(ADC1, LL_ADC_RESOLUTION_12B);
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LL_ADC_SetResolution(ADC1, LL_ADC_DATA_ALIGN_RIGHT);
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/* Low power mode off */
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LL_ADC_SetLowPowerMode(ADC1, LL_ADC_LP_MODE_NONE);
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LL_ADC_SetSamplingTimeCommonChannels(ADC1, LL_ADC_SAMPLINGTIME_41CYCLES_5);
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/* Set TIM1 as trigger source */
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LL_ADC_REG_SetTriggerSource(ADC1, LL_ADC_REG_TRIG_EXT_TIM1_TRGO);
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LL_ADC_REG_SetTriggerEdge(ADC1, LL_ADC_REG_TRIG_EXT_RISING);
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LL_ADC_REG_SetContinuousMode(ADC1, LL_ADC_REG_CONV_SINGLE);
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/* DMA off */
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LL_ADC_REG_SetDMATransfer(ADC1, LL_ADC_REG_DMA_TRANSFER_NONE);
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LL_ADC_REG_SetOverrun(ADC1, LL_ADC_REG_OVR_DATA_OVERWRITTEN);
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LL_ADC_REG_SetSequencerDiscont(ADC1, LL_ADC_REG_SEQ_DISCONT_DISABLE);
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LL_ADC_REG_SetSequencerChannels(ADC1, LL_ADC_CHANNEL_4);
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}
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static void APP_AwdConfig(uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue)
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{
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/* ADC watchdog on channel4, use LL_ADC_AWD_ALL_CHANNELS_REG to monitor all channels */
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LL_ADC_SetAnalogWDMonitChannels(ADC1, LL_ADC_AWD_CHANNEL_4_REG);
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/* Set threshold */
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LL_ADC_ConfigAnalogWDThresholds(ADC1, AWDThresholdHighValue, AWDThresholdLowValue);
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/*
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* Turn on/off AWD interrupt when ADC conversion is stopped.
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* Note: LL_ADC_EnableIT_AWD / LL_ADC_DisableIT_AWD doesn't work when conversion is ongoing
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*/
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LL_ADC_EnableIT_AWD(ADC1);
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NVIC_SetPriority(ADC_COMP_IRQn, 0);
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NVIC_EnableIRQ(ADC_COMP_IRQn);
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}
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void APP_AdcAnalogWatchdogCallback(void)
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{
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ubAnalogWatchdog1Status = 1;
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}
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static void APP_TimerInit(void)
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{
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM1);
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/* Set period to 48000000 for 48MHz clock */
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LL_TIM_SetPrescaler(TIM1,8000);
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LL_TIM_SetAutoReload(TIM1, 6000);
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LL_TIM_SetTriggerOutput(TIM1,LL_TIM_TRGO_UPDATE);
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LL_TIM_EnableCounter(TIM1);
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}
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static void APP_SystemClockConfig(void)
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{
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LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct;
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LL_RCC_HSI_Enable();
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/* Change this value to adjust clock frequency, larger is faster */
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LL_RCC_HSI_SetCalibFreq(LL_RCC_HSICALIBRATION_24MHz + 15);
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while(LL_RCC_HSI_IsReady() != 1);
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UTILS_ClkInitStruct.AHBCLKDivider = LL_RCC_SYSCLK_DIV_1;
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UTILS_ClkInitStruct.APB1CLKDivider = LL_RCC_APB1_DIV_1;
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LL_PLL_ConfigSystemClock_HSI(&UTILS_ClkInitStruct);
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/* Set PLL as clock source */
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LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL);
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while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL);
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/* Re-init frequency of SysTick source, reload = freq/ticks = 48000000/1000 = 48000 */
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LL_InitTick(48000000, 1000U);
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/* Update global SystemCoreClock(or through SystemCoreClockUpdate function) */
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LL_SetSystemCoreClock(48000000);
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}
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static void APP_GPIOConfig(void)
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{
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/* Set PB5 as GPIO output */
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LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB);
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LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_5, LL_GPIO_MODE_OUTPUT);
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}
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void APP_ErrorHandler(void)
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{
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while (1);
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}
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28
Examples/LL/ADC/ADC_SingleConversion_AnalogWatchdog/main.h
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28
Examples/LL/ADC/ADC_SingleConversion_AnalogWatchdog/main.h
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#ifndef __MAIN_H
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#define __MAIN_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "py32f0xx_ll_adc.h"
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#include "py32f0xx_ll_bus.h"
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#include "py32f0xx_ll_cortex.h"
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#include "py32f0xx_ll_dma.h"
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#include "py32f0xx_ll_exti.h"
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#include "py32f0xx_ll_gpio.h"
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#include "py32f0xx_ll_pwr.h"
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#include "py32f0xx_ll_rcc.h"
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#include "py32f0xx_ll_system.h"
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#include "py32f0xx_ll_tim.h"
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#include "py32f0xx_ll_utils.h"
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void APP_ErrorHandler(void);
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void APP_AdcAnalogWatchdogCallback(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __MAIN_H */
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@ -0,0 +1,49 @@
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#include "main.h"
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#include "py32f0xx_it.h"
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/**
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* @brief This function handles Non maskable interrupt.
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*/
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void NMI_Handler(void)
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{
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}
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/**
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* @brief This function handles Hard fault interrupt.
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*/
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void HardFault_Handler(void)
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{
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while (1)
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{
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}
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}
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/**
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* @brief This function handles System service call via SWI instruction.
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*/
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void SVC_Handler(void)
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{
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}
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/**
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* @brief This function handles Pendable request for system service.
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*/
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void PendSV_Handler(void)
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{
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}
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/**
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* @brief This function handles System tick timer.
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*/
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void SysTick_Handler(void)
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{
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}
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void ADC_COMP_IRQHandler(void)
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{
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if(LL_ADC_IsActiveFlag_AWD(ADC1) != 0)
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{
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LL_ADC_ClearFlag_AWD(ADC1);
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APP_AdcAnalogWatchdogCallback();
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}
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}
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@ -0,0 +1,20 @@
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#ifndef __PY32F0XX_IT_H
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#define __PY32F0XX_IT_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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void NMI_Handler(void);
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void HardFault_Handler(void);
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void SVC_Handler(void);
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void PendSV_Handler(void);
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void SysTick_Handler(void);
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void ADC_COMP_IRQHandler(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PY32F0XX_IT_H */
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@ -36,7 +36,7 @@ int main(void)
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APP_AdcCalibrate();
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APP_AdcConfig();
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LL_ADC_Enable(ADC1);
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/* Ensure ADC is stable, >= 8 ADC Clock */
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/* Delay 1ms(>= 8 ADC Clock) to ensure ADC is stable */
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LL_mDelay(1);
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LL_ADC_REG_StartConversion(ADC1);
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@ -109,7 +109,7 @@ static void APP_AdcCalibrate(void)
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#endif
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}
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/* Delay before re-enable ADC */
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/* Delay 1ms(>= 4 ADC clocks) before re-enable ADC */
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LL_mDelay(1);
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/* Apply saved settings */
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LL_ADC_REG_SetDMATransfer(ADC1, backup_setting_adc_dma_transfer);
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@ -119,7 +119,7 @@ static void APP_AdcCalibrate(void)
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static void APP_TimerInit(void)
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{
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LL_APB1_GRP2_EnableClock(LL_APB1_GRP2_PERIPH_TIM1);
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/* Set period to 48000000 */
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/* Set period to 48000000 for 48MHz clock */
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LL_TIM_SetPrescaler(TIM1, 6000);
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LL_TIM_SetAutoReload(TIM1, 8000);
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/* Triggered by update */
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@ -164,7 +164,7 @@ static void APP_SystemClockConfig(void)
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LL_UTILS_ClkInitTypeDef UTILS_ClkInitStruct;
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LL_RCC_HSI_Enable();
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/* Change this value to adjust frequency */
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/* Change this value to adjust clock frequency, larger is faster */
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LL_RCC_HSI_SetCalibFreq(LL_RCC_HSICALIBRATION_24MHz + 15);
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while(LL_RCC_HSI_IsReady() != 1);
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