From dafe61f45e176302ddd79c3dd14fd8545dce26dc Mon Sep 17 00:00:00 2001 From: IOsetting Date: Mon, 12 Dec 2022 23:07:35 +0800 Subject: [PATCH] feat: ll lib option --- Examples/Raw_LL/GPIO/LED_Toggle/main.c | 130 + Examples/Raw_LL/GPIO/LED_Toggle/main.h | 59 + Examples/Raw_LL/GPIO/LED_Toggle/py32_assert.h | 59 + Examples/Raw_LL/GPIO/LED_Toggle/py32f0xx_it.c | 84 + Examples/Raw_LL/GPIO/LED_Toggle/py32f0xx_it.h | 49 + .../Inc}/py32f003xx_ll_Start_Kit.h | 281 +- Libraries/BSP_LL/Inc/py32f0xx_bsp_printf.h | 69 + .../Src}/py32f003xx_ll_Start_Kit.c | 480 +- Libraries/BSP_LL/Src/py32f0xx_bsp_printf.c | 151 + .../Inc/py32f0xx_ll_adc.h | 6564 +++++++------- .../Inc/py32f0xx_ll_bus.h | 1192 +-- .../Inc/py32f0xx_ll_comp.h | 24 +- .../Inc/py32f0xx_ll_cortex.h | 620 +- .../Inc/py32f0xx_ll_crc.h | 408 +- .../Inc/py32f0xx_ll_dma.h | 2740 +++--- .../Inc/py32f0xx_ll_exti.h | 1772 ++-- .../Inc/py32f0xx_ll_gpio.h | 2216 ++--- .../Inc/py32f0xx_ll_i2c.h | 2812 +++--- .../Inc/py32f0xx_ll_iwdg.h | 626 +- .../Inc/py32f0xx_ll_led.h | 950 +- .../Inc/py32f0xx_ll_lptim.h | 24 +- .../Inc/py32f0xx_ll_pwr.h | 0 .../Inc/py32f0xx_ll_rcc.h | 3842 ++++---- .../Inc/py32f0xx_ll_rtc.h | 1320 +-- .../Inc/py32f0xx_ll_spi.h | 2350 ++--- .../Inc/py32f0xx_ll_system.h | 1936 ++--- .../Inc/py32f0xx_ll_tim.h | 7742 ++++++++--------- .../Inc/py32f0xx_ll_usart.h | 4142 ++++----- .../Inc/py32f0xx_ll_utils.h | 24 +- .../Inc/py32f0xx_ll_wwdg.h | 642 +- .../Src/py32f0xx_ll_adc.c | 1164 +-- .../Src/py32f0xx_ll_comp.c | 30 +- .../Src/py32f0xx_ll_crc.c | 222 +- .../Src/py32f0xx_ll_dma.c | 530 +- .../Src/py32f0xx_ll_exti.c | 476 +- .../Src/py32f0xx_ll_gpio.c | 522 +- .../Src/py32f0xx_ll_i2c.c | 388 +- .../Src/py32f0xx_ll_led.c | 316 +- .../Src/py32f0xx_ll_lptim.c | 30 +- .../Src/py32f0xx_ll_pwr.c | 30 +- .../Src/py32f0xx_ll_rcc.c | 1116 +-- .../Src/py32f0xx_ll_rtc.c | 1100 +-- .../Src/py32f0xx_ll_spi.c | 1024 +-- .../Src/py32f0xx_ll_tim.c | 2402 ++--- .../Src/py32f0xx_ll_usart.c | 776 +- .../Src/py32f0xx_ll_utils.c | 1012 +-- Makefile | 20 +- 47 files changed, 27483 insertions(+), 26983 deletions(-) create mode 100644 Examples/Raw_LL/GPIO/LED_Toggle/main.c create mode 100644 Examples/Raw_LL/GPIO/LED_Toggle/main.h create mode 100644 Examples/Raw_LL/GPIO/LED_Toggle/py32_assert.h create mode 100644 Examples/Raw_LL/GPIO/LED_Toggle/py32f0xx_it.c create mode 100644 Examples/Raw_LL/GPIO/LED_Toggle/py32f0xx_it.h rename Libraries/{BSP/PY32F003xx_LL_Start_Kit => BSP_LL/Inc}/py32f003xx_ll_Start_Kit.h (73%) create mode 100644 Libraries/BSP_LL/Inc/py32f0xx_bsp_printf.h rename Libraries/{BSP/PY32F003xx_LL_Start_Kit => BSP_LL/Src}/py32f003xx_ll_Start_Kit.c (71%) create mode 100644 Libraries/BSP_LL/Src/py32f0xx_bsp_printf.c rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_adc.h (98%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_bus.h (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_comp.h (99%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_cortex.h (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_crc.h (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_dma.h (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_exti.h (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_gpio.h (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_i2c.h (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_iwdg.h (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_led.h (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_lptim.h (99%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_pwr.h (100%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_rcc.h (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_rtc.h (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_spi.h (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_system.h (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_tim.h (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_usart.h (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_utils.h (99%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Inc/py32f0xx_ll_wwdg.h (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_adc.c (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_comp.c (99%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_crc.c (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_dma.c (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_exti.c (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_gpio.c (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_i2c.c (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_led.c (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_lptim.c (99%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_pwr.c (99%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_rcc.c (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_rtc.c (96%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_spi.c (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_tim.c (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_usart.c (97%) rename Libraries/{PY32F0xx_HAL_Driver => PY32F0xx_LL_Driver}/Src/py32f0xx_ll_utils.c (96%) diff --git a/Examples/Raw_LL/GPIO/LED_Toggle/main.c b/Examples/Raw_LL/GPIO/LED_Toggle/main.c new file mode 100644 index 0000000..7eea040 --- /dev/null +++ b/Examples/Raw_LL/GPIO/LED_Toggle/main.c @@ -0,0 +1,130 @@ +/** + ****************************************************************************** + * @file main.c + * @author MCU Application Team + * @brief Main program body + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "py32f003xx_ll_Start_Kit.h" + +/* Private define ------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private user code ---------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +static void APP_SystemClockConfig(void); +static void APP_GpioConfig(void); + +/** + * @brief 应用程序入口函数. + * @retval int + */ +int main(void) +{ + /* 配置系统时钟 */ + APP_SystemClockConfig(); + + /* 初始化GPIO */ + APP_GpioConfig(); + + while (1) + { + /* LED灯闪烁 */ + LL_mDelay(500); + LL_GPIO_TogglePin(GPIOB,LL_GPIO_PIN_5); + } +} + +/** + * @brief 系统时钟配置函数 + * @param 无 + * @retval 无 + */ +static void APP_SystemClockConfig(void) +{ + /* 使能HSI */ + LL_RCC_HSI_Enable(); + while(LL_RCC_HSI_IsReady() != 1) + { + } + + /* 设置 AHB 分频*/ + LL_RCC_SetAHBPrescaler(LL_RCC_SYSCLK_DIV_1); + + /* 配置HSISYS作为系统时钟源 */ + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_HSISYS); + while(LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS) + { + } + + /* 设置 APB1 分频*/ + LL_RCC_SetAPB1Prescaler(LL_RCC_APB1_DIV_1); + LL_Init1msTick(8000000); + + /* 更新系统时钟全局变量SystemCoreClock(也可以通过调用SystemCoreClockUpdate函数更新) */ + LL_SetSystemCoreClock(8000000); +} + +/** + * @brief 配置GPIO + * @param 无 + * @retval 无 + */ +static void APP_GpioConfig(void) +{ + /* 使能时钟 */ + LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB); + + /* 将PA5引脚配置为输出 */ + LL_GPIO_SetPinMode(GPIOB, LL_GPIO_PIN_5, LL_GPIO_MODE_OUTPUT); +} + +/** + * @brief 错误执行函数 + * @param 无 + * @retval 无 + */ +void APP_ErrorHandler(void) +{ + /* 无限循环 */ + while (1) + { + } +} + +#ifdef USE_FULL_ASSERT +/** + * @brief 输出产生断言错误的源文件名及行号 + * @param file：源文件名指针 + * @param line：发生断言错误的行号 + * @retval 无 + */ +void assert_failed(uint8_t *file, uint32_t line) +{ + /* 用户可以根据需要添加自己的打印信息, + 例如: printf("Wrong parameters value: file %s on line %d\r\n", file, line) */ + /* 无限循环 */ + while (1) + { + } +} +#endif /* USE_FULL_ASSERT */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE******************/ diff --git a/Examples/Raw_LL/GPIO/LED_Toggle/main.h b/Examples/Raw_LL/GPIO/LED_Toggle/main.h new file mode 100644 index 0000000..ac239bb --- /dev/null +++ b/Examples/Raw_LL/GPIO/LED_Toggle/main.h @@ -0,0 +1,59 @@ +/** + ****************************************************************************** + * @file main.h + * @author MCU Application Team + * @brief Header for main.c file. + * This file contains the common defines of the application. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __MAIN_H +#define __MAIN_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_system.h" +#include "py32f0xx_ll_exti.h" +#include "py32f0xx_ll_cortex.h" +#include "py32f0xx_ll_utils.h" +#include "py32f0xx_ll_pwr.h" +#include "py32f0xx_ll_dma.h" +#include "py32f0xx_ll_gpio.h" + +#if defined(USE_FULL_ASSERT) +#include "py32_assert.h" +#endif /* USE_FULL_ASSERT */ + +/* Private includes ----------------------------------------------------------*/ +/* Private defines -----------------------------------------------------------*/ +/* Exported variables prototypes ---------------------------------------------*/ +/* Exported functions prototypes ---------------------------------------------*/ +void APP_ErrorHandler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __MAIN_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE******************/ diff --git a/Examples/Raw_LL/GPIO/LED_Toggle/py32_assert.h b/Examples/Raw_LL/GPIO/LED_Toggle/py32_assert.h new file mode 100644 index 0000000..6b7dc2a --- /dev/null +++ b/Examples/Raw_LL/GPIO/LED_Toggle/py32_assert.h @@ -0,0 +1,59 @@ +/** + ****************************************************************************** + * @file py32_assert.h + * @brief PY32 assert file. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32_ASSERT_H +#define __PY32_ASSERT_H + +#ifdef __cplusplus + extern "C" { +#endif + +#ifdef USE_FULL_ASSERT +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Includes ------------------------------------------------------------------*/ +#include "stdint.h" + +/* Exported macro ------------------------------------------------------------*/ + +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0U : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32_ASSERT_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE******************/ diff --git a/Examples/Raw_LL/GPIO/LED_Toggle/py32f0xx_it.c b/Examples/Raw_LL/GPIO/LED_Toggle/py32f0xx_it.c new file mode 100644 index 0000000..2d2f6e3 --- /dev/null +++ b/Examples/Raw_LL/GPIO/LED_Toggle/py32f0xx_it.c @@ -0,0 +1,84 @@ +/** + ****************************************************************************** + * @file py32f0xx_it.c + * @author MCU Application Team + * @brief Interrupt Service Routines. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Includes ------------------------------------------------------------------*/ +#include "main.h" +#include "py32f0xx_it.h" + +/* Private includes ----------------------------------------------------------*/ +/* Private typedef -----------------------------------------------------------*/ +/* Private define ------------------------------------------------------------*/ +/* Private macro -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ +/* Private user code ---------------------------------------------------------*/ +/* External variables --------------------------------------------------------*/ + +/******************************************************************************/ +/* Cortex-M0+ Processor Interruption and Exception Handlers */ +/******************************************************************************/ +/** + * @brief This function handles Non maskable interrupt. + */ +void NMI_Handler(void) +{ +} + +/** + * @brief This function handles Hard fault interrupt. + */ +void HardFault_Handler(void) +{ + while (1) + { + } +} + +/** + * @brief This function handles System service call via SWI instruction. + */ +void SVC_Handler(void) +{ +} + +/** + * @brief This function handles Pendable request for system service. + */ +void PendSV_Handler(void) +{ +} + +/** + * @brief This function handles System tick timer. + */ +void SysTick_Handler(void) +{ +} + +/******************************************************************************/ +/* PY32F0xx Peripheral Interrupt Handlers */ +/* Add here the Interrupt Handlers for the used peripherals. */ +/* For the available peripheral interrupt handler names, */ +/* please refer to the startup file. */ +/******************************************************************************/ + +/************************ (C) COPYRIGHT Puya *****END OF FILE******************/ diff --git a/Examples/Raw_LL/GPIO/LED_Toggle/py32f0xx_it.h b/Examples/Raw_LL/GPIO/LED_Toggle/py32f0xx_it.h new file mode 100644 index 0000000..633fddb --- /dev/null +++ b/Examples/Raw_LL/GPIO/LED_Toggle/py32f0xx_it.h @@ -0,0 +1,49 @@ +/** + ****************************************************************************** + * @file py32f0xx_it.h + * @author MCU Application Team + * @brief This file contains the headers of the interrupt handlers. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32F0XX_IT_H +#define __PY32F0XX_IT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Private includes ----------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions prototypes ---------------------------------------------*/ +void NMI_Handler(void); +void HardFault_Handler(void); +void SVC_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_IT_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE******************/ diff --git a/Libraries/BSP/PY32F003xx_LL_Start_Kit/py32f003xx_ll_Start_Kit.h b/Libraries/BSP_LL/Inc/py32f003xx_ll_Start_Kit.h similarity index 73% rename from Libraries/BSP/PY32F003xx_LL_Start_Kit/py32f003xx_ll_Start_Kit.h rename to Libraries/BSP_LL/Inc/py32f003xx_ll_Start_Kit.h index 4dd8517..4ca1e08 100755 --- a/Libraries/BSP/PY32F003xx_LL_Start_Kit/py32f003xx_ll_Start_Kit.h +++ b/Libraries/BSP_LL/Inc/py32f003xx_ll_Start_Kit.h @@ -1,9 +1,9 @@ -/** - ****************************************************************************** - * @file py32f003xx_ll_Start_Kit.h - * @author MCU Application Team +/** + ****************************************************************************** + * @file py32f003xx_ll_Start_Kit.h + * @author MCU Application Team * @brief This file provides set of firmware functions to manage Leds, - * push-button available on Start Kit. + * push-button available on Start Kit. ****************************************************************************** * @attention * @@ -19,153 +19,126 @@ * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** - */ + */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef PY32F0XX_LL_START_KIT_H -#define PY32F0XX_LL_START_KIT_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include -#include "py32f0xx_ll_rcc.h" -#include "py32f0xx_ll_bus.h" -#include "py32f0xx_ll_system.h" -#include "py32f0xx_ll_exti.h" -#include "py32f0xx_ll_cortex.h" -#include "py32f0xx_ll_utils.h" -#include "py32f0xx_ll_pwr.h" -#include "py32f0xx_ll_dma.h" -#include "py32f0xx_ll_gpio.h" -#include "py32f0xx_ll_usart.h" - -/** @addtogroup BSP - * @{ - */ - -/** @defgroup py32f0xx_Start_Kit - * @brief This section contains the exported types, contants and functions - * required to use the Nucleo 32 board. - * @{ - */ - -/** @defgroup py32f0xx_Start_Kit_Exported_Types Exported Types - * @{ - */ -typedef enum -{ - LED3 = 0, - LED_GREEN = LED3 -} Led_TypeDef; - -typedef enum -{ - BUTTON_USER = 0, - /* Alias */ - BUTTON_KEY = BUTTON_USER -} Button_TypeDef; - -typedef enum -{ - BUTTON_MODE_GPIO = 0, - BUTTON_MODE_EXTI = 1 -} ButtonMode_TypeDef; - -#define LEDn 1 - -#define LED3_PIN LL_GPIO_PIN_5 -#define LED3_GPIO_PORT GPIOB -#define LED3_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB) -#define LED3_GPIO_CLK_DISABLE() LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOB) - -#define LEDx_GPIO_CLK_ENABLE(__INDEX__) do {LED3_GPIO_CLK_ENABLE(); } while(0U) -#define LEDx_GPIO_CLK_DISABLE(__INDEX__) LED3_GPIO_CLK_DISABLE()) - -#define BUTTONn 1 - -/** - * @brief User push-button - */ -#define USER_BUTTON_PIN LL_GPIO_PIN_12 -#define USER_BUTTON_GPIO_PORT GPIOA -#define USER_BUTTON_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA) -#define USER_BUTTON_GPIO_CLK_DISABLE() LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOA) -#define USER_BUTTON_EXTI_IRQn EXTI4_15_IRQn -#define USER_BUTTON_EXTI_LINE LL_EXTI_LINE_12 -#define USER_BUTTON_EXTI_LINE_ENABLE() LL_EXTI_EnableIT(USER_BUTTON_EXTI_LINE) -#define USER_BUTTON_EXTI_FALLING_TRIG_ENABLE() LL_EXTI_EnableFallingTrig(USER_BUTTON_EXTI_LINE) -#define USER_BUTTON_IRQHANDLER EXTI4_15_IRQHandler - -/* Aliases */ -#define KEY_BUTTON_PIN USER_BUTTON_PIN -#define KEY_BUTTON_GPIO_PORT USER_BUTTON_GPIO_PORT -#define KEY_BUTTON_GPIO_CLK_ENABLE() USER_BUTTON_GPIO_CLK_ENABLE() -#define KEY_BUTTON_GPIO_CLK_DISABLE() USER_BUTTON_GPIO_CLK_DISABLE() -#define KEY_BUTTON_EXTI_IRQn USER_BUTTON_EXTI_IRQn - -#define BUTTONx_GPIO_CLK_ENABLE(__INDEX__) do { if((__INDEX__) == 0) USER_BUTTON_GPIO_CLK_ENABLE();} while(0) -#define BUTTONx_GPIO_CLK_DISABLE(__INDEX__) (((__INDEX__) == 0) ? USER_BUTTON_GPIO_CLK_DISABLE() : 0) - - -//debug printf redirect config -#define DEBUG_USART_BAUDRATE 115200 - -#define DEBUG_USART USART2 -#define DEBUG_USART_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2) - -#define __GPIOA_CLK_ENABLE() do { \ - __IO uint32_t tmpreg = 0x00U; \ - SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ - /* Delay after an RCC peripheral clock enabling */ \ - tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ - UNUSED(tmpreg); \ - } while(0U) - -#define DEBUG_USART_RX_GPIO_PORT GPIOA -#define DEBUG_USART_RX_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA) -#define DEBUG_USART_RX_PIN LL_GPIO_PIN_3 -#define DEBUG_USART_RX_AF LL_GPIO_AF_4 - -#define DEBUG_USART_TX_GPIO_PORT GPIOA -#define DEBUG_USART_TX_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA) -#define DEBUG_USART_TX_PIN LL_GPIO_PIN_2 -#define DEBUG_USART_TX_AF LL_GPIO_AF_4 - -#define DEBUG_USART_IRQHandler USART2_IRQHandler -#define DEBUG_USART_IRQ USART2_IRQn -/************************************************************/ - -/** @defgroup Functions - * @{ - */ -uint32_t BSP_GetVersion(void); - -void BSP_LED_Init(Led_TypeDef Led); -void BSP_LED_DeInit(Led_TypeDef Led); -void BSP_LED_On(Led_TypeDef Led); -void BSP_LED_Off(Led_TypeDef Led); -void BSP_LED_Toggle(Led_TypeDef Led); - -void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode); -void BSP_PB_DeInit(Button_TypeDef Button); -uint32_t BSP_PB_GetState(Button_TypeDef Button); - -void BSP_USART_Config(void); -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* PY32F003XX_LL_START_KIT_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef PY32F0XX_LL_START_KIT_H +#define PY32F0XX_LL_START_KIT_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_system.h" +#include "py32f0xx_ll_exti.h" +#include "py32f0xx_ll_cortex.h" +#include "py32f0xx_ll_utils.h" +#include "py32f0xx_ll_pwr.h" +#include "py32f0xx_ll_dma.h" +#include "py32f0xx_ll_gpio.h" +#include "py32f0xx_ll_usart.h" + +/** @addtogroup BSP + * @{ + */ + +/** @defgroup py32f0xx_Start_Kit + * @brief This section contains the exported types, contants and functions + * required to use the Nucleo 32 board. + * @{ + */ + +/** @defgroup py32f0xx_Start_Kit_Exported_Types Exported Types + * @{ + */ +typedef enum +{ + LED3 = 0, + LED_GREEN = LED3 +} Led_TypeDef; + +typedef enum +{ + BUTTON_USER = 0, + /* Alias */ + BUTTON_KEY = BUTTON_USER +} Button_TypeDef; + +typedef enum +{ + BUTTON_MODE_GPIO = 0, + BUTTON_MODE_EXTI = 1 +} ButtonMode_TypeDef; + +#define LEDn 1 + +#define LED3_PIN LL_GPIO_PIN_5 +#define LED3_GPIO_PORT GPIOB +#define LED3_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOB) +#define LED3_GPIO_CLK_DISABLE() LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOB) + +#define LEDx_GPIO_CLK_ENABLE(__INDEX__) do {LED3_GPIO_CLK_ENABLE(); } while(0U) +#define LEDx_GPIO_CLK_DISABLE(__INDEX__) LED3_GPIO_CLK_DISABLE()) + +#define BUTTONn 1 + +/** + * @brief User push-button + */ +#define USER_BUTTON_PIN LL_GPIO_PIN_12 +#define USER_BUTTON_GPIO_PORT GPIOA +#define USER_BUTTON_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA) +#define USER_BUTTON_GPIO_CLK_DISABLE() LL_IOP_GRP1_DisableClock(LL_IOP_GRP1_PERIPH_GPIOA) +#define USER_BUTTON_EXTI_IRQn EXTI4_15_IRQn +#define USER_BUTTON_EXTI_LINE LL_EXTI_LINE_12 +#define USER_BUTTON_EXTI_LINE_ENABLE() LL_EXTI_EnableIT(USER_BUTTON_EXTI_LINE) +#define USER_BUTTON_EXTI_FALLING_TRIG_ENABLE() LL_EXTI_EnableFallingTrig(USER_BUTTON_EXTI_LINE) +#define USER_BUTTON_IRQHANDLER EXTI4_15_IRQHandler + +/* Aliases */ +#define KEY_BUTTON_PIN USER_BUTTON_PIN +#define KEY_BUTTON_GPIO_PORT USER_BUTTON_GPIO_PORT +#define KEY_BUTTON_GPIO_CLK_ENABLE() USER_BUTTON_GPIO_CLK_ENABLE() +#define KEY_BUTTON_GPIO_CLK_DISABLE() USER_BUTTON_GPIO_CLK_DISABLE() +#define KEY_BUTTON_EXTI_IRQn USER_BUTTON_EXTI_IRQn + +#define BUTTONx_GPIO_CLK_ENABLE(__INDEX__) do { if((__INDEX__) == 0) USER_BUTTON_GPIO_CLK_ENABLE();} while(0) +#define BUTTONx_GPIO_CLK_DISABLE(__INDEX__) (((__INDEX__) == 0) ? USER_BUTTON_GPIO_CLK_DISABLE() : 0) + + +/************************************************************/ + +/** @defgroup Functions + * @{ + */ +uint32_t BSP_GetVersion(void); + +void BSP_LED_Init(Led_TypeDef Led); +void BSP_LED_DeInit(Led_TypeDef Led); +void BSP_LED_On(Led_TypeDef Led); +void BSP_LED_Off(Led_TypeDef Led); +void BSP_LED_Toggle(Led_TypeDef Led); + +void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode); +void BSP_PB_DeInit(Button_TypeDef Button); +uint32_t BSP_PB_GetState(Button_TypeDef Button); + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PY32F003XX_LL_START_KIT_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/BSP_LL/Inc/py32f0xx_bsp_printf.h b/Libraries/BSP_LL/Inc/py32f0xx_bsp_printf.h new file mode 100644 index 0000000..1ef360e --- /dev/null +++ b/Libraries/BSP_LL/Inc/py32f0xx_bsp_printf.h @@ -0,0 +1,69 @@ +/** + ****************************************************************************** + * @file py32f0xx_bsp_printf.h + * @author MCU Application Team + * @brief + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef PY32F003_BSP_PRINTF_H +#define PY32F003_BSP_PRINTF_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_system.h" +#include "py32f0xx_ll_exti.h" +#include "py32f0xx_ll_cortex.h" +#include "py32f0xx_ll_utils.h" +#include "py32f0xx_ll_pwr.h" +#include "py32f0xx_ll_dma.h" +#include "py32f0xx_ll_gpio.h" +#include "py32f0xx_ll_usart.h" + + + + +//debug printf redirect config +#define DEBUG_USART_BAUDRATE 115200 + +#define DEBUG_USART USART2 +#define DEBUG_USART_CLK_ENABLE() LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_USART2) + +#define __GPIOA_CLK_ENABLE() do { \ + __IO uint32_t tmpreg = 0x00U; \ + SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ + /* Delay after an RCC peripheral clock enabling */ \ + tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOAEN);\ + UNUSED(tmpreg); \ + } while(0U) + +#define DEBUG_USART_RX_GPIO_PORT GPIOA +#define DEBUG_USART_RX_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA) +#define DEBUG_USART_RX_PIN LL_GPIO_PIN_3 +#define DEBUG_USART_RX_AF LL_GPIO_AF_4 + +#define DEBUG_USART_TX_GPIO_PORT GPIOA +#define DEBUG_USART_TX_GPIO_CLK_ENABLE() LL_IOP_GRP1_EnableClock(LL_IOP_GRP1_PERIPH_GPIOA) +#define DEBUG_USART_TX_PIN LL_GPIO_PIN_2 +#define DEBUG_USART_TX_AF LL_GPIO_AF_4 + +#define DEBUG_USART_IRQHandler USART2_IRQHandler +#define DEBUG_USART_IRQ USART2_IRQn + +/************************************************************/ + +void BSP_USART_Config(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* PY32F003_BSP_PRINTF_H */ diff --git a/Libraries/BSP/PY32F003xx_LL_Start_Kit/py32f003xx_ll_Start_Kit.c b/Libraries/BSP_LL/Src/py32f003xx_ll_Start_Kit.c similarity index 71% rename from Libraries/BSP/PY32F003xx_LL_Start_Kit/py32f003xx_ll_Start_Kit.c rename to Libraries/BSP_LL/Src/py32f003xx_ll_Start_Kit.c index f01540a..70463fb 100755 --- a/Libraries/BSP/PY32F003xx_LL_Start_Kit/py32f003xx_ll_Start_Kit.c +++ b/Libraries/BSP_LL/Src/py32f003xx_ll_Start_Kit.c @@ -1,9 +1,9 @@ -/** - ****************************************************************************** - * @file py32f003xx_ll_Start_Kit.c - * @author MCU Application Team - * @brief This file provides set of firmware functions to manage Leds, - * push-button available on Start Kit. +/** + ****************************************************************************** + * @file py32f003xx_ll_Start_Kit.c + * @author MCU Application Team + * @brief This file provides set of firmware functions to manage Leds, + * push-button available on Start Kit. ****************************************************************************** * @attention * @@ -20,279 +20,195 @@ * ****************************************************************************** */ - -/* Includes ------------------------------------------------------------------*/ -#include "py32f003xx_ll_Start_Kit.h" - -/** - * @brief PY32F003xx STK BSP Driver version number - */ -#define __PY32F003xx_STK_BSP_VERSION_MAIN (0x01U) /*!< [31:24] main version */ -#define __PY32F003xx_STK_BSP_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ -#define __PY32F003xx_STK_BSP_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ -#define __PY32F003xx_STK_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */ -#define __PY32F003xx_STK_BSP_VERSION ((__PY32F003xx_STK_BSP_VERSION_MAIN << 24) \ - |(__PY32F003xx_STK_BSP_VERSION_SUB1 << 16) \ - |(__PY32F003xx_STK_BSP_VERSION_SUB2 << 8 ) \ - |(__PY32F003xx_STK_BSP_VERSION_RC)) - -GPIO_TypeDef* LED_PORT[LEDn] = {LED3_GPIO_PORT}; -const uint16_t LED_PIN[LEDn] = {LED3_PIN}; - -GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {USER_BUTTON_GPIO_PORT }; -const uint16_t BUTTON_PIN[BUTTONn] = {USER_BUTTON_PIN }; -const uint8_t BUTTON_IRQn[BUTTONn] = {USER_BUTTON_EXTI_IRQn }; -const uint32_t BUTTON_EXTI_LINE[BUTTONn] = {USER_BUTTON_EXTI_LINE }; - -/** @addtogroup PY32F003xx_STK_Exported_Functions - * @{ - */ - -/** - * @brief This method returns the PY32F003 STK BSP Driver revision. - * @retval version : 0xXYZR (8bits for each decimal, R for RC) - */ -uint32_t BSP_GetVersion(void) -{ - return __PY32F003xx_STK_BSP_VERSION; -} - -/** @addtogroup LED_Functions - * @{ - */ - -/** - * @brief Configures LED GPIO. - * @param Led Specifies the Led to be configured. - * This parameter can be one of following parameters: - * @arg LED3 - * @retval None - */ -void BSP_LED_Init(Led_TypeDef Led) -{ - /* Enable the GPIO_LED Clock */ - LEDx_GPIO_CLK_ENABLE(Led); - - /* Configure the GPIO_LED pin */ - LL_GPIO_SetPinMode(LED_PORT[Led], LED_PIN[Led], LL_GPIO_MODE_OUTPUT); - /* LL_GPIO_SetPinOutputType(LED_PORT[Led], LED_PIN[Led], LL_GPIO_OUTPUT_PUSHPULL); */ - /* LL_GPIO_SetPinSpeed(LED_PORT[Led], LED_PIN[Led], LL_GPIO_SPEED_FREQ_LOW); */ - /* LL_GPIO_SetPinPull(LED_PORT[Led], LED_PIN[Led], LL_GPIO_PULL_NO); */ - - LL_GPIO_SetOutputPin(LED_PORT[Led], LED_PIN[Led]); -} - -/** - * @brief DeInitialize LED GPIO. - * @param Led Specifies the Led to be deconfigured. - * This parameter can be one of the following values: - * @arg LED3 - * @note BSP_LED_DeInit() does not disable the GPIO clock - * @retval None - */ -void BSP_LED_DeInit(Led_TypeDef Led) -{ - /* Turn off LED */ - LL_GPIO_ResetOutputPin(LED_PORT[Led], LED_PIN[Led]); - /* DeInit the GPIO_LED pin */ - LL_GPIO_SetPinMode(LED_PORT[Led], LED_PIN[Led], LL_GPIO_MODE_ANALOG); - /* LL_GPIO_SetPinOutputType(LED_PORT[Led], LED_PIN[Led], LL_GPIO_OUTPUT_PUSHPULL); */ - /* LL_GPIO_SetPinSpeed(LED_PORT[Led], LED_PIN[Led], LL_GPIO_SPEED_FREQ_LOW); */ - /* LL_GPIO_SetPinPull(LED_PORT[Led], LED_PIN[Led], LL_GPIO_PULL_NO); */ -} - -/** - * @brief Turns selected LED On. - * @param Led Specifies the Led to be set on. - * This parameter can be one of following parameters: - * @arg LED3 - * @retval None - */ -void BSP_LED_On(Led_TypeDef Led) -{ - LL_GPIO_ResetOutputPin(LED_PORT[Led], LED_PIN[Led]); -} - -/** - * @brief Turns selected LED Off. - * @param Led Specifies the Led to be set off. - * This parameter can be one of following parameters: - * @arg LED3 - * @retval None - */ -void BSP_LED_Off(Led_TypeDef Led) -{ - LL_GPIO_SetOutputPin(LED_PORT[Led], LED_PIN[Led]); -} - -/** - * @brief Toggles the selected LED. - * @param Led Specifies the Led to be toggled. - * This parameter can be one of following parameters: - * @arg LED3 - * @retval None - */ -void BSP_LED_Toggle(Led_TypeDef Led) -{ - LL_GPIO_TogglePin(LED_PORT[Led], LED_PIN[Led]); -} - -/** - * @brief Configures Button GPIO and EXTI Line. - * @param Button: Specifies the Button to be configured. - * This parameter should be: BUTTON_USER - * @param ButtonMode: Specifies Button mode. - * This parameter can be one of following parameters: - * @arg BUTTON_MODE_GPIO: Button will be used as simple IO - * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt - * generation capability - * @retval None - */ -void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode) -{ - /* Enable the BUTTON Clock */ - BUTTONx_GPIO_CLK_ENABLE(Button); - - /* Configure GPIO for BUTTON */ - LL_GPIO_SetPinMode(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_MODE_INPUT); - LL_GPIO_SetPinPull(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_PULL_NO); - /* LL_GPIO_SetPinSpeed(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_SPEED_FREQ_HIGH); */ - - if(ButtonMode == BUTTON_MODE_EXTI) - { - /* Configure Button pin as input with External interrupt */ - LL_EXTI_EnableIT(BUTTON_EXTI_LINE[Button]); - LL_EXTI_EnableFallingTrig(BUTTON_EXTI_LINE[Button]); - - /* Enable and set Button EXTI Interrupt to the lowest priority */ - NVIC_SetPriority((IRQn_Type)(BUTTON_IRQn[Button]), 0x0F); - NVIC_EnableIRQ((IRQn_Type)(BUTTON_IRQn[Button])); - } -} - -/** - * @brief Push Button DeInit. - * @param Button: Button to be configured - * This parameter should be: BUTTON_USER - * @note PB DeInit does not disable the GPIO clock - * @retval None - */ -void BSP_PB_DeInit(Button_TypeDef Button) -{ - NVIC_DisableIRQ((IRQn_Type)(BUTTON_IRQn[Button])); - LL_GPIO_SetPinMode(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_MODE_ANALOG); - /* LL_GPIO_SetPinSpeed(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_SPEED_FREQ_LOW); */ - /* LL_GPIO_SetPinPull(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_PULL_NO); */ - /* LL_GPIO_SetAFPin_8_15(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_AF_0); */ -} - -/** - * @brief Returns the selected Button state. - * @param Button: Specifies the Button to be checked. - * This parameter should be: BUTTON_USER - * @retval Button state. - */ -uint32_t BSP_PB_GetState(Button_TypeDef Button) -{ - return LL_GPIO_IsInputPinSet(BUTTON_PORT[Button], BUTTON_PIN[Button]); -} - -/** - * @brief DEBUG_USART GPIO Config,Mode Config,115200 8-N-1 - * @param None - * @retval None - */ -void BSP_USART_Config(void) -{ - DEBUG_USART_CLK_ENABLE(); - - /* USART Init */ - LL_USART_SetBaudRate(DEBUG_USART, SystemCoreClock, LL_USART_OVERSAMPLING_16, DEBUG_USART_BAUDRATE); - LL_USART_SetDataWidth(DEBUG_USART, LL_USART_DATAWIDTH_8B); - LL_USART_SetStopBitsLength(DEBUG_USART, LL_USART_STOPBITS_1); - LL_USART_SetParity(DEBUG_USART, LL_USART_PARITY_NONE); - LL_USART_SetHWFlowCtrl(DEBUG_USART, LL_USART_HWCONTROL_NONE); - LL_USART_SetTransferDirection(DEBUG_USART, LL_USART_DIRECTION_TX_RX); - LL_USART_Enable(DEBUG_USART); - LL_USART_ClearFlag_TC(DEBUG_USART); - - /**USART GPIO Configuration - PA2 ------> USART1_TX - PA3 ------> USART1_RX - */ - DEBUG_USART_RX_GPIO_CLK_ENABLE(); - DEBUG_USART_TX_GPIO_CLK_ENABLE(); - - LL_GPIO_SetPinMode(DEBUG_USART_TX_GPIO_PORT, DEBUG_USART_TX_PIN, LL_GPIO_MODE_ALTERNATE); - LL_GPIO_SetPinSpeed(DEBUG_USART_TX_GPIO_PORT, DEBUG_USART_TX_PIN, LL_GPIO_SPEED_FREQ_VERY_HIGH); - LL_GPIO_SetPinPull(DEBUG_USART_TX_GPIO_PORT, DEBUG_USART_TX_PIN, LL_GPIO_PULL_UP); - LL_GPIO_SetAFPin_0_7(DEBUG_USART_TX_GPIO_PORT, DEBUG_USART_TX_PIN, DEBUG_USART_TX_AF); - - LL_GPIO_SetPinMode(DEBUG_USART_RX_GPIO_PORT, DEBUG_USART_RX_PIN, LL_GPIO_MODE_ALTERNATE); - LL_GPIO_SetPinSpeed(DEBUG_USART_RX_GPIO_PORT, DEBUG_USART_RX_PIN, LL_GPIO_SPEED_FREQ_VERY_HIGH); - LL_GPIO_SetPinPull(DEBUG_USART_RX_GPIO_PORT, DEBUG_USART_RX_PIN, LL_GPIO_PULL_UP); - LL_GPIO_SetAFPin_0_7(DEBUG_USART_RX_GPIO_PORT, DEBUG_USART_RX_PIN, DEBUG_USART_RX_AF); -} - -#if (defined (__CC_ARM)) || (defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)) -/** - * @brief writes a character to the usart - * @param ch - * *f - * @retval the character - */ -int fputc(int ch, FILE *f) -{ - /* Send a byte to USART */ - LL_USART_TransmitData8(DEBUG_USART, ch); - while (!LL_USART_IsActiveFlag_TC(DEBUG_USART)); - LL_USART_ClearFlag_TC(DEBUG_USART); - - return (ch); -} - -/** - * @brief get a character from the usart - * @param *f - * @retval a character - */ -int fgetc(FILE *f) -{ - int ch; - while (!LL_USART_IsActiveFlag_RXNE(DEBUG_USART)); - ch = LL_USART_ReceiveData8(DEBUG_USART); - return (ch); -} - -#elif defined(__ICCARM__) -/** - * @brief writes a character to the usart - * @param ch - * *f - * @retval the character - */ -int putchar(int ch) -{ - /* Send a byte to USART */ - LL_USART_TransmitData8(DEBUG_USART, ch); - while (!LL_USART_IsActiveFlag_TC(DEBUG_USART)); - LL_USART_ClearFlag_TC(DEBUG_USART); - - return (ch); -} -#endif - -//#endif -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ + +/* Includes ------------------------------------------------------------------*/ +#include "py32f003xx_ll_Start_Kit.h" + +/** + * @brief PY32F003xx STK BSP Driver version number + */ +#define __PY32F003xx_STK_BSP_VERSION_MAIN (0x01U) /*!< [31:24] main version */ +#define __PY32F003xx_STK_BSP_VERSION_SUB1 (0x00U) /*!< [23:16] sub1 version */ +#define __PY32F003xx_STK_BSP_VERSION_SUB2 (0x00U) /*!< [15:8] sub2 version */ +#define __PY32F003xx_STK_BSP_VERSION_RC (0x00U) /*!< [7:0] release candidate */ +#define __PY32F003xx_STK_BSP_VERSION ((__PY32F003xx_STK_BSP_VERSION_MAIN << 24) \ + |(__PY32F003xx_STK_BSP_VERSION_SUB1 << 16) \ + |(__PY32F003xx_STK_BSP_VERSION_SUB2 << 8 ) \ + |(__PY32F003xx_STK_BSP_VERSION_RC)) + +GPIO_TypeDef* LED_PORT[LEDn] = {LED3_GPIO_PORT}; +const uint16_t LED_PIN[LEDn] = {LED3_PIN}; + +GPIO_TypeDef* BUTTON_PORT[BUTTONn] = {USER_BUTTON_GPIO_PORT }; +const uint16_t BUTTON_PIN[BUTTONn] = {USER_BUTTON_PIN }; +const uint8_t BUTTON_IRQn[BUTTONn] = {USER_BUTTON_EXTI_IRQn }; +const uint32_t BUTTON_EXTI_LINE[BUTTONn] = {USER_BUTTON_EXTI_LINE }; + +/** @addtogroup PY32F003xx_STK_Exported_Functions + * @{ + */ + +/** + * @brief This method returns the PY32F003 STK BSP Driver revision. + * @retval version : 0xXYZR (8bits for each decimal, R for RC) + */ +uint32_t BSP_GetVersion(void) +{ + return __PY32F003xx_STK_BSP_VERSION; +} + +/** @addtogroup LED_Functions + * @{ + */ + +/** + * @brief Configures LED GPIO. + * @param Led Specifies the Led to be configured. + * This parameter can be one of following parameters: + * @arg LED3 + * @retval None + */ +void BSP_LED_Init(Led_TypeDef Led) +{ + /* Enable the GPIO_LED Clock */ + LEDx_GPIO_CLK_ENABLE(Led); + + /* Configure the GPIO_LED pin */ + LL_GPIO_SetPinMode(LED_PORT[Led], LED_PIN[Led], LL_GPIO_MODE_OUTPUT); + /* LL_GPIO_SetPinOutputType(LED_PORT[Led], LED_PIN[Led], LL_GPIO_OUTPUT_PUSHPULL); */ + /* LL_GPIO_SetPinSpeed(LED_PORT[Led], LED_PIN[Led], LL_GPIO_SPEED_FREQ_LOW); */ + /* LL_GPIO_SetPinPull(LED_PORT[Led], LED_PIN[Led], LL_GPIO_PULL_NO); */ + + LL_GPIO_SetOutputPin(LED_PORT[Led], LED_PIN[Led]); +} + +/** + * @brief DeInitialize LED GPIO. + * @param Led Specifies the Led to be deconfigured. + * This parameter can be one of the following values: + * @arg LED3 + * @note BSP_LED_DeInit() does not disable the GPIO clock + * @retval None + */ +void BSP_LED_DeInit(Led_TypeDef Led) +{ + /* Turn off LED */ + LL_GPIO_ResetOutputPin(LED_PORT[Led], LED_PIN[Led]); + /* DeInit the GPIO_LED pin */ + LL_GPIO_SetPinMode(LED_PORT[Led], LED_PIN[Led], LL_GPIO_MODE_ANALOG); + /* LL_GPIO_SetPinOutputType(LED_PORT[Led], LED_PIN[Led], LL_GPIO_OUTPUT_PUSHPULL); */ + /* LL_GPIO_SetPinSpeed(LED_PORT[Led], LED_PIN[Led], LL_GPIO_SPEED_FREQ_LOW); */ + /* LL_GPIO_SetPinPull(LED_PORT[Led], LED_PIN[Led], LL_GPIO_PULL_NO); */ +} + +/** + * @brief Turns selected LED On. + * @param Led Specifies the Led to be set on. + * This parameter can be one of following parameters: + * @arg LED3 + * @retval None + */ +void BSP_LED_On(Led_TypeDef Led) +{ + LL_GPIO_ResetOutputPin(LED_PORT[Led], LED_PIN[Led]); +} + +/** + * @brief Turns selected LED Off. + * @param Led Specifies the Led to be set off. + * This parameter can be one of following parameters: + * @arg LED3 + * @retval None + */ +void BSP_LED_Off(Led_TypeDef Led) +{ + LL_GPIO_SetOutputPin(LED_PORT[Led], LED_PIN[Led]); +} + +/** + * @brief Toggles the selected LED. + * @param Led Specifies the Led to be toggled. + * This parameter can be one of following parameters: + * @arg LED3 + * @retval None + */ +void BSP_LED_Toggle(Led_TypeDef Led) +{ + LL_GPIO_TogglePin(LED_PORT[Led], LED_PIN[Led]); +} + +/** + * @brief Configures Button GPIO and EXTI Line. + * @param Button: Specifies the Button to be configured. + * This parameter should be: BUTTON_USER + * @param ButtonMode: Specifies Button mode. + * This parameter can be one of following parameters: + * @arg BUTTON_MODE_GPIO: Button will be used as simple IO + * @arg BUTTON_MODE_EXTI: Button will be connected to EXTI line with interrupt + * generation capability + * @retval None + */ +void BSP_PB_Init(Button_TypeDef Button, ButtonMode_TypeDef ButtonMode) +{ + /* Enable the BUTTON Clock */ + BUTTONx_GPIO_CLK_ENABLE(Button); + + /* Configure GPIO for BUTTON */ + LL_GPIO_SetPinMode(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_MODE_INPUT); + LL_GPIO_SetPinPull(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_PULL_NO); + /* LL_GPIO_SetPinSpeed(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_SPEED_FREQ_HIGH); */ + + if(ButtonMode == BUTTON_MODE_EXTI) + { + /* Configure Button pin as input with External interrupt */ + LL_EXTI_EnableIT(BUTTON_EXTI_LINE[Button]); + LL_EXTI_EnableFallingTrig(BUTTON_EXTI_LINE[Button]); + + /* Enable and set Button EXTI Interrupt to the lowest priority */ + NVIC_SetPriority((IRQn_Type)(BUTTON_IRQn[Button]), 0x0F); + NVIC_EnableIRQ((IRQn_Type)(BUTTON_IRQn[Button])); + } +} + +/** + * @brief Push Button DeInit. + * @param Button: Button to be configured + * This parameter should be: BUTTON_USER + * @note PB DeInit does not disable the GPIO clock + * @retval None + */ +void BSP_PB_DeInit(Button_TypeDef Button) +{ + NVIC_DisableIRQ((IRQn_Type)(BUTTON_IRQn[Button])); + LL_GPIO_SetPinMode(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_MODE_ANALOG); + /* LL_GPIO_SetPinSpeed(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_SPEED_FREQ_LOW); */ + /* LL_GPIO_SetPinPull(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_PULL_NO); */ + /* LL_GPIO_SetAFPin_8_15(BUTTON_PORT[Button], BUTTON_PIN[Button], LL_GPIO_AF_0); */ +} + +/** + * @brief Returns the selected Button state. + * @param Button: Specifies the Button to be checked. + * This parameter should be: BUTTON_USER + * @retval Button state. + */ +uint32_t BSP_PB_GetState(Button_TypeDef Button) +{ + return LL_GPIO_IsInputPinSet(BUTTON_PORT[Button], BUTTON_PIN[Button]); +} + + +//#endif +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/BSP_LL/Src/py32f0xx_bsp_printf.c b/Libraries/BSP_LL/Src/py32f0xx_bsp_printf.c new file mode 100644 index 0000000..80dc6d8 --- /dev/null +++ b/Libraries/BSP_LL/Src/py32f0xx_bsp_printf.c @@ -0,0 +1,151 @@ +#include +#include +#include +#include "py32f0xx_bsp_printf.h" + +/** + * @brief DEBUG_USART GPIO Config,Mode Config,115200 8-N-1 + * @param None + * @retval None + */ +void BSP_USART_Config(void) +{ + DEBUG_USART_CLK_ENABLE(); + + /* USART Init */ + LL_USART_SetBaudRate(DEBUG_USART, SystemCoreClock, LL_USART_OVERSAMPLING_16, DEBUG_USART_BAUDRATE); + LL_USART_SetDataWidth(DEBUG_USART, LL_USART_DATAWIDTH_8B); + LL_USART_SetStopBitsLength(DEBUG_USART, LL_USART_STOPBITS_1); + LL_USART_SetParity(DEBUG_USART, LL_USART_PARITY_NONE); + LL_USART_SetHWFlowCtrl(DEBUG_USART, LL_USART_HWCONTROL_NONE); + LL_USART_SetTransferDirection(DEBUG_USART, LL_USART_DIRECTION_TX_RX); + LL_USART_Enable(DEBUG_USART); + LL_USART_ClearFlag_TC(DEBUG_USART); + + /**USART GPIO Configuration + PA2 ------> USART1_TX + PA3 ------> USART1_RX + */ + DEBUG_USART_RX_GPIO_CLK_ENABLE(); + DEBUG_USART_TX_GPIO_CLK_ENABLE(); + + LL_GPIO_SetPinMode(DEBUG_USART_TX_GPIO_PORT, DEBUG_USART_TX_PIN, LL_GPIO_MODE_ALTERNATE); + LL_GPIO_SetPinSpeed(DEBUG_USART_TX_GPIO_PORT, DEBUG_USART_TX_PIN, LL_GPIO_SPEED_FREQ_VERY_HIGH); + LL_GPIO_SetPinPull(DEBUG_USART_TX_GPIO_PORT, DEBUG_USART_TX_PIN, LL_GPIO_PULL_UP); + LL_GPIO_SetAFPin_0_7(DEBUG_USART_TX_GPIO_PORT, DEBUG_USART_TX_PIN, DEBUG_USART_TX_AF); + + LL_GPIO_SetPinMode(DEBUG_USART_RX_GPIO_PORT, DEBUG_USART_RX_PIN, LL_GPIO_MODE_ALTERNATE); + LL_GPIO_SetPinSpeed(DEBUG_USART_RX_GPIO_PORT, DEBUG_USART_RX_PIN, LL_GPIO_SPEED_FREQ_VERY_HIGH); + LL_GPIO_SetPinPull(DEBUG_USART_RX_GPIO_PORT, DEBUG_USART_RX_PIN, LL_GPIO_PULL_UP); + LL_GPIO_SetAFPin_0_7(DEBUG_USART_RX_GPIO_PORT, DEBUG_USART_RX_PIN, DEBUG_USART_RX_AF); +} + + +#if defined (__GNUC__) && !defined (__clang__) + #define GETCHAR_PROTOTYPE int __io_getchar (void) + #define PUTCHAR_PROTOTYPE int __io_putchar(int ch) +#else + #define GETCHAR_PROTOTYPE int fgetc(FILE * f) + #define PUTCHAR_PROTOTYPE int fputc(int ch, FILE *f) +#endif + +/** + * @brief retargets the c library printf function to the usart. + * @param none + * @retval none + */ +PUTCHAR_PROTOTYPE +{ + /* Send a byte to USART */ + LL_USART_TransmitData8(DEBUG_USART, ch); + while (!LL_USART_IsActiveFlag_TC(DEBUG_USART)); + LL_USART_ClearFlag_TC(DEBUG_USART); + + return (ch); +} + +GETCHAR_PROTOTYPE +{ + int ch; + while (!LL_USART_IsActiveFlag_RXNE(DEBUG_USART)); + ch = LL_USART_ReceiveData8(DEBUG_USART); + return (ch); +} + +#if defined (__GNUC__) && !defined (__clang__) +__attribute__((weak)) int _write(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + __io_putchar(*ptr++); + } + return len; +} +#endif + +__attribute__((weak)) int _read(int file, char *ptr, int len) +{ + (void)file; + int DataIdx; + for (DataIdx = 0; DataIdx < len; DataIdx++) + { + *ptr++ = __io_getchar(); + } + return len; +} + +__attribute__((weak)) int _isatty(int fd) +{ + if (fd >= STDIN_FILENO && fd <= STDERR_FILENO) + return 1; + + errno = EBADF; + return 0; +} + +__attribute__((weak)) int _close(int fd) +{ + if (fd >= STDIN_FILENO && fd <= STDERR_FILENO) + return 0; + + errno = EBADF; + return -1; +} + +__attribute__((weak)) int _lseek(int fd, int ptr, int dir) +{ + (void)fd; + (void)ptr; + (void)dir; + + errno = EBADF; + return -1; +} + +__attribute__((weak)) int _fstat(int fd, struct stat *st) +{ + if (fd >= STDIN_FILENO && fd <= STDERR_FILENO) + { + st->st_mode = S_IFCHR; + return 0; + } + + errno = EBADF; + return 0; +} + +__attribute__((weak)) int _getpid(void) +{ + errno = ENOSYS; + return -1; +} + +__attribute__((weak)) int _kill(pid_t pid, int sig) +{ + (void)pid; + (void)sig; + errno = ENOSYS; + return -1; +} diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_adc.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_adc.h similarity index 98% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_adc.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_adc.h index 7cc2934..a8e752a 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_adc.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_adc.h @@ -1,3282 +1,3282 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_adc.h - * @author MCU Application Team - * @brief Header file of ADC LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PY32F0XX_LL_ADC_H -#define __PY32F0XX_LL_ADC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" -#include "py32f0xx_ll_bus.h" -/** @addtogroup PY320xx_LL_Driver - * @{ - */ - -#if defined (ADC1) - -/** @defgroup ADC_LL ADC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup ADC_LL_Private_Constants ADC Private Constants - * @{ - */ - -/* Internal mask for ADC group regular trigger: */ -/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ -/* - regular trigger source */ -/* - regular trigger edge */ -#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other PY32 families having this setting set by HW default value) */ - -/* Mask containing trigger source masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0U)) | \ - (( ADC_CFGR1_EXTSEL) << (4U * 1U)) | \ - (( ADC_CFGR1_EXTSEL) << (4U * 2U)) | \ - (( ADC_CFGR1_EXTSEL) << (4U * 3U)) ) - -/* Mask containing trigger edge masks for each of possible */ -/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ -/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ -#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \ - ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) - -/* Definition of ADC group regular trigger bits information. */ -#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */ -#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */ - - - -/* Internal mask for ADC channel: */ -/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ -/* - channel identifier defined by number */ -/* - channel identifier defined by bitfield */ -/* - channel differentiation between external channels (connected to */ -/* GPIO pins) and internal channels (connected to internal paths) */ -#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH) -#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) -#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ -#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) -/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ -#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ - -/* Channel differentiation between external and internal channels */ -#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */ -#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH) - -/* Definition of channels ID number information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_NUMBER (0x00000000U) -#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR1_AWDCH_0) -#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR1_AWDCH_1 ) -#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) -#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR1_AWDCH_2 ) -#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_0) -#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 ) -#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) -#define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWDCH_3 ) -#define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_0) -#define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) -#define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 ) - -/* Definition of channels ID bitfield information to be inserted into */ -/* channels literals definition. */ -#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0) -#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1) -#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2) -#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3) -#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4) -#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5) -#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6) -#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7) -#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8) -#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9) -#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11) -#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12) - - -/* Internal mask for ADC analog watchdog: */ -/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ -/* - analog watchdog 1: monitored channel defined by number, */ -/* selection of ADC group (ADC group regular). */ - -/* Internal register offset for ADC analog watchdog channel configuration */ -#define ADC_AWD_CR1_REGOFFSET (0x00000000U) - -#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) - -#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) -#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) - -/* Internal register offset for ADC analog watchdog threshold configuration */ -#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) -#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET) - - -/* ADC registers bits positions */ -#define ADC_CFGR1_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RESSEL) */ -#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */ -#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ -#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */ -#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */ -#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */ -#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */ -#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */ -#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */ -#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */ -#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */ -#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */ -#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */ -#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */ -#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */ - - - -/* ADC registers bits groups */ -#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ - - -/* ADC internal channels related definitions */ -/* Internal voltage reference VrefInt */ -#define VREFINT_CAL_VREF ( 1200U) /* Analog voltage reference (Vref+) value (tolerance: +-10 mV) (unit: mV). */ -/* Temperature sensor */ -#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1fff0f14)) /* Internal temperature sensor, address of parameter TS_CAL1: On PY32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1fff0f18)) /* Internal temperature sensor, address of parameter TS_CAL2: On PY32F0, temperature sensor ADC raw data acquired at temperature 85 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ -#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL2_TEMP (( int32_t) 85) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ -#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ - -/* Definitions of ADC hardware constraints delays */ -/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ -/* not timeout values: */ -/* Timeout values for ADC operations are dependent to device clock */ -/* configuration (system clock versus ADC clock), */ -/* and therefore must be defined in user application. */ -/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ -/* values definition. */ -/* Unit: CPU cycles. */ -#define LL_ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U) -#define LL_ADC_TIMEOUT_DISABLE_CPU_CYCLES (LL_ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) -#define LL_ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (LL_ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) - - -/** - * @} - */ - - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure - * @{ - */ - -/** - * @brief Structure definition of some features of ADC instance. - * @note These parameters have an impact on ADC scope: ADC instance. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Instance . - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all PY32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - */ -typedef struct -{ - uint32_t Clock; /*!< Set ADC instance clock source and prescaler. - This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE - @note On this PY32 serie, this parameter has some clock ratio constraints: - Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. - Note: This parameter can be modified only if the ADC is disabled - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock(). - For more details, refer to description of this function. */ - - uint32_t Resolution; /*!< Set ADC resolution. - This parameter can be a value of @ref ADC_LL_EC_RESOLUTION - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ - - uint32_t DataAlignment; /*!< Set ADC conversion data alignment. - This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ - - uint32_t LowPowerMode; /*!< Set ADC low power mode. - This parameter can be a value of @ref ADC_LL_EC_LP_MODE - - This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ - -} LL_ADC_InitTypeDef; - -/** - * @brief Structure definition of some features of ADC group regular. - * @note These parameters have an impact on ADC scope: ADC group regular. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "REG"). - * @note The setting of these parameters by function @ref LL_ADC_REG_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all PY32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - */ -typedef struct -{ - uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event). - This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE - @note On this PY32 serie, setting trigger source to external trigger also set trigger polarity to rising edge - (default setting for compatibility with some ADC on other PY32 families having this setting set by HW default value). - In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ - - uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. - This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE - @note This parameter has an effect only if group regular sequencer is enabled - (several ADC channels enabled in group regular sequencer). - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ - - uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). - This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE - Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ -#if (defined(DMA) || defined(DMA1)) - uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. - This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ -#endif - - uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: - data preserved or overwritten. - This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR - - This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ - -} LL_ADC_REG_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants - * @{ - */ - -/** @defgroup ADC_LL_EC_FLAG ADC flags - * @brief Flags defines which can be used with LL_ADC_ReadReg function - * @{ - */ - -#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ -#define LL_ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC flag ADC group regular end of sequence conversions */ -#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ -#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ -#define LL_ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC flag ADC analog watchdog 1 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) - * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions - * @{ - */ - -#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ -#define LL_ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC interruption ADC group regular end of sequence conversions */ -#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ -#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */ -#define LL_ADC_IT_AWD ADC_IER_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose - * @{ - */ -/* List of ADC registers intended to be used (most commonly) with */ -/* DMA transfer. */ -/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ -#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels - * @{ - */ -/* Note: Other measurement paths to internal channels may be available */ -/* (connections to other peripherals). */ -/* If they are not listed below, they do not require any specific */ -/* path enable. In this case, Access to measurement path is done */ -/* only by selecting the corresponding ADC internal channel. */ -#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U) /*!< ADC measurement pathes all disabled */ -#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ -#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source - * @{ - */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (0x00000000U) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 1 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 2 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CFGR2_CKMODE_1 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 4 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CFGR2_CKMODE_0 | ADC_CFGR2_CKMODE_1 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 8 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV16 ( ADC_CFGR2_CKMODE_2 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 16 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV32 (ADC_CFGR2_CKMODE_0 | ADC_CFGR2_CKMODE_2 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 32 */ -#define LL_ADC_CLOCK_SYNC_PCLK_DIV64 ( ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_2 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 64 */ -#define LL_ADC_CLOCK_ASYNC_HSI_DIV1 ( ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 1 */ -#define LL_ADC_CLOCK_ASYNC_HSI_DIV2 (ADC_CFGR2_CKMODE_0 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 2 */ -#define LL_ADC_CLOCK_ASYNC_HSI_DIV4 ( ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 4 */ -#define LL_ADC_CLOCK_ASYNC_HSI_DIV8 (ADC_CFGR2_CKMODE_0 | ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 8 */ -#define LL_ADC_CLOCK_ASYNC_HSI_DIV16 ( ADC_CFGR2_CKMODE_2 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 16 */ -#define LL_ADC_CLOCK_ASYNC_HSI_DIV32 (ADC_CFGR2_CKMODE_0 | ADC_CFGR2_CKMODE_2 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 32 */ -#define LL_ADC_CLOCK_ASYNC_HSI_DIV64 ( ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_2 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 64 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution - * @{ - */ -#define LL_ADC_RESOLUTION_12B (0x00000000U) /*!< ADC resolution 12 bits */ -#define LL_ADC_RESOLUTION_10B (ADC_CFGR1_RESSEL_0) /*!< ADC resolution 10 bits */ -#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RESSEL_1) /*!< ADC resolution 8 bits */ -#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RESSEL_1 | ADC_CFGR1_RESSEL_0) /*!< ADC resolution 6 bits */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment - * @{ - */ -#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ -#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode - * @{ - */ -#define LL_ADC_LP_MODE_NONE (0x00000000U) /*!< No ADC low power mode activated */ -#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups - * @{ - */ -#define LL_ADC_GROUP_REGULAR (0x00000001U) /*!< ADC group regular (available on all PY32 devices) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number - * @{ - */ -#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ -#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ -#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ -#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ -#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ -#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ -#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ -#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ -#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ -#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ -#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ -#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ -#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ -#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_11 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source - * @{ - */ -#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ -#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ -#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge - * @{ - */ -#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ -#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ -#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode -* @{ -*/ -#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ -#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ -/** - * @} - */ -#if (defined(DMA) || defined(DMA1)) -/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data - * @{ - */ -#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ -#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ -#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ -/** - * @} - */ -#endif - -/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data -* @{ -*/ -#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U) /*!< ADC group regular behavior in case of overrun: data preserved */ -#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction - * @{ - */ -#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000U) /*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other PY32 families, this setting is not available and the default scan direction is forward. */ -#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode - * @{ - */ -#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ -#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time - * @{ - */ -#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (0x00000000U) /*!< Sampling time 3.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_5CYCLES_5 ( ADC_SMPR_SMP_0) /*!< Sampling time 5.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_7CYCLES_5 ( ADC_SMPR_SMP_1 ) /*!< Sampling time 7.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_13CYCLES_5 ( ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 13.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR_SMP_2 ) /*!< Sampling time 28.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0) /*!< Sampling time 41.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 ) /*!< Sampling time 71.5 ADC clock cycles */ -#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 239.5 ADC clock cycles */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number - * @{ - */ -#define LL_ADC_AWD (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels - * @{ - */ -#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ -#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ -#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ -#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ -#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds - * @{ - */ -#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR_HT ) /*!< ADC analog watchdog threshold high */ -#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR_LT) /*!< ADC analog watchdog threshold low */ -#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR_HT | ADC_TR_LT) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CAL_SAMPLINGTIME Calibration - Sampling time - * @{ - */ -#define LL_ADC_CAL_SAMPLINGTIME_2CYCLES (0x00000000U) /*!< CAL Sampling time 2 ADC clock cycles */ -#define LL_ADC_CAL_SAMPLINGTIME_4CYCLES ( ADC_CCSR_CALSMP_0) /*!< CAL Sampling time 4 ADC clock cycles */ -#define LL_ADC_CAL_SAMPLINGTIME_8CYCLES (ADC_CCSR_CALSMP_1 ) /*!< CAL Sampling time 8 ADC clock cycles */ -#define LL_ADC_CAL_SAMPLINGTIME_1CYCLE (ADC_CCSR_CALSMP_1 | ADC_CCSR_CALSMP_0) /*!< CAL Sampling time 1 ADC clock cycle */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CAL_MODE Calibration - Mode - * @{ - */ -#define LL_ADC_CAL_MODE_OFFSET (0x00000000U) /*!< ADC calibration mode selection only OFFSET */ -#define LL_ADC_CAL_MODE_OFFSETANDLINEARITY ADC_CCSR_CALSEL /*!< ADC calibration mode selection OFFSET AND LINERARITY */ -/** - * @} - */ - -/** @defgroup ADC_LL_EC_CAL_STATUS Calibration - Status - * @{ - */ -#define LL_ADC_CAL_STATUS_SUCCESS (0x00000000U) /*!< ADC calibration status SUCCESS */ -#define LL_ADC_CAL_STATUS_FAIL ( ADC_CCSR_CALFAIL) /*!< ADC calibration status FAIL */ -#define LL_ADC_CAL_STATUS_ONGOING (ADC_CCSR_CALON ) /*!< ADC calibration status ONGOING */ -#define LL_ADC_CAL_STATUS_INVALID (ADC_CCSR_CALON | ADC_CCSR_CALFAIL) /*!< ADC calibration status INVALID */ - - -/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays - * @note Only ADC IP HW delays are defined in ADC LL driver driver, - * not timeout values. - * For details on delays values, refer to descriptions in source code - * above each literal definition. - * @{ - */ - -/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ -/* not timeout values. */ -/* Timeout values for ADC operations are dependent to device clock */ -/* configuration (system clock versus ADC clock), */ -/* and therefore must be defined in user application. */ -/* Indications for estimation of ADC timeout delays, for this */ -/* PY32 serie: */ -/* - ADC calibration time: maximum delay is 64/fADC. */ -/* - ADC enable time: maximum delay is 8 ADC Clock Cycles. */ -/* - ADC disable time: maximum delay should be a few ADC clock cycles */ -/* - ADC stop conversion time: maximum delay should be a few ADC clock */ -/* cycles */ -/* - ADC conversion time: duration depending on ADC clock and ADC */ -/* configuration. */ -/* (refer to device reference manual, section "Timing") */ - - -/* Delay for internal voltage reference stabilization time. */ -/* Delay set to maximum value (refer to device datasheet, */ -/* parameter "tSTART"). */ -/* Unit: us */ -#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ - -/* Delay for temperature sensor stabilization time. */ -/* Literal set to maximum value (refer to device datasheet, */ -/* parameter "tSTART"). */ -/* Unit: us */ -#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for temperature sensor stabilization time */ - -/* Delay required between ADC end of calibration and ADC enable. */ -/* Note: On this PY32 serie, a minimum number of ADC clock cycles */ -/* are required between ADC end of calibration and ADC enable. */ -/* Wait time can be computed in user application by waiting for the */ -/* equivalent number of CPU cycles, by taking into account */ -/* ratio of CPU clock versus ADC clock prescalers. */ -/* Unit: ADC clock cycles. */ -#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4U) /*!< Delay required between ADC end of calibration and ADC enable */ - - /* Delay between ADC end of calibration and ADC enable. */ - /* Delay estimation in CPU cycles: Case of ADC enable done */ - /* immediately after ADC calibration, ADC clock setting slow */ - /* (CPU clock / ADC clock) is above 64. */ -#define LL_ADC_DELAY_CALIB_ENABLE_CPU_CYCLES (LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES * 64) - - /* Timeout values for ADC Calibration. */ -#define LL_ADC_CALIBRATION_TIMEOUT_CPU_CYCLES ( 1000U) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros - * @{ - */ - -/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in ADC register - * @param __INSTANCE__ ADC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in ADC register - * @param __INSTANCE__ ADC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro - * @{ - */ - -/** - * @brief Helper macro to get ADC channel number in decimal format - * from literals LL_ADC_CHANNEL_x. - * @note Example: - * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) - * will return decimal number "4". - * @note The input can be a value from functions where a channel - * number is returned, either defined with number - * or with bitfield (only one bit must be set). - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR - * @retval Value between Min_Data=0 and Max_Data=12 - */ -#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ - ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \ - ? ( \ - ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ - ) \ - : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : \ - ( \ - (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) : \ - (0U) \ - ) \ - ) \ - ) \ - ) \ - ) \ - ) \ - ) \ - ) \ - ) \ - ) \ - ) \ - ) \ - ) - -/** - * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x - * from number in decimal format. - * @note Example: - * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) - * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=12 - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * (1) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - */ -#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ - ( \ - ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ - (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \ - ) - -/** - * @brief Helper macro to determine whether the selected channel - * corresponds to literal definitions of driver. - * @note The different literal definitions of ADC channels are: - * - ADC internal channel: - * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... - * - ADC external channel (channel connected to a GPIO pin): - * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... - * @note The channel parameter must be a value defined from literal - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), - * must not be a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR - * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). - * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. - */ -#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ - (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) - -/** - * @brief Helper macro to convert a channel defined from parameter - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * to its equivalent parameter definition of a ADC external channel - * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). - * @note The channel parameter can be, additionally to a value - * defined from parameter definition of a ADC internal channel - * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), - * a value defined from parameter definition of - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is returned - * from ADC registers. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - */ -#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ - ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) - -/** - * @brief Helper macro to determine whether the internal channel - * selected is available on the ADC instance selected. - * @note The channel parameter must be a value defined from parameter - * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, - * LL_ADC_CHANNEL_TEMPSENSOR, ...), - * must not be a value defined from parameter definition of - * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) - * or a value from functions where a channel number is - * returned from ADC registers, - * because internal and external channels share the same channel - * number in ADC registers. The differentiation is made only with - * parameters definitions of driver. - * @param __ADC_INSTANCE__ ADC instance - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR - * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. - * Value "1" if the internal channel selected is available on the ADC instance selected. - */ - -#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ - ( \ - ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ - ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \ - ) - -/** - * @brief Helper macro to define ADC analog watchdog parameter: - * define a single channel to monitor with analog watchdog - * from sequencer channel and groups definition. - * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). - * Example: - * LL_ADC_SetAnalogWDMonitChannels( - * ADC1, LL_ADC_AWD, - * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_VREFINT (1) - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) - * (1) For ADC channel read back from ADC register, - * comparison with internal channel parameter to be done - * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). - * @param __GROUP__ This parameter can be one of the following values: - * @arg @ref LL_ADC_GROUP_REGULAR - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG - */ -#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)\ - (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) - -/** - * @brief Helper macro to set the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is - * different of 12 bits. - * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() - * or @ref LL_ADC_SetAnalogWDThresholds(). - * Example, with a ADC resolution of 8 bits, to set the value of - * analog watchdog threshold high (on 8 bits): - * LL_ADC_SetAnalogWDThresholds - * (< ADCx param >, - * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) - * ); - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ - ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) - -/** - * @brief Helper macro to get the value of ADC analog watchdog threshold high - * or low in function of ADC resolution, when ADC resolution is - * different of 12 bits. - * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). - * Example, with a ADC resolution of 8 bits, to get the value of - * analog watchdog threshold high (on 8 bits): - * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION - * (LL_ADC_RESOLUTION_8B, - * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) - * ); - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ - ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) - -/** - * @brief Helper macro to get the ADC analog watchdog threshold high - * or low from raw value containing both thresholds concatenated. - * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). - * Example, to get analog watchdog threshold high from the register raw value: - * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, ); - * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ - (((__AWD_THRESHOLD_TYPE__) == LL_ADC_AWD_THRESHOLD_LOW) \ - ? ( \ - (__AWD_THRESHOLDS__) & LL_ADC_AWD_THRESHOLD_LOW \ - ) \ - : \ - ( \ - ((__AWD_THRESHOLDS__) >> ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW \ - ) \ - ) - -/** - * @brief Helper macro to select the ADC common instance - * to which is belonging the selected ADC instance. - * @note ADC common register instance can be used for: - * - Set parameters common to several ADC instances - * - Multimode (for devices with several ADC instances) - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @param __ADCx__ ADC instance - * @retval ADC common register instance - */ -#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ - (ADC1_COMMON) - -/** - * @brief Helper macro to check if all ADC instances sharing the same - * ADC common instance are disabled. - * @note This check is required by functions with setting conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * Refer to functions having argument "ADCxy_COMMON" as parameter. - * @note On devices with only 1 ADC common instance, parameter of this macro - * is useless and can be ignored (parameter kept for compatibility - * with devices featuring several ADC common instances). - * @param __ADCXY_COMMON__ ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Value "0" if all ADC instances sharing the same ADC common instance - * are disabled. - * Value "1" if at least one ADC instance sharing the same ADC common instance - * is enabled. - */ -#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ - LL_ADC_IsEnabled(ADC1) - -/** - * @brief Helper macro to define the ADC conversion data full-scale digital - * value corresponding to the selected ADC resolution. - * @note ADC conversion data full-scale corresponds to voltage range - * determined by analog voltage references Vref+ and Vref- - * (refer to reference manual). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ - (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) - -/** - * @brief Helper macro to convert the ADC conversion data from - * a resolution to another resolution. - * @param __DATA__ ADC conversion data to be converted - * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data to the requested resolution - */ -#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \ - (((__DATA__) \ - << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) \ - >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)) \ - ) - -/** - * @brief Helper macro to calculate the voltage (unit: mVolt) - * corresponding to a ADC conversion data (unit: digital value). - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) - * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) - * (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval ADC conversion data equivalent voltage value (unit: mVolt) - */ -#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,__ADC_DATA__,__ADC_RESOLUTION__) \ - ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) - -/** - * @brief Helper macro to calculate analog reference voltage (Vref+) - * (unit: mVolt) from ADC conversion data of internal voltage - * reference VrefInt. - * @note Computation is using VrefInt calibration value - * stored in system memory for each device during production. - * @note This voltage depends on user board environment: voltage level - * connected to pin Vref+. - * On devices with small package, the pin Vref+ is not present - * and internally bonded to pin Vdda. - * @note On this PY32 serie, calibration data of internal voltage reference - * VrefInt corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * internal voltage reference VrefInt. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) - * of internal voltage reference VrefInt (unit: digital value). - * @param __ADC_RESOLUTION__ This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Analog reference voltage (unit: mV) - */ -#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,__ADC_RESOLUTION__) \ - (4095*( VREFINT_CAL_VREF)/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),(__ADC_RESOLUTION__),LL_ADC_RESOLUTION_12B)) - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor calibration values - * stored in system memory for each device during production. - * @note Calculation formula: - * Temperature = ((TS_ADC_DATA - TS_CAL1) - * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) - * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * Avg_Slope = (TS_CAL2 - TS_CAL1) - * / (TS_CAL2_TEMP - TS_CAL1_TEMP) - * TS_CAL1 = equivalent TS_ADC_DATA at temperature - * TEMP_DEGC_CAL1 (calibrated in factory) - * TS_CAL2 = equivalent TS_ADC_DATA at temperature - * TEMP_DEGC_CAL2 (calibrated in factory) - * Caution: Calculation relevancy under reserve that calibration - * parameters are correct (address and data). - * To calculate temperature using temperature sensor - * datasheet typical values (generic values less, therefore - * less accurate than calibrated values), - * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note On this PY32 serie, calibration data of temperature sensor - * corresponds to a resolution of 12 bits, - * this is the recommended ADC resolution to convert voltage of - * temperature sensor. - * Otherwise, this macro performs the processing to scale - * ADC conversion data to 12 bits. - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal - * temperature sensor (unit: digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature - * sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Temperature (unit: degree Celsius) - */ -#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ - (__ADC_RESOLUTION__), \ - LL_ADC_RESOLUTION_12B) \ - * (__VREFANALOG_VOLTAGE__)) \ - / TEMPSENSOR_CAL_VREFANALOG) \ - - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ - ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ - ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ - ) + TEMPSENSOR_CAL1_TEMP \ - ) - -/** - * @brief Helper macro to calculate the temperature (unit: degree Celsius) - * from ADC conversion data of internal temperature sensor. - * @note Computation is using temperature sensor typical values - * (refer to device datasheet). - * @note Calculation formula: - * Temperature = (TS_ADC_DATA * Conversion_uV-TS_TYP_CALx_VOLT(uV) ) - * / Avg_Slope + CALx_TEMP - * with TS_ADC_DATA = temperature sensor raw data measured by ADC - * (unit: digital value) - * Avg_Slope = temperature sensor slope - * (unit: uV/Degree Celsius) - * TS_TYP_CALx_VOLT = temperature sensor digital value at - * temperature CALx_TEMP (unit: mV) - * Caution: Calculation relevancy under reserve the temperature sensor - * of the current device has characteristics in line with - * datasheet typical values. - * If temperature sensor calibration values are available on - * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), - * temperature calculation will be more accurate using - * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). - * @note As calculation input, the analog reference voltage (Vref+) must be - * defined as it impacts the ADC LSB equivalent voltage. - * @note Analog reference voltage (Vref+) must be either known from - * user board environment or can be calculated using ADC measurement - * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @note ADC measurement data must correspond to a resolution of 12bits - * (full scale digital value 4095). If not the case, the data must be - * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). - * On PY32F0, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). - * On PY32F0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). - * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. - * This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval Temperature (unit: degree Celsius) - */ - -#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ - __TEMPSENSOR_TYP_CALX_V__,\ - __TEMPSENSOR_CALX_TEMP__,\ - __VREFANALOG_VOLTAGE__,\ - __TEMPSENSOR_ADC_DATA__,\ - __ADC_RESOLUTION__) \ - (((( (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ - / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ - * 1000)- (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ - * 1000))) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ - ) + (__TEMPSENSOR_CALX_TEMP__) \ - ) - -#if (defined(DMA) || defined(DMA1)) -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions - * @{ - */ - -/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management - * @{ - */ -/* Note: LL ADC functions to set DMA transfer are located into sections of */ -/* configuration of ADC instance, groups and multimode (if available): */ -/* @ref LL_ADC_REG_SetDMATransfer(), ... */ - -/** - * @brief Function to help to configure DMA transfer from ADC: retrieve the - * ADC register address from ADC instance and a list of ADC registers - * intended to be used (most commonly) with DMA transfer. - * @note These ADC registers are data registers: - * when ADC conversion data is available in ADC data registers, - * ADC generates a DMA transfer request. - * @note This macro is intended to be used with LL DMA driver, refer to - * function "LL_DMA_ConfigAddresses()". - * Example: - * LL_DMA_ConfigAddresses(DMA1, - * LL_DMA_CHANNEL_1, - * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), - * (uint32_t)&< array or variable >, - * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); - * @note For devices with several ADC: in multimode, some devices - * use a different data register outside of ADC instance scope - * (common data register). This macro manages this register difference, - * only ADC instance has to be set as parameter. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr - * @param ADCx ADC instance - * @param Register This parameter can be one of the following values: - * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA - * @retval ADC register address - */ -__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) -{ - /* Retrieve address of register DR */ - return (uint32_t)&(ADCx->DR); -} -#endif - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances - * @{ - */ - -/** - * @brief Set parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @note Stabilization time of measurement path to internal channel: - * After enabling internal paths, before starting ADC conversion, - * a delay is required for internal voltage reference and - * temperature sensor stabilization time. - * Refer to device datasheet. - * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. - * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. - * @note ADC internal channel sampling time constraint: - * For ADC conversion of internal channels, - * a sampling time minimum value is required. - * Refer to device datasheet. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * All ADC instances of the ADC common group must be disabled. - * This check can be done with function @ref LL_ADC_IsEnabled() for each - * ADC instance or by using helper macro helper macro - * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). - * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n - * CCR TSEN LL_ADC_SetCommonPathInternalCh - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @param PathInternal This parameter can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) -{ - MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal); -} - -/** - * @brief Get parameter common to several ADC: measurement path to internal - * channels (VrefInt, temperature sensor, ...). - * @note One or several values can be selected. - * Example: (LL_ADC_PATH_INTERNAL_VREFINT | - * LL_ADC_PATH_INTERNAL_TEMPSENSOR) - * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n - * CCR TSEN LL_ADC_GetCommonPathInternalCh - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval Returned value can be a combination of the following values: - * @arg @ref LL_ADC_PATH_INTERNAL_NONE - * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT - * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR - */ -__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) -{ - return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance - * @{ - */ - -/** - * @brief Set ADC instance clock source and prescaler. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled. - * @rmtoll CFGR2 CKMODE LL_ADC_SetClock - * @param ADCx ADC instance - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV16 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV32 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV64 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV1 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV2 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV4 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV8 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV16 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV32 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV64 - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource) -{ - MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); -} - -/** - * @brief Get ADC instance clock source and prescaler. - * @rmtoll CFGR2 CKMODE LL_ADC_GetClock - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV16 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV32 - * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV64 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV1 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV2 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV4 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV8 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV16 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV32 - * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV64 - */ -__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); -} - -/** - * @brief Set ADC resolution. - * Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR1 RES LL_ADC_SetResolution - * @param ADCx ADC instance - * @param Resolution This parameter can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RESSEL, Resolution); -} - -/** - * @brief Get ADC resolution. - * Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CFGR1 RES LL_ADC_GetResolution - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_RESOLUTION_12B - * @arg @ref LL_ADC_RESOLUTION_10B - * @arg @ref LL_ADC_RESOLUTION_8B - * @arg @ref LL_ADC_RESOLUTION_6B - */ -__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RESSEL)); -} - -/** - * @brief Set ADC conversion data alignment. - * @note Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment - * @param ADCx ADC instance - * @param DataAlignment This parameter can be one of the following values: - * @arg @ref LL_ADC_DATA_ALIGN_RIGHT - * @arg @ref LL_ADC_DATA_ALIGN_LEFT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment); -} - -/** - * @brief Get ADC conversion data alignment. - * @note Refer to reference manual for alignments formats - * dependencies to ADC resolutions. - * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_DATA_ALIGN_RIGHT - * @arg @ref LL_ADC_DATA_ALIGN_LEFT - */ -__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); -} - -/** - * @brief Set ADC low power mode. - * @note Description of ADC low power modes: - * - ADC low power mode "auto wait": Dynamic low power mode, - * ADC conversions occurrences are limited to the minimum necessary - * in order to reduce power consumption. - * New ADC conversion starts only when the previous - * unitary conversion data (for ADC group regular) - * has been retrieved by user software. - * In the meantime, ADC remains idle: does not performs any - * other conversion. - * This mode allows to automatically adapt the ADC conversions - * triggers to the speed of the software that reads the data. - * Moreover, this avoids risk of overrun for low frequency - * applications. - * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. - * - Do use with polling: 1. Start conversion, - * 2. Later on, when conversion data is needed: poll for end of - * conversion to ensure that conversion is completed and - * retrieve ADC conversion data. This will trig another - * ADC conversion start. - * - * @note With ADC low power mode "auto wait", the ADC conversion data read - * is corresponding to previous ADC conversion start, independently - * of delay during which ADC was idle. - * Therefore, the ADC conversion data may be outdated: does not - * correspond to the current voltage level on the selected - * ADC channel. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode - * @param ADCx ADC instance - * @param LowPowerMode This parameter can be one of the following values: - * @arg @ref LL_ADC_LP_MODE_NONE - * @arg @ref LL_ADC_LP_AUTOWAIT - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) -{ - MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT), LowPowerMode); -} - -/** - * @brief Get ADC low power mode: - * @note Description of ADC low power modes: - * - ADC low power mode "auto wait": Dynamic low power mode, - * ADC conversions occurrences are limited to the minimum necessary - * in order to reduce power consumption. - * New ADC conversion starts only when the previous - * unitary conversion data (for ADC group regular) - * has been retrieved by user software. - * In the meantime, ADC remains idle: does not performs any - * other conversion. - * This mode allows to automatically adapt the ADC conversions - * triggers to the speed of the software that reads the data. - * Moreover, this avoids risk of overrun for low frequency - * applications. - * How to use this low power mode: - * - Do not use with interruption or DMA since these modes - * have to clear immediately the EOC flag to free the - * IRQ vector sequencer. - * - Do use with polling: 1. Start conversion, - * 2. Later on, when conversion data is needed: poll for end of - * conversion to ensure that conversion is completed and - * retrieve ADC conversion data. This will trig another - * ADC conversion start. - * This feature can be combined with low power mode "auto wait". - * @note With ADC low power mode "auto wait", the ADC conversion data read - * is corresponding to previous ADC conversion start, independently - * of delay during which ADC was idle. - * Therefore, the ADC conversion data may be outdated: does not - * correspond to the current voltage level on the selected - * ADC channel. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_LP_MODE_NONE - * @arg @ref LL_ADC_LP_AUTOWAIT - */ -__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT ))); -} - -/** - * @brief Set sampling time common to a group of channels. - * @note Unit: ADC clock cycles. - * @note On this PY32 serie, sampling time scope is on ADC instance: - * Sampling time common to all channels. - * (on some other PY32 families, sampling time is channel wise) - * @note In case of internal channel (VrefInt, TempSensor, ...) to be - * converted: - * sampling time constraints must be respected (sampling time can be - * adjusted in function of ADC clock frequency and sampling time - * setting). - * Refer to device datasheet for timings values (parameters TS_vrefint, - * TS_temp, ...). - * @note Conversion time is the addition of sampling time and processing time. - * On this PY32 serie, ADC processing time is: - * - 12.5 ADC clock cycles at ADC resolution 12 bits - * - 10.5 ADC clock cycles at ADC resolution 10 bits - * - 8.5 ADC clock cycles at ADC resolution 8 bits - * - 6.5 ADC clock cycles at ADC resolution 6 bits - * @note In case of ADC conversion of internal channel (VrefInt, - * temperature sensor, ...), a sampling time minimum value - * is required. - * Refer to device datasheet. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll SMPR SMP LL_ADC_SetSamplingTimeCommonChannels - * @param ADCx ADC instance - * @param SamplingTime This parameter can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime) -{ - MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime); -} - -/** - * @brief Get sampling time common to a group of channels. - * @note Unit: ADC clock cycles. - * @note On this PY32 serie, sampling time scope is on ADC instance: - * Sampling time common to all channels. - * (on some other PY32 families, sampling time is channel wise) - * @note Conversion time is the addition of sampling time and processing time. - * Refer to reference manual for ADC processing time of - * this PY32 serie. - * @rmtoll SMPR SMP LL_ADC_GetSamplingTimeCommonChannels - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 - * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 - */ -__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular - * @{ - */ - -/** - * @brief Set ADC group regular conversion trigger source: - * internal (SW start) or from external IP (timer event, - * external interrupt line). - * @note On this PY32 serie, setting trigger source to external trigger - * also set trigger polarity to rising edge - * (default setting for compatibility with some ADC on other - * PY32 families having this setting set by HW default value). - * In case of need to modify trigger edge, use - * function @ref LL_ADC_REG_SetTriggerEdge(). - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n - * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource - * @param ADCx ADC instance - * @param TriggerSource This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource); -} - -/** - * @brief Get ADC group regular conversion trigger source: - * internal (SW start) or from external IP (timer event, - * external interrupt line). - * @note To determine whether group regular trigger source is - * internal (SW start) or external, without detail - * of which peripheral is selected as external trigger, - * (equivalent to - * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") - * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. - * @note Availability of parameters of trigger sources from timer - * depends on timers availability on the selected device. - * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n - * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_SOFTWARE - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 - * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) -{ - register uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); - - /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ - /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ - register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); - - /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ - /* to match with triggers literals definition. */ - return ((TriggerSource - & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) - | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN) - ); -} - -/** - * @brief Get ADC group regular conversion trigger source internal (SW start) - * or external. - * @note In case of group regular trigger source set to external trigger, - * to determine which peripheral is selected as external trigger, - * use function @ref LL_ADC_REG_GetTriggerSource(). - * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart - * @param ADCx ADC instance - * @retval Value "0" if trigger source external trigger - * Value "1" if trigger source SW start. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)); -} - -/** - * @brief Set ADC group regular conversion trigger polarity. - * @note Applicable only for trigger source set to external trigger. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge - * @param ADCx ADC instance - * @param ExternalTriggerEdge This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_EXT_RISING - * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING - * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge); -} - -/** - * @brief Get ADC group regular conversion trigger polarity. - * @note Applicable only for trigger source set to external trigger. - * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_TRIG_EXT_RISING - * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING - * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); -} - - -/** - * @brief Set ADC group regular sequencer scan direction. - * @note On some other PY32 families, this setting is not available and - * the default scan direction is forward. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection - * @param ADCx ADC instance - * @param ScanDirection This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD - * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection); -} - -/** - * @brief Get ADC group regular sequencer scan direction. - * @note On some other PY32 families, this setting is not available and - * the default scan direction is forward. - * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD - * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); -} - -/** - * @brief Set ADC group regular sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @note It is not possible to enable both ADC group regular - * continuous mode and sequencer discontinuous mode. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n - * @param ADCx ADC instance - * @param SeqDiscont This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont); -} - -/** - * @brief Get ADC group regular sequencer discontinuous mode: - * sequence subdivided and scan conversions interrupted every selected - * number of ranks. - * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE - * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); -} - -/** - * @brief Set ADC group regular sequence: channel on rank corresponding to - * channel number. - * @note This function performs: - * - Channels ordering into each rank of scan sequence: - * rank of each channel is fixed by channel HW number - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Set channels selected by overwriting the current sequencer - * configuration. - * @note On this PY32 serie, ADC group regular sequencer is - * not fully configurable: sequencer length and each rank - * affectation to a channel are fixed by channel HW number. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this PY32 serie, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note One or several values can be selected. - * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels - * @param ADCx ADC instance - * @param Channel This parameter can be a combination of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel) -{ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); -} - -/** - * @brief Add channel to ADC group regular sequence: channel on rank corresponding to - * channel number. - * @note This function performs: - * - Channels ordering into each rank of scan sequence: - * rank of each channel is fixed by channel HW number - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Set channels selected by adding them to the current sequencer - * configuration. - * @note On this PY32 serie, ADC group regular sequencer is - * not fully configurable: sequencer length and each rank - * affectation to a channel are fixed by channel HW number. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this PY32 serie, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note One or several values can be selected. - * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd - * @param ADCx ADC instance - * @param Channel This parameter can be a combination of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel) -{ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); -} - -/** - * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to - * channel number. - * @note This function performs: - * - Channels ordering into each rank of scan sequence: - * rank of each channel is fixed by channel HW number - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * - Set channels selected by removing them to the current sequencer - * configuration. - * @note On this PY32 serie, ADC group regular sequencer is - * not fully configurable: sequencer length and each rank - * affectation to a channel are fixed by channel HW number. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this PY32 serie, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note One or several values can be selected. - * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n - * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem - * @param ADCx ADC instance - * @param Channel This parameter can be a combination of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel) -{ - /* Parameter "Channel" is used with masks because containing */ - /* other bits reserved for other purpose. */ - CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); -} - -/** - * @brief Get ADC group regular sequence: channel on rank corresponding to - * channel number. - * @note This function performs: - * - Channels order reading into each rank of scan sequence: - * rank of each channel is fixed by channel HW number - * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). - * @note On this PY32 serie, ADC group regular sequencer is - * not fully configurable: sequencer length and each rank - * affectation to a channel are fixed by channel HW number. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @note On this PY32 serie, to measure internal channels (VrefInt, - * TempSensor, ...), measurement paths to internal channels must be - * enabled separately. - * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note One or several values can be retrieved. - * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) - * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n - * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels - * @param ADCx ADC instance - * @retval Returned value can be a combination of the following values: - * @arg @ref LL_ADC_CHANNEL_0 - * @arg @ref LL_ADC_CHANNEL_1 - * @arg @ref LL_ADC_CHANNEL_2 - * @arg @ref LL_ADC_CHANNEL_3 - * @arg @ref LL_ADC_CHANNEL_4 - * @arg @ref LL_ADC_CHANNEL_5 - * @arg @ref LL_ADC_CHANNEL_6 - * @arg @ref LL_ADC_CHANNEL_7 - * @arg @ref LL_ADC_CHANNEL_8 - * @arg @ref LL_ADC_CHANNEL_9 - * @arg @ref LL_ADC_CHANNEL_10 - * @arg @ref LL_ADC_CHANNEL_11 - * @arg @ref LL_ADC_CHANNEL_12 - * @arg @ref LL_ADC_CHANNEL_VREFINT - * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) -{ - register uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); - - return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) - | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) - ); - -} -/** - * @brief Set ADC continuous conversion mode on ADC group regular. - * @note Description of ADC continuous conversion mode: - * - single mode: one conversion per trigger - * - continuous mode: after the first trigger, following - * conversions launched successively automatically. - * @note It is not possible to enable both ADC group regular - * continuous mode and sequencer discontinuous mode. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode - * @param ADCx ADC instance - * @param Continuous This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_CONV_SINGLE - * @arg @ref LL_ADC_REG_CONV_CONTINUOUS - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous); -} - -/** - * @brief Get ADC continuous conversion mode on ADC group regular. - * @note Description of ADC continuous conversion mode: - * - single mode: one conversion per trigger - * - continuous mode: after the first trigger, following - * conversions launched successively automatically. - * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_CONV_SINGLE - * @arg @ref LL_ADC_REG_CONV_CONTINUOUS - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); -} - -#if (defined(DMA) || defined(DMA1)) -/** - * @brief Set ADC group regular conversion data transfer: no transfer or - * transfer by DMA, and DMA requests mode. - * @note If transfer by DMA selected, specifies the DMA requests - * mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note To configure DMA source address (peripheral address), - * use function @ref LL_ADC_DMA_GetRegAddr(). - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n - * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer - * @param ADCx ADC instance - * @param DMATransfer This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE - * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED - * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer); -} - -/** - * @brief Get ADC group regular conversion data transfer: no transfer or - * transfer by DMA, and DMA requests mode. - * @note If transfer by DMA selected, specifies the DMA requests - * mode: - * - Limited mode (One shot mode): DMA transfer requests are stopped - * when number of DMA data transfers (number of - * ADC conversions) is reached. - * This ADC mode is intended to be used with DMA mode non-circular. - * - Unlimited mode: DMA transfer requests are unlimited, - * whatever number of DMA data transfers (number of - * ADC conversions). - * This ADC mode is intended to be used with DMA mode circular. - * @note If ADC DMA requests mode is set to unlimited and DMA is set to - * mode non-circular: - * when DMA transfers size will be reached, DMA will stop transfers of - * ADC conversions data ADC will raise an overrun error - * (overrun flag and interruption if enabled). - * @note To configure DMA source address (peripheral address), - * use function @ref LL_ADC_DMA_GetRegAddr(). - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n - * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE - * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED - * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); -} -#endif - -/** - * @brief Set ADC group regular behavior in case of overrun: - * data preserved or overwritten. - * @note Compatibility with devices without feature overrun: - * other devices without this feature have a behavior - * equivalent to data overwritten. - * The default setting of overrun is data preserved. - * Therefore, for compatibility with all devices, parameter - * overrun should be set to data overwritten. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun - * @param ADCx ADC instance - * @param Overrun This parameter can be one of the following values: - * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED - * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) -{ - MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun); -} - -/** - * @brief Get ADC group regular behavior in case of overrun: - * data preserved or overwritten. - * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED - * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN - */ -__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog - * @{ - */ - -/** - * @brief Set ADC analog watchdog monitored channels: - * a single channel or all channels, - * on ADC group regular. - * @note Once monitored channels are selected, analog watchdog - * is enabled. - * @note In case of need to define a single channel to monitor - * with analog watchdog from sequencer channel definition, - * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). - * @note On this PY32 serie, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC group regular. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @rmtoll CFGR1 AWDCH LL_ADC_SetAnalogWDMonitChannels\n - * CFGR1 AWDSGL LL_ADC_SetAnalogWDMonitChannels\n - * CFGR1 AWDEN LL_ADC_SetAnalogWDMonitChannels - * @param ADCx ADC instance - * @param AWDChannelGroup This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - * @arg @ref LL_ADC_AWD_CH_VREFINT_REG - * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) -{ - MODIFY_REG(ADCx->CFGR1, - (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN), - (AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK)); -} - -/** - * @brief Get ADC analog watchdog monitored channel. - * @note Usage of the returned channel number: - * - To reinject this channel into another function LL_ADC_xxx: - * the returned channel number is only partly formatted on definition - * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared - * with parts of literals LL_ADC_CHANNEL_x or using - * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Then the selected literal LL_ADC_CHANNEL_x can be used - * as parameter for another function. - * - To get the channel number in decimal format: - * process the returned value with the helper macro - * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). - * Applicable only when the analog watchdog is set to monitor - * one channel. - * @note On this PY32 serie, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC group regular. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @note Depending on devices and packages, some channels may not be available. - * Refer to device datasheet for channels availability. - * @rmtoll CFGR1 AWDCH LL_ADC_GetAnalogWDMonitChannels\n - * CFGR1 AWDSGL LL_ADC_GetAnalogWDMonitChannels\n - * CFGR1 AWDEN LL_ADC_GetAnalogWDMonitChannels - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_AWD_DISABLE - * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG - * @arg @ref LL_ADC_AWD_CHANNEL_0_REG - * @arg @ref LL_ADC_AWD_CHANNEL_1_REG - * @arg @ref LL_ADC_AWD_CHANNEL_2_REG - * @arg @ref LL_ADC_AWD_CHANNEL_3_REG - * @arg @ref LL_ADC_AWD_CHANNEL_4_REG - * @arg @ref LL_ADC_AWD_CHANNEL_5_REG - * @arg @ref LL_ADC_AWD_CHANNEL_6_REG - * @arg @ref LL_ADC_AWD_CHANNEL_7_REG - * @arg @ref LL_ADC_AWD_CHANNEL_8_REG - * @arg @ref LL_ADC_AWD_CHANNEL_9_REG - * @arg @ref LL_ADC_AWD_CHANNEL_11_REG - * @arg @ref LL_ADC_AWD_CHANNEL_12_REG - */ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) -{ - register uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)); - - /* Note: Set variable according to channel definition including channel ID */ - /* with bitfield. */ - register uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS); - register uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)); - - return (AWDChannelGroup | (AWDChannelBitField * AWDChannelSingle)); -} - -/** - * @brief Set ADC analog watchdog thresholds value of both thresholds - * high and low. - * @note If value of only one threshold high or low must be set, - * use function @ref LL_ADC_SetAnalogWDThresholds(). - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this PY32 serie, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC group regular. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll TR HT LL_ADC_ConfigAnalogWDThresholds\n - * TR LT LL_ADC_ConfigAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF - * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue) -{ - MODIFY_REG(ADCx->TR,ADC_TR_HT | ADC_TR_LT,(AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) | AWDThresholdLowValue); -} - -/** - * @brief Set ADC analog watchdog threshold value of threshold - * high or low. - * @note If values of both thresholds high or low must be set, - * use function @ref LL_ADC_ConfigAnalogWDThresholds(). - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). - * @note On this PY32 serie, there is only 1 kind of analog watchdog - * instance: - * - AWD standard (instance AWD): - * - channels monitored: can monitor 1 channel or all channels. - * - groups monitored: ADC group regular. - * - resolution: resolution is not limited (corresponds to - * ADC resolution configured). - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be disabled or enabled without conversion on going - * on group regular. - * @rmtoll TR HT LL_ADC_SetAnalogWDThresholds\n - * TR LT LL_ADC_SetAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDThresholdsHighLow This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) -{ - /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */ - /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */ - /* high is selected, then data is shifted to LSB. Else(threshold low), */ - /* data is not shifted. */ - MODIFY_REG(ADCx->TR, AWDThresholdsHighLow,AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & 0x00000010U)); -} - -/** - * @brief Get ADC analog watchdog threshold value of threshold high, - * threshold low or raw data with ADC thresholds high and low - * concatenated. - * @note If raw data with ADC thresholds high and low is retrieved, - * the data of each threshold high or low can be isolated - * using helper macro: - * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). - * @note In case of ADC resolution different of 12 bits, - * analog watchdog thresholds data require a specific shift. - * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). - * @rmtoll TR HT LL_ADC_GetAnalogWDThresholds\n - * TR LT LL_ADC_GetAnalogWDThresholds - * @param ADCx ADC instance - * @param AWDThresholdsHighLow This parameter can be one of the following values: - * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH - * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF -*/ -__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) -{ - /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */ - /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */ - /* high is selected, then data is shifted to LSB. Else(threshold low or */ - /* both thresholds), data is not shifted. */ - return (uint32_t)(READ_BIT(ADCx->TR,(AWDThresholdsHighLow | ADC_TR_LT))>> ((~AWDThresholdsHighLow) & 0x00000010U)); -} - - -/** - * @brief Start ADC calibration in the mode single-ended - * or differential (for devices with differential mode available). - * @note On this PY32 serie, a minimum number of ADC clock cycles - * are required between ADC end of calibration and ADC enable. - * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. - * @note In case of usage of ADC with DMA transfer: - * On this PY32 serie, ADC DMA transfer request should be disabled - * during calibration: - * Calibration factor is available in data register - * and also transfered by DMA. - * To not insert ADC calibration factor among ADC conversion data - * in array variable, DMA transfer must be disabled during - * calibration. - * (DMA transfer setting backup and disable before calibration, - * DMA transfer setting restore after calibration. - * Refer to functions @ref LL_ADC_REG_GetDMATransfer(), - * @ref LL_ADC_REG_SetDMATransfer() ). - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR ADCAL LL_ADC_StartCalibration - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR,ADC_CR_BITS_PROPERTY_RS,ADC_CR_ADCAL); -} - -/** - * @brief Get ADC calibration state. - * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing - * @param ADCx ADC instance - * @retval 0: calibration complete, 1: calibration in progress. - */ -__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)); -} -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance - * @{ - */ - -/** - * @brief Enable the selected ADC instance. - * @note On this PY32 serie, after ADC enable, a delay for - * ADC internal analog stabilization is required before performing a - * ADC conversion start. - * Refer to device datasheet, parameter tSTAB. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be ADC disabled and ADC internal voltage regulator enabled. - * @rmtoll CR ADEN LL_ADC_Enable - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR,ADC_CR_BITS_PROPERTY_RS,ADC_CR_ADEN); -} - -/** - * @brief Reset the selected ADC instance. - * @note On this PY32 serie, Reset the ADC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_Reset(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function */ - - /* Force reset of ADC clock (core clock) */ - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1); - - /* Release reset of ADC clock (core clock) */ - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1); -} - -/** - * @brief Get the selected ADC instance enable state. - * (not only core clock: this ADC has a dual clock domain) - * @rmtoll CR ADEN LL_ADC_IsEnabled - * @param ADCx ADC instance - * @retval 0: ADC is disabled, 1: ADC is enabled. - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular - * @{ - */ - -/** - * @brief Start ADC group regular conversion. - * @note On this PY32 serie, this function is relevant for both - * internal trigger (SW start) and external trigger: - * - If ADC trigger has been set to software start, ADC conversion - * starts immediately. - * - If ADC trigger has been set to external trigger, ADC conversion - * will start at next trigger event (on the selected trigger edge) - * following the ADC start conversion command. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled without conversion on going on group regular, - * without conversion stop command on going on group regular, - * without ADC disable command on going. - * @rmtoll CR ADSTART LL_ADC_REG_StartConversion - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS,ADC_CR_ADSTART); -} - -/** - * @brief Stop ADC group regular conversion. - * @note On this PY32 serie, setting of this feature is conditioned to - * ADC state: - * ADC must be enabled with conversion on going on group regular, - * without ADC disable command on going. - * @rmtoll CR ADSTP LL_ADC_REG_StopConversion - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) -{ - /* Note: Write register with some additional bits forced to state reset */ - /* instead of modifying only the selected bit for this function, */ - /* to not interfere with bits with HW property "rs". */ - MODIFY_REG(ADCx->CR,ADC_CR_BITS_PROPERTY_RS,ADC_CR_ADSTP); -} - -/** - * @brief Get ADC group regular conversion state. - * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing - * @param ADCx ADC instance - * @retval 0: no conversion is on going on ADC group regular. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)); -} - -/** - * @brief Get ADC group regular command of conversion stop state - * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing - * @param ADCx ADC instance - * @retval 0: no command of conversion stop is on going on ADC group regular. - */ -__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * all ADC configurations: all ADC resolutions and - * all oversampling increased data width (for devices - * with feature oversampling). - * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 12 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x000 and Max_Data=0xFFF - */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 10 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x000 and Max_Data=0x3FF - */ -__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) -{ - return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 8 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) -{ - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Get ADC group regular conversion data, range fit for - * ADC resolution 6 bits. - * @note For devices with feature oversampling: Oversampling - * can increase data width, function for extended range - * may be needed: @ref LL_ADC_REG_ReadConversionData32. - * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6 - * @param ADCx ADC instance - * @retval Value between Min_Data=0x00 and Max_Data=0x3F - */ -__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) -{ - return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); -} - -/** - * @brief Disable the selected ADC instance. - * @note On this PY32 serie, Disable the selected ADC instance - * @param ADCx ADC instance - * @retval 0: ADC Disable Failed,1:ADC Disable Success. - */ -__STATIC_INLINE ErrorStatus LL_ADC_Disable(ADC_TypeDef *ADCx) -{ - ErrorStatus status = SUCCESS; - uint32_t tmpCFGR1=ADCx->CFGR1; - __IO uint32_t timeout_cpu_cycles = 0U; - - /* Check the parameters */ - /* Disable ADC instance if not already disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 1U) - { - /* Set ADC group regular trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - - /* Stop potential ADC conversion on going on ADC group regular. */ - if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U) - { - if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U) - { - LL_ADC_REG_StopConversion(ADCx); - } - } - else - { - (ADCx->CFGR1)|=(0x7<<6); - (ADCx->CFGR1)|=(0x3<<10); - __disable_irq(); - LL_ADC_REG_StartConversion(ADCx); - LL_ADC_REG_StopConversion(ADCx); - __enable_irq(); - } - - /* Wait for ADC conversions are effectively stopped */ - timeout_cpu_cycles =LL_ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; - while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U) - { - if(timeout_cpu_cycles-- == 0U) - { - /* Time-out error */ - status = ERROR; - } - } - - /* Wait for ADC instance is effectively disabled */ - timeout_cpu_cycles =LL_ADC_TIMEOUT_DISABLE_CPU_CYCLES; - while (LL_ADC_IsEnabled(ADCx) == 1U) - { - if(timeout_cpu_cycles-- == 0U) - { - /* Time-out error */ - status = ERROR; - } - } - - /* Restore the CFGR1 Configure */ - ADCx->CFGR1=tmpCFGR1; - } - - return status; -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management - * @{ - */ - -/** - * @brief Get flag ADC group regular end of unitary conversion. - * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)); -} - -/** - * @brief Get flag ADC group regular end of sequence conversions. - * @rmtoll ISR EOSEQ LL_ADC_IsActiveFlag_EOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); -} - -/** - * @brief Get flag ADC group regular overrun. - * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); -} - -/** - * @brief Get flag ADC group regular end of sampling phase. - * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)); -} - -/** - * @brief Get flag ADC analog watchdog 1 flag - * @rmtoll ISR AWD LL_ADC_IsActiveFlag_AWD - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD) == (LL_ADC_FLAG_AWD)); -} - -/** - * @brief Clear flag ADC group regular end of unitary conversion. - * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); -} - -/** - * @brief Clear flag ADC group regular end of sequence conversions. - * @rmtoll ISR EOSEQ LL_ADC_ClearFlag_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); -} - -/** - * @brief Clear flag ADC group regular overrun. - * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); -} - -/** - * @brief Clear flag ADC group regular end of sampling phase. - * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); -} - -/** - * @brief Clear flag ADC analog watchdog 1. - * @rmtoll ISR AWD LL_ADC_ClearFlag_AWD - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearFlag_AWD(ADC_TypeDef *ADCx) -{ - WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD); -} - -/** - * @} - */ - -/** @defgroup ADC_LL_EF_IT_Management ADC IT management - * @{ - */ -/** - * @brief Enable interruption ADC group regular end of unitary conversion. - * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_EOC); -} - -/** - * @brief Enable interruption ADC group regular end of sequence conversions. - * @rmtoll IER EOSEQIE LL_ADC_EnableIT_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_EOS); -} - -/** - * @brief Enable ADC group regular interruption overrun. - * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_OVR); -} - -/** - * @brief Enable interruption ADC group regular end of sampling. - * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); -} - -/** - * @brief Enable interruption ADC analog watchdog 1. - * @rmtoll IER AWDIE LL_ADC_EnableIT_AWD - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_EnableIT_AWD(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->IER, LL_ADC_IT_AWD); -} - -/** - * @brief Disable interruption ADC group regular end of unitary conversion. - * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); -} - -/** - * @brief Disable interruption ADC group regular end of sequence conversions. - * @rmtoll IER EOSEQIE LL_ADC_DisableIT_EOS - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); -} - -/** - * @brief Disable interruption ADC group regular overrun. - * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); -} - -/** - * @brief Disable interruption ADC group regular end of sampling. - * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); -} - -/** - * @brief Disable interruption ADC analog watchdog 1. - * @rmtoll IER AWDIE LL_ADC_DisableIT_AWD - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_DisableIT_AWD(ADC_TypeDef *ADCx) -{ - CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD); -} - -/** - * @brief Get state of interruption ADC group regular end of unitary conversion - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)); -} - -/** - * @brief Get state of interruption ADC group regular end of sequence conversions - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER EOSEQIE LL_ADC_IsEnabledIT_EOS - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); -} - -/** - * @brief Get state of interruption ADC group regular overrun - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); -} - -/** - * @brief Get state of interruption ADC group regular end of sampling - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)); -} - -/** - * @brief Get state of interruption ADC analog watchdog 1 - * (0: interrupt disabled, 1: interrupt enabled). - * @rmtoll IER AWDIE LL_ADC_IsEnabledIT_AWD - * @param ADCx ADC instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD(ADC_TypeDef *ADCx) -{ - return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD) == (LL_ADC_IT_AWD)); -} -/** - * @} - */ - -/** @defgroup ADC_LL_EF_Calibration_Management ADC Calibration management - * @{ - */ -/** - * @brief Set calibration sample time - * @note Unit: ADC clock cycles. - * @rmtoll CCSR CALSMP LL_ADC_SetCalSamplingTime - * @param ADCx ADC instance - * @param SamplingTime This parameter can be one of the following values: - * @arg @ref LL_ADC_CAL_SAMPLINGTIME_2CYCLES - * @arg @ref LL_ADC_CAL_SAMPLINGTIME_4CYCLES - * @arg @ref LL_ADC_CAL_SAMPLINGTIME_8CYCLES - * @arg @ref LL_ADC_CAL_SAMPLINGTIME_1CYCLE - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCalibrationSamplingTime(ADC_TypeDef *ADCx, uint32_t CalibrationSamplingTime) -{ - MODIFY_REG(ADCx->CCSR, ADC_CCSR_CALSMP, CalibrationSamplingTime); -} - -/** - * @brief Get sampling time common to a group of channels. - * @note Unit: ADC clock cycles. - * @rmtoll CCSR CALSMP LL_ADC_GetCalSamplingTime - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CAL_SAMPLINGTIME_2CYCLES - * @arg @ref LL_ADC_CAL_SAMPLINGTIME_4CYCLES - * @arg @ref LL_ADC_CAL_SAMPLINGTIME_8CYCLES - * @arg @ref LL_ADC_CAL_SAMPLINGTIME_1CYCLE - */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationSamplingTime(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CCSR, ADC_CCSR_CALSMP)); -} - -/** - * @brief Clear the calibration status - * @rmtoll CCSR CALFAIL LL_ADC_ClearCalibrationStatus - * @param ADCx ADC instance - * @retval None - */ -__STATIC_INLINE void LL_ADC_ClearCalibrationStatus(ADC_TypeDef *ADCx) -{ - SET_BIT(ADCx->CCSR, ADC_CCSR_CALFAIL); -} - -/** - * @brief Get the calibration status - * @rmtoll CCSR CALFAIL LL_ADC_GetCalibrationStatus - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CAL_STATUS_SUCCESS - * @arg @ref LL_ADC_CAL_STATUS_FAIL - * @arg @ref LL_ADC_CAL_STATUS_ONGOING - * @arg @ref LL_ADC_CAL_STATUS_INVALID - */ - -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CCSR, ADC_CCSR_CALFAIL)) | (uint32_t)(READ_BIT(ADCx->CCSR, ADC_CCSR_CALON)); -} - -/** - * @brief Set the calibration mode - * @rmtoll CCSR CALSEL LL_ADC_SetCalibrationMode - * @param ADCx ADC instance - * @param This parameter can be one of the following values: - @arg @ref LL_ADC_CAL_MODE_OFFSET - * @arg @ref LL_ADC_CAL_MODE_OFFSETANDLINEARITY - * @retval None - */ -__STATIC_INLINE void LL_ADC_SetCalibrationMode(ADC_TypeDef *ADCx,uint32_t CalibrationMode) -{ - MODIFY_REG(ADCx->CCSR,ADC_CCSR_CALSEL, CalibrationMode); -} - -/** - * @brief Get the calibration contents - * @rmtoll CCSR CALSEL LL_ADC_GetCalibrationMode - * @param ADCx ADC instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_ADC_CAL_MODE_OFFSET - * @arg @ref LL_ADC_CAL_MODE_OFFSETANDLINEARITY - */ -__STATIC_INLINE uint32_t LL_ADC_GetCalibrationMode(ADC_TypeDef *ADCx) -{ - return (uint32_t)(READ_BIT(ADCx->CCSR, ADC_CCSR_CALSEL)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -/* Initialization of some features of ADC common parameters and multimode */ -/* Note: On this PY32 serie, there is no ADC common initialization */ -/* function. */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); - -/* De-initialization of ADC instance */ -ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); - -/* Initialization of some features of ADC instance */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); - -/* Initialization of some features of ADC instance and ADC group regular */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ADC1 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PY32F0xx_LL_ADC_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_adc.h + * @author MCU Application Team + * @brief Header file of ADC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32F0XX_LL_ADC_H +#define __PY32F0XX_LL_ADC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" +#include "py32f0xx_ll_bus.h" +/** @addtogroup PY320xx_LL_Driver + * @{ + */ + +#if defined (ADC1) + +/** @defgroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup ADC_LL_Private_Constants ADC Private Constants + * @{ + */ + +/* Internal mask for ADC group regular trigger: */ +/* To select into literal LL_ADC_REG_TRIG_x the relevant bits for: */ +/* - regular trigger source */ +/* - regular trigger edge */ +#define ADC_REG_TRIG_EXT_EDGE_DEFAULT (ADC_CFGR1_EXTEN_0) /* Trigger edge set to rising edge (default setting for compatibility with some ADC on other PY32 families having this setting set by HW default value) */ + +/* Mask containing trigger source masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_SOURCE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTSEL) << (4U * 0U)) | \ + (( ADC_CFGR1_EXTSEL) << (4U * 1U)) | \ + (( ADC_CFGR1_EXTSEL) << (4U * 2U)) | \ + (( ADC_CFGR1_EXTSEL) << (4U * 3U)) ) + +/* Mask containing trigger edge masks for each of possible */ +/* trigger edge selection duplicated with shifts [0; 4; 8; 12] */ +/* corresponding to {SW start; ext trigger; ext trigger; ext trigger}. */ +#define ADC_REG_TRIG_EDGE_MASK (((LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN) << (4U * 0U)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 1U)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 2U)) | \ + ((ADC_REG_TRIG_EXT_EDGE_DEFAULT) << (4U * 3U)) ) + +/* Definition of ADC group regular trigger bits information. */ +#define ADC_REG_TRIG_EXTSEL_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTSEL) */ +#define ADC_REG_TRIG_EXTEN_BITOFFSET_POS (10U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_EXTEN) */ + + + +/* Internal mask for ADC channel: */ +/* To select into literal LL_ADC_CHANNEL_x the relevant bits for: */ +/* - channel identifier defined by number */ +/* - channel identifier defined by bitfield */ +/* - channel differentiation between external channels (connected to */ +/* GPIO pins) and internal channels (connected to internal paths) */ +#define ADC_CHANNEL_ID_NUMBER_MASK (ADC_CFGR1_AWDCH) +#define ADC_CHANNEL_ID_BITFIELD_MASK (ADC_CHSELR_CHSEL) +#define ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS (26U)/* Value equivalent to POSITION_VAL(ADC_CHANNEL_ID_NUMBER_MASK) */ +#define ADC_CHANNEL_ID_MASK (ADC_CHANNEL_ID_NUMBER_MASK | ADC_CHANNEL_ID_BITFIELD_MASK | ADC_CHANNEL_ID_INTERNAL_CH_MASK) +/* Equivalent mask of ADC_CHANNEL_NUMBER_MASK aligned on register LSB (bit 0) */ +#define ADC_CHANNEL_ID_NUMBER_MASK_POSBIT0 (0x0000001FU) /* Equivalent to shift: (ADC_CHANNEL_NUMBER_MASK >> POSITION_VAL(ADC_CHANNEL_NUMBER_MASK)) */ + +/* Channel differentiation between external and internal channels */ +#define ADC_CHANNEL_ID_INTERNAL_CH (0x80000000U) /* Marker of internal channel */ +#define ADC_CHANNEL_ID_INTERNAL_CH_MASK (ADC_CHANNEL_ID_INTERNAL_CH) + +/* Definition of channels ID number information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_NUMBER (0x00000000U) +#define ADC_CHANNEL_1_NUMBER ( ADC_CFGR1_AWDCH_0) +#define ADC_CHANNEL_2_NUMBER ( ADC_CFGR1_AWDCH_1 ) +#define ADC_CHANNEL_3_NUMBER ( ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) +#define ADC_CHANNEL_4_NUMBER ( ADC_CFGR1_AWDCH_2 ) +#define ADC_CHANNEL_5_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_0) +#define ADC_CHANNEL_6_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 ) +#define ADC_CHANNEL_7_NUMBER ( ADC_CFGR1_AWDCH_2 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) +#define ADC_CHANNEL_8_NUMBER (ADC_CFGR1_AWDCH_3 ) +#define ADC_CHANNEL_9_NUMBER (ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_0) +#define ADC_CHANNEL_11_NUMBER (ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_1 | ADC_CFGR1_AWDCH_0) +#define ADC_CHANNEL_12_NUMBER (ADC_CFGR1_AWDCH_3 | ADC_CFGR1_AWDCH_2 ) + +/* Definition of channels ID bitfield information to be inserted into */ +/* channels literals definition. */ +#define ADC_CHANNEL_0_BITFIELD (ADC_CHSELR_CHSEL0) +#define ADC_CHANNEL_1_BITFIELD (ADC_CHSELR_CHSEL1) +#define ADC_CHANNEL_2_BITFIELD (ADC_CHSELR_CHSEL2) +#define ADC_CHANNEL_3_BITFIELD (ADC_CHSELR_CHSEL3) +#define ADC_CHANNEL_4_BITFIELD (ADC_CHSELR_CHSEL4) +#define ADC_CHANNEL_5_BITFIELD (ADC_CHSELR_CHSEL5) +#define ADC_CHANNEL_6_BITFIELD (ADC_CHSELR_CHSEL6) +#define ADC_CHANNEL_7_BITFIELD (ADC_CHSELR_CHSEL7) +#define ADC_CHANNEL_8_BITFIELD (ADC_CHSELR_CHSEL8) +#define ADC_CHANNEL_9_BITFIELD (ADC_CHSELR_CHSEL9) +#define ADC_CHANNEL_11_BITFIELD (ADC_CHSELR_CHSEL11) +#define ADC_CHANNEL_12_BITFIELD (ADC_CHSELR_CHSEL12) + + +/* Internal mask for ADC analog watchdog: */ +/* To select into literals LL_ADC_AWD_CHANNELx_xxx the relevant bits for: */ +/* - analog watchdog 1: monitored channel defined by number, */ +/* selection of ADC group (ADC group regular). */ + +/* Internal register offset for ADC analog watchdog channel configuration */ +#define ADC_AWD_CR1_REGOFFSET (0x00000000U) + +#define ADC_AWD_CRX_REGOFFSET_MASK (ADC_AWD_CR1_REGOFFSET) + +#define ADC_AWD_CR1_CHANNEL_MASK (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) +#define ADC_AWD_CR_ALL_CHANNEL_MASK (ADC_AWD_CR1_CHANNEL_MASK) + +/* Internal register offset for ADC analog watchdog threshold configuration */ +#define ADC_AWD_TR1_REGOFFSET (ADC_AWD_CR1_REGOFFSET) +#define ADC_AWD_TRX_REGOFFSET_MASK (ADC_AWD_TR1_REGOFFSET) + + +/* ADC registers bits positions */ +#define ADC_CFGR1_RES_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_RESSEL) */ +#define ADC_CFGR1_AWDSGL_BITOFFSET_POS (22U) /* Value equivalent to POSITION_VAL(ADC_CFGR1_AWDSGL) */ +#define ADC_TR_HT_BITOFFSET_POS (16U) /* Value equivalent to POSITION_VAL(ADC_TR_HT) */ +#define ADC_CHSELR_CHSEL0_BITOFFSET_POS ( 0U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL0) */ +#define ADC_CHSELR_CHSEL1_BITOFFSET_POS ( 1U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL1) */ +#define ADC_CHSELR_CHSEL2_BITOFFSET_POS ( 2U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL2) */ +#define ADC_CHSELR_CHSEL3_BITOFFSET_POS ( 3U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL3) */ +#define ADC_CHSELR_CHSEL4_BITOFFSET_POS ( 4U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL4) */ +#define ADC_CHSELR_CHSEL5_BITOFFSET_POS ( 5U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL5) */ +#define ADC_CHSELR_CHSEL6_BITOFFSET_POS ( 6U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL6) */ +#define ADC_CHSELR_CHSEL7_BITOFFSET_POS ( 7U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL7) */ +#define ADC_CHSELR_CHSEL8_BITOFFSET_POS ( 8U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL8) */ +#define ADC_CHSELR_CHSEL9_BITOFFSET_POS ( 9U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL9) */ +#define ADC_CHSELR_CHSEL11_BITOFFSET_POS (11U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL11) */ +#define ADC_CHSELR_CHSEL12_BITOFFSET_POS (12U) /* Value equivalent to POSITION_VAL(ADC_CHSELR_CHSEL12) */ + + + +/* ADC registers bits groups */ +#define ADC_CR_BITS_PROPERTY_RS (ADC_CR_ADCAL | ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADEN) /* ADC register CR bits with HW property "rs": Software can read as well as set this bit. Writing '0' has no effect on the bit value. */ + + +/* ADC internal channels related definitions */ +/* Internal voltage reference VrefInt */ +#define VREFINT_CAL_VREF ( 1200U) /* Analog voltage reference (Vref+) value (tolerance: +-10 mV) (unit: mV). */ +/* Temperature sensor */ +#define TEMPSENSOR_CAL1_ADDR ((uint16_t*) (0x1fff0f14)) /* Internal temperature sensor, address of parameter TS_CAL1: On PY32F0, temperature sensor ADC raw data acquired at temperature 30 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL2_ADDR ((uint16_t*) (0x1fff0f18)) /* Internal temperature sensor, address of parameter TS_CAL2: On PY32F0, temperature sensor ADC raw data acquired at temperature 85 DegC (tolerance: +-5 DegC), Vref+ = 3.3 V (tolerance: +-10 mV). */ +#define TEMPSENSOR_CAL1_TEMP (( int32_t) 30) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL1_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL2_TEMP (( int32_t) 85) /* Internal temperature sensor, temperature at which temperature sensor has been calibrated in production for data into TEMPSENSOR_CAL2_ADDR (tolerance: +-5 DegC) (unit: DegC). */ +#define TEMPSENSOR_CAL_VREFANALOG ( 3300U) /* Analog voltage reference (Vref+) voltage with which temperature sensor has been calibrated in production (+-10 mV) (unit: mV). */ + +/* Definitions of ADC hardware constraints delays */ +/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* not timeout values: */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ +/* values definition. */ +/* Unit: CPU cycles. */ +#define LL_ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U) +#define LL_ADC_TIMEOUT_DISABLE_CPU_CYCLES (LL_ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) +#define LL_ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (LL_ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) + + +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_ES_INIT ADC Exported Init structure + * @{ + */ + +/** + * @brief Structure definition of some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all PY32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + */ +typedef struct +{ + uint32_t Clock; /*!< Set ADC instance clock source and prescaler. + This parameter can be a value of @ref ADC_LL_EC_CLOCK_SOURCE + @note On this PY32 serie, this parameter has some clock ratio constraints: + Note: In case of usage of the ADC dedicated HSI RC oscillator, it must be preliminarily enabled at RCC top level. + Note: This parameter can be modified only if the ADC is disabled + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetClock(). + For more details, refer to description of this function. */ + + uint32_t Resolution; /*!< Set ADC resolution. + This parameter can be a value of @ref ADC_LL_EC_RESOLUTION + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetResolution(). */ + + uint32_t DataAlignment; /*!< Set ADC conversion data alignment. + This parameter can be a value of @ref ADC_LL_EC_DATA_ALIGN + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetDataAlignment(). */ + + uint32_t LowPowerMode; /*!< Set ADC low power mode. + This parameter can be a value of @ref ADC_LL_EC_LP_MODE + + This feature can be modified afterwards using unitary function @ref LL_ADC_SetLowPowerMode(). */ + +} LL_ADC_InitTypeDef; + +/** + * @brief Structure definition of some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_REG_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all PY32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + */ +typedef struct +{ + uint32_t TriggerSource; /*!< Set ADC group regular conversion trigger source: internal (SW start) or from external IP (timer event). + This parameter can be a value of @ref ADC_LL_EC_REG_TRIGGER_SOURCE + @note On this PY32 serie, setting trigger source to external trigger also set trigger polarity to rising edge + (default setting for compatibility with some ADC on other PY32 families having this setting set by HW default value). + In case of need to modify trigger edge, use function @ref LL_ADC_REG_SetTriggerEdge(). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetTriggerSource(). */ + + uint32_t SequencerDiscont; /*!< Set ADC group regular sequencer discontinuous mode: sequence subdivided and scan conversions interrupted every selected number of ranks. + This parameter can be a value of @ref ADC_LL_EC_REG_SEQ_DISCONT_MODE + @note This parameter has an effect only if group regular sequencer is enabled + (several ADC channels enabled in group regular sequencer). + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetSequencerDiscont(). */ + + uint32_t ContinuousMode; /*!< Set ADC continuous conversion mode on ADC group regular, whether ADC conversions are performed in single mode (one conversion per trigger) or in continuous mode (after the first trigger, following conversions launched successively automatically). + This parameter can be a value of @ref ADC_LL_EC_REG_CONTINUOUS_MODE + Note: It is not possible to enable both ADC group regular continuous mode and discontinuous mode. + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetContinuousMode(). */ +#if (defined(DMA) || defined(DMA1)) + uint32_t DMATransfer; /*!< Set ADC group regular conversion data transfer: no transfer or transfer by DMA, and DMA requests mode. + This parameter can be a value of @ref ADC_LL_EC_REG_DMA_TRANSFER + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetDMATransfer(). */ +#endif + + uint32_t Overrun; /*!< Set ADC group regular behavior in case of overrun: + data preserved or overwritten. + This parameter can be a value of @ref ADC_LL_EC_REG_OVR_DATA_BEHAVIOR + + This feature can be modified afterwards using unitary function @ref LL_ADC_REG_SetOverrun(). */ + +} LL_ADC_REG_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Constants ADC Exported Constants + * @{ + */ + +/** @defgroup ADC_LL_EC_FLAG ADC flags + * @brief Flags defines which can be used with LL_ADC_ReadReg function + * @{ + */ + +#define LL_ADC_FLAG_EOC ADC_ISR_EOC /*!< ADC flag ADC group regular end of unitary conversion */ +#define LL_ADC_FLAG_EOS ADC_ISR_EOSEQ /*!< ADC flag ADC group regular end of sequence conversions */ +#define LL_ADC_FLAG_OVR ADC_ISR_OVR /*!< ADC flag ADC group regular overrun */ +#define LL_ADC_FLAG_EOSMP ADC_ISR_EOSMP /*!< ADC flag ADC group regular end of sampling phase */ +#define LL_ADC_FLAG_AWD ADC_ISR_AWD /*!< ADC flag ADC analog watchdog 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_IT ADC interruptions for configuration (interruption enable or disable) + * @brief IT defines which can be used with LL_ADC_ReadReg and LL_ADC_WriteReg functions + * @{ + */ + +#define LL_ADC_IT_EOC ADC_IER_EOCIE /*!< ADC interruption ADC group regular end of unitary conversion */ +#define LL_ADC_IT_EOS ADC_IER_EOSEQIE /*!< ADC interruption ADC group regular end of sequence conversions */ +#define LL_ADC_IT_OVR ADC_IER_OVRIE /*!< ADC interruption ADC group regular overrun */ +#define LL_ADC_IT_EOSMP ADC_IER_EOSMPIE /*!< ADC interruption ADC group regular end of sampling phase */ +#define LL_ADC_IT_AWD ADC_IER_AWDIE /*!< ADC interruption ADC analog watchdog 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REGISTERS ADC registers compliant with specific purpose + * @{ + */ +/* List of ADC registers intended to be used (most commonly) with */ +/* DMA transfer. */ +/* Refer to function @ref LL_ADC_DMA_GetRegAddr(). */ +#define LL_ADC_DMA_REG_REGULAR_DATA (0x00000000U) /* ADC group regular conversion data register (corresponding to register DR) to be used with ADC configured in independent mode. Without DMA transfer, register accessed by LL function @ref LL_ADC_REG_ReadConversionData32() and other functions @ref LL_ADC_REG_ReadConversionDatax() */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_COMMON_PATH_INTERNAL ADC common - Measurement path to internal channels + * @{ + */ +/* Note: Other measurement paths to internal channels may be available */ +/* (connections to other peripherals). */ +/* If they are not listed below, they do not require any specific */ +/* path enable. In this case, Access to measurement path is done */ +/* only by selecting the corresponding ADC internal channel. */ +#define LL_ADC_PATH_INTERNAL_NONE (0x00000000U) /*!< ADC measurement pathes all disabled */ +#define LL_ADC_PATH_INTERNAL_VREFINT (ADC_CCR_VREFEN) /*!< ADC measurement path to internal channel VrefInt */ +#define LL_ADC_PATH_INTERNAL_TEMPSENSOR (ADC_CCR_TSEN) /*!< ADC measurement path to internal channel temperature sensor */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CLOCK_SOURCE ADC instance - Clock source + * @{ + */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV1 (0x00000000U) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 1 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV2 (ADC_CFGR2_CKMODE_0 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 2 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV4 ( ADC_CFGR2_CKMODE_1 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 4 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV8 (ADC_CFGR2_CKMODE_0 | ADC_CFGR2_CKMODE_1 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 8 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV16 ( ADC_CFGR2_CKMODE_2 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 16 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV32 (ADC_CFGR2_CKMODE_0 | ADC_CFGR2_CKMODE_2 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 32 */ +#define LL_ADC_CLOCK_SYNC_PCLK_DIV64 ( ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_2 ) /*!< ADC synchronous clock derived from APB clock divided by a prescaler of 64 */ +#define LL_ADC_CLOCK_ASYNC_HSI_DIV1 ( ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 1 */ +#define LL_ADC_CLOCK_ASYNC_HSI_DIV2 (ADC_CFGR2_CKMODE_0 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 2 */ +#define LL_ADC_CLOCK_ASYNC_HSI_DIV4 ( ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 4 */ +#define LL_ADC_CLOCK_ASYNC_HSI_DIV8 (ADC_CFGR2_CKMODE_0 | ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 8 */ +#define LL_ADC_CLOCK_ASYNC_HSI_DIV16 ( ADC_CFGR2_CKMODE_2 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 16 */ +#define LL_ADC_CLOCK_ASYNC_HSI_DIV32 (ADC_CFGR2_CKMODE_0 | ADC_CFGR2_CKMODE_2 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 32 */ +#define LL_ADC_CLOCK_ASYNC_HSI_DIV64 ( ADC_CFGR2_CKMODE_1 | ADC_CFGR2_CKMODE_2 | ADC_CFGR2_CKMODE_3) /*!< ADC asynchronous clock derived from HSI clock divided by a prescaler of 64 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_RESOLUTION ADC instance - Resolution + * @{ + */ +#define LL_ADC_RESOLUTION_12B (0x00000000U) /*!< ADC resolution 12 bits */ +#define LL_ADC_RESOLUTION_10B (ADC_CFGR1_RESSEL_0) /*!< ADC resolution 10 bits */ +#define LL_ADC_RESOLUTION_8B (ADC_CFGR1_RESSEL_1) /*!< ADC resolution 8 bits */ +#define LL_ADC_RESOLUTION_6B (ADC_CFGR1_RESSEL_1 | ADC_CFGR1_RESSEL_0) /*!< ADC resolution 6 bits */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_DATA_ALIGN ADC instance - Data alignment + * @{ + */ +#define LL_ADC_DATA_ALIGN_RIGHT (0x00000000U) /*!< ADC conversion data alignment: right aligned (alignment on data register LSB bit 0)*/ +#define LL_ADC_DATA_ALIGN_LEFT (ADC_CFGR1_ALIGN) /*!< ADC conversion data alignment: left aligned (aligment on data register MSB bit 15)*/ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_LP_MODE ADC instance - Low power mode + * @{ + */ +#define LL_ADC_LP_MODE_NONE (0x00000000U) /*!< No ADC low power mode activated */ +#define LL_ADC_LP_AUTOWAIT (ADC_CFGR1_WAIT) /*!< ADC low power mode auto delay: Dynamic low power mode, ADC conversions are performed only when necessary (when previous ADC conversion data is read). See description with function @ref LL_ADC_SetLowPowerMode(). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_GROUPS ADC instance - Groups + * @{ + */ +#define LL_ADC_GROUP_REGULAR (0x00000001U) /*!< ADC group regular (available on all PY32 devices) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL ADC instance - Channel number + * @{ + */ +#define LL_ADC_CHANNEL_0 (ADC_CHANNEL_0_NUMBER | ADC_CHANNEL_0_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN0 */ +#define LL_ADC_CHANNEL_1 (ADC_CHANNEL_1_NUMBER | ADC_CHANNEL_1_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN1 */ +#define LL_ADC_CHANNEL_2 (ADC_CHANNEL_2_NUMBER | ADC_CHANNEL_2_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN2 */ +#define LL_ADC_CHANNEL_3 (ADC_CHANNEL_3_NUMBER | ADC_CHANNEL_3_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN3 */ +#define LL_ADC_CHANNEL_4 (ADC_CHANNEL_4_NUMBER | ADC_CHANNEL_4_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN4 */ +#define LL_ADC_CHANNEL_5 (ADC_CHANNEL_5_NUMBER | ADC_CHANNEL_5_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN5 */ +#define LL_ADC_CHANNEL_6 (ADC_CHANNEL_6_NUMBER | ADC_CHANNEL_6_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN6 */ +#define LL_ADC_CHANNEL_7 (ADC_CHANNEL_7_NUMBER | ADC_CHANNEL_7_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN7 */ +#define LL_ADC_CHANNEL_8 (ADC_CHANNEL_8_NUMBER | ADC_CHANNEL_8_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN8 */ +#define LL_ADC_CHANNEL_9 (ADC_CHANNEL_9_NUMBER | ADC_CHANNEL_9_BITFIELD ) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN9 */ +#define LL_ADC_CHANNEL_11 (ADC_CHANNEL_11_NUMBER | ADC_CHANNEL_11_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN11 */ +#define LL_ADC_CHANNEL_12 (ADC_CHANNEL_12_NUMBER | ADC_CHANNEL_12_BITFIELD) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN12 */ +#define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_12 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. */ +#define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_11 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_SOURCE ADC group regular - Trigger source + * @{ + */ +#define LL_ADC_REG_TRIG_SOFTWARE (0x00000000U) /*!< ADC group regular conversion trigger internal: SW start. */ +#define LL_ADC_REG_TRIG_EXT_TIM1_TRGO ( ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 TRGO. Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM1_CH4 ( ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM1 channel 4 event (capture compare: input capture or output capture). Trigger edge set to rising edge (default setting). */ +#define LL_ADC_REG_TRIG_EXT_TIM3_TRGO (ADC_CFGR1_EXTSEL_1 | ADC_CFGR1_EXTSEL_0 | ADC_REG_TRIG_EXT_EDGE_DEFAULT) /*!< ADC group regular conversion trigger from external IP: TIM3 TRGO. Trigger edge set to rising edge (default setting). */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_TRIGGER_EDGE ADC group regular - Trigger edge + * @{ + */ +#define LL_ADC_REG_TRIG_EXT_RISING ( ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to rising edge */ +#define LL_ADC_REG_TRIG_EXT_FALLING (ADC_CFGR1_EXTEN_1 ) /*!< ADC group regular conversion trigger polarity set to falling edge */ +#define LL_ADC_REG_TRIG_EXT_RISINGFALLING (ADC_CFGR1_EXTEN_1 | ADC_CFGR1_EXTEN_0) /*!< ADC group regular conversion trigger polarity set to both rising and falling edges */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_CONTINUOUS_MODE ADC group regular - Continuous mode +* @{ +*/ +#define LL_ADC_REG_CONV_SINGLE (0x00000000U) /*!< ADC conversions are performed in single mode: one conversion per trigger */ +#define LL_ADC_REG_CONV_CONTINUOUS (ADC_CFGR1_CONT) /*!< ADC conversions are performed in continuous mode: after the first trigger, following conversions launched successively automatically */ +/** + * @} + */ +#if (defined(DMA) || defined(DMA1)) +/** @defgroup ADC_LL_EC_REG_DMA_TRANSFER ADC group regular - DMA transfer of ADC conversion data + * @{ + */ +#define LL_ADC_REG_DMA_TRANSFER_NONE (0x00000000U) /*!< ADC conversions are not transferred by DMA */ +#define LL_ADC_REG_DMA_TRANSFER_LIMITED ( ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in limited mode (one shot mode): DMA transfer requests are stopped when number of DMA data transfers (number of ADC conversions) is reached. This ADC mode is intended to be used with DMA mode non-circular. */ +#define LL_ADC_REG_DMA_TRANSFER_UNLIMITED (ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN) /*!< ADC conversion data are transferred by DMA, in unlimited mode: DMA transfer requests are unlimited, whatever number of DMA data transferred (number of ADC conversions). This ADC mode is intended to be used with DMA mode circular. */ +/** + * @} + */ +#endif + +/** @defgroup ADC_LL_EC_REG_OVR_DATA_BEHAVIOR ADC group regular - Overrun behavior on conversion data +* @{ +*/ +#define LL_ADC_REG_OVR_DATA_PRESERVED (0x00000000U) /*!< ADC group regular behavior in case of overrun: data preserved */ +#define LL_ADC_REG_OVR_DATA_OVERWRITTEN (ADC_CFGR1_OVRMOD) /*!< ADC group regular behavior in case of overrun: data overwritten */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_SCAN_DIRECTION ADC group regular - Sequencer scan direction + * @{ + */ +#define LL_ADC_REG_SEQ_SCAN_DIR_FORWARD (0x00000000U) /*!< ADC group regular sequencer scan direction forward: from lowest channel number to highest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer). On some other PY32 families, this setting is not available and the default scan direction is forward. */ +#define LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD (ADC_CFGR1_SCANDIR) /*!< ADC group regular sequencer scan direction backward: from highest channel number to lowest channel number (scan of all ranks, ADC conversion of ranks with channels enabled in sequencer) */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_REG_SEQ_DISCONT_MODE ADC group regular - Sequencer discontinuous mode + * @{ + */ +#define LL_ADC_REG_SEQ_DISCONT_DISABLE (0x00000000U) /*!< ADC group regular sequencer discontinuous mode disable */ +#define LL_ADC_REG_SEQ_DISCONT_1RANK (ADC_CFGR1_DISCEN) /*!< ADC group regular sequencer discontinuous mode enable with sequence interruption every rank */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CHANNEL_SAMPLINGTIME Channel - Sampling time + * @{ + */ +#define LL_ADC_SAMPLINGTIME_3CYCLES_5 (0x00000000U) /*!< Sampling time 3.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_5CYCLES_5 ( ADC_SMPR_SMP_0) /*!< Sampling time 5.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_7CYCLES_5 ( ADC_SMPR_SMP_1 ) /*!< Sampling time 7.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_13CYCLES_5 ( ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 13.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_28CYCLES_5 (ADC_SMPR_SMP_2 ) /*!< Sampling time 28.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_41CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_0) /*!< Sampling time 41.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_71CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 ) /*!< Sampling time 71.5 ADC clock cycles */ +#define LL_ADC_SAMPLINGTIME_239CYCLES_5 (ADC_SMPR_SMP_2 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_0) /*!< Sampling time 239.5 ADC clock cycles */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_NUMBER Analog watchdog - Analog watchdog number + * @{ + */ +#define LL_ADC_AWD (ADC_AWD_CR1_CHANNEL_MASK | ADC_AWD_CR1_REGOFFSET) /*!< ADC analog watchdog number 1 */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_CHANNELS Analog watchdog - Monitored channels + * @{ + */ +#define LL_ADC_AWD_DISABLE (0x00000000U) /*!< ADC analog watchdog monitoring disabled */ +#define LL_ADC_AWD_ALL_CHANNELS_REG ( ADC_CFGR1_AWDEN ) /*!< ADC analog watchdog monitoring of all channels, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_0_REG ((LL_ADC_CHANNEL_0 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN0, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_1_REG ((LL_ADC_CHANNEL_1 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN1, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_2_REG ((LL_ADC_CHANNEL_2 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN2, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_3_REG ((LL_ADC_CHANNEL_3 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN3, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_4_REG ((LL_ADC_CHANNEL_4 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN4, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_5_REG ((LL_ADC_CHANNEL_5 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN5, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_6_REG ((LL_ADC_CHANNEL_6 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN6, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_7_REG ((LL_ADC_CHANNEL_7 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN7, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_8_REG ((LL_ADC_CHANNEL_8 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN8, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_9_REG ((LL_ADC_CHANNEL_9 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN9, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_11_REG ((LL_ADC_CHANNEL_11 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN11, converted by group regular only */ +#define LL_ADC_AWD_CHANNEL_12_REG ((LL_ADC_CHANNEL_12 & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC external channel (channel connected to GPIO pin) ADCx_IN12, converted by group regular only */ +#define LL_ADC_AWD_CH_VREFINT_REG ((LL_ADC_CHANNEL_VREFINT & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to VrefInt: Internal voltage reference, converted by group regular only */ +#define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_AWD_THRESHOLDS Analog watchdog - Thresholds + * @{ + */ +#define LL_ADC_AWD_THRESHOLD_HIGH (ADC_TR_HT ) /*!< ADC analog watchdog threshold high */ +#define LL_ADC_AWD_THRESHOLD_LOW ( ADC_TR_LT) /*!< ADC analog watchdog threshold low */ +#define LL_ADC_AWD_THRESHOLDS_HIGH_LOW (ADC_TR_HT | ADC_TR_LT) /*!< ADC analog watchdog both thresholds high and low concatenated into the same data */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CAL_SAMPLINGTIME Calibration - Sampling time + * @{ + */ +#define LL_ADC_CAL_SAMPLINGTIME_2CYCLES (0x00000000U) /*!< CAL Sampling time 2 ADC clock cycles */ +#define LL_ADC_CAL_SAMPLINGTIME_4CYCLES ( ADC_CCSR_CALSMP_0) /*!< CAL Sampling time 4 ADC clock cycles */ +#define LL_ADC_CAL_SAMPLINGTIME_8CYCLES (ADC_CCSR_CALSMP_1 ) /*!< CAL Sampling time 8 ADC clock cycles */ +#define LL_ADC_CAL_SAMPLINGTIME_1CYCLE (ADC_CCSR_CALSMP_1 | ADC_CCSR_CALSMP_0) /*!< CAL Sampling time 1 ADC clock cycle */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CAL_MODE Calibration - Mode + * @{ + */ +#define LL_ADC_CAL_MODE_OFFSET (0x00000000U) /*!< ADC calibration mode selection only OFFSET */ +#define LL_ADC_CAL_MODE_OFFSETANDLINEARITY ADC_CCSR_CALSEL /*!< ADC calibration mode selection OFFSET AND LINERARITY */ +/** + * @} + */ + +/** @defgroup ADC_LL_EC_CAL_STATUS Calibration - Status + * @{ + */ +#define LL_ADC_CAL_STATUS_SUCCESS (0x00000000U) /*!< ADC calibration status SUCCESS */ +#define LL_ADC_CAL_STATUS_FAIL ( ADC_CCSR_CALFAIL) /*!< ADC calibration status FAIL */ +#define LL_ADC_CAL_STATUS_ONGOING (ADC_CCSR_CALON ) /*!< ADC calibration status ONGOING */ +#define LL_ADC_CAL_STATUS_INVALID (ADC_CCSR_CALON | ADC_CCSR_CALFAIL) /*!< ADC calibration status INVALID */ + + +/** @defgroup ADC_LL_EC_HW_DELAYS Definitions of ADC hardware constraints delays + * @note Only ADC IP HW delays are defined in ADC LL driver driver, + * not timeout values. + * For details on delays values, refer to descriptions in source code + * above each literal definition. + * @{ + */ + +/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* not timeout values. */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Indications for estimation of ADC timeout delays, for this */ +/* PY32 serie: */ +/* - ADC calibration time: maximum delay is 64/fADC. */ +/* - ADC enable time: maximum delay is 8 ADC Clock Cycles. */ +/* - ADC disable time: maximum delay should be a few ADC clock cycles */ +/* - ADC stop conversion time: maximum delay should be a few ADC clock */ +/* cycles */ +/* - ADC conversion time: duration depending on ADC clock and ADC */ +/* configuration. */ +/* (refer to device reference manual, section "Timing") */ + + +/* Delay for internal voltage reference stabilization time. */ +/* Delay set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_VREFINT_STAB_US ( 10U) /*!< Delay for internal voltage reference stabilization time */ + +/* Delay for temperature sensor stabilization time. */ +/* Literal set to maximum value (refer to device datasheet, */ +/* parameter "tSTART"). */ +/* Unit: us */ +#define LL_ADC_DELAY_TEMPSENSOR_STAB_US ( 10U) /*!< Delay for temperature sensor stabilization time */ + +/* Delay required between ADC end of calibration and ADC enable. */ +/* Note: On this PY32 serie, a minimum number of ADC clock cycles */ +/* are required between ADC end of calibration and ADC enable. */ +/* Wait time can be computed in user application by waiting for the */ +/* equivalent number of CPU cycles, by taking into account */ +/* ratio of CPU clock versus ADC clock prescalers. */ +/* Unit: ADC clock cycles. */ +#define LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES ( 4U) /*!< Delay required between ADC end of calibration and ADC enable */ + + /* Delay between ADC end of calibration and ADC enable. */ + /* Delay estimation in CPU cycles: Case of ADC enable done */ + /* immediately after ADC calibration, ADC clock setting slow */ + /* (CPU clock / ADC clock) is above 64. */ +#define LL_ADC_DELAY_CALIB_ENABLE_CPU_CYCLES (LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES * 64) + + /* Timeout values for ADC Calibration. */ +#define LL_ADC_CALIBRATION_TIMEOUT_CPU_CYCLES ( 1000U) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Macros ADC Exported Macros + * @{ + */ + +/** @defgroup ADC_LL_EM_WRITE_READ Common write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_ADC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in ADC register + * @param __INSTANCE__ ADC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_ADC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup ADC_LL_EM_HELPER_MACRO ADC helper macro + * @{ + */ + +/** + * @brief Helper macro to get ADC channel number in decimal format + * from literals LL_ADC_CHANNEL_x. + * @note Example: + * __LL_ADC_CHANNEL_TO_DECIMAL_NB(LL_ADC_CHANNEL_4) + * will return decimal number "4". + * @note The input can be a value from functions where a channel + * number is returned, either defined with number + * or with bitfield (only one bit must be set). + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @retval Value between Min_Data=0 and Max_Data=12 + */ +#define __LL_ADC_CHANNEL_TO_DECIMAL_NB(__CHANNEL__) \ + ((((__CHANNEL__) & ADC_CHANNEL_ID_BITFIELD_MASK) == 0U) \ + ? ( \ + ((__CHANNEL__) & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS \ + ) \ + : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL0) == ADC_CHSELR_CHSEL0) ? (0U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL1) == ADC_CHSELR_CHSEL1) ? (1U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL2) == ADC_CHSELR_CHSEL2) ? (2U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL3) == ADC_CHSELR_CHSEL3) ? (3U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL4) == ADC_CHSELR_CHSEL4) ? (4U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL5) == ADC_CHSELR_CHSEL5) ? (5U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL6) == ADC_CHSELR_CHSEL6) ? (6U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL7) == ADC_CHSELR_CHSEL7) ? (7U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL8) == ADC_CHSELR_CHSEL8) ? (8U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL9) == ADC_CHSELR_CHSEL9) ? (9U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL11) == ADC_CHSELR_CHSEL11) ? (11U) : \ + ( \ + (((__CHANNEL__) & ADC_CHSELR_CHSEL12) == ADC_CHSELR_CHSEL12) ? (12U) : \ + (0U) \ + ) \ + ) \ + ) \ + ) \ + ) \ + ) \ + ) \ + ) \ + ) \ + ) \ + ) \ + ) \ + ) + +/** + * @brief Helper macro to get ADC channel in literal format LL_ADC_CHANNEL_x + * from number in decimal format. + * @note Example: + * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) + * will return a data equivalent to "LL_ADC_CHANNEL_4". + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=12 + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + */ +#define __LL_ADC_DECIMAL_NB_TO_CHANNEL(__DECIMAL_NB__) \ + ( \ + ((__DECIMAL_NB__) << ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS) | \ + (ADC_CHSELR_CHSEL0 << (__DECIMAL_NB__)) \ + ) + +/** + * @brief Helper macro to determine whether the selected channel + * corresponds to literal definitions of driver. + * @note The different literal definitions of ADC channels are: + * - ADC internal channel: + * LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ... + * - ADC external channel (channel connected to a GPIO pin): + * LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ... + * @note The channel parameter must be a value defined from literal + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...), + * must not be a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @retval Value "0" if the channel corresponds to a parameter definition of a ADC external channel (channel connected to a GPIO pin). + * Value "1" if the channel corresponds to a parameter definition of a ADC internal channel. + */ +#define __LL_ADC_IS_CHANNEL_INTERNAL(__CHANNEL__) \ + (((__CHANNEL__) & ADC_CHANNEL_ID_INTERNAL_CH_MASK) != 0U) + +/** + * @brief Helper macro to convert a channel defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * to its equivalent parameter definition of a ADC external channel + * (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...). + * @note The channel parameter can be, additionally to a value + * defined from parameter definition of a ADC internal channel + * (LL_ADC_CHANNEL_VREFINT, LL_ADC_CHANNEL_TEMPSENSOR, ...), + * a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is returned + * from ADC registers. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + */ +#define __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(__CHANNEL__) \ + ((__CHANNEL__) & ~ADC_CHANNEL_ID_INTERNAL_CH_MASK) + +/** + * @brief Helper macro to determine whether the internal channel + * selected is available on the ADC instance selected. + * @note The channel parameter must be a value defined from parameter + * definition of a ADC internal channel (LL_ADC_CHANNEL_VREFINT, + * LL_ADC_CHANNEL_TEMPSENSOR, ...), + * must not be a value defined from parameter definition of + * ADC external channel (LL_ADC_CHANNEL_1, LL_ADC_CHANNEL_2, ...) + * or a value from functions where a channel number is + * returned from ADC registers, + * because internal and external channels share the same channel + * number in ADC registers. The differentiation is made only with + * parameters definitions of driver. + * @param __ADC_INSTANCE__ ADC instance + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @retval Value "0" if the internal channel selected is not available on the ADC instance selected. + * Value "1" if the internal channel selected is available on the ADC instance selected. + */ + +#define __LL_ADC_IS_CHANNEL_INTERNAL_AVAILABLE(__ADC_INSTANCE__, __CHANNEL__) \ + ( \ + ((__CHANNEL__) == LL_ADC_CHANNEL_VREFINT) || \ + ((__CHANNEL__) == LL_ADC_CHANNEL_TEMPSENSOR) \ + ) + +/** + * @brief Helper macro to define ADC analog watchdog parameter: + * define a single channel to monitor with analog watchdog + * from sequencer channel and groups definition. + * @note To be used with function @ref LL_ADC_SetAnalogWDMonitChannels(). + * Example: + * LL_ADC_SetAnalogWDMonitChannels( + * ADC1, LL_ADC_AWD, + * __LL_ADC_ANALOGWD_CHANNEL_GROUP(LL_ADC_CHANNEL4, LL_ADC_GROUP_REGULAR)) + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_VREFINT (1) + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR (1) + * (1) For ADC channel read back from ADC register, + * comparison with internal channel parameter to be done + * using helper macro @ref __LL_ADC_CHANNEL_INTERNAL_TO_EXTERNAL(). + * @param __GROUP__ This parameter can be one of the following values: + * @arg @ref LL_ADC_GROUP_REGULAR + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG + */ +#define __LL_ADC_ANALOGWD_CHANNEL_GROUP(__CHANNEL__, __GROUP__)\ + (((__CHANNEL__) & ADC_CHANNEL_ID_MASK) | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL) + +/** + * @brief Helper macro to set the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_ConfigAnalogWDThresholds() + * or @ref LL_ADC_SetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to set the value of + * analog watchdog threshold high (on 8 bits): + * LL_ADC_SetAnalogWDThresholds + * (< ADCx param >, + * __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(LL_ADC_RESOLUTION_8B, ) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD__) \ + ((__AWD_THRESHOLD__) << ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the value of ADC analog watchdog threshold high + * or low in function of ADC resolution, when ADC resolution is + * different of 12 bits. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, with a ADC resolution of 8 bits, to get the value of + * analog watchdog threshold high (on 8 bits): + * < threshold_value_6_bits > = __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION + * (LL_ADC_RESOLUTION_8B, + * LL_ADC_GetAnalogWDThresholds(, LL_ADC_AWD_THRESHOLD_HIGH) + * ); + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __AWD_THRESHOLD_12_BITS__ Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(__ADC_RESOLUTION__, __AWD_THRESHOLD_12_BITS__) \ + ((__AWD_THRESHOLD_12_BITS__) >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U ))) + +/** + * @brief Helper macro to get the ADC analog watchdog threshold high + * or low from raw value containing both thresholds concatenated. + * @note To be used with function @ref LL_ADC_GetAnalogWDThresholds(). + * Example, to get analog watchdog threshold high from the register raw value: + * __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(LL_ADC_AWD_THRESHOLD_HIGH, ); + * @param __AWD_THRESHOLD_TYPE__ This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param __AWD_THRESHOLDS__ Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +#define __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(__AWD_THRESHOLD_TYPE__, __AWD_THRESHOLDS__) \ + (((__AWD_THRESHOLD_TYPE__) == LL_ADC_AWD_THRESHOLD_LOW) \ + ? ( \ + (__AWD_THRESHOLDS__) & LL_ADC_AWD_THRESHOLD_LOW \ + ) \ + : \ + ( \ + ((__AWD_THRESHOLDS__) >> ADC_TR_HT_BITOFFSET_POS) & LL_ADC_AWD_THRESHOLD_LOW \ + ) \ + ) + +/** + * @brief Helper macro to select the ADC common instance + * to which is belonging the selected ADC instance. + * @note ADC common register instance can be used for: + * - Set parameters common to several ADC instances + * - Multimode (for devices with several ADC instances) + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @param __ADCx__ ADC instance + * @retval ADC common register instance + */ +#define __LL_ADC_COMMON_INSTANCE(__ADCx__) \ + (ADC1_COMMON) + +/** + * @brief Helper macro to check if all ADC instances sharing the same + * ADC common instance are disabled. + * @note This check is required by functions with setting conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * Refer to functions having argument "ADCxy_COMMON" as parameter. + * @note On devices with only 1 ADC common instance, parameter of this macro + * is useless and can be ignored (parameter kept for compatibility + * with devices featuring several ADC common instances). + * @param __ADCXY_COMMON__ ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Value "0" if all ADC instances sharing the same ADC common instance + * are disabled. + * Value "1" if at least one ADC instance sharing the same ADC common instance + * is enabled. + */ +#define __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(__ADCXY_COMMON__) \ + LL_ADC_IsEnabled(ADC1) + +/** + * @brief Helper macro to define the ADC conversion data full-scale digital + * value corresponding to the selected ADC resolution. + * @note ADC conversion data full-scale corresponds to voltage range + * determined by analog voltage references Vref+ and Vref- + * (refer to reference manual). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__) \ + (0xFFFU >> ((__ADC_RESOLUTION__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) + +/** + * @brief Helper macro to convert the ADC conversion data from + * a resolution to another resolution. + * @param __DATA__ ADC conversion data to be converted + * @param __ADC_RESOLUTION_CURRENT__ Resolution of to the data to be converted + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @param __ADC_RESOLUTION_TARGET__ Resolution of the data after conversion + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data to the requested resolution + */ +#define __LL_ADC_CONVERT_DATA_RESOLUTION(__DATA__, __ADC_RESOLUTION_CURRENT__, __ADC_RESOLUTION_TARGET__) \ + (((__DATA__) \ + << ((__ADC_RESOLUTION_CURRENT__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U))) \ + >> ((__ADC_RESOLUTION_TARGET__) >> (ADC_CFGR1_RES_BITOFFSET_POS - 1U)) \ + ) + +/** + * @brief Helper macro to calculate the voltage (unit: mVolt) + * corresponding to a ADC conversion data (unit: digital value). + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) + * (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval ADC conversion data equivalent voltage value (unit: mVolt) + */ +#define __LL_ADC_CALC_DATA_TO_VOLTAGE(__VREFANALOG_VOLTAGE__,__ADC_DATA__,__ADC_RESOLUTION__) \ + ((__ADC_DATA__) * (__VREFANALOG_VOLTAGE__)/ __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) + +/** + * @brief Helper macro to calculate analog reference voltage (Vref+) + * (unit: mVolt) from ADC conversion data of internal voltage + * reference VrefInt. + * @note Computation is using VrefInt calibration value + * stored in system memory for each device during production. + * @note This voltage depends on user board environment: voltage level + * connected to pin Vref+. + * On devices with small package, the pin Vref+ is not present + * and internally bonded to pin Vdda. + * @note On this PY32 serie, calibration data of internal voltage reference + * VrefInt corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * internal voltage reference VrefInt. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) + * of internal voltage reference VrefInt (unit: digital value). + * @param __ADC_RESOLUTION__ This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Analog reference voltage (unit: mV) + */ +#define __LL_ADC_CALC_VREFANALOG_VOLTAGE(__VREFINT_ADC_DATA__,__ADC_RESOLUTION__) \ + (4095*( VREFINT_CAL_VREF)/ __LL_ADC_CONVERT_DATA_RESOLUTION((__VREFINT_ADC_DATA__),(__ADC_RESOLUTION__),LL_ADC_RESOLUTION_12B)) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor calibration values + * stored in system memory for each device during production. + * @note Calculation formula: + * Temperature = ((TS_ADC_DATA - TS_CAL1) + * * (TS_CAL2_TEMP - TS_CAL1_TEMP)) + * / (TS_CAL2 - TS_CAL1) + TS_CAL1_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * Avg_Slope = (TS_CAL2 - TS_CAL1) + * / (TS_CAL2_TEMP - TS_CAL1_TEMP) + * TS_CAL1 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL1 (calibrated in factory) + * TS_CAL2 = equivalent TS_ADC_DATA at temperature + * TEMP_DEGC_CAL2 (calibrated in factory) + * Caution: Calculation relevancy under reserve that calibration + * parameters are correct (address and data). + * To calculate temperature using temperature sensor + * datasheet typical values (generic values less, therefore + * less accurate than calibrated values), + * use helper macro @ref __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note On this PY32 serie, calibration data of temperature sensor + * corresponds to a resolution of 12 bits, + * this is the recommended ADC resolution to convert voltage of + * temperature sensor. + * Otherwise, this macro performs the processing to scale + * ADC conversion data to 12 bits. + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal + * temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature + * sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ +#define __LL_ADC_CALC_TEMPERATURE(__VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + (((( ((int32_t)((__LL_ADC_CONVERT_DATA_RESOLUTION((__TEMPSENSOR_ADC_DATA__), \ + (__ADC_RESOLUTION__), \ + LL_ADC_RESOLUTION_12B) \ + * (__VREFANALOG_VOLTAGE__)) \ + / TEMPSENSOR_CAL_VREFANALOG) \ + - (int32_t) *TEMPSENSOR_CAL1_ADDR) \ + ) * (int32_t)(TEMPSENSOR_CAL2_TEMP - TEMPSENSOR_CAL1_TEMP) \ + ) / (int32_t)((int32_t)*TEMPSENSOR_CAL2_ADDR - (int32_t)*TEMPSENSOR_CAL1_ADDR) \ + ) + TEMPSENSOR_CAL1_TEMP \ + ) + +/** + * @brief Helper macro to calculate the temperature (unit: degree Celsius) + * from ADC conversion data of internal temperature sensor. + * @note Computation is using temperature sensor typical values + * (refer to device datasheet). + * @note Calculation formula: + * Temperature = (TS_ADC_DATA * Conversion_uV-TS_TYP_CALx_VOLT(uV) ) + * / Avg_Slope + CALx_TEMP + * with TS_ADC_DATA = temperature sensor raw data measured by ADC + * (unit: digital value) + * Avg_Slope = temperature sensor slope + * (unit: uV/Degree Celsius) + * TS_TYP_CALx_VOLT = temperature sensor digital value at + * temperature CALx_TEMP (unit: mV) + * Caution: Calculation relevancy under reserve the temperature sensor + * of the current device has characteristics in line with + * datasheet typical values. + * If temperature sensor calibration values are available on + * on this device (presence of macro __LL_ADC_CALC_TEMPERATURE()), + * temperature calculation will be more accurate using + * helper macro @ref __LL_ADC_CALC_TEMPERATURE(). + * @note As calculation input, the analog reference voltage (Vref+) must be + * defined as it impacts the ADC LSB equivalent voltage. + * @note Analog reference voltage (Vref+) must be either known from + * user board environment or can be calculated using ADC measurement + * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). + * @note ADC measurement data must correspond to a resolution of 12bits + * (full scale digital value 4095). If not the case, the data must be + * preliminarily rescaled to an equivalent resolution of 12 bits. + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * On PY32F0, refer to device datasheet parameter "Avg_Slope". + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * On PY32F0, refer to device datasheet parameter "V30" (corresponding to TS_CAL1). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. + * This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval Temperature (unit: degree Celsius) + */ + +#define __LL_ADC_CALC_TEMPERATURE_TYP_PARAMS(__TEMPSENSOR_TYP_AVGSLOPE__,\ + __TEMPSENSOR_TYP_CALX_V__,\ + __TEMPSENSOR_CALX_TEMP__,\ + __VREFANALOG_VOLTAGE__,\ + __TEMPSENSOR_ADC_DATA__,\ + __ADC_RESOLUTION__) \ + (((( (int32_t)((((__TEMPSENSOR_ADC_DATA__) * (__VREFANALOG_VOLTAGE__)) \ + / __LL_ADC_DIGITAL_SCALE(__ADC_RESOLUTION__)) \ + * 1000)- (int32_t)(((__TEMPSENSOR_TYP_CALX_V__)) \ + * 1000))) / (__TEMPSENSOR_TYP_AVGSLOPE__) \ + ) + (__TEMPSENSOR_CALX_TEMP__) \ + ) + +#if (defined(DMA) || defined(DMA1)) +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup ADC_LL_Exported_Functions ADC Exported Functions + * @{ + */ + +/** @defgroup ADC_LL_EF_DMA_Management ADC DMA management + * @{ + */ +/* Note: LL ADC functions to set DMA transfer are located into sections of */ +/* configuration of ADC instance, groups and multimode (if available): */ +/* @ref LL_ADC_REG_SetDMATransfer(), ... */ + +/** + * @brief Function to help to configure DMA transfer from ADC: retrieve the + * ADC register address from ADC instance and a list of ADC registers + * intended to be used (most commonly) with DMA transfer. + * @note These ADC registers are data registers: + * when ADC conversion data is available in ADC data registers, + * ADC generates a DMA transfer request. + * @note This macro is intended to be used with LL DMA driver, refer to + * function "LL_DMA_ConfigAddresses()". + * Example: + * LL_DMA_ConfigAddresses(DMA1, + * LL_DMA_CHANNEL_1, + * LL_ADC_DMA_GetRegAddr(ADC1, LL_ADC_DMA_REG_REGULAR_DATA), + * (uint32_t)&< array or variable >, + * LL_DMA_DIRECTION_PERIPH_TO_MEMORY); + * @note For devices with several ADC: in multimode, some devices + * use a different data register outside of ADC instance scope + * (common data register). This macro manages this register difference, + * only ADC instance has to be set as parameter. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll DR DATA LL_ADC_DMA_GetRegAddr + * @param ADCx ADC instance + * @param Register This parameter can be one of the following values: + * @arg @ref LL_ADC_DMA_REG_REGULAR_DATA + * @retval ADC register address + */ +__STATIC_INLINE uint32_t LL_ADC_DMA_GetRegAddr(ADC_TypeDef *ADCx, uint32_t Register) +{ + /* Retrieve address of register DR */ + return (uint32_t)&(ADCx->DR); +} +#endif + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Common Configuration of ADC hierarchical scope: common to several ADC instances + * @{ + */ + +/** + * @brief Set parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @note Stabilization time of measurement path to internal channel: + * After enabling internal paths, before starting ADC conversion, + * a delay is required for internal voltage reference and + * temperature sensor stabilization time. + * Refer to device datasheet. + * Refer to literal @ref LL_ADC_DELAY_VREFINT_STAB_US. + * Refer to literal @ref LL_ADC_DELAY_TEMPSENSOR_STAB_US. + * @note ADC internal channel sampling time constraint: + * For ADC conversion of internal channels, + * a sampling time minimum value is required. + * Refer to device datasheet. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * All ADC instances of the ADC common group must be disabled. + * This check can be done with function @ref LL_ADC_IsEnabled() for each + * ADC instance or by using helper macro helper macro + * @ref __LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(). + * @rmtoll CCR VREFEN LL_ADC_SetCommonPathInternalCh\n + * CCR TSEN LL_ADC_SetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @param PathInternal This parameter can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON, uint32_t PathInternal) +{ + MODIFY_REG(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN, PathInternal); +} + +/** + * @brief Get parameter common to several ADC: measurement path to internal + * channels (VrefInt, temperature sensor, ...). + * @note One or several values can be selected. + * Example: (LL_ADC_PATH_INTERNAL_VREFINT | + * LL_ADC_PATH_INTERNAL_TEMPSENSOR) + * @rmtoll CCR VREFEN LL_ADC_GetCommonPathInternalCh\n + * CCR TSEN LL_ADC_GetCommonPathInternalCh + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_PATH_INTERNAL_NONE + * @arg @ref LL_ADC_PATH_INTERNAL_VREFINT + * @arg @ref LL_ADC_PATH_INTERNAL_TEMPSENSOR + */ +__STATIC_INLINE uint32_t LL_ADC_GetCommonPathInternalCh(ADC_Common_TypeDef *ADCxy_COMMON) +{ + return (uint32_t)(READ_BIT(ADCxy_COMMON->CCR, ADC_CCR_VREFEN | ADC_CCR_TSEN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Instance Configuration of ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Set ADC instance clock source and prescaler. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled. + * @rmtoll CFGR2 CKMODE LL_ADC_SetClock + * @param ADCx ADC instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV16 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV32 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV64 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV1 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV2 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV4 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV8 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV16 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV32 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV64 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetClock(ADC_TypeDef *ADCx, uint32_t ClockSource) +{ + MODIFY_REG(ADCx->CFGR2, ADC_CFGR2_CKMODE, ClockSource); +} + +/** + * @brief Get ADC instance clock source and prescaler. + * @rmtoll CFGR2 CKMODE LL_ADC_GetClock + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV1 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV2 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV4 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV8 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV16 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV32 + * @arg @ref LL_ADC_CLOCK_SYNC_PCLK_DIV64 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV1 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV2 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV4 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV8 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV16 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV32 + * @arg @ref LL_ADC_CLOCK_ASYNC_HSI_DIV64 + */ +__STATIC_INLINE uint32_t LL_ADC_GetClock(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE)); +} + +/** + * @brief Set ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 RES LL_ADC_SetResolution + * @param ADCx ADC instance + * @param Resolution This parameter can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetResolution(ADC_TypeDef *ADCx, uint32_t Resolution) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_RESSEL, Resolution); +} + +/** + * @brief Get ADC resolution. + * Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CFGR1 RES LL_ADC_GetResolution + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_RESOLUTION_12B + * @arg @ref LL_ADC_RESOLUTION_10B + * @arg @ref LL_ADC_RESOLUTION_8B + * @arg @ref LL_ADC_RESOLUTION_6B + */ +__STATIC_INLINE uint32_t LL_ADC_GetResolution(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_RESSEL)); +} + +/** + * @brief Set ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 ALIGN LL_ADC_SetDataAlignment + * @param ADCx ADC instance + * @param DataAlignment This parameter can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetDataAlignment(ADC_TypeDef *ADCx, uint32_t DataAlignment) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_ALIGN, DataAlignment); +} + +/** + * @brief Get ADC conversion data alignment. + * @note Refer to reference manual for alignments formats + * dependencies to ADC resolutions. + * @rmtoll CFGR1 ALIGN LL_ADC_GetDataAlignment + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_DATA_ALIGN_RIGHT + * @arg @ref LL_ADC_DATA_ALIGN_LEFT + */ +__STATIC_INLINE uint32_t LL_ADC_GetDataAlignment(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_ALIGN)); +} + +/** + * @brief Set ADC low power mode. + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - Do not use with interruption or DMA since these modes + * have to clear immediately the EOC flag to free the + * IRQ vector sequencer. + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data may be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CFGR1 WAIT LL_ADC_SetLowPowerMode + * @param ADCx ADC instance + * @param LowPowerMode This parameter can be one of the following values: + * @arg @ref LL_ADC_LP_MODE_NONE + * @arg @ref LL_ADC_LP_AUTOWAIT + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetLowPowerMode(ADC_TypeDef *ADCx, uint32_t LowPowerMode) +{ + MODIFY_REG(ADCx->CFGR1, (ADC_CFGR1_WAIT), LowPowerMode); +} + +/** + * @brief Get ADC low power mode: + * @note Description of ADC low power modes: + * - ADC low power mode "auto wait": Dynamic low power mode, + * ADC conversions occurrences are limited to the minimum necessary + * in order to reduce power consumption. + * New ADC conversion starts only when the previous + * unitary conversion data (for ADC group regular) + * has been retrieved by user software. + * In the meantime, ADC remains idle: does not performs any + * other conversion. + * This mode allows to automatically adapt the ADC conversions + * triggers to the speed of the software that reads the data. + * Moreover, this avoids risk of overrun for low frequency + * applications. + * How to use this low power mode: + * - Do not use with interruption or DMA since these modes + * have to clear immediately the EOC flag to free the + * IRQ vector sequencer. + * - Do use with polling: 1. Start conversion, + * 2. Later on, when conversion data is needed: poll for end of + * conversion to ensure that conversion is completed and + * retrieve ADC conversion data. This will trig another + * ADC conversion start. + * This feature can be combined with low power mode "auto wait". + * @note With ADC low power mode "auto wait", the ADC conversion data read + * is corresponding to previous ADC conversion start, independently + * of delay during which ADC was idle. + * Therefore, the ADC conversion data may be outdated: does not + * correspond to the current voltage level on the selected + * ADC channel. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CFGR1 WAIT LL_ADC_GetLowPowerMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_LP_MODE_NONE + * @arg @ref LL_ADC_LP_AUTOWAIT + */ +__STATIC_INLINE uint32_t LL_ADC_GetLowPowerMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, (ADC_CFGR1_WAIT ))); +} + +/** + * @brief Set sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @note On this PY32 serie, sampling time scope is on ADC instance: + * Sampling time common to all channels. + * (on some other PY32 families, sampling time is channel wise) + * @note In case of internal channel (VrefInt, TempSensor, ...) to be + * converted: + * sampling time constraints must be respected (sampling time can be + * adjusted in function of ADC clock frequency and sampling time + * setting). + * Refer to device datasheet for timings values (parameters TS_vrefint, + * TS_temp, ...). + * @note Conversion time is the addition of sampling time and processing time. + * On this PY32 serie, ADC processing time is: + * - 12.5 ADC clock cycles at ADC resolution 12 bits + * - 10.5 ADC clock cycles at ADC resolution 10 bits + * - 8.5 ADC clock cycles at ADC resolution 8 bits + * - 6.5 ADC clock cycles at ADC resolution 6 bits + * @note In case of ADC conversion of internal channel (VrefInt, + * temperature sensor, ...), a sampling time minimum value + * is required. + * Refer to device datasheet. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll SMPR SMP LL_ADC_SetSamplingTimeCommonChannels + * @param ADCx ADC instance + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetSamplingTimeCommonChannels(ADC_TypeDef *ADCx, uint32_t SamplingTime) +{ + MODIFY_REG(ADCx->SMPR, ADC_SMPR_SMP, SamplingTime); +} + +/** + * @brief Get sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @note On this PY32 serie, sampling time scope is on ADC instance: + * Sampling time common to all channels. + * (on some other PY32 families, sampling time is channel wise) + * @note Conversion time is the addition of sampling time and processing time. + * Refer to reference manual for ADC processing time of + * this PY32 serie. + * @rmtoll SMPR SMP LL_ADC_GetSamplingTimeCommonChannels + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_SAMPLINGTIME_3CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_5CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_7CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_13CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_28CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_41CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_71CYCLES_5 + * @arg @ref LL_ADC_SAMPLINGTIME_239CYCLES_5 + */ +__STATIC_INLINE uint32_t LL_ADC_GetSamplingTimeCommonChannels(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->SMPR, ADC_SMPR_SMP)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_Group_Regular Configuration of ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Set ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note On this PY32 serie, setting trigger source to external trigger + * also set trigger polarity to rising edge + * (default setting for compatibility with some ADC on other + * PY32 families having this setting set by HW default value). + * In case of need to modify trigger edge, use + * function @ref LL_ADC_REG_SetTriggerEdge(). + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 EXTSEL LL_ADC_REG_SetTriggerSource\n + * CFGR1 EXTEN LL_ADC_REG_SetTriggerSource + * @param ADCx ADC instance + * @param TriggerSource This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerSource(ADC_TypeDef *ADCx, uint32_t TriggerSource) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL, TriggerSource); +} + +/** + * @brief Get ADC group regular conversion trigger source: + * internal (SW start) or from external IP (timer event, + * external interrupt line). + * @note To determine whether group regular trigger source is + * internal (SW start) or external, without detail + * of which peripheral is selected as external trigger, + * (equivalent to + * "if(LL_ADC_REG_GetTriggerSource(ADC1) == LL_ADC_REG_TRIG_SOFTWARE)") + * use function @ref LL_ADC_REG_IsTriggerSourceSWStart. + * @note Availability of parameters of trigger sources from timer + * depends on timers availability on the selected device. + * @rmtoll CFGR1 EXTSEL LL_ADC_REG_GetTriggerSource\n + * CFGR1 EXTEN LL_ADC_REG_GetTriggerSource + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_SOFTWARE + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_TRGO + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM1_CH4 + * @arg @ref LL_ADC_REG_TRIG_EXT_TIM3_TRGO + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerSource(ADC_TypeDef *ADCx) +{ + register uint32_t TriggerSource = READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTSEL | ADC_CFGR1_EXTEN); + + /* Value for shift of {0; 4; 8; 12} depending on value of bitfield */ + /* corresponding to ADC_CFGR1_EXTEN {0; 1; 2; 3}. */ + register uint32_t ShiftExten = ((TriggerSource & ADC_CFGR1_EXTEN) >> (ADC_REG_TRIG_EXTEN_BITOFFSET_POS - 2U)); + + /* Set bitfield corresponding to ADC_CFGR1_EXTEN and ADC_CFGR1_EXTSEL */ + /* to match with triggers literals definition. */ + return ((TriggerSource + & (ADC_REG_TRIG_SOURCE_MASK >> ShiftExten) & ADC_CFGR1_EXTSEL) + | ((ADC_REG_TRIG_EDGE_MASK >> ShiftExten) & ADC_CFGR1_EXTEN) + ); +} + +/** + * @brief Get ADC group regular conversion trigger source internal (SW start) + * or external. + * @note In case of group regular trigger source set to external trigger, + * to determine which peripheral is selected as external trigger, + * use function @ref LL_ADC_REG_GetTriggerSource(). + * @rmtoll CFGR1 EXTEN LL_ADC_REG_IsTriggerSourceSWStart + * @param ADCx ADC instance + * @retval Value "0" if trigger source external trigger + * Value "1" if trigger source SW start. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsTriggerSourceSWStart(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN) == (LL_ADC_REG_TRIG_SOFTWARE & ADC_CFGR1_EXTEN)); +} + +/** + * @brief Set ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 EXTEN LL_ADC_REG_SetTriggerEdge + * @param ADCx ADC instance + * @param ExternalTriggerEdge This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetTriggerEdge(ADC_TypeDef *ADCx, uint32_t ExternalTriggerEdge) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_EXTEN, ExternalTriggerEdge); +} + +/** + * @brief Get ADC group regular conversion trigger polarity. + * @note Applicable only for trigger source set to external trigger. + * @rmtoll CFGR1 EXTEN LL_ADC_REG_GetTriggerEdge + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_TRIG_EXT_RISING + * @arg @ref LL_ADC_REG_TRIG_EXT_FALLING + * @arg @ref LL_ADC_REG_TRIG_EXT_RISINGFALLING + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetTriggerEdge(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_EXTEN)); +} + + +/** + * @brief Set ADC group regular sequencer scan direction. + * @note On some other PY32 families, this setting is not available and + * the default scan direction is forward. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 SCANDIR LL_ADC_REG_SetSequencerScanDirection + * @param ADCx ADC instance + * @param ScanDirection This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerScanDirection(ADC_TypeDef *ADCx, uint32_t ScanDirection) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_SCANDIR, ScanDirection); +} + +/** + * @brief Get ADC group regular sequencer scan direction. + * @note On some other PY32 families, this setting is not available and + * the default scan direction is forward. + * @rmtoll CFGR1 SCANDIR LL_ADC_REG_GetSequencerScanDirection + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_FORWARD + * @arg @ref LL_ADC_REG_SEQ_SCAN_DIR_BACKWARD + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerScanDirection(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_SCANDIR)); +} + +/** + * @brief Set ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 DISCEN LL_ADC_REG_SetSequencerDiscont\n + * @param ADCx ADC instance + * @param SeqDiscont This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerDiscont(ADC_TypeDef *ADCx, uint32_t SeqDiscont) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DISCEN, SeqDiscont); +} + +/** + * @brief Get ADC group regular sequencer discontinuous mode: + * sequence subdivided and scan conversions interrupted every selected + * number of ranks. + * @rmtoll CFGR1 DISCEN LL_ADC_REG_GetSequencerDiscont\n + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_SEQ_DISCONT_DISABLE + * @arg @ref LL_ADC_REG_SEQ_DISCONT_1RANK + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerDiscont(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DISCEN)); +} + +/** + * @brief Set ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by overwriting the current sequencer + * configuration. + * @note On this PY32 serie, ADC group regular sequencer is + * not fully configurable: sequencer length and each rank + * affectation to a channel are fixed by channel HW number. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this PY32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChannels + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChannels(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + WRITE_REG(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Add channel to ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by adding them to the current sequencer + * configuration. + * @note On this PY32 serie, ADC group regular sequencer is + * not fully configurable: sequencer length and each rank + * affectation to a channel are fixed by channel HW number. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this PY32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChAdd\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChAdd + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChAdd(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + SET_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Remove channel to ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels ordering into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * - Set channels selected by removing them to the current sequencer + * configuration. + * @note On this PY32 serie, ADC group regular sequencer is + * not fully configurable: sequencer length and each rank + * affectation to a channel are fixed by channel HW number. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this PY32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be selected. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL1 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL2 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL3 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL4 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL5 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL6 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL7 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL8 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL9 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL11 LL_ADC_REG_SetSequencerChRem\n + * CHSELR CHSEL12 LL_ADC_REG_SetSequencerChRem + * @param ADCx ADC instance + * @param Channel This parameter can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetSequencerChRem(ADC_TypeDef *ADCx, uint32_t Channel) +{ + /* Parameter "Channel" is used with masks because containing */ + /* other bits reserved for other purpose. */ + CLEAR_BIT(ADCx->CHSELR, (Channel & ADC_CHANNEL_ID_BITFIELD_MASK)); +} + +/** + * @brief Get ADC group regular sequence: channel on rank corresponding to + * channel number. + * @note This function performs: + * - Channels order reading into each rank of scan sequence: + * rank of each channel is fixed by channel HW number + * (channel 0 fixed on rank 0, channel 1 fixed on rank1, ...). + * @note On this PY32 serie, ADC group regular sequencer is + * not fully configurable: sequencer length and each rank + * affectation to a channel are fixed by channel HW number. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @note On this PY32 serie, to measure internal channels (VrefInt, + * TempSensor, ...), measurement paths to internal channels must be + * enabled separately. + * This can be done using function @ref LL_ADC_SetCommonPathInternalCh(). + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note One or several values can be retrieved. + * Example: (LL_ADC_CHANNEL_4 | LL_ADC_CHANNEL_12 | ...) + * @rmtoll CHSELR CHSEL0 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL1 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL2 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL3 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL4 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL5 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL6 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL7 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL8 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL9 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL11 LL_ADC_REG_GetSequencerChannels\n + * CHSELR CHSEL12 LL_ADC_REG_GetSequencerChannels + * @param ADCx ADC instance + * @retval Returned value can be a combination of the following values: + * @arg @ref LL_ADC_CHANNEL_0 + * @arg @ref LL_ADC_CHANNEL_1 + * @arg @ref LL_ADC_CHANNEL_2 + * @arg @ref LL_ADC_CHANNEL_3 + * @arg @ref LL_ADC_CHANNEL_4 + * @arg @ref LL_ADC_CHANNEL_5 + * @arg @ref LL_ADC_CHANNEL_6 + * @arg @ref LL_ADC_CHANNEL_7 + * @arg @ref LL_ADC_CHANNEL_8 + * @arg @ref LL_ADC_CHANNEL_9 + * @arg @ref LL_ADC_CHANNEL_10 + * @arg @ref LL_ADC_CHANNEL_11 + * @arg @ref LL_ADC_CHANNEL_12 + * @arg @ref LL_ADC_CHANNEL_VREFINT + * @arg @ref LL_ADC_CHANNEL_TEMPSENSOR + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetSequencerChannels(ADC_TypeDef *ADCx) +{ + register uint32_t ChannelsBitfield = READ_BIT(ADCx->CHSELR, ADC_CHSELR_CHSEL); + + return ( (((ChannelsBitfield & ADC_CHSELR_CHSEL0) >> ADC_CHSELR_CHSEL0_BITOFFSET_POS) * LL_ADC_CHANNEL_0) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL1) >> ADC_CHSELR_CHSEL1_BITOFFSET_POS) * LL_ADC_CHANNEL_1) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL2) >> ADC_CHSELR_CHSEL2_BITOFFSET_POS) * LL_ADC_CHANNEL_2) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL3) >> ADC_CHSELR_CHSEL3_BITOFFSET_POS) * LL_ADC_CHANNEL_3) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL4) >> ADC_CHSELR_CHSEL4_BITOFFSET_POS) * LL_ADC_CHANNEL_4) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL5) >> ADC_CHSELR_CHSEL5_BITOFFSET_POS) * LL_ADC_CHANNEL_5) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL6) >> ADC_CHSELR_CHSEL6_BITOFFSET_POS) * LL_ADC_CHANNEL_6) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL7) >> ADC_CHSELR_CHSEL7_BITOFFSET_POS) * LL_ADC_CHANNEL_7) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL8) >> ADC_CHSELR_CHSEL8_BITOFFSET_POS) * LL_ADC_CHANNEL_8) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL9) >> ADC_CHSELR_CHSEL9_BITOFFSET_POS) * LL_ADC_CHANNEL_9) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL11) >> ADC_CHSELR_CHSEL11_BITOFFSET_POS) * LL_ADC_CHANNEL_11) + | (((ChannelsBitfield & ADC_CHSELR_CHSEL12) >> ADC_CHSELR_CHSEL12_BITOFFSET_POS) * LL_ADC_CHANNEL_12) + ); + +} +/** + * @brief Set ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @note It is not possible to enable both ADC group regular + * continuous mode and sequencer discontinuous mode. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 CONT LL_ADC_REG_SetContinuousMode + * @param ADCx ADC instance + * @param Continuous This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetContinuousMode(ADC_TypeDef *ADCx, uint32_t Continuous) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_CONT, Continuous); +} + +/** + * @brief Get ADC continuous conversion mode on ADC group regular. + * @note Description of ADC continuous conversion mode: + * - single mode: one conversion per trigger + * - continuous mode: after the first trigger, following + * conversions launched successively automatically. + * @rmtoll CFGR1 CONT LL_ADC_REG_GetContinuousMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_CONV_SINGLE + * @arg @ref LL_ADC_REG_CONV_CONTINUOUS + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetContinuousMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_CONT)); +} + +#if (defined(DMA) || defined(DMA1)) +/** + * @brief Set ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CFGR1 DMAEN LL_ADC_REG_SetDMATransfer\n + * CFGR1 DMACFG LL_ADC_REG_SetDMATransfer + * @param ADCx ADC instance + * @param DMATransfer This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetDMATransfer(ADC_TypeDef *ADCx, uint32_t DMATransfer) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG, DMATransfer); +} + +/** + * @brief Get ADC group regular conversion data transfer: no transfer or + * transfer by DMA, and DMA requests mode. + * @note If transfer by DMA selected, specifies the DMA requests + * mode: + * - Limited mode (One shot mode): DMA transfer requests are stopped + * when number of DMA data transfers (number of + * ADC conversions) is reached. + * This ADC mode is intended to be used with DMA mode non-circular. + * - Unlimited mode: DMA transfer requests are unlimited, + * whatever number of DMA data transfers (number of + * ADC conversions). + * This ADC mode is intended to be used with DMA mode circular. + * @note If ADC DMA requests mode is set to unlimited and DMA is set to + * mode non-circular: + * when DMA transfers size will be reached, DMA will stop transfers of + * ADC conversions data ADC will raise an overrun error + * (overrun flag and interruption if enabled). + * @note To configure DMA source address (peripheral address), + * use function @ref LL_ADC_DMA_GetRegAddr(). + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CFGR1 DMAEN LL_ADC_REG_GetDMATransfer\n + * CFGR1 DMACFG LL_ADC_REG_GetDMATransfer + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_DMA_TRANSFER_NONE + * @arg @ref LL_ADC_REG_DMA_TRANSFER_LIMITED + * @arg @ref LL_ADC_REG_DMA_TRANSFER_UNLIMITED + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetDMATransfer(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_DMAEN | ADC_CFGR1_DMACFG)); +} +#endif + +/** + * @brief Set ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @note Compatibility with devices without feature overrun: + * other devices without this feature have a behavior + * equivalent to data overwritten. + * The default setting of overrun is data preserved. + * Therefore, for compatibility with all devices, parameter + * overrun should be set to data overwritten. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll CFGR1 OVRMOD LL_ADC_REG_SetOverrun + * @param ADCx ADC instance + * @param Overrun This parameter can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_SetOverrun(ADC_TypeDef *ADCx, uint32_t Overrun) +{ + MODIFY_REG(ADCx->CFGR1, ADC_CFGR1_OVRMOD, Overrun); +} + +/** + * @brief Get ADC group regular behavior in case of overrun: + * data preserved or overwritten. + * @rmtoll CFGR1 OVRMOD LL_ADC_REG_GetOverrun + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_REG_OVR_DATA_PRESERVED + * @arg @ref LL_ADC_REG_OVR_DATA_OVERWRITTEN + */ +__STATIC_INLINE uint32_t LL_ADC_REG_GetOverrun(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CFGR1, ADC_CFGR1_OVRMOD)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Configuration_ADC_AnalogWatchdog Configuration of ADC transversal scope: analog watchdog + * @{ + */ + +/** + * @brief Set ADC analog watchdog monitored channels: + * a single channel or all channels, + * on ADC group regular. + * @note Once monitored channels are selected, analog watchdog + * is enabled. + * @note In case of need to define a single channel to monitor + * with analog watchdog from sequencer channel definition, + * use helper macro @ref __LL_ADC_ANALOGWD_CHANNEL_GROUP(). + * @note On this PY32 serie, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @rmtoll CFGR1 AWDCH LL_ADC_SetAnalogWDMonitChannels\n + * CFGR1 AWDSGL LL_ADC_SetAnalogWDMonitChannels\n + * CFGR1 AWDEN LL_ADC_SetAnalogWDMonitChannels + * @param ADCx ADC instance + * @param AWDChannelGroup This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + * @arg @ref LL_ADC_AWD_CH_VREFINT_REG + * @arg @ref LL_ADC_AWD_CH_TEMPSENSOR_REG + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDMonitChannels(ADC_TypeDef *ADCx, uint32_t AWDChannelGroup) +{ + MODIFY_REG(ADCx->CFGR1, + (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN), + (AWDChannelGroup & ADC_AWD_CR_ALL_CHANNEL_MASK)); +} + +/** + * @brief Get ADC analog watchdog monitored channel. + * @note Usage of the returned channel number: + * - To reinject this channel into another function LL_ADC_xxx: + * the returned channel number is only partly formatted on definition + * of literals LL_ADC_CHANNEL_x. Therefore, it has to be compared + * with parts of literals LL_ADC_CHANNEL_x or using + * helper macro @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Then the selected literal LL_ADC_CHANNEL_x can be used + * as parameter for another function. + * - To get the channel number in decimal format: + * process the returned value with the helper macro + * @ref __LL_ADC_CHANNEL_TO_DECIMAL_NB(). + * Applicable only when the analog watchdog is set to monitor + * one channel. + * @note On this PY32 serie, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @note Depending on devices and packages, some channels may not be available. + * Refer to device datasheet for channels availability. + * @rmtoll CFGR1 AWDCH LL_ADC_GetAnalogWDMonitChannels\n + * CFGR1 AWDSGL LL_ADC_GetAnalogWDMonitChannels\n + * CFGR1 AWDEN LL_ADC_GetAnalogWDMonitChannels + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_AWD_DISABLE + * @arg @ref LL_ADC_AWD_ALL_CHANNELS_REG + * @arg @ref LL_ADC_AWD_CHANNEL_0_REG + * @arg @ref LL_ADC_AWD_CHANNEL_1_REG + * @arg @ref LL_ADC_AWD_CHANNEL_2_REG + * @arg @ref LL_ADC_AWD_CHANNEL_3_REG + * @arg @ref LL_ADC_AWD_CHANNEL_4_REG + * @arg @ref LL_ADC_AWD_CHANNEL_5_REG + * @arg @ref LL_ADC_AWD_CHANNEL_6_REG + * @arg @ref LL_ADC_AWD_CHANNEL_7_REG + * @arg @ref LL_ADC_AWD_CHANNEL_8_REG + * @arg @ref LL_ADC_AWD_CHANNEL_9_REG + * @arg @ref LL_ADC_AWD_CHANNEL_11_REG + * @arg @ref LL_ADC_AWD_CHANNEL_12_REG + */ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDMonitChannels(ADC_TypeDef *ADCx) +{ + register uint32_t AWDChannelGroup = READ_BIT(ADCx->CFGR1, (ADC_CFGR1_AWDCH | ADC_CFGR1_AWDSGL | ADC_CFGR1_AWDEN)); + + /* Note: Set variable according to channel definition including channel ID */ + /* with bitfield. */ + register uint32_t AWDChannelSingle = ((AWDChannelGroup & ADC_CFGR1_AWDSGL) >> ADC_CFGR1_AWDSGL_BITOFFSET_POS); + register uint32_t AWDChannelBitField = (ADC_CHANNEL_0_BITFIELD << ((AWDChannelGroup & ADC_CHANNEL_ID_NUMBER_MASK) >> ADC_CHANNEL_ID_NUMBER_BITOFFSET_POS)); + + return (AWDChannelGroup | (AWDChannelBitField * AWDChannelSingle)); +} + +/** + * @brief Set ADC analog watchdog thresholds value of both thresholds + * high and low. + * @note If value of only one threshold high or low must be set, + * use function @ref LL_ADC_SetAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this PY32 serie, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll TR HT LL_ADC_ConfigAnalogWDThresholds\n + * TR LT LL_ADC_ConfigAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdHighValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdLowValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_ConfigAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdHighValue, uint32_t AWDThresholdLowValue) +{ + MODIFY_REG(ADCx->TR,ADC_TR_HT | ADC_TR_LT,(AWDThresholdHighValue << ADC_TR_HT_BITOFFSET_POS) | AWDThresholdLowValue); +} + +/** + * @brief Set ADC analog watchdog threshold value of threshold + * high or low. + * @note If values of both thresholds high or low must be set, + * use function @ref LL_ADC_ConfigAnalogWDThresholds(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_SET_THRESHOLD_RESOLUTION(). + * @note On this PY32 serie, there is only 1 kind of analog watchdog + * instance: + * - AWD standard (instance AWD): + * - channels monitored: can monitor 1 channel or all channels. + * - groups monitored: ADC group regular. + * - resolution: resolution is not limited (corresponds to + * ADC resolution configured). + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be disabled or enabled without conversion on going + * on group regular. + * @rmtoll TR HT LL_ADC_SetAnalogWDThresholds\n + * TR LT LL_ADC_SetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue) +{ + /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */ + /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */ + /* high is selected, then data is shifted to LSB. Else(threshold low), */ + /* data is not shifted. */ + MODIFY_REG(ADCx->TR, AWDThresholdsHighLow,AWDThresholdValue << ((AWDThresholdsHighLow >> ADC_TR_HT_BITOFFSET_POS) & 0x00000010U)); +} + +/** + * @brief Get ADC analog watchdog threshold value of threshold high, + * threshold low or raw data with ADC thresholds high and low + * concatenated. + * @note If raw data with ADC thresholds high and low is retrieved, + * the data of each threshold high or low can be isolated + * using helper macro: + * @ref __LL_ADC_ANALOGWD_THRESHOLDS_HIGH_LOW(). + * @note In case of ADC resolution different of 12 bits, + * analog watchdog thresholds data require a specific shift. + * Use helper macro @ref __LL_ADC_ANALOGWD_GET_THRESHOLD_RESOLUTION(). + * @rmtoll TR HT LL_ADC_GetAnalogWDThresholds\n + * TR LT LL_ADC_GetAnalogWDThresholds + * @param ADCx ADC instance + * @param AWDThresholdsHighLow This parameter can be one of the following values: + * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH + * @arg @ref LL_ADC_AWD_THRESHOLD_LOW + * @arg @ref LL_ADC_AWD_THRESHOLDS_HIGH_LOW + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF +*/ +__STATIC_INLINE uint32_t LL_ADC_GetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow) +{ + /* Parameter "AWDThresholdsHighLow" is used with mask "0x00000010" */ + /* to be equivalent to "POSITION_VAL(AWDThresholdsHighLow)": if threshold */ + /* high is selected, then data is shifted to LSB. Else(threshold low or */ + /* both thresholds), data is not shifted. */ + return (uint32_t)(READ_BIT(ADCx->TR,(AWDThresholdsHighLow | ADC_TR_LT))>> ((~AWDThresholdsHighLow) & 0x00000010U)); +} + + +/** + * @brief Start ADC calibration in the mode single-ended + * or differential (for devices with differential mode available). + * @note On this PY32 serie, a minimum number of ADC clock cycles + * are required between ADC end of calibration and ADC enable. + * Refer to literal @ref LL_ADC_DELAY_CALIB_ENABLE_ADC_CYCLES. + * @note In case of usage of ADC with DMA transfer: + * On this PY32 serie, ADC DMA transfer request should be disabled + * during calibration: + * Calibration factor is available in data register + * and also transfered by DMA. + * To not insert ADC calibration factor among ADC conversion data + * in array variable, DMA transfer must be disabled during + * calibration. + * (DMA transfer setting backup and disable before calibration, + * DMA transfer setting restore after calibration. + * Refer to functions @ref LL_ADC_REG_GetDMATransfer(), + * @ref LL_ADC_REG_SetDMATransfer() ). + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR ADCAL LL_ADC_StartCalibration + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_StartCalibration(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR,ADC_CR_BITS_PROPERTY_RS,ADC_CR_ADCAL); +} + +/** + * @brief Get ADC calibration state. + * @rmtoll CR ADCAL LL_ADC_IsCalibrationOnGoing + * @param ADCx ADC instance + * @retval 0: calibration complete, 1: calibration in progress. + */ +__STATIC_INLINE uint32_t LL_ADC_IsCalibrationOnGoing(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR, ADC_CR_ADCAL) == (ADC_CR_ADCAL)); +} +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Instance Operation on ADC hierarchical scope: ADC instance + * @{ + */ + +/** + * @brief Enable the selected ADC instance. + * @note On this PY32 serie, after ADC enable, a delay for + * ADC internal analog stabilization is required before performing a + * ADC conversion start. + * Refer to device datasheet, parameter tSTAB. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be ADC disabled and ADC internal voltage regulator enabled. + * @rmtoll CR ADEN LL_ADC_Enable + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Enable(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR,ADC_CR_BITS_PROPERTY_RS,ADC_CR_ADEN); +} + +/** + * @brief Reset the selected ADC instance. + * @note On this PY32 serie, Reset the ADC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_Reset(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function */ + + /* Force reset of ADC clock (core clock) */ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1); + + /* Release reset of ADC clock (core clock) */ + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1); +} + +/** + * @brief Get the selected ADC instance enable state. + * (not only core clock: this ADC has a dual clock domain) + * @rmtoll CR ADEN LL_ADC_IsEnabled + * @param ADCx ADC instance + * @retval 0: ADC is disabled, 1: ADC is enabled. + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabled(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR, ADC_CR_ADEN) == (ADC_CR_ADEN)); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Operation_ADC_Group_Regular Operation on ADC hierarchical scope: group regular + * @{ + */ + +/** + * @brief Start ADC group regular conversion. + * @note On this PY32 serie, this function is relevant for both + * internal trigger (SW start) and external trigger: + * - If ADC trigger has been set to software start, ADC conversion + * starts immediately. + * - If ADC trigger has been set to external trigger, ADC conversion + * will start at next trigger event (on the selected trigger edge) + * following the ADC start conversion command. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled without conversion on going on group regular, + * without conversion stop command on going on group regular, + * without ADC disable command on going. + * @rmtoll CR ADSTART LL_ADC_REG_StartConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StartConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR, ADC_CR_BITS_PROPERTY_RS,ADC_CR_ADSTART); +} + +/** + * @brief Stop ADC group regular conversion. + * @note On this PY32 serie, setting of this feature is conditioned to + * ADC state: + * ADC must be enabled with conversion on going on group regular, + * without ADC disable command on going. + * @rmtoll CR ADSTP LL_ADC_REG_StopConversion + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_REG_StopConversion(ADC_TypeDef *ADCx) +{ + /* Note: Write register with some additional bits forced to state reset */ + /* instead of modifying only the selected bit for this function, */ + /* to not interfere with bits with HW property "rs". */ + MODIFY_REG(ADCx->CR,ADC_CR_BITS_PROPERTY_RS,ADC_CR_ADSTP); +} + +/** + * @brief Get ADC group regular conversion state. + * @rmtoll CR ADSTART LL_ADC_REG_IsConversionOngoing + * @param ADCx ADC instance + * @retval 0: no conversion is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsConversionOngoing(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR, ADC_CR_ADSTART) == (ADC_CR_ADSTART)); +} + +/** + * @brief Get ADC group regular command of conversion stop state + * @rmtoll CR ADSTP LL_ADC_REG_IsStopConversionOngoing + * @param ADCx ADC instance + * @retval 0: no command of conversion stop is on going on ADC group regular. + */ +__STATIC_INLINE uint32_t LL_ADC_REG_IsStopConversionOngoing(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->CR, ADC_CR_ADSTP) == (ADC_CR_ADSTP)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * all ADC configurations: all ADC resolutions and + * all oversampling increased data width (for devices + * with feature oversampling). + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData32 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00000000 and Max_Data=0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_ADC_REG_ReadConversionData32(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 12 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData12 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0xFFF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData12(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 10 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData10 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x000 and Max_Data=0x3FF + */ +__STATIC_INLINE uint16_t LL_ADC_REG_ReadConversionData10(ADC_TypeDef *ADCx) +{ + return (uint16_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 8 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData8 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData8(ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Get ADC group regular conversion data, range fit for + * ADC resolution 6 bits. + * @note For devices with feature oversampling: Oversampling + * can increase data width, function for extended range + * may be needed: @ref LL_ADC_REG_ReadConversionData32. + * @rmtoll DR DATA LL_ADC_REG_ReadConversionData6 + * @param ADCx ADC instance + * @retval Value between Min_Data=0x00 and Max_Data=0x3F + */ +__STATIC_INLINE uint8_t LL_ADC_REG_ReadConversionData6(ADC_TypeDef *ADCx) +{ + return (uint8_t)(READ_BIT(ADCx->DR, ADC_DR_DATA)); +} + +/** + * @brief Disable the selected ADC instance. + * @note On this PY32 serie, Disable the selected ADC instance + * @param ADCx ADC instance + * @retval 0: ADC Disable Failed,1:ADC Disable Success. + */ +__STATIC_INLINE ErrorStatus LL_ADC_Disable(ADC_TypeDef *ADCx) +{ + ErrorStatus status = SUCCESS; + uint32_t tmpCFGR1=ADCx->CFGR1; + __IO uint32_t timeout_cpu_cycles = 0U; + + /* Check the parameters */ + /* Disable ADC instance if not already disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 1U) + { + /* Set ADC group regular trigger source to SW start to ensure to not */ + /* have an external trigger event occurring during the conversion stop */ + /* ADC disable process. */ + LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); + + /* Stop potential ADC conversion on going on ADC group regular. */ + if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U) + { + if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U) + { + LL_ADC_REG_StopConversion(ADCx); + } + } + else + { + (ADCx->CFGR1)|=(0x7<<6); + (ADCx->CFGR1)|=(0x3<<10); + __disable_irq(); + LL_ADC_REG_StartConversion(ADCx); + LL_ADC_REG_StopConversion(ADCx); + __enable_irq(); + } + + /* Wait for ADC conversions are effectively stopped */ + timeout_cpu_cycles =LL_ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; + while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U) + { + if(timeout_cpu_cycles-- == 0U) + { + /* Time-out error */ + status = ERROR; + } + } + + /* Wait for ADC instance is effectively disabled */ + timeout_cpu_cycles =LL_ADC_TIMEOUT_DISABLE_CPU_CYCLES; + while (LL_ADC_IsEnabled(ADCx) == 1U) + { + if(timeout_cpu_cycles-- == 0U) + { + /* Time-out error */ + status = ERROR; + } + } + + /* Restore the CFGR1 Configure */ + ADCx->CFGR1=tmpCFGR1; + } + + return status; +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_FLAG_Management ADC flag management + * @{ + */ + +/** + * @brief Get flag ADC group regular end of unitary conversion. + * @rmtoll ISR EOC LL_ADC_IsActiveFlag_EOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOC(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->ISR, ADC_ISR_EOC) == (ADC_ISR_EOC)); +} + +/** + * @brief Get flag ADC group regular end of sequence conversions. + * @rmtoll ISR EOSEQ LL_ADC_IsActiveFlag_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOS(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOS) == (LL_ADC_FLAG_EOS)); +} + +/** + * @brief Get flag ADC group regular overrun. + * @rmtoll ISR OVR LL_ADC_IsActiveFlag_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_OVR(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_OVR) == (LL_ADC_FLAG_OVR)); +} + +/** + * @brief Get flag ADC group regular end of sampling phase. + * @rmtoll ISR EOSMP LL_ADC_IsActiveFlag_EOSMP + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_EOSMP(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_EOSMP) == (LL_ADC_FLAG_EOSMP)); +} + +/** + * @brief Get flag ADC analog watchdog 1 flag + * @rmtoll ISR AWD LL_ADC_IsActiveFlag_AWD + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsActiveFlag_AWD(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->ISR, LL_ADC_FLAG_AWD) == (LL_ADC_FLAG_AWD)); +} + +/** + * @brief Clear flag ADC group regular end of unitary conversion. + * @rmtoll ISR EOC LL_ADC_ClearFlag_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOC(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOC); +} + +/** + * @brief Clear flag ADC group regular end of sequence conversions. + * @rmtoll ISR EOSEQ LL_ADC_ClearFlag_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOS(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOS); +} + +/** + * @brief Clear flag ADC group regular overrun. + * @rmtoll ISR OVR LL_ADC_ClearFlag_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_OVR(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_OVR); +} + +/** + * @brief Clear flag ADC group regular end of sampling phase. + * @rmtoll ISR EOSMP LL_ADC_ClearFlag_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_EOSMP(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_EOSMP); +} + +/** + * @brief Clear flag ADC analog watchdog 1. + * @rmtoll ISR AWD LL_ADC_ClearFlag_AWD + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearFlag_AWD(ADC_TypeDef *ADCx) +{ + WRITE_REG(ADCx->ISR, LL_ADC_FLAG_AWD); +} + +/** + * @} + */ + +/** @defgroup ADC_LL_EF_IT_Management ADC IT management + * @{ + */ +/** + * @brief Enable interruption ADC group regular end of unitary conversion. + * @rmtoll IER EOCIE LL_ADC_EnableIT_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOC(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Enable interruption ADC group regular end of sequence conversions. + * @rmtoll IER EOSEQIE LL_ADC_EnableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOS(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Enable ADC group regular interruption overrun. + * @rmtoll IER OVRIE LL_ADC_EnableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_OVR(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Enable interruption ADC group regular end of sampling. + * @rmtoll IER EOSMPIE LL_ADC_EnableIT_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_EOSMP(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Enable interruption ADC analog watchdog 1. + * @rmtoll IER AWDIE LL_ADC_EnableIT_AWD + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_EnableIT_AWD(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->IER, LL_ADC_IT_AWD); +} + +/** + * @brief Disable interruption ADC group regular end of unitary conversion. + * @rmtoll IER EOCIE LL_ADC_DisableIT_EOC + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOC(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOC); +} + +/** + * @brief Disable interruption ADC group regular end of sequence conversions. + * @rmtoll IER EOSEQIE LL_ADC_DisableIT_EOS + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOS(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOS); +} + +/** + * @brief Disable interruption ADC group regular overrun. + * @rmtoll IER OVRIE LL_ADC_DisableIT_OVR + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_OVR(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_OVR); +} + +/** + * @brief Disable interruption ADC group regular end of sampling. + * @rmtoll IER EOSMPIE LL_ADC_DisableIT_EOSMP + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_EOSMP(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_EOSMP); +} + +/** + * @brief Disable interruption ADC analog watchdog 1. + * @rmtoll IER AWDIE LL_ADC_DisableIT_AWD + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_DisableIT_AWD(ADC_TypeDef *ADCx) +{ + CLEAR_BIT(ADCx->IER, LL_ADC_IT_AWD); +} + +/** + * @brief Get state of interruption ADC group regular end of unitary conversion + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOCIE LL_ADC_IsEnabledIT_EOC + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOC(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IER, LL_ADC_IT_EOC) == (LL_ADC_IT_EOC)); +} + +/** + * @brief Get state of interruption ADC group regular end of sequence conversions + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOSEQIE LL_ADC_IsEnabledIT_EOS + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOS(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IER, LL_ADC_IT_EOS) == (LL_ADC_IT_EOS)); +} + +/** + * @brief Get state of interruption ADC group regular overrun + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER OVRIE LL_ADC_IsEnabledIT_OVR + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_OVR(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IER, LL_ADC_IT_OVR) == (LL_ADC_IT_OVR)); +} + +/** + * @brief Get state of interruption ADC group regular end of sampling + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER EOSMPIE LL_ADC_IsEnabledIT_EOSMP + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_EOSMP(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IER, LL_ADC_IT_EOSMP) == (LL_ADC_IT_EOSMP)); +} + +/** + * @brief Get state of interruption ADC analog watchdog 1 + * (0: interrupt disabled, 1: interrupt enabled). + * @rmtoll IER AWDIE LL_ADC_IsEnabledIT_AWD + * @param ADCx ADC instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_ADC_IsEnabledIT_AWD(ADC_TypeDef *ADCx) +{ + return (READ_BIT(ADCx->IER, LL_ADC_IT_AWD) == (LL_ADC_IT_AWD)); +} +/** + * @} + */ + +/** @defgroup ADC_LL_EF_Calibration_Management ADC Calibration management + * @{ + */ +/** + * @brief Set calibration sample time + * @note Unit: ADC clock cycles. + * @rmtoll CCSR CALSMP LL_ADC_SetCalSamplingTime + * @param ADCx ADC instance + * @param SamplingTime This parameter can be one of the following values: + * @arg @ref LL_ADC_CAL_SAMPLINGTIME_2CYCLES + * @arg @ref LL_ADC_CAL_SAMPLINGTIME_4CYCLES + * @arg @ref LL_ADC_CAL_SAMPLINGTIME_8CYCLES + * @arg @ref LL_ADC_CAL_SAMPLINGTIME_1CYCLE + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCalibrationSamplingTime(ADC_TypeDef *ADCx, uint32_t CalibrationSamplingTime) +{ + MODIFY_REG(ADCx->CCSR, ADC_CCSR_CALSMP, CalibrationSamplingTime); +} + +/** + * @brief Get sampling time common to a group of channels. + * @note Unit: ADC clock cycles. + * @rmtoll CCSR CALSMP LL_ADC_GetCalSamplingTime + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CAL_SAMPLINGTIME_2CYCLES + * @arg @ref LL_ADC_CAL_SAMPLINGTIME_4CYCLES + * @arg @ref LL_ADC_CAL_SAMPLINGTIME_8CYCLES + * @arg @ref LL_ADC_CAL_SAMPLINGTIME_1CYCLE + */ +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationSamplingTime(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CCSR, ADC_CCSR_CALSMP)); +} + +/** + * @brief Clear the calibration status + * @rmtoll CCSR CALFAIL LL_ADC_ClearCalibrationStatus + * @param ADCx ADC instance + * @retval None + */ +__STATIC_INLINE void LL_ADC_ClearCalibrationStatus(ADC_TypeDef *ADCx) +{ + SET_BIT(ADCx->CCSR, ADC_CCSR_CALFAIL); +} + +/** + * @brief Get the calibration status + * @rmtoll CCSR CALFAIL LL_ADC_GetCalibrationStatus + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CAL_STATUS_SUCCESS + * @arg @ref LL_ADC_CAL_STATUS_FAIL + * @arg @ref LL_ADC_CAL_STATUS_ONGOING + * @arg @ref LL_ADC_CAL_STATUS_INVALID + */ + +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationStatus(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CCSR, ADC_CCSR_CALFAIL)) | (uint32_t)(READ_BIT(ADCx->CCSR, ADC_CCSR_CALON)); +} + +/** + * @brief Set the calibration mode + * @rmtoll CCSR CALSEL LL_ADC_SetCalibrationMode + * @param ADCx ADC instance + * @param This parameter can be one of the following values: + @arg @ref LL_ADC_CAL_MODE_OFFSET + * @arg @ref LL_ADC_CAL_MODE_OFFSETANDLINEARITY + * @retval None + */ +__STATIC_INLINE void LL_ADC_SetCalibrationMode(ADC_TypeDef *ADCx,uint32_t CalibrationMode) +{ + MODIFY_REG(ADCx->CCSR,ADC_CCSR_CALSEL, CalibrationMode); +} + +/** + * @brief Get the calibration contents + * @rmtoll CCSR CALSEL LL_ADC_GetCalibrationMode + * @param ADCx ADC instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_ADC_CAL_MODE_OFFSET + * @arg @ref LL_ADC_CAL_MODE_OFFSETANDLINEARITY + */ +__STATIC_INLINE uint32_t LL_ADC_GetCalibrationMode(ADC_TypeDef *ADCx) +{ + return (uint32_t)(READ_BIT(ADCx->CCSR, ADC_CCSR_CALSEL)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup ADC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +/* Initialization of some features of ADC common parameters and multimode */ +/* Note: On this PY32 serie, there is no ADC common initialization */ +/* function. */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON); + +/* De-initialization of ADC instance */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx); + +/* Initialization of some features of ADC instance */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct); +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct); + +/* Initialization of some features of ADC instance and ADC group regular */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0xx_LL_ADC_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_bus.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_bus.h similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_bus.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_bus.h index 39b2251..20b97f8 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_bus.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_bus.h @@ -1,596 +1,596 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_bus.h - * @author MCU Application Team - * @brief Header file of BUS LL module. - - @verbatim - ##### RCC Limitations ##### - ============================================================================== - [..] - A delay between an RCC peripheral clock enable and the effective peripheral - enabling should be taken into account in order to manage the peripheral read/write - from/to registers. - (+) This delay depends on the peripheral mapping. - (++) AHB & APB1 peripherals, 1 dummy read is necessary - - [..] - Workarounds: - (#) For AHB & APB1 peripherals, a dummy read to the peripheral register has been - inserted in each LL_{BUS}_GRP{x}_EnableClock() function. - - @endverbatim - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef PY32F0XX_LL_BUS_H -#define PY32F0XX_LL_BUS_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup py32f0xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup BUS_LL BUS - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants - * @{ - */ - -/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH - * @{ - */ -#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU -#if (defined(DMA) || defined(DMA1)) -#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMAEN -#endif -#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN -#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN -#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN -/** - * @} - */ - - -/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH - * @{ - */ -#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU -#if defined(TIM3) -#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN -#endif -#if defined(RTC) -#define LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN -#endif -#if defined(WWDG) -#define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN -#endif -#if defined(SPI2) -#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN -#endif -#if defined(USART2) -#define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN -#endif -#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2CEN -#define LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN -#define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN -#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APBENR1_LPTIMEN -/** - * @} - */ - -/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH - * @{ - */ -#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU -#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN -#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APBENR2_TIM1EN -#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APBENR2_SPI1EN -#define LL_APB1_GRP2_PERIPH_USART1 RCC_APBENR2_USART1EN -#if defined(TIM14) -#define LL_APB1_GRP2_PERIPH_TIM14 RCC_APBENR2_TIM14EN -#endif -#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APBENR2_TIM16EN -#if defined(TIM17) -#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APBENR2_TIM17EN -#endif -#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APBENR2_ADCEN -#if defined(COMP1) -#define LL_APB1_GRP2_PERIPH_COMP1 RCC_APBENR2_COMP1EN -#endif -#if defined(COMP2) -#define LL_APB1_GRP2_PERIPH_COMP2 RCC_APBENR2_COMP2EN -#endif -#if defined(LED) -#define LL_APB1_GRP2_PERIPH_LED RCC_APBENR2_LEDEN -#endif -/** - * @} - */ - -/** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH - * @{ - */ -#define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU -#define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN -#define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN -#define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions - * @{ - */ - -/** @defgroup BUS_LL_EF_AHB1 AHB1 - * @{ - */ - -/** - * @brief Enable AHB1 peripherals clock. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->AHBENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->AHBENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if AHB1 peripheral clock is enabled or not - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable AHB1 peripherals clock. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH - * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHBENR, Periphs); -} - -/** - * @brief Force AHB1 peripherals reset. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->AHBRSTR, Periphs); -} - -/** - * @brief Release AHB1 peripherals reset. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_AHB1_GRP1_PERIPH_ALL - * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 - * @arg @ref LL_AHB1_GRP1_PERIPH_CRC - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->AHBRSTR, Periphs); -} -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1 - * @{ - */ - -/** - * @brief Enable APB1 GRP1 peripherals clock. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_RTC - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APBENR1, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APBENR1, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 GRP1 peripheral clock is enabled or not - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_RTC - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL); -} - -/** - * @brief Disable APB1 GRP1 peripherals clock. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_RTC - * @arg @ref LL_APB1_GRP1_PERIPH_WWDG - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APBENR1, Periphs); -} - -/** - * @brief Force APB1 GRP1 peripherals reset. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APBRSTR1, Periphs); -} - -/** - * @brief Release APB1 GRP1 peripherals reset. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 - * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 - * @arg @ref LL_APB1_GRP1_PERIPH_USART2 - * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 - * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU - * @arg @ref LL_APB1_GRP1_PERIPH_PWR - * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APBRSTR1, Periphs); -} -/** - * @} - */ - -/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2 - * @{ - */ - -/** - * @brief Enable APB1 GRP2 peripherals clock. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_COMP1 - * @arg @ref LL_APB1_GRP2_PERIPH_COMP2 - * @arg @ref LL_APB1_GRP2_PERIPH_LED - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->APBENR2, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->APBENR2, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if APB1 GRP2 peripheral clock is enabled or not - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_COMP1 - * @arg @ref LL_APB1_GRP2_PERIPH_COMP2 - * @arg @ref LL_APB1_GRP2_PERIPH_LED - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL); -} - -/** - * @brief Disable APB1 GRP2 peripherals clock. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_COMP1 - * @arg @ref LL_APB1_GRP2_PERIPH_COMP2 - * @arg @ref LL_APB1_GRP2_PERIPH_LED - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APBENR2, Periphs); -} - -/** - * @brief Force APB1 GRP2 peripherals reset. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_COMP1 - * @arg @ref LL_APB1_GRP2_PERIPH_COMP2 - * @arg @ref LL_APB1_GRP2_PERIPH_LED - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->APBRSTR2, Periphs); -} - -/** - * @brief Release APB1 GRP2 peripherals reset. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_APB1_GRP2_PERIPH_ALL - * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG - * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 - * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 - * @arg @ref LL_APB1_GRP2_PERIPH_USART1 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 - * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 - * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 - * @arg @ref LL_APB1_GRP2_PERIPH_COMP1 - * @arg @ref LL_APB1_GRP2_PERIPH_COMP2 - * @arg @ref LL_APB1_GRP2_PERIPH_LED - * @note Depending on devices and packages, some peripherals may not be available. - * Refer to device datasheet for peripherals availability. - * @note (*) peripheral not available on all devices - * @retval None - */ -__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->APBRSTR2, Periphs); -} - -/** - * @} - */ - -/** @defgroup BUS_LL_EF_IOP IOP - * @{ - */ - -/** - * @brief Enable IOP peripherals clock. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF - * @retval None - */ -__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs) -{ - __IO uint32_t tmpreg; - SET_BIT(RCC->IOPENR, Periphs); - /* Delay after an RCC peripheral clock enabling */ - tmpreg = READ_BIT(RCC->IOPENR, Periphs); - (void)tmpreg; -} - -/** - * @brief Check if IOP peripheral clock is enabled or not - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF - * @retval State of Periphs (1 or 0). - */ -__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs) -{ - return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL); -} - -/** - * @brief Disable IOP peripherals clock. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF - * @retval None - */ -__STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs) -{ - CLEAR_BIT(RCC->IOPENR, Periphs); -} - -/** - * @brief Disable IOP peripherals clock. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_IOP_GRP1_PERIPH_ALL - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF - * @retval None - */ -__STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs) -{ - SET_BIT(RCC->IOPRSTR, Periphs); -} - -/** - * @brief Release IOP peripherals reset. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_IOP_GRP1_PERIPH_ALL - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB - * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF - * @retval None - */ -__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs) -{ - CLEAR_BIT(RCC->IOPRSTR, Periphs); -} -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* RCC */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* PY32F0XX_LL_BUS_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_bus.h + * @author MCU Application Team + * @brief Header file of BUS LL module. + + @verbatim + ##### RCC Limitations ##### + ============================================================================== + [..] + A delay between an RCC peripheral clock enable and the effective peripheral + enabling should be taken into account in order to manage the peripheral read/write + from/to registers. + (+) This delay depends on the peripheral mapping. + (++) AHB & APB1 peripherals, 1 dummy read is necessary + + [..] + Workarounds: + (#) For AHB & APB1 peripherals, a dummy read to the peripheral register has been + inserted in each LL_{BUS}_GRP{x}_EnableClock() function. + + @endverbatim + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef PY32F0XX_LL_BUS_H +#define PY32F0XX_LL_BUS_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup py32f0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup BUS_LL BUS + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants + * @{ + */ + +/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH + * @{ + */ +#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if (defined(DMA) || defined(DMA1)) +#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMAEN +#endif +#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN +#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN +#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN +/** + * @} + */ + + +/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH + * @{ + */ +#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU +#if defined(TIM3) +#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN +#endif +#if defined(RTC) +#define LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN +#endif +#if defined(WWDG) +#define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN +#endif +#if defined(SPI2) +#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN +#endif +#if defined(USART2) +#define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN +#endif +#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2CEN +#define LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN +#define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN +#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APBENR1_LPTIMEN +/** + * @} + */ + +/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH + * @{ + */ +#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU +#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN +#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APBENR2_TIM1EN +#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APBENR2_SPI1EN +#define LL_APB1_GRP2_PERIPH_USART1 RCC_APBENR2_USART1EN +#if defined(TIM14) +#define LL_APB1_GRP2_PERIPH_TIM14 RCC_APBENR2_TIM14EN +#endif +#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APBENR2_TIM16EN +#if defined(TIM17) +#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APBENR2_TIM17EN +#endif +#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APBENR2_ADCEN +#if defined(COMP1) +#define LL_APB1_GRP2_PERIPH_COMP1 RCC_APBENR2_COMP1EN +#endif +#if defined(COMP2) +#define LL_APB1_GRP2_PERIPH_COMP2 RCC_APBENR2_COMP2EN +#endif +#if defined(LED) +#define LL_APB1_GRP2_PERIPH_LED RCC_APBENR2_LEDEN +#endif +/** + * @} + */ + +/** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH + * @{ + */ +#define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU +#define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN +#define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN +#define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions + * @{ + */ + +/** @defgroup BUS_LL_EF_AHB1 AHB1 + * @{ + */ + +/** + * @brief Enable AHB1 peripherals clock. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->AHBENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->AHBENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if AHB1 peripheral clock is enabled or not + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable AHB1 peripherals clock. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_FLASH + * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBENR, Periphs); +} + +/** + * @brief Force AHB1 peripherals reset. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->AHBRSTR, Periphs); +} + +/** + * @brief Release AHB1 peripherals reset. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_AHB1_GRP1_PERIPH_ALL + * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1 + * @arg @ref LL_AHB1_GRP1_PERIPH_CRC + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->AHBRSTR, Periphs); +} +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1 + * @{ + */ + +/** + * @brief Enable APB1 GRP1 peripherals clock. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_RTC + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APBENR1, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APBENR1, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 GRP1 peripheral clock is enabled or not + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_RTC + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 GRP1 peripherals clock. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_RTC + * @arg @ref LL_APB1_GRP1_PERIPH_WWDG + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APBENR1, Periphs); +} + +/** + * @brief Force APB1 GRP1 peripherals reset. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APBRSTR1, Periphs); +} + +/** + * @brief Release APB1 GRP1 peripherals reset. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP1_PERIPH_TIM3 + * @arg @ref LL_APB1_GRP1_PERIPH_SPI2 + * @arg @ref LL_APB1_GRP1_PERIPH_USART2 + * @arg @ref LL_APB1_GRP1_PERIPH_I2C1 + * @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU + * @arg @ref LL_APB1_GRP1_PERIPH_PWR + * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1 + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APBRSTR1, Periphs); +} +/** + * @} + */ + +/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2 + * @{ + */ + +/** + * @brief Enable APB1 GRP2 peripherals clock. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_COMP1 + * @arg @ref LL_APB1_GRP2_PERIPH_COMP2 + * @arg @ref LL_APB1_GRP2_PERIPH_LED + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->APBENR2, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->APBENR2, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if APB1 GRP2 peripheral clock is enabled or not + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_COMP1 + * @arg @ref LL_APB1_GRP2_PERIPH_COMP2 + * @arg @ref LL_APB1_GRP2_PERIPH_LED + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Disable APB1 GRP2 peripherals clock. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_COMP1 + * @arg @ref LL_APB1_GRP2_PERIPH_COMP2 + * @arg @ref LL_APB1_GRP2_PERIPH_LED + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APBENR2, Periphs); +} + +/** + * @brief Force APB1 GRP2 peripherals reset. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_COMP1 + * @arg @ref LL_APB1_GRP2_PERIPH_COMP2 + * @arg @ref LL_APB1_GRP2_PERIPH_LED + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->APBRSTR2, Periphs); +} + +/** + * @brief Release APB1 GRP2 peripherals reset. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_APB1_GRP2_PERIPH_ALL + * @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG + * @arg @ref LL_APB1_GRP2_PERIPH_TIM1 + * @arg @ref LL_APB1_GRP2_PERIPH_SPI1 + * @arg @ref LL_APB1_GRP2_PERIPH_USART1 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM14 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM16 + * @arg @ref LL_APB1_GRP2_PERIPH_TIM17 + * @arg @ref LL_APB1_GRP2_PERIPH_ADC1 + * @arg @ref LL_APB1_GRP2_PERIPH_COMP1 + * @arg @ref LL_APB1_GRP2_PERIPH_COMP2 + * @arg @ref LL_APB1_GRP2_PERIPH_LED + * @note Depending on devices and packages, some peripherals may not be available. + * Refer to device datasheet for peripherals availability. + * @note (*) peripheral not available on all devices + * @retval None + */ +__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->APBRSTR2, Periphs); +} + +/** + * @} + */ + +/** @defgroup BUS_LL_EF_IOP IOP + * @{ + */ + +/** + * @brief Enable IOP peripherals clock. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval None + */ +__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs) +{ + __IO uint32_t tmpreg; + SET_BIT(RCC->IOPENR, Periphs); + /* Delay after an RCC peripheral clock enabling */ + tmpreg = READ_BIT(RCC->IOPENR, Periphs); + (void)tmpreg; +} + +/** + * @brief Check if IOP peripheral clock is enabled or not + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval State of Periphs (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs) +{ + return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL); +} + +/** + * @brief Disable IOP peripherals clock. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval None + */ +__STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs) +{ + CLEAR_BIT(RCC->IOPENR, Periphs); +} + +/** + * @brief Disable IOP peripherals clock. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_ALL + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval None + */ +__STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs) +{ + SET_BIT(RCC->IOPRSTR, Periphs); +} + +/** + * @brief Release IOP peripherals reset. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_IOP_GRP1_PERIPH_ALL + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOA + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOB + * @arg @ref LL_IOP_GRP1_PERIPH_GPIOF + * @retval None + */ +__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs) +{ + CLEAR_BIT(RCC->IOPRSTR, Periphs); +} +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* RCC */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PY32F0XX_LL_BUS_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_comp.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_comp.h similarity index 99% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_comp.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_comp.h index 7abcda5..934b01f 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_comp.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_comp.h @@ -4,18 +4,18 @@ * @author MCU Application Team * @brief Header file of COMP LL module. ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_cortex.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_cortex.h similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_cortex.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_cortex.h index a2dbfe8..562fecb 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_cortex.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_cortex.h @@ -1,310 +1,310 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_cortex.h - * @author MCU Application Team - * @brief Header file of CORTEX LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PY32F0XX_LL_CORTEX_H -#define __PY32F0XX_LL_CORTEX_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0XX_LL_Driver - * @{ - */ - -/** @defgroup CORTEX_LL CORTEX - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants - * @{ - */ - -/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source - * @{ - */ -#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ -#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions - * @{ - */ - -/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK - * @{ - */ - -/** - * @brief This function checks if the Systick counter flag is active or not. - * @note It can be used in timeout function on application side. - * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) -{ - return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); -} - -/** - * @brief Configures the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) -{ - if (Source == LL_SYSTICK_CLKSOURCE_HCLK) - { - SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } - else - { - CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); - } -} - -/** - * @brief Get the SysTick clock source - * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 - * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK - */ -__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) -{ - return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); -} - -/** - * @brief Enable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_EnableIT(void) -{ - SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Disable SysTick exception request - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT - * @retval None - */ -__STATIC_INLINE void LL_SYSTICK_DisableIT(void) -{ - CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); -} - -/** - * @brief Checks if the SYSTICK interrupt is enabled or disabled. - * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) -{ - return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE - * @{ - */ - -/** - * @brief Processor uses sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleep(void) -{ - /* Clear SLEEPDEEP bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Processor uses deep sleep as its low power mode - * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) -{ - /* Set SLEEPDEEP bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); -} - -/** - * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. - * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an - * empty main application. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) -{ - /* Set SLEEPONEXIT bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Do not sleep when returning to Thread mode. - * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) -{ - /* Clear SLEEPONEXIT bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); -} - -/** - * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the - * processor. - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) -{ - /* Set SEVEONPEND bit of Cortex System Control Register */ - SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are - * excluded - * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend - * @retval None - */ -__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) -{ - /* Clear SEVEONPEND bit of Cortex System Control Register */ - CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); -} - -/** - * @} - */ - -/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO - * @{ - */ - -/** - * @brief Get Implementer code - * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer - * @retval Value should be equal to 0x41 for ARM - */ -__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); -} - -/** - * @brief Get Variant number (The r value in the rnpn product revision identifier) - * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant - * @retval Value between 0 and 255 (0x0: revision 0) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); -} - -/** - * @brief Get Architecture number - * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture - * @retval Value should be equal to 0xC for Cortex-M0+ devices - */ -__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); -} - -/** - * @brief Get Part number - * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo - * @retval Value should be equal to 0xC60 for Cortex-M0+ - */ -__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); -} - -/** - * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) - * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision - * @retval Value between 0 and 255 (0x1: patch 1) - */ -__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) -{ - return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PY32F0XX_LL_CORTEX_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_cortex.h + * @author MCU Application Team + * @brief Header file of CORTEX LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32F0XX_LL_CORTEX_H +#define __PY32F0XX_LL_CORTEX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0XX_LL_Driver + * @{ + */ + +/** @defgroup CORTEX_LL CORTEX + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants + * @{ + */ + +/** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source + * @{ + */ +#define LL_SYSTICK_CLKSOURCE_HCLK_DIV8 0x00000000U /*!< AHB clock divided by 8 selected as SysTick clock source.*/ +#define LL_SYSTICK_CLKSOURCE_HCLK SysTick_CTRL_CLKSOURCE_Msk /*!< AHB clock selected as SysTick clock source. */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions + * @{ + */ + +/** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK + * @{ + */ + +/** + * @brief This function checks if the Systick counter flag is active or not. + * @note It can be used in timeout function on application side. + * @rmtoll STK_CTRL COUNTFLAG LL_SYSTICK_IsActiveCounterFlag + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void) +{ + return (((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk)) ? 1UL : 0UL); +} + +/** + * @brief Configures the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_SetClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source) +{ + if (Source == LL_SYSTICK_CLKSOURCE_HCLK) + { + SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } + else + { + CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); + } +} + +/** + * @brief Get the SysTick clock source + * @rmtoll STK_CTRL CLKSOURCE LL_SYSTICK_GetClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8 + * @arg @ref LL_SYSTICK_CLKSOURCE_HCLK + */ +__STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void) +{ + return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK); +} + +/** + * @brief Enable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_EnableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_EnableIT(void) +{ + SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Disable SysTick exception request + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_DisableIT + * @retval None + */ +__STATIC_INLINE void LL_SYSTICK_DisableIT(void) +{ + CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk); +} + +/** + * @brief Checks if the SYSTICK interrupt is enabled or disabled. + * @rmtoll STK_CTRL TICKINT LL_SYSTICK_IsEnabledIT + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void) +{ + return ((READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE + * @{ + */ + +/** + * @brief Processor uses sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleep(void) +{ + /* Clear SLEEPDEEP bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Processor uses deep sleep as its low power mode + * @rmtoll SCB_SCR SLEEPDEEP LL_LPM_EnableDeepSleep + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableDeepSleep(void) +{ + /* Set SLEEPDEEP bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk)); +} + +/** + * @brief Configures sleep-on-exit when returning from Handler mode to Thread mode. + * @note Setting this bit to 1 enables an interrupt-driven application to avoid returning to an + * empty main application. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_EnableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableSleepOnExit(void) +{ + /* Set SLEEPONEXIT bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Do not sleep when returning to Thread mode. + * @rmtoll SCB_SCR SLEEPONEXIT LL_LPM_DisableSleepOnExit + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableSleepOnExit(void) +{ + /* Clear SLEEPONEXIT bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk)); +} + +/** + * @brief Enabled events and all interrupts, including disabled interrupts, can wakeup the + * processor. + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_EnableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_EnableEventOnPend(void) +{ + /* Set SEVEONPEND bit of Cortex System Control Register */ + SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @brief Only enabled interrupts or events can wakeup the processor, disabled interrupts are + * excluded + * @rmtoll SCB_SCR SEVEONPEND LL_LPM_DisableEventOnPend + * @retval None + */ +__STATIC_INLINE void LL_LPM_DisableEventOnPend(void) +{ + /* Clear SEVEONPEND bit of Cortex System Control Register */ + CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk)); +} + +/** + * @} + */ + +/** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO + * @{ + */ + +/** + * @brief Get Implementer code + * @rmtoll SCB_CPUID IMPLEMENTER LL_CPUID_GetImplementer + * @retval Value should be equal to 0x41 for ARM + */ +__STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos); +} + +/** + * @brief Get Variant number (The r value in the rnpn product revision identifier) + * @rmtoll SCB_CPUID VARIANT LL_CPUID_GetVariant + * @retval Value between 0 and 255 (0x0: revision 0) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetVariant(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos); +} + +/** + * @brief Get Architecture number + * @rmtoll SCB_CPUID ARCHITECTURE LL_CPUID_GetArchitecture + * @retval Value should be equal to 0xC for Cortex-M0+ devices + */ +__STATIC_INLINE uint32_t LL_CPUID_GetArchitecture(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos); +} + +/** + * @brief Get Part number + * @rmtoll SCB_CPUID PARTNO LL_CPUID_GetParNo + * @retval Value should be equal to 0xC60 for Cortex-M0+ + */ +__STATIC_INLINE uint32_t LL_CPUID_GetParNo(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos); +} + +/** + * @brief Get Revision number (The p value in the rnpn product revision identifier, indicates patch release) + * @rmtoll SCB_CPUID REVISION LL_CPUID_GetRevision + * @retval Value between 0 and 255 (0x1: patch 1) + */ +__STATIC_INLINE uint32_t LL_CPUID_GetRevision(void) +{ + return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_LL_CORTEX_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_crc.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_crc.h similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_crc.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_crc.h index 9aa9ce8..7a7a35e 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_crc.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_crc.h @@ -1,204 +1,204 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_crc.h - * @author MCU Application Team - * @brief Header file of CRC LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef PY32F0xx_LL_CRC_H -#define PY32F0xx_LL_CRC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined(CRC) - -/** @defgroup CRC_LL CRC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants - * @{ - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros - * @{ - */ - -/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in CRC register - * @param __INSTANCE__ CRC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) - -/** - * @brief Read a value in CRC register - * @param __INSTANCE__ CRC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions - * @{ - */ - -/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions - * @{ - */ - -/** - * @brief Reset the CRC calculation unit. - * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit - * @param CRCx CRC Instance - * @retval None - */ -__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) -{ - SET_BIT(CRCx->CR, CRC_CR_RESET); -} - -/** - * @} - */ - -/** @defgroup CRC_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Write given 32-bit data to the CRC calculator - * @rmtoll DR DR LL_CRC_FeedData32 - * @param CRCx CRC Instance - * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) -{ - WRITE_REG(CRCx->DR, InData); -} - -/** - * @brief Return current CRC calculation result. 32 bits value is returned. - * @rmtoll DR DR LL_CRC_ReadData32 - * @param CRCx CRC Instance - * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). - */ -__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) -{ - return (uint32_t)(READ_REG(CRCx->DR)); -} - -/** - * @brief Return data stored in the Independent Data(IDR) register. - * @note This register can be used as a temporary storage location for one byte. - * @rmtoll IDR IDR LL_CRC_Read_IDR - * @param CRCx CRC Instance - * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). - */ -__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) -{ - return (uint32_t)(READ_REG(CRCx->IDR)); -} - -/** - * @brief Store data in the Independent Data(IDR) register. - * @note This register can be used as a temporary storage location for one byte. - * @rmtoll IDR IDR LL_CRC_Write_IDR - * @param CRCx CRC Instance - * @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) -{ - *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; -} -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(CRC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* PY32F0xx_LL_CRC_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_crc.h + * @author MCU Application Team + * @brief Header file of CRC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef PY32F0xx_LL_CRC_H +#define PY32F0xx_LL_CRC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined(CRC) + +/** @defgroup CRC_LL CRC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Constants CRC Exported Constants + * @{ + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Macros CRC Exported Macros + * @{ + */ + +/** @defgroup CRC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_CRC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, __VALUE__) + +/** + * @brief Read a value in CRC register + * @param __INSTANCE__ CRC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_CRC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup CRC_LL_Exported_Functions CRC Exported Functions + * @{ + */ + +/** @defgroup CRC_LL_EF_Configuration CRC Configuration functions + * @{ + */ + +/** + * @brief Reset the CRC calculation unit. + * @rmtoll CR RESET LL_CRC_ResetCRCCalculationUnit + * @param CRCx CRC Instance + * @retval None + */ +__STATIC_INLINE void LL_CRC_ResetCRCCalculationUnit(CRC_TypeDef *CRCx) +{ + SET_BIT(CRCx->CR, CRC_CR_RESET); +} + +/** + * @} + */ + +/** @defgroup CRC_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Write given 32-bit data to the CRC calculator + * @rmtoll DR DR LL_CRC_FeedData32 + * @param CRCx CRC Instance + * @param InData value to be provided to CRC calculator between between Min_Data=0 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_FeedData32(CRC_TypeDef *CRCx, uint32_t InData) +{ + WRITE_REG(CRCx->DR, InData); +} + +/** + * @brief Return current CRC calculation result. 32 bits value is returned. + * @rmtoll DR DR LL_CRC_ReadData32 + * @param CRCx CRC Instance + * @retval Current CRC calculation result as stored in CRC_DR register (32 bits). + */ +__STATIC_INLINE uint32_t LL_CRC_ReadData32(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->DR)); +} + +/** + * @brief Return data stored in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one byte. + * @rmtoll IDR IDR LL_CRC_Read_IDR + * @param CRCx CRC Instance + * @retval Value stored in CRC_IDR register (General-purpose 8-bit data register). + */ +__STATIC_INLINE uint32_t LL_CRC_Read_IDR(CRC_TypeDef *CRCx) +{ + return (uint32_t)(READ_REG(CRCx->IDR)); +} + +/** + * @brief Store data in the Independent Data(IDR) register. + * @note This register can be used as a temporary storage location for one byte. + * @rmtoll IDR IDR LL_CRC_Write_IDR + * @param CRCx CRC Instance + * @param InData value to be stored in CRC_IDR register (8-bit) between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_CRC_Write_IDR(CRC_TypeDef *CRCx, uint32_t InData) +{ + *((uint8_t __IO *)(&CRCx->IDR)) = (uint8_t) InData; +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup CRC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(CRC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PY32F0xx_LL_CRC_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_dma.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_dma.h similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_dma.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_dma.h index 3b994f4..1720d65 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_dma.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_dma.h @@ -1,1370 +1,1370 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_dma.h - * @author MCU Application Team - * @brief Header file of DMA LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PY32F0XX_LL_DMA_H -#define __PY32F0XX_LL_DMA_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0XX_LL_Driver - * @{ - */ -#if defined (DMA1) - -/** @defgroup DMA_LL DMA - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup DMA_LL_Private_Variables DMA Private Variables - * @{ - */ -/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ -static const uint8_t CHANNEL_OFFSET_TAB[] = -{ - (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), - (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), -}; -/** - * @} - */ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_Private_Macros DMA Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure - * @{ - */ -typedef struct -{ - uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer - or as Source base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer - or as Destination base address in case of memory to memory transfer direction. - - This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ - - uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, - from memory to memory or from peripheral to memory. - This parameter can be a value of @ref DMA_LL_EC_DIRECTION - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ - - uint32_t Mode; /*!< Specifies the normal or circular operation mode. - This parameter can be a value of @ref DMA_LL_EC_MODE - @note: The circular buffer mode cannot be used if the memory to memory - data transfer direction is configured on the selected Channel - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ - - uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_PERIPH - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ - - uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction - is incremented or not. - This parameter can be a value of @ref DMA_LL_EC_MEMORY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ - - uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ - - uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) - in case of memory to memory transfer direction. - This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ - - uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. - The data unit is equal to the source buffer configuration set in PeripheralSize - or MemorySize parameters depending in the transfer direction. - This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ - - uint32_t Priority; /*!< Specifies the channel priority level. - This parameter can be a value of @ref DMA_LL_EC_PRIORITY - - This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ - -} LL_DMA_InitTypeDef; -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants - * @{ - */ -/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_DMA_WriteReg function - * @{ - */ -#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ -#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ -#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ -#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ -#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ -#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ -#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ -#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ -#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ -#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_DMA_ReadReg function - * @{ - */ -#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ -#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ -#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ -#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ -#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ -#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ -#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ -#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ -#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ -#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ -#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ -#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions - * @{ - */ -#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ -#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ -#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_CHANNEL CHANNEL - * @{ - */ -#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ -#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ -#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction - * @{ - */ -#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ -#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MODE Transfer mode - * @{ - */ -#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ -#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode - * @{ - */ -#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ -#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MEMORY Memory increment mode - * @{ - */ -#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ -#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment - * @{ - */ -#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ -#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ -#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment - * @{ - */ -#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ -#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ -#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ -/** - * @} - */ - -/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level - * @{ - */ -#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ -#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ -#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ -#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros - * @{ - */ - -/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros - * @{ - */ -/** - * @brief Write a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in DMA register - * @param __INSTANCE__ DMA Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely - * @{ - */ - -/** - * @brief Convert DMAx_Channely into DMAx - * @param __CHANNEL_INSTANCE__ DMAx_Channely - * @retval DMAx - */ -#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) - -/** - * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y - * @param __CHANNEL_INSTANCE__ DMAx_Channely - * @retval LL_DMA_CHANNEL_y - */ -#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ -(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ - ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ -LL_DMA_CHANNEL_3 ) - -/** - * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely - * @param __DMA_INSTANCE__ DMAx - * @param __CHANNEL__ LL_DMA_CHANNEL_y - * @retval DMAx_Channely - */ -#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ -((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ - (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ -DMA1_Channel3 ) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions - * @{ - */ - -/** @defgroup DMA_LL_EF_Configuration Configuration - * @{ - */ -/** - * @brief Enable DMA channel. - * @rmtoll CCR EN LL_DMA_EnableChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); -} - -/** - * @brief Disable DMA channel. - * @rmtoll CCR EN LL_DMA_DisableChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); -} - -/** - * @brief Check if DMA channel is enabled or disabled. - * @rmtoll CCR EN LL_DMA_IsEnabledChannel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_EN) == (DMA_CCR_EN)); -} - -/** - * @brief Configure all parameters link to DMA transfer. - * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n - * CCR MEM2MEM LL_DMA_ConfigTransfer\n - * CCR CIRC LL_DMA_ConfigTransfer\n - * CCR PINC LL_DMA_ConfigTransfer\n - * CCR MINC LL_DMA_ConfigTransfer\n - * CCR PSIZE LL_DMA_ConfigTransfer\n - * CCR MSIZE LL_DMA_ConfigTransfer\n - * CCR PL LL_DMA_ConfigTransfer - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR - * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT - * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT - * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD - * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD - * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, - Configuration); -} - -/** - * @brief Set Data transfer direction (read from peripheral or from memory). - * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n - * CCR MEM2MEM LL_DMA_SetDataTransferDirection - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); -} - -/** - * @brief Get Data transfer direction (read from peripheral or from memory). - * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n - * CCR MEM2MEM LL_DMA_GetDataTransferDirection - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_DIR | DMA_CCR_MEM2MEM)); -} - -/** - * @brief Set DMA mode circular or normal. - * @note The circular buffer mode cannot be used if the memory-to-memory - * data transfer is configured on the selected Channel. - * @rmtoll CCR CIRC LL_DMA_SetMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, - Mode); -} - -/** - * @brief Get DMA mode circular or normal. - * @rmtoll CCR CIRC LL_DMA_GetMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MODE_NORMAL - * @arg @ref LL_DMA_MODE_CIRCULAR - */ -__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_CIRC)); -} - -/** - * @brief Set Peripheral increment mode. - * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: - * @arg @ref LL_DMA_PERIPH_INCREMENT - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, - PeriphOrM2MSrcIncMode); -} - -/** - * @brief Get Peripheral increment mode. - * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PERIPH_INCREMENT - * @arg @ref LL_DMA_PERIPH_NOINCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PINC)); -} - -/** - * @brief Set Memory increment mode. - * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: - * @arg @ref LL_DMA_MEMORY_INCREMENT - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, - MemoryOrM2MDstIncMode); -} - -/** - * @brief Get Memory increment mode. - * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MEMORY_INCREMENT - * @arg @ref LL_DMA_MEMORY_NOINCREMENT - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_MINC)); -} - -/** - * @brief Set Peripheral size. - * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, - PeriphOrM2MSrcDataSize); -} - -/** - * @brief Get Peripheral size. - * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PDATAALIGN_BYTE - * @arg @ref LL_DMA_PDATAALIGN_HALFWORD - * @arg @ref LL_DMA_PDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PSIZE)); -} - -/** - * @brief Set Memory size. - * @rmtoll CCR MSIZE LL_DMA_SetMemorySize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, - MemoryOrM2MDstDataSize); -} - -/** - * @brief Get Memory size. - * @rmtoll CCR MSIZE LL_DMA_GetMemorySize - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_MDATAALIGN_BYTE - * @arg @ref LL_DMA_MDATAALIGN_HALFWORD - * @arg @ref LL_DMA_MDATAALIGN_WORD - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_MSIZE)); -} - -/** - * @brief Set Channel priority level. - * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param Priority This parameter can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, - Priority); -} - -/** - * @brief Get Channel priority level. - * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_DMA_PRIORITY_LOW - * @arg @ref LL_DMA_PRIORITY_MEDIUM - * @arg @ref LL_DMA_PRIORITY_HIGH - * @arg @ref LL_DMA_PRIORITY_VERYHIGH - */ -__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_PL)); -} - -/** - * @brief Set Number of data to transfer. - * @note This action has no effect if - * channel is enabled. - * @rmtoll CNDTR NDT LL_DMA_SetDataLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) -{ - MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, - DMA_CNDTR_NDT, NbData); -} - -/** - * @brief Get Number of data to transfer. - * @note Once the channel is enabled, the return value indicate the - * remaining bytes to be transmitted. - * @rmtoll CNDTR NDT LL_DMA_GetDataLength - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, - DMA_CNDTR_NDT)); -} - -/** - * @brief Configure the Source and Destination addresses. - * @note This API must not be called when the DMA channel is enabled. - * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). - * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n - * CMAR MA LL_DMA_ConfigAddresses - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @param Direction This parameter can be one of the following values: - * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH - * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY - * @retval None - */ -__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, - uint32_t DstAddress, uint32_t Direction) -{ - /* Direction Memory to Periph */ - if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) - { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); - } - /* Direction Periph to Memory and Memory to Memory */ - else - { - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); - } -} - -/** - * @brief Set the Memory address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CMAR MA LL_DMA_SetMemoryAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); -} - -/** - * @brief Set the Peripheral address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CPAR PA LL_DMA_SetPeriphAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); -} - -/** - * @brief Get Memory address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @rmtoll CMAR MA LL_DMA_GetMemoryAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); -} - -/** - * @brief Get Peripheral address. - * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. - * @rmtoll CPAR PA LL_DMA_GetPeriphAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); -} - -/** - * @brief Set the Memory to Memory Source address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); -} - -/** - * @brief Set the Memory to Memory Destination address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @note This API must not be called when the DMA channel is enabled. - * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) -{ - WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); -} - -/** - * @brief Get the Memory to Memory Source address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); -} - -/** - * @brief Get the Memory to Memory Destination address. - * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. - * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); -} - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Channel 1 global interrupt flag. - * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); -} - -/** - * @brief Get Channel 2 global interrupt flag. - * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); -} - -/** - * @brief Get Channel 3 global interrupt flag. - * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); -} - -/** - * @brief Get Channel 1 transfer complete flag. - * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); -} - -/** - * @brief Get Channel 2 transfer complete flag. - * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); -} - -/** - * @brief Get Channel 3 transfer complete flag. - * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); -} - -/** - * @brief Get Channel 1 half transfer flag. - * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); -} - -/** - * @brief Get Channel 2 half transfer flag. - * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); -} - -/** - * @brief Get Channel 3 half transfer flag. - * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); -} - -/** - * @brief Get Channel 1 transfer error flag. - * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); -} - -/** - * @brief Get Channel 2 transfer error flag. - * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); -} - -/** - * @brief Get Channel 3 transfer error flag. - * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 - * @param DMAx DMAx Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) -{ - return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); -} - -/** - * @brief Clear Channel 1 global interrupt flag. - * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); -} - -/** - * @brief Clear Channel 2 global interrupt flag. - * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); -} - -/** - * @brief Clear Channel 3 global interrupt flag. - * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); -} - -/** - * @brief Clear Channel 1 transfer complete flag. - * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); -} - -/** - * @brief Clear Channel 2 transfer complete flag. - * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); -} - -/** - * @brief Clear Channel 3 transfer complete flag. - * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); -} - -/** - * @brief Clear Channel 1 half transfer flag. - * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); -} - -/** - * @brief Clear Channel 2 half transfer flag. - * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); -} - -/** - * @brief Clear Channel 3 half transfer flag. - * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); -} - -/** - * @brief Clear Channel 1 transfer error flag. - * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); -} - -/** - * @brief Clear Channel 2 transfer error flag. - * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); -} - -/** - * @brief Clear Channel 3 transfer error flag. - * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 - * @param DMAx DMAx Instance - * @retval None - */ -__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) -{ - WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); -} - -/** - * @} - */ - -/** @defgroup DMA_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable Transfer complete interrupt. - * @rmtoll CCR TCIE LL_DMA_EnableIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); -} - -/** - * @brief Enable Half transfer interrupt. - * @rmtoll CCR HTIE LL_DMA_EnableIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); -} - -/** - * @brief Enable Transfer error interrupt. - * @rmtoll CCR TEIE LL_DMA_EnableIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval None - */ -__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); -} - -/** - * @brief Disable Transfer complete interrupt. - * @rmtoll CCR TCIE LL_DMA_DisableIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); -} - -/** - * @brief Disable Half transfer interrupt. - * @rmtoll CCR HTIE LL_DMA_DisableIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); -} - -/** - * @brief Disable Transfer error interrupt. - * @rmtoll CCR TEIE LL_DMA_DisableIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval None - */ -__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); -} - -/** - * @brief Check if Transfer complete Interrupt is enabled. - * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TCIE) == (DMA_CCR_TCIE)); -} - -/** - * @brief Check if Half transfer Interrupt is enabled. - * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_HTIE) == (DMA_CCR_HTIE)); -} - -/** - * @brief Check if Transfer error Interrupt is enabled. - * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) -{ - return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, - DMA_CCR_TEIE) == (DMA_CCR_TEIE)); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMA1 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PY32F0XX_LL_DMA_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_dma.h + * @author MCU Application Team + * @brief Header file of DMA LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32F0XX_LL_DMA_H +#define __PY32F0XX_LL_DMA_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0XX_LL_Driver + * @{ + */ +#if defined (DMA1) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup DMA_LL_Private_Variables DMA Private Variables + * @{ + */ +/* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */ +static const uint8_t CHANNEL_OFFSET_TAB[] = +{ + (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE), + (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE), +}; +/** + * @} + */ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_Private_Macros DMA Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_ES_INIT DMA Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer + or as Source base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer + or as Destination base address in case of memory to memory transfer direction. + + This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */ + + uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral, + from memory to memory or from peripheral to memory. + This parameter can be a value of @ref DMA_LL_EC_DIRECTION + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */ + + uint32_t Mode; /*!< Specifies the normal or circular operation mode. + This parameter can be a value of @ref DMA_LL_EC_MODE + @note: The circular buffer mode cannot be used if the memory to memory + data transfer direction is configured on the selected Channel + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */ + + uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_PERIPH + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */ + + uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction + is incremented or not. + This parameter can be a value of @ref DMA_LL_EC_MEMORY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */ + + uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */ + + uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word) + in case of memory to memory transfer direction. + This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */ + + uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit. + The data unit is equal to the source buffer configuration set in PeripheralSize + or MemorySize parameters depending in the transfer direction. + This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */ + + uint32_t Priority; /*!< Specifies the channel priority level. + This parameter can be a value of @ref DMA_LL_EC_PRIORITY + + This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */ + +} LL_DMA_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Constants DMA Exported Constants + * @{ + */ +/** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_DMA_WriteReg function + * @{ + */ +#define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */ +#define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */ +#define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */ +#define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_DMA_ReadReg function + * @{ + */ +#define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */ +#define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */ +#define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */ +#define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */ +#define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */ +#define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */ +#define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */ +#define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */ +#define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */ +#define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */ +#define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */ +#define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions + * @{ + */ +#define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */ +#define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */ +#define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_CHANNEL CHANNEL + * @{ + */ +#define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */ +#define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */ +#define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_DIRECTION Transfer Direction + * @{ + */ +#define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */ +#define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MODE Transfer mode + * @{ + */ +#define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */ +#define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode + * @{ + */ +#define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */ +#define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MEMORY Memory increment mode + * @{ + */ +#define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */ +#define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment + * @{ + */ +#define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */ +#define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */ +#define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment + * @{ + */ +#define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */ +#define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */ +#define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */ +/** + * @} + */ + +/** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level + * @{ + */ +#define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */ +#define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */ +#define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */ +#define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Macros DMA Exported Macros + * @{ + */ + +/** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in DMA register + * @param __INSTANCE__ DMA Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely + * @{ + */ + +/** + * @brief Convert DMAx_Channely into DMAx + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval DMAx + */ +#define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1) + +/** + * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y + * @param __CHANNEL_INSTANCE__ DMAx_Channely + * @retval LL_DMA_CHANNEL_y + */ +#define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \ +(((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \ + ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \ +LL_DMA_CHANNEL_3 ) + +/** + * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely + * @param __DMA_INSTANCE__ DMAx + * @param __CHANNEL__ LL_DMA_CHANNEL_y + * @retval DMAx_Channely + */ +#define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \ +((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \ + (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \ +DMA1_Channel3 ) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup DMA_LL_Exported_Functions DMA Exported Functions + * @{ + */ + +/** @defgroup DMA_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable DMA channel. + * @rmtoll CCR EN LL_DMA_EnableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Disable DMA channel. + * @rmtoll CCR EN LL_DMA_DisableChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN); +} + +/** + * @brief Check if DMA channel is enabled or disabled. + * @rmtoll CCR EN LL_DMA_IsEnabledChannel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_EN) == (DMA_CCR_EN)); +} + +/** + * @brief Configure all parameters link to DMA transfer. + * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n + * CCR MEM2MEM LL_DMA_ConfigTransfer\n + * CCR CIRC LL_DMA_ConfigTransfer\n + * CCR PINC LL_DMA_ConfigTransfer\n + * CCR MINC LL_DMA_ConfigTransfer\n + * CCR PSIZE LL_DMA_ConfigTransfer\n + * CCR MSIZE LL_DMA_ConfigTransfer\n + * CCR PL LL_DMA_ConfigTransfer + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR + * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT + * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT + * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD + * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD + * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL, + Configuration); +} + +/** + * @brief Set Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_SetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction); +} + +/** + * @brief Get Data transfer direction (read from peripheral or from memory). + * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n + * CCR MEM2MEM LL_DMA_GetDataTransferDirection + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_DIR | DMA_CCR_MEM2MEM)); +} + +/** + * @brief Set DMA mode circular or normal. + * @note The circular buffer mode cannot be used if the memory-to-memory + * data transfer is configured on the selected Channel. + * @rmtoll CCR CIRC LL_DMA_SetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC, + Mode); +} + +/** + * @brief Get DMA mode circular or normal. + * @rmtoll CCR CIRC LL_DMA_GetMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MODE_NORMAL + * @arg @ref LL_DMA_MODE_CIRCULAR + */ +__STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_CIRC)); +} + +/** + * @brief Set Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC, + PeriphOrM2MSrcIncMode); +} + +/** + * @brief Get Peripheral increment mode. + * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PERIPH_INCREMENT + * @arg @ref LL_DMA_PERIPH_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PINC)); +} + +/** + * @brief Set Memory increment mode. + * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param MemoryOrM2MDstIncMode This parameter can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC, + MemoryOrM2MDstIncMode); +} + +/** + * @brief Get Memory increment mode. + * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MEMORY_INCREMENT + * @arg @ref LL_DMA_MEMORY_NOINCREMENT + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MINC)); +} + +/** + * @brief Set Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE, + PeriphOrM2MSrcDataSize); +} + +/** + * @brief Get Peripheral size. + * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PDATAALIGN_BYTE + * @arg @ref LL_DMA_PDATAALIGN_HALFWORD + * @arg @ref LL_DMA_PDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PSIZE)); +} + +/** + * @brief Set Memory size. + * @rmtoll CCR MSIZE LL_DMA_SetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param MemoryOrM2MDstDataSize This parameter can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE, + MemoryOrM2MDstDataSize); +} + +/** + * @brief Get Memory size. + * @rmtoll CCR MSIZE LL_DMA_GetMemorySize + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_MDATAALIGN_BYTE + * @arg @ref LL_DMA_MDATAALIGN_HALFWORD + * @arg @ref LL_DMA_MDATAALIGN_WORD + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_MSIZE)); +} + +/** + * @brief Set Channel priority level. + * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param Priority This parameter can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL, + Priority); +} + +/** + * @brief Get Channel priority level. + * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_DMA_PRIORITY_LOW + * @arg @ref LL_DMA_PRIORITY_MEDIUM + * @arg @ref LL_DMA_PRIORITY_HIGH + * @arg @ref LL_DMA_PRIORITY_VERYHIGH + */ +__STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_PL)); +} + +/** + * @brief Set Number of data to transfer. + * @note This action has no effect if + * channel is enabled. + * @rmtoll CNDTR NDT LL_DMA_SetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData) +{ + MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT, NbData); +} + +/** + * @brief Get Number of data to transfer. + * @note Once the channel is enabled, the return value indicate the + * remaining bytes to be transmitted. + * @rmtoll CNDTR NDT LL_DMA_GetDataLength + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR, + DMA_CNDTR_NDT)); +} + +/** + * @brief Configure the Source and Destination addresses. + * @note This API must not be called when the DMA channel is enabled. + * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr). + * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n + * CMAR MA LL_DMA_ConfigAddresses + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @param Direction This parameter can be one of the following values: + * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH + * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY + * @retval None + */ +__STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress, + uint32_t DstAddress, uint32_t Direction) +{ + /* Direction Memory to Periph */ + if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress); + } + /* Direction Periph to Memory and Memory to Memory */ + else + { + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress); + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress); + } +} + +/** + * @brief Set the Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Set the Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress); +} + +/** + * @brief Get Memory address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CMAR MA LL_DMA_GetMemoryAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @brief Get Peripheral address. + * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only. + * @rmtoll CPAR PA LL_DMA_GetPeriphAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Set the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress); +} + +/** + * @brief Set the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @note This API must not be called when the DMA channel is enabled. + * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress) +{ + WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress); +} + +/** + * @brief Get the Memory to Memory Source address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR)); +} + +/** + * @brief Get the Memory to Memory Destination address. + * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only. + * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR)); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Channel 1 global interrupt flag. + * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)); +} + +/** + * @brief Get Channel 2 global interrupt flag. + * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)); +} + +/** + * @brief Get Channel 3 global interrupt flag. + * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)); +} + +/** + * @brief Get Channel 1 transfer complete flag. + * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)); +} + +/** + * @brief Get Channel 2 transfer complete flag. + * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)); +} + +/** + * @brief Get Channel 3 transfer complete flag. + * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)); +} + +/** + * @brief Get Channel 1 half transfer flag. + * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)); +} + +/** + * @brief Get Channel 2 half transfer flag. + * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)); +} + +/** + * @brief Get Channel 3 half transfer flag. + * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)); +} + +/** + * @brief Get Channel 1 transfer error flag. + * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)); +} + +/** + * @brief Get Channel 2 transfer error flag. + * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)); +} + +/** + * @brief Get Channel 3 transfer error flag. + * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3 + * @param DMAx DMAx Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx) +{ + return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)); +} + +/** + * @brief Clear Channel 1 global interrupt flag. + * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1); +} + +/** + * @brief Clear Channel 2 global interrupt flag. + * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2); +} + +/** + * @brief Clear Channel 3 global interrupt flag. + * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3); +} + +/** + * @brief Clear Channel 1 transfer complete flag. + * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1); +} + +/** + * @brief Clear Channel 2 transfer complete flag. + * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2); +} + +/** + * @brief Clear Channel 3 transfer complete flag. + * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3); +} + +/** + * @brief Clear Channel 1 half transfer flag. + * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1); +} + +/** + * @brief Clear Channel 2 half transfer flag. + * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2); +} + +/** + * @brief Clear Channel 3 half transfer flag. + * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3); +} + +/** + * @brief Clear Channel 1 transfer error flag. + * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1); +} + +/** + * @brief Clear Channel 2 transfer error flag. + * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2); +} + +/** + * @brief Clear Channel 3 transfer error flag. + * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3 + * @param DMAx DMAx Instance + * @retval None + */ +__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx) +{ + WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3); +} + +/** + * @} + */ + +/** @defgroup DMA_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_EnableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Enable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_EnableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Enable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_EnableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval None + */ +__STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Disable Transfer complete interrupt. + * @rmtoll CCR TCIE LL_DMA_DisableIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE); +} + +/** + * @brief Disable Half transfer interrupt. + * @rmtoll CCR HTIE LL_DMA_DisableIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE); +} + +/** + * @brief Disable Transfer error interrupt. + * @rmtoll CCR TEIE LL_DMA_DisableIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval None + */ +__STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE); +} + +/** + * @brief Check if Transfer complete Interrupt is enabled. + * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TCIE) == (DMA_CCR_TCIE)); +} + +/** + * @brief Check if Half transfer Interrupt is enabled. + * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_HTIE) == (DMA_CCR_HTIE)); +} + +/** + * @brief Check if Transfer error Interrupt is enabled. + * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel) +{ + return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, + DMA_CCR_TEIE) == (DMA_CCR_TEIE)); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct); +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel); +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_LL_DMA_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_exti.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_exti.h similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_exti.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_exti.h index 65defb9..e101150 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_exti.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_exti.h @@ -1,886 +1,886 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_exti.h - * @author MCU Application Team - * @brief Header file of RCC LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef PY32F0XX_LL_EXTI_H -#define PY32F0XX_LL_EXTI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup py32f0xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -#define LL_EXTI_REGISTER_PINPOS_SHFT 8U /*!< Define used to shift pin position in EXTICR register */ -#define LL_EXTI_REGISTER_PINMASK_SHFT 16U /*!< Define used to shift pin mask in EXTICR register */ - -/* Private Macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure - * @{ - */ -typedef struct -{ - - uint32_t Line; /*!< Specifies the EXTI lines to be enabled or disabled for Lines - This parameter can be any combination of @ref EXTI_LL_EC_LINE */ - - FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. - This parameter can be set either to ENABLE or DISABLE */ - - uint8_t Mode; /*!< Specifies the mode for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_MODE. */ - - uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. - This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ -} LL_EXTI_InitTypeDef; - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants - * @{ - */ - -/** @defgroup EXTI_LL_EC_LINE LINE - * @{ - */ -#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ -#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ -#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ -#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ -#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ -#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ -#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ -#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ -#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ -#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ -#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ -#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ -#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ -#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ -#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ -#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ -#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ -#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ -#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ -#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ -#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ - -#if defined(USE_FULL_LL_DRIVER) -#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */ -#endif /*USE_FULL_LL_DRIVER*/ - - -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) - -/** @defgroup EXTI_LL_EC_MODE Mode - * @{ - */ -#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ -#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ -#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ -/** - * @} - */ - -/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger - * @{ - */ -#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ -#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ -#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ -#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ - -/** - * @} - */ - - -#endif /*USE_FULL_LL_DRIVER*/ - -/** @defgroup EXTI_LL_EC_CONFIG_PORT EXTI CONFIG PORT - * @{ - */ -#define LL_EXTI_CONFIG_PORTA 0x0U /*!< EXTI PORT A */ -#define LL_EXTI_CONFIG_PORTB 0x1U /*!< EXTI PORT B */ -#define LL_EXTI_CONFIG_PORTF 0x2U /*!< EXTI PORT F */ -/** - * @} - */ - -/** @defgroup EXTI_LL_EC_CONFIG_LINE EXTI CONFIG LINE - * @{ - */ -#define LL_EXTI_CONFIG_LINE0 ((0x3U << LL_EXTI_REGISTER_PINMASK_SHFT) | ( 0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_MASK_3 | EXTI_POSITION_0 | EXTICR[0] */ -#define LL_EXTI_CONFIG_LINE1 ((0x3U << LL_EXTI_REGISTER_PINMASK_SHFT) | ( 8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_MASK_3 | EXTI_POSITION_8 | EXTICR[0] */ -#define LL_EXTI_CONFIG_LINE2 ((0x3U << LL_EXTI_REGISTER_PINMASK_SHFT) | (16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_MASK_3 | EXTI_POSITION_16 | EXTICR[0] */ -#define LL_EXTI_CONFIG_LINE3 ((0x3U << LL_EXTI_REGISTER_PINMASK_SHFT) | (24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_MASK_3 | EXTI_POSITION_24 | EXTICR[0] */ -#define LL_EXTI_CONFIG_LINE4 ((0x3U << LL_EXTI_REGISTER_PINMASK_SHFT) | ( 0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_MASK_3 | EXTI_POSITION_0 | EXTICR[1] */ -#define LL_EXTI_CONFIG_LINE5 ((0x1U << LL_EXTI_REGISTER_PINMASK_SHFT) | ( 8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_MASK_1 | EXTI_POSITION_8 | EXTICR[1] */ -#define LL_EXTI_CONFIG_LINE6 ((0x1U << LL_EXTI_REGISTER_PINMASK_SHFT) | (16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_MASK_1 | EXTI_POSITION_16 | EXTICR[1] */ -#define LL_EXTI_CONFIG_LINE7 ((0x1U << LL_EXTI_REGISTER_PINMASK_SHFT) | (24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_MASK_1 | EXTI_POSITION_19 | EXTICR[1] */ -#define LL_EXTI_CONFIG_LINE8 ((0x1U << LL_EXTI_REGISTER_PINMASK_SHFT) | ( 0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_MASK_1 | EXTI_POSITION_0 | EXTICR[2] */ -/** - * @} - */ - - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros - * @{ - */ - -/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in EXTI register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) - -/** - * @brief Read a value in EXTI register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) -/** - * @} - */ - - -/** - * @} - */ - - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions - * @{ - */ -/** @defgroup EXTI_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Interrupt request for Lines - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_29 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableIT(uint32_t ExtiLine) -{ - SET_BIT(EXTI->IMR, ExtiLine); -} - -/** - * @brief Disable ExtiLine Interrupt request for Lines - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_29 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableIT(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->IMR, ExtiLine); -} - -/** - * @brief Indicate if ExtiLine Interrupt request is enabled for Lines - * Bits are set automatically at Power on. - * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_29 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); -} - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Event_Management Event_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Event request for Lines - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_29 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableEvent(uint32_t ExtiLine) -{ - SET_BIT(EXTI->EMR, ExtiLine); - -} -/** - * @brief Disable ExtiLine Event request for Lines - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_29 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableEvent(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->EMR, ExtiLine); -} - -/** - * @brief Indicate if ExtiLine Event request is enabled for Lines - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @arg @ref LL_EXTI_LINE_19 - * @arg @ref LL_EXTI_LINE_29 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); -} - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Rising Edge Trigger for Lines - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableRisingTrig(uint32_t ExtiLine) -{ - SET_BIT(EXTI->RTSR, ExtiLine); - -} - -/** - * @brief Disable ExtiLine Rising Edge Trigger for Lines - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a rising edge on a configurable interrupt - * line occurs during a write operation in the EXTI_RTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableRisingTrig(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->RTSR, ExtiLine); - -} - - -/** - * @brief Check if rising edge trigger is enabled for Lines - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); -} - - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management - * @{ - */ - -/** - * @brief Enable ExtiLine Falling Edge Trigger for Lines - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for - * the same interrupt line. In this case, both generate a trigger - * condition. - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_EnableFallingTrig(uint32_t ExtiLine) -{ - SET_BIT(EXTI->FTSR, ExtiLine); -} - -/** - * @brief Disable ExtiLine Falling Edge Trigger for Lines - * @note The configurable wakeup lines are edge-triggered. No glitch must be - * generated on these lines. If a Falling edge on a configurable interrupt - * line occurs during a write operation in the EXTI_FTSR register, the - * pending bit is not set. - * Rising and falling edge triggers can be set for the same interrupt line. - * In this case, both generate a trigger condition. - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_DisableFallingTrig(uint32_t ExtiLine) -{ - CLEAR_BIT(EXTI->FTSR, ExtiLine); -} - -/** - * @brief Check if falling edge trigger is enabled for Lines - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); -} - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management - * @{ - */ - -/** - * @brief Generate a software Interrupt Event for Lines - * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to - * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR - * resulting in an interrupt request generation. - * This bit is cleared by clearing the corresponding bit in the EXTI_PR - * register (by writing a 1 into the bit) - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_GenerateSWI(uint32_t ExtiLine) -{ - SET_BIT(EXTI->SWIER, ExtiLine); -} - -/** - * @} - */ - -/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management - * @{ - */ - -/** - * @brief Check if the ExtLine Flag is set or not for Lines - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @note Please check each device line mapping for EXTI Line availability - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); -} - -/** - * @brief Read ExtLine Combination Flag for Lines - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @note Please check each device line mapping for EXTI Line availability - * @retval @note This bit is set when the selected edge event arrives on the interrupt - */ -__STATIC_INLINE uint32_t LL_EXTI_ReadFlag(uint32_t ExtiLine) -{ - return (READ_BIT(EXTI->PR, ExtiLine)); -} - -/** - * @brief Clear ExtLine Flags for Lines - * @param ExtiLine This parameter can be a combination of the following values: - * @arg @ref LL_EXTI_LINE_0 - * @arg @ref LL_EXTI_LINE_1 - * @arg @ref LL_EXTI_LINE_2 - * @arg @ref LL_EXTI_LINE_3 - * @arg @ref LL_EXTI_LINE_4 - * @arg @ref LL_EXTI_LINE_5 - * @arg @ref LL_EXTI_LINE_6 - * @arg @ref LL_EXTI_LINE_7 - * @arg @ref LL_EXTI_LINE_8 - * @arg @ref LL_EXTI_LINE_9 - * @arg @ref LL_EXTI_LINE_10 - * @arg @ref LL_EXTI_LINE_11 - * @arg @ref LL_EXTI_LINE_12 - * @arg @ref LL_EXTI_LINE_13 - * @arg @ref LL_EXTI_LINE_14 - * @arg @ref LL_EXTI_LINE_15 - * @arg @ref LL_EXTI_LINE_16 - * @arg @ref LL_EXTI_LINE_17 - * @arg @ref LL_EXTI_LINE_18 - * @note Please check each device line mapping for EXTI Line availability - * @retval None - */ -__STATIC_INLINE void LL_EXTI_ClearFlag(uint32_t ExtiLine) -{ - WRITE_REG(EXTI->PR, ExtiLine); -} - -/** - * @brief Configure source input for the EXTI external interrupt. - * @param Port This parameter can be one of the following values: - * @arg @ref LL_EXTI_CONFIG_PORTA - * @arg @ref LL_EXTI_CONFIG_PORTB - * @arg @ref LL_EXTI_CONFIG_PORTF - * @param Line This parameter can be one of the following values: - * @arg @ref LL_EXTI_CONFIG_LINE0 - * @arg @ref LL_EXTI_CONFIG_LINE1 - * @arg @ref LL_EXTI_CONFIG_LINE2 - * @arg @ref LL_EXTI_CONFIG_LINE3 - * @arg @ref LL_EXTI_CONFIG_LINE4 - * @arg @ref LL_EXTI_CONFIG_LINE5 - * @arg @ref LL_EXTI_CONFIG_LINE6 - * @arg @ref LL_EXTI_CONFIG_LINE7 - * @arg @ref LL_EXTI_CONFIG_LINE8 - * @retval None - */ -__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) -{ - uint32_t mask = (Line >> LL_EXTI_REGISTER_PINMASK_SHFT) & 0xFF; - uint32_t pos = (Line >> LL_EXTI_REGISTER_PINPOS_SHFT) & 0xFF; - MODIFY_REG(EXTI->EXTICR[Line & 0x03u], (mask << pos), (Port << pos)); -} - -/** - * @brief Get the configured defined for specific EXTI Line - * @param Line This parameter can be one of the following values: - * @arg @ref LL_EXTI_CONFIG_LINE0 - * @arg @ref LL_EXTI_CONFIG_LINE1 - * @arg @ref LL_EXTI_CONFIG_LINE2 - * @arg @ref LL_EXTI_CONFIG_LINE3 - * @arg @ref LL_EXTI_CONFIG_LINE4 - * @arg @ref LL_EXTI_CONFIG_LINE5 - * @arg @ref LL_EXTI_CONFIG_LINE6 - * @arg @ref LL_EXTI_CONFIG_LINE7 - * @arg @ref LL_EXTI_CONFIG_LINE8 - * @retval Returned value can be one of the following values: - * @arg @ref LL_EXTI_CONFIG_PORTA - * @arg @ref LL_EXTI_CONFIG_PORTB - * @arg @ref LL_EXTI_CONFIG_PORTF - */ -__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) -{ - uint32_t mask = (Line >> LL_EXTI_REGISTER_PINMASK_SHFT) & 0xFF; - uint32_t pos = (Line >> LL_EXTI_REGISTER_PINPOS_SHFT) & 0xFF; - return (READ_BIT(EXTI->EXTICR[Line & 0x03u], (mask << pos)) >> pos); -} - - -/** - * @} - */ -/** @defgroup EXTI_LL_EF_Config EF configuration functions - * @{ - */ - - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); -uint32_t LL_EXTI_DeInit(void); -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); - - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* EXTI */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* PY32F0XX_LL_EXTI_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_exti.h + * @author MCU Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef PY32F0XX_LL_EXTI_H +#define PY32F0XX_LL_EXTI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup py32f0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +#define LL_EXTI_REGISTER_PINPOS_SHFT 8U /*!< Define used to shift pin position in EXTICR register */ +#define LL_EXTI_REGISTER_PINMASK_SHFT 16U /*!< Define used to shift pin mask in EXTICR register */ + +/* Private Macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_Private_Macros EXTI Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_ES_INIT EXTI Exported Init structure + * @{ + */ +typedef struct +{ + + uint32_t Line; /*!< Specifies the EXTI lines to be enabled or disabled for Lines + This parameter can be any combination of @ref EXTI_LL_EC_LINE */ + + FunctionalState LineCommand; /*!< Specifies the new state of the selected EXTI lines. + This parameter can be set either to ENABLE or DISABLE */ + + uint8_t Mode; /*!< Specifies the mode for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_MODE. */ + + uint8_t Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines. + This parameter can be a value of @ref EXTI_LL_EC_TRIGGER. */ +} LL_EXTI_InitTypeDef; + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Constants EXTI Exported Constants + * @{ + */ + +/** @defgroup EXTI_LL_EC_LINE LINE + * @{ + */ +#define LL_EXTI_LINE_0 EXTI_IMR_IM0 /*!< Extended line 0 */ +#define LL_EXTI_LINE_1 EXTI_IMR_IM1 /*!< Extended line 1 */ +#define LL_EXTI_LINE_2 EXTI_IMR_IM2 /*!< Extended line 2 */ +#define LL_EXTI_LINE_3 EXTI_IMR_IM3 /*!< Extended line 3 */ +#define LL_EXTI_LINE_4 EXTI_IMR_IM4 /*!< Extended line 4 */ +#define LL_EXTI_LINE_5 EXTI_IMR_IM5 /*!< Extended line 5 */ +#define LL_EXTI_LINE_6 EXTI_IMR_IM6 /*!< Extended line 6 */ +#define LL_EXTI_LINE_7 EXTI_IMR_IM7 /*!< Extended line 7 */ +#define LL_EXTI_LINE_8 EXTI_IMR_IM8 /*!< Extended line 8 */ +#define LL_EXTI_LINE_9 EXTI_IMR_IM9 /*!< Extended line 9 */ +#define LL_EXTI_LINE_10 EXTI_IMR_IM10 /*!< Extended line 10 */ +#define LL_EXTI_LINE_11 EXTI_IMR_IM11 /*!< Extended line 11 */ +#define LL_EXTI_LINE_12 EXTI_IMR_IM12 /*!< Extended line 12 */ +#define LL_EXTI_LINE_13 EXTI_IMR_IM13 /*!< Extended line 13 */ +#define LL_EXTI_LINE_14 EXTI_IMR_IM14 /*!< Extended line 14 */ +#define LL_EXTI_LINE_15 EXTI_IMR_IM15 /*!< Extended line 15 */ +#define LL_EXTI_LINE_16 EXTI_IMR_IM16 /*!< Extended line 16 */ +#define LL_EXTI_LINE_17 EXTI_IMR_IM17 /*!< Extended line 17 */ +#define LL_EXTI_LINE_18 EXTI_IMR_IM18 /*!< Extended line 18 */ +#define LL_EXTI_LINE_19 EXTI_IMR_IM19 /*!< Extended line 19 */ +#define LL_EXTI_LINE_29 EXTI_IMR_IM29 /*!< Extended line 29 */ + +#if defined(USE_FULL_LL_DRIVER) +#define LL_EXTI_LINE_NONE 0x00000000U /*!< None Extended line */ +#endif /*USE_FULL_LL_DRIVER*/ + + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +/** @defgroup EXTI_LL_EC_MODE Mode + * @{ + */ +#define LL_EXTI_MODE_IT ((uint8_t)0x00U) /*!< Interrupt Mode */ +#define LL_EXTI_MODE_EVENT ((uint8_t)0x01U) /*!< Event Mode */ +#define LL_EXTI_MODE_IT_EVENT ((uint8_t)0x02U) /*!< Interrupt & Event Mode */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_TRIGGER Edge Trigger + * @{ + */ +#define LL_EXTI_TRIGGER_NONE ((uint8_t)0x00U) /*!< No Trigger Mode */ +#define LL_EXTI_TRIGGER_RISING ((uint8_t)0x01U) /*!< Trigger Rising Mode */ +#define LL_EXTI_TRIGGER_FALLING ((uint8_t)0x02U) /*!< Trigger Falling Mode */ +#define LL_EXTI_TRIGGER_RISING_FALLING ((uint8_t)0x03U) /*!< Trigger Rising & Falling Mode */ + +/** + * @} + */ + + +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup EXTI_LL_EC_CONFIG_PORT EXTI CONFIG PORT + * @{ + */ +#define LL_EXTI_CONFIG_PORTA 0x0U /*!< EXTI PORT A */ +#define LL_EXTI_CONFIG_PORTB 0x1U /*!< EXTI PORT B */ +#define LL_EXTI_CONFIG_PORTF 0x2U /*!< EXTI PORT F */ +/** + * @} + */ + +/** @defgroup EXTI_LL_EC_CONFIG_LINE EXTI CONFIG LINE + * @{ + */ +#define LL_EXTI_CONFIG_LINE0 ((0x3U << LL_EXTI_REGISTER_PINMASK_SHFT) | ( 0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_MASK_3 | EXTI_POSITION_0 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE1 ((0x3U << LL_EXTI_REGISTER_PINMASK_SHFT) | ( 8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_MASK_3 | EXTI_POSITION_8 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE2 ((0x3U << LL_EXTI_REGISTER_PINMASK_SHFT) | (16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_MASK_3 | EXTI_POSITION_16 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE3 ((0x3U << LL_EXTI_REGISTER_PINMASK_SHFT) | (24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 0U) /*!< EXTI_MASK_3 | EXTI_POSITION_24 | EXTICR[0] */ +#define LL_EXTI_CONFIG_LINE4 ((0x3U << LL_EXTI_REGISTER_PINMASK_SHFT) | ( 0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_MASK_3 | EXTI_POSITION_0 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE5 ((0x1U << LL_EXTI_REGISTER_PINMASK_SHFT) | ( 8U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_MASK_1 | EXTI_POSITION_8 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE6 ((0x1U << LL_EXTI_REGISTER_PINMASK_SHFT) | (16U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_MASK_1 | EXTI_POSITION_16 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE7 ((0x1U << LL_EXTI_REGISTER_PINMASK_SHFT) | (24U << LL_EXTI_REGISTER_PINPOS_SHFT) | 1U) /*!< EXTI_MASK_1 | EXTI_POSITION_19 | EXTICR[1] */ +#define LL_EXTI_CONFIG_LINE8 ((0x1U << LL_EXTI_REGISTER_PINMASK_SHFT) | ( 0U << LL_EXTI_REGISTER_PINPOS_SHFT) | 2U) /*!< EXTI_MASK_1 | EXTI_POSITION_0 | EXTICR[2] */ +/** + * @} + */ + + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Macros EXTI Exported Macros + * @{ + */ + +/** @defgroup EXTI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in EXTI register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_EXTI_WriteReg(__REG__, __VALUE__) WRITE_REG(EXTI->__REG__, (__VALUE__)) + +/** + * @brief Read a value in EXTI register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_EXTI_ReadReg(__REG__) READ_REG(EXTI->__REG__) +/** + * @} + */ + + +/** + * @} + */ + + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup EXTI_LL_Exported_Functions EXTI Exported Functions + * @{ + */ +/** @defgroup EXTI_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Interrupt request for Lines + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_29 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableIT(uint32_t ExtiLine) +{ + SET_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Interrupt request for Lines + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_29 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableIT(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->IMR, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Interrupt request is enabled for Lines + * Bits are set automatically at Power on. + * @rmtoll IMR1 IMx LL_EXTI_IsEnabledIT_0_31 + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_29 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledIT(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->IMR, ExtiLine) == (ExtiLine)); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Event_Management Event_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Event request for Lines + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_29 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableEvent(uint32_t ExtiLine) +{ + SET_BIT(EXTI->EMR, ExtiLine); + +} +/** + * @brief Disable ExtiLine Event request for Lines + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_29 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableEvent(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->EMR, ExtiLine); +} + +/** + * @brief Indicate if ExtiLine Event request is enabled for Lines + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @arg @ref LL_EXTI_LINE_19 + * @arg @ref LL_EXTI_LINE_29 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledEvent(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->EMR, ExtiLine) == (ExtiLine)); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Rising_Trigger_Management Rising_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Rising Edge Trigger for Lines + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableRisingTrig(uint32_t ExtiLine) +{ + SET_BIT(EXTI->RTSR, ExtiLine); + +} + +/** + * @brief Disable ExtiLine Rising Edge Trigger for Lines + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a rising edge on a configurable interrupt + * line occurs during a write operation in the EXTI_RTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableRisingTrig(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->RTSR, ExtiLine); + +} + + +/** + * @brief Check if rising edge trigger is enabled for Lines + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledRisingTrig(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->RTSR, ExtiLine) == (ExtiLine)); +} + + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Falling_Trigger_Management Falling_Trigger_Management + * @{ + */ + +/** + * @brief Enable ExtiLine Falling Edge Trigger for Lines + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for + * the same interrupt line. In this case, both generate a trigger + * condition. + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_EnableFallingTrig(uint32_t ExtiLine) +{ + SET_BIT(EXTI->FTSR, ExtiLine); +} + +/** + * @brief Disable ExtiLine Falling Edge Trigger for Lines + * @note The configurable wakeup lines are edge-triggered. No glitch must be + * generated on these lines. If a Falling edge on a configurable interrupt + * line occurs during a write operation in the EXTI_FTSR register, the + * pending bit is not set. + * Rising and falling edge triggers can be set for the same interrupt line. + * In this case, both generate a trigger condition. + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_DisableFallingTrig(uint32_t ExtiLine) +{ + CLEAR_BIT(EXTI->FTSR, ExtiLine); +} + +/** + * @brief Check if falling edge trigger is enabled for Lines + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsEnabledFallingTrig(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->FTSR, ExtiLine) == (ExtiLine)); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Software_Interrupt_Management Software_Interrupt_Management + * @{ + */ + +/** + * @brief Generate a software Interrupt Event for Lines + * @note If the interrupt is enabled on this line in the EXTI_IMR, writing a 1 to + * this bit when it is at '0' sets the corresponding pending bit in EXTI_PR + * resulting in an interrupt request generation. + * This bit is cleared by clearing the corresponding bit in the EXTI_PR + * register (by writing a 1 into the bit) + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_GenerateSWI(uint32_t ExtiLine) +{ + SET_BIT(EXTI->SWIER, ExtiLine); +} + +/** + * @} + */ + +/** @defgroup EXTI_LL_EF_Flag_Management Flag_Management + * @{ + */ + +/** + * @brief Check if the ExtLine Flag is set or not for Lines + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_EXTI_IsActiveFlag(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine) == (ExtiLine)); +} + +/** + * @brief Read ExtLine Combination Flag for Lines + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval @note This bit is set when the selected edge event arrives on the interrupt + */ +__STATIC_INLINE uint32_t LL_EXTI_ReadFlag(uint32_t ExtiLine) +{ + return (READ_BIT(EXTI->PR, ExtiLine)); +} + +/** + * @brief Clear ExtLine Flags for Lines + * @param ExtiLine This parameter can be a combination of the following values: + * @arg @ref LL_EXTI_LINE_0 + * @arg @ref LL_EXTI_LINE_1 + * @arg @ref LL_EXTI_LINE_2 + * @arg @ref LL_EXTI_LINE_3 + * @arg @ref LL_EXTI_LINE_4 + * @arg @ref LL_EXTI_LINE_5 + * @arg @ref LL_EXTI_LINE_6 + * @arg @ref LL_EXTI_LINE_7 + * @arg @ref LL_EXTI_LINE_8 + * @arg @ref LL_EXTI_LINE_9 + * @arg @ref LL_EXTI_LINE_10 + * @arg @ref LL_EXTI_LINE_11 + * @arg @ref LL_EXTI_LINE_12 + * @arg @ref LL_EXTI_LINE_13 + * @arg @ref LL_EXTI_LINE_14 + * @arg @ref LL_EXTI_LINE_15 + * @arg @ref LL_EXTI_LINE_16 + * @arg @ref LL_EXTI_LINE_17 + * @arg @ref LL_EXTI_LINE_18 + * @note Please check each device line mapping for EXTI Line availability + * @retval None + */ +__STATIC_INLINE void LL_EXTI_ClearFlag(uint32_t ExtiLine) +{ + WRITE_REG(EXTI->PR, ExtiLine); +} + +/** + * @brief Configure source input for the EXTI external interrupt. + * @param Port This parameter can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_PORTA + * @arg @ref LL_EXTI_CONFIG_PORTB + * @arg @ref LL_EXTI_CONFIG_PORTF + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_LINE0 + * @arg @ref LL_EXTI_CONFIG_LINE1 + * @arg @ref LL_EXTI_CONFIG_LINE2 + * @arg @ref LL_EXTI_CONFIG_LINE3 + * @arg @ref LL_EXTI_CONFIG_LINE4 + * @arg @ref LL_EXTI_CONFIG_LINE5 + * @arg @ref LL_EXTI_CONFIG_LINE6 + * @arg @ref LL_EXTI_CONFIG_LINE7 + * @arg @ref LL_EXTI_CONFIG_LINE8 + * @retval None + */ +__STATIC_INLINE void LL_EXTI_SetEXTISource(uint32_t Port, uint32_t Line) +{ + uint32_t mask = (Line >> LL_EXTI_REGISTER_PINMASK_SHFT) & 0xFF; + uint32_t pos = (Line >> LL_EXTI_REGISTER_PINPOS_SHFT) & 0xFF; + MODIFY_REG(EXTI->EXTICR[Line & 0x03u], (mask << pos), (Port << pos)); +} + +/** + * @brief Get the configured defined for specific EXTI Line + * @param Line This parameter can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_LINE0 + * @arg @ref LL_EXTI_CONFIG_LINE1 + * @arg @ref LL_EXTI_CONFIG_LINE2 + * @arg @ref LL_EXTI_CONFIG_LINE3 + * @arg @ref LL_EXTI_CONFIG_LINE4 + * @arg @ref LL_EXTI_CONFIG_LINE5 + * @arg @ref LL_EXTI_CONFIG_LINE6 + * @arg @ref LL_EXTI_CONFIG_LINE7 + * @arg @ref LL_EXTI_CONFIG_LINE8 + * @retval Returned value can be one of the following values: + * @arg @ref LL_EXTI_CONFIG_PORTA + * @arg @ref LL_EXTI_CONFIG_PORTB + * @arg @ref LL_EXTI_CONFIG_PORTF + */ +__STATIC_INLINE uint32_t LL_EXTI_GetEXTISource(uint32_t Line) +{ + uint32_t mask = (Line >> LL_EXTI_REGISTER_PINMASK_SHFT) & 0xFF; + uint32_t pos = (Line >> LL_EXTI_REGISTER_PINPOS_SHFT) & 0xFF; + return (READ_BIT(EXTI->EXTICR[Line & 0x03u], (mask << pos)) >> pos); +} + + +/** + * @} + */ +/** @defgroup EXTI_LL_EF_Config EF configuration functions + * @{ + */ + + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup EXTI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct); +uint32_t LL_EXTI_DeInit(void); +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* EXTI */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PY32F0XX_LL_EXTI_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_gpio.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_gpio.h similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_gpio.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_gpio.h index 38f41a8..83ac1ae 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_gpio.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_gpio.h @@ -1,1108 +1,1108 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_gpio.h - * @author MCU Application Team - * @brief Header file of GPIO LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PY32F0xx_LL_GPIO_H -#define __PY32F0xx_LL_GPIO_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOF) - -/** @defgroup GPIO_LL GPIO - * @{ - */ -/** MISRA C:2012 deviation rule has been granted for following rules: - * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] - * which may be out of array bounds [..,UNKNOWN] in following APIs: - * LL_GPIO_GetAFPin_0_7 - * LL_GPIO_SetAFPin_0_7 - * LL_GPIO_SetAFPin_8_15 - * LL_GPIO_GetAFPin_8_15 - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros - * @{ - */ - -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures - * @{ - */ - -/** - * @brief LL GPIO Init Structure definition - */ -typedef struct -{ - uint32_t Pin; /*!< Specifies the GPIO pins to be configured. - This parameter can be any value of @ref GPIO_LL_EC_PIN */ - - uint32_t Mode; /*!< Specifies the operating mode for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_MODE. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ - - uint32_t Speed; /*!< Specifies the speed for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_SPEED. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ - - uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ - - uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_PULL. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ - - uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. - This parameter can be a value of @ref GPIO_LL_EC_AF. - - GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ -} LL_GPIO_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants - * @{ - */ -#define LL_GPIO_LCKR_LCKK 0x00030000U - -/** @defgroup GPIO_LL_EC_PIN PIN - * @{ - */ -#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ -#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ -#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ -#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ -#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ -#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ -#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ -#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ -#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ -#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ -#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ -#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ -#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ -#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ -#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ -#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ -#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ - GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ - GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ - GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ - GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ - GPIO_BSRR_BS15) /*!< Select all pins */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_MODE Mode - * @{ - */ -#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ -#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ -#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ -#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_OUTPUT Output Type - * @{ - */ -#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ -#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_SPEED Output Speed - * @{ - */ -#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ -#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ -#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ -#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down - * @{ - */ -#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ -#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ -#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ -/** - * @} - */ - -/** @defgroup GPIO_LL_EC_AF Alternate Function - * @{ - */ -#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ -#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ -#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ -#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ -#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ -#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ -#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ -#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ -#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ -#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ -#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ -#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ -#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ -#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ -#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ -#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ - -/** - * @} - */ - -/** @defgroup GPIO_LL_Alternate_function_selection Alternate function selection - * @{ - */ - -/** - * @brief AF 0 selection - */ - -#define LL_GPIO_AF0_SWJ LL_GPIO_AF_0 /*!< SWJ (SWD) Alternate Function mapping */ -#define LL_GPIO_AF0_SPI1 LL_GPIO_AF_0 /*!< SPI1 Alternate Function mapping */ -#define LL_GPIO_AF0_SPI2 LL_GPIO_AF_0 /*!< SPI2 Alternate Function mapping */ -#define LL_GPIO_AF0_TIM14 LL_GPIO_AF_0 /*!< TIM14 Alternate Function mapping */ -#define LL_GPIO_AF0_USART1 LL_GPIO_AF_0 /*!< USART1 Alternate Function mapping */ - -/** - * @brief AF 1 selection - */ -#define LL_GPIO_AF1_IR LL_GPIO_AF_1 /*!< IR Alternate Function mapping */ -#define LL_GPIO_AF1_SPI2 LL_GPIO_AF_1 /*!< SPI2 Alternate Function mapping */ -#define LL_GPIO_AF1_TIM1 LL_GPIO_AF_1 /*!< TIM1 Alternate Function mapping */ -#define LL_GPIO_AF1_TIM3 LL_GPIO_AF_1 /*!< TIM3 Alternate Function mapping */ -#define LL_GPIO_AF1_USART1 LL_GPIO_AF_1 /*!< USART1 Alternate Function mapping */ - -/** - * @brief AF 2 selection - */ -#define LL_GPIO_AF2_SPI2 LL_GPIO_AF_2 /*!< SPI2 Alternate Function mapping */ -#define LL_GPIO_AF2_TIM1 LL_GPIO_AF_2 /*!< TIM1 Alternate Function mapping */ -#define LL_GPIO_AF2_TIM14 LL_GPIO_AF_2 /*!< TIM14 Alternate Function mapping */ -#define LL_GPIO_AF2_TIM16 LL_GPIO_AF_2 /*!< TIM16 Alternate Function mapping */ -#define LL_GPIO_AF2_TIM17 LL_GPIO_AF_2 /*!< TIM17 Alternate Function mapping */ - -/** - * @brief AF 3 selection - */ -#define LL_GPIO_AF3_LED LL_GPIO_AF_3 /*!< AF3: LED Alternate Function mapping*/ -#define LL_GPIO_AF3_USART1 LL_GPIO_AF_3 /*!< AF3: USART1 Alternate Function mapping*/ -#define LL_GPIO_AF3_USART2 LL_GPIO_AF_3 /*!< AF3: USART2 Alternate Function mapping*/ -#define LL_GPIO_AF3_SPI2 LL_GPIO_AF_3 /*!< AF3: SPI2 Alternate Function mapping*/ - -/** - * @brief AF 4 selection - */ -#define LL_GPIO_AF4_TIM14 LL_GPIO_AF_4 /*!< TIM14 Alternate Function mapping*/ -#define LL_GPIO_AF4_USART2 LL_GPIO_AF_4 /*!< USART2 Alternate Function mapping*/ - -/** - * @brief AF 5 selection - */ -#define LL_GPIO_AF5_LPTIM LL_GPIO_AF_5 /*!< LPTIM1 Alternate Function mapping*/ -#define LL_GPIO_AF5_USART2 LL_GPIO_AF_5 /*!< USART2 Alternate Function mapping*/ -#define LL_GPIO_AF5_EVENTOUT LL_GPIO_AF_5 /*!< EVENTOUT Alternate Function mapping*/ -#define LL_GPIO_AF5_TIM16 LL_GPIO_AF_5 /*!< TIM16 Alternate Function mapping*/ -#define LL_GPIO_AF5_TIM17 LL_GPIO_AF_5 /*!< TIM17 Alternate Function mapping*/ -#define LL_GPIO_AF5_MCO LL_GPIO_AF_5 /*!< MCO Alternate Function mapping*/ - -/** - * @brief AF 6 selection - */ -#define LL_GPIO_AF6_I2C LL_GPIO_AF_6 /*!< I2C1 Alternate Function mapping */ -#define LL_GPIO_AF6_LED LL_GPIO_AF_6 /*!< AF6: LED Alternate Function mapping*/ -#define LL_GPIO_AF6_MCO LL_GPIO_AF_6 /*!< MCO Alternate Function mapping */ -#define LL_GPIO_AF6_EVENTOUT LL_GPIO_AF_6 /*!< AF6: EVENTOUT Alternate Function mapping*/ - -/** - * @brief AF 7 selection - */ -#define LL_GPIO_AF7_EVENTOUT LL_GPIO_AF_7 /*!< EVENTOUT Alternate Function mapping */ -#define LL_GPIO_AF7_COMP1 LL_GPIO_AF_7 /*!< AF7: COMP1 Alternate Function mapping*/ -#define LL_GPIO_AF7_COMP2 LL_GPIO_AF_7 /*!< AF7: COMP2 Alternate Function mapping*/ - -/** - * @brief AF 8 selection - */ -#define LL_GPIO_AF8_USART1 LL_GPIO_AF_8 /*!< AF8: USART1 Alternate Function mapping*/ - -/** - * @brief AF 9 selection - */ -#define LL_GPIO_AF9_USART2 LL_GPIO_AF_9 /*!< USART2 Alternate Function mapping*/ - -/** - * @brief AF 10 selection - */ -#define LL_GPIO_AF10_SPI1 LL_GPIO_AF_10 /*!< SPI2 Alternate Function mapping*/ - -/** - * @brief AF 11 selection - */ -#define LL_GPIO_AF11_SPI2 LL_GPIO_AF_11 /*!< SPI2 Alternate Function mapping*/ - -/** - * @brief AF 12 selection - */ -#define LL_GPIO_AF12_I2C LL_GPIO_AF_12 /*!< I2C1 Alternate Function mapping*/ - -/** - * @brief AF 13 selection - */ -#define LL_GPIO_AF13_TIM1 LL_GPIO_AF_13 /*!< TIM1 Alternate Function mapping*/ -#define LL_GPIO_AF13_TIM3 LL_GPIO_AF_13 /*!< TIM3 Alternate Function mapping*/ -#define LL_GPIO_AF13_TIM14 LL_GPIO_AF_13 /*!< TIM14 Alternate Function mapping*/ -#define LL_GPIO_AF13_TIM17 LL_GPIO_AF_13 /*!< TIM17 Alternate Function mapping*/ - -/** - * @brief AF 14 selection - */ -#define LL_GPIO_AF14_TIM1 LL_GPIO_AF_14 /*!< TIM1 Alternate Function mapping*/ - -/** - * @brief AF 15 selection - */ -#define LL_GPIO_AF15_RTCOUT LL_GPIO_AF_15 -#define LL_GPIO_AF15_MCO LL_GPIO_AF_15 /*!< MCO Alternate Function mapping*/ -#define LL_GPIO_AF15_IR LL_GPIO_AF_15 /*!< IR Alternate Function mapping*/ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros - * @{ - */ - -/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in GPIO register - * @param __INSTANCE__ GPIO Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions - * @{ - */ - -/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration - * @{ - */ - -/** - * @brief Configure gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_SetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) -{ - MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); -} - -/** - * @brief Return gpio mode for a dedicated pin on dedicated port. - * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll MODER MODEy LL_GPIO_GetPinMode - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_MODE_INPUT - * @arg @ref LL_GPIO_MODE_OUTPUT - * @arg @ref LL_GPIO_MODE_ALTERNATE - * @arg @ref LL_GPIO_MODE_ANALOG - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); -} - -/** - * @brief Configure gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @param OutputType This parameter can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) -{ - MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); -} - -/** - * @brief Return gpio output type for several pins on dedicated port. - * @note Output type as to be set when gpio pin is in output or - * alternate modes. Possible type are Push-pull or Open-drain. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_OUTPUT_PUSHPULL - * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); -} - -/** - * @brief Configure gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, High or Very High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Speed This parameter can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) -{ - MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed)); -} - -/** - * @brief Return gpio speed for a dedicated pin on dedicated port. - * @note I/O speed can be Low, Medium, High or Very High speed. - * @note Warning: only one pin can be passed as parameter. - * @note Refer to datasheet for frequency specifications and the power - * supply and load conditions for each speed. - * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_SPEED_FREQ_LOW - * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM - * @arg @ref LL_GPIO_SPEED_FREQ_HIGH - * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); -} - -/** - * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Pull This parameter can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) -{ - MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); -} - -/** - * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port - * @note Warning: only one pin can be passed as parameter. - * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_PULL_NO - * @arg @ref LL_GPIO_PULL_UP - * @arg @ref LL_GPIO_PULL_DOWN - */ -__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @note Possible values are from AF0 to AF7 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), - ((((Pin * Pin) * Pin) * Pin) * Alternate)); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. - * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[0], - ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); -} - -/** - * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF7 depending on target. - * @note Warning: only one pin can be passed as parameter. - * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @param Alternate This parameter can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) -{ - MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), - (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); -} - -/** - * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. - * @note Possible values are from AF0 to AF7 depending on target. - * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 - * @param GPIOx GPIO Port - * @param Pin This parameter can be one of the following values: - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @retval Returned value can be one of the following values: - * @arg @ref LL_GPIO_AF_0 - * @arg @ref LL_GPIO_AF_1 - * @arg @ref LL_GPIO_AF_2 - * @arg @ref LL_GPIO_AF_3 - * @arg @ref LL_GPIO_AF_4 - * @arg @ref LL_GPIO_AF_5 - * @arg @ref LL_GPIO_AF_6 - * @arg @ref LL_GPIO_AF_7 - * @arg @ref LL_GPIO_AF_8 - * @arg @ref LL_GPIO_AF_9 - * @arg @ref LL_GPIO_AF_10 - * @arg @ref LL_GPIO_AF_11 - * @arg @ref LL_GPIO_AF_12 - * @arg @ref LL_GPIO_AF_13 - * @arg @ref LL_GPIO_AF_14 - * @arg @ref LL_GPIO_AF_15 - */ -__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) -{ - return (uint32_t)(READ_BIT(GPIOx->AFR[1], - (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / - ((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); -} - - -/** - * @brief Lock configuration of several pins for a dedicated port. - * @note When the lock sequence has been applied on a port bit, the - * value of this port bit can no longer be modified until the - * next reset. - * @note Each lock bit freezes a specific configuration register - * (control and alternate function registers). - * @rmtoll LCKR LCKK LL_GPIO_LockPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - __IO uint32_t temp; - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - WRITE_REG(GPIOx->LCKR, PinMask); - WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); - /* Read LCKK register. This read is mandatory to complete key lock sequence */ - temp = READ_REG(GPIOx->LCKR); - (void) temp; -} - -/** - * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. - * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); -} - -/** - * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. - * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked - * @param GPIOx GPIO Port - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) -{ - return (READ_BIT(GPIOx->LCKR, LL_GPIO_LCKR_LCKK) != 0U); -} - -/** - * @} - */ - -/** @defgroup GPIO_LL_EF_Data_Access Data Access - * @{ - */ - -/** - * @brief Return full input data register value for a dedicated port. - * @rmtoll IDR IDy LL_GPIO_ReadInputPort - * @param GPIOx GPIO Port - * @retval Input data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->IDR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll IDR IDy LL_GPIO_IsInputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); -} - -/** - * @brief Write output data register for the port. - * @rmtoll ODR ODy LL_GPIO_WriteOutputPort - * @param GPIOx GPIO Port - * @param PortValue Level value for each pin of the port - * @retval None - */ -__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) -{ - WRITE_REG(GPIOx->ODR, PortValue); -} - -/** - * @brief Return full output data register value for a dedicated port. - * @rmtoll ODR ODy LL_GPIO_ReadOutputPort - * @param GPIOx GPIO Port - * @retval Output data register value of port - */ -__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) -{ - return (uint32_t)(READ_REG(GPIOx->ODR)); -} - -/** - * @brief Return if input data level for several pins of dedicated port is high or low. - * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); -} - -/** - * @brief Set several pins to high level on dedicated gpio port. - * @rmtoll BSRR BSy LL_GPIO_SetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BSRR, PinMask); -} - -/** - * @brief Set several pins to low level on dedicated gpio port. - * @rmtoll BRR BRy LL_GPIO_ResetOutputPin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->BRR, PinMask); -} - -/** - * @brief Toggle data value for several pin of dedicated port. - * @rmtoll ODR ODy LL_GPIO_TogglePin - * @param GPIOx GPIO Port - * @param PinMask This parameter can be a combination of the following values: - * @arg @ref LL_GPIO_PIN_0 - * @arg @ref LL_GPIO_PIN_1 - * @arg @ref LL_GPIO_PIN_2 - * @arg @ref LL_GPIO_PIN_3 - * @arg @ref LL_GPIO_PIN_4 - * @arg @ref LL_GPIO_PIN_5 - * @arg @ref LL_GPIO_PIN_6 - * @arg @ref LL_GPIO_PIN_7 - * @arg @ref LL_GPIO_PIN_8 - * @arg @ref LL_GPIO_PIN_9 - * @arg @ref LL_GPIO_PIN_10 - * @arg @ref LL_GPIO_PIN_11 - * @arg @ref LL_GPIO_PIN_12 - * @arg @ref LL_GPIO_PIN_13 - * @arg @ref LL_GPIO_PIN_14 - * @arg @ref LL_GPIO_PIN_15 - * @arg @ref LL_GPIO_PIN_ALL - * @retval None - */ -__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) -{ - WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOF) */ -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PY32F0xx_LL_GPIO_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_gpio.h + * @author MCU Application Team + * @brief Header file of GPIO LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32F0xx_LL_GPIO_H +#define __PY32F0xx_LL_GPIO_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOF) + +/** @defgroup GPIO_LL GPIO + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-18.1_d - Medium: Array pointer `GPIOx' is accessed with index [..,..] + * which may be out of array bounds [..,UNKNOWN] in following APIs: + * LL_GPIO_GetAFPin_0_7 + * LL_GPIO_SetAFPin_0_7 + * LL_GPIO_SetAFPin_8_15 + * LL_GPIO_GetAFPin_8_15 + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_Private_Macros GPIO Private Macros + * @{ + */ + +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_ES_INIT GPIO Exported Init structures + * @{ + */ + +/** + * @brief LL GPIO Init Structure definition + */ +typedef struct +{ + uint32_t Pin; /*!< Specifies the GPIO pins to be configured. + This parameter can be any value of @ref GPIO_LL_EC_PIN */ + + uint32_t Mode; /*!< Specifies the operating mode for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_MODE. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinMode().*/ + + uint32_t Speed; /*!< Specifies the speed for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_SPEED. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinSpeed().*/ + + uint32_t OutputType; /*!< Specifies the operating output type for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_OUTPUT. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinOutputType().*/ + + uint32_t Pull; /*!< Specifies the operating Pull-up/Pull down for the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_PULL. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetPinPull().*/ + + uint32_t Alternate; /*!< Specifies the Peripheral to be connected to the selected pins. + This parameter can be a value of @ref GPIO_LL_EC_AF. + + GPIO HW configuration can be modified afterwards using unitary function @ref LL_GPIO_SetAFPin_0_7() and LL_GPIO_SetAFPin_8_15().*/ +} LL_GPIO_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Constants GPIO Exported Constants + * @{ + */ +#define LL_GPIO_LCKR_LCKK 0x00030000U + +/** @defgroup GPIO_LL_EC_PIN PIN + * @{ + */ +#define LL_GPIO_PIN_0 GPIO_BSRR_BS0 /*!< Select pin 0 */ +#define LL_GPIO_PIN_1 GPIO_BSRR_BS1 /*!< Select pin 1 */ +#define LL_GPIO_PIN_2 GPIO_BSRR_BS2 /*!< Select pin 2 */ +#define LL_GPIO_PIN_3 GPIO_BSRR_BS3 /*!< Select pin 3 */ +#define LL_GPIO_PIN_4 GPIO_BSRR_BS4 /*!< Select pin 4 */ +#define LL_GPIO_PIN_5 GPIO_BSRR_BS5 /*!< Select pin 5 */ +#define LL_GPIO_PIN_6 GPIO_BSRR_BS6 /*!< Select pin 6 */ +#define LL_GPIO_PIN_7 GPIO_BSRR_BS7 /*!< Select pin 7 */ +#define LL_GPIO_PIN_8 GPIO_BSRR_BS8 /*!< Select pin 8 */ +#define LL_GPIO_PIN_9 GPIO_BSRR_BS9 /*!< Select pin 9 */ +#define LL_GPIO_PIN_10 GPIO_BSRR_BS10 /*!< Select pin 10 */ +#define LL_GPIO_PIN_11 GPIO_BSRR_BS11 /*!< Select pin 11 */ +#define LL_GPIO_PIN_12 GPIO_BSRR_BS12 /*!< Select pin 12 */ +#define LL_GPIO_PIN_13 GPIO_BSRR_BS13 /*!< Select pin 13 */ +#define LL_GPIO_PIN_14 GPIO_BSRR_BS14 /*!< Select pin 14 */ +#define LL_GPIO_PIN_15 GPIO_BSRR_BS15 /*!< Select pin 15 */ +#define LL_GPIO_PIN_ALL (GPIO_BSRR_BS0 | GPIO_BSRR_BS1 | GPIO_BSRR_BS2 | \ + GPIO_BSRR_BS3 | GPIO_BSRR_BS4 | GPIO_BSRR_BS5 | \ + GPIO_BSRR_BS6 | GPIO_BSRR_BS7 | GPIO_BSRR_BS8 | \ + GPIO_BSRR_BS9 | GPIO_BSRR_BS10 | GPIO_BSRR_BS11 | \ + GPIO_BSRR_BS12 | GPIO_BSRR_BS13 | GPIO_BSRR_BS14 | \ + GPIO_BSRR_BS15) /*!< Select all pins */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_MODE Mode + * @{ + */ +#define LL_GPIO_MODE_INPUT (0x00000000U) /*!< Select input mode */ +#define LL_GPIO_MODE_OUTPUT GPIO_MODER_MODE0_0 /*!< Select output mode */ +#define LL_GPIO_MODE_ALTERNATE GPIO_MODER_MODE0_1 /*!< Select alternate function mode */ +#define LL_GPIO_MODE_ANALOG GPIO_MODER_MODE0 /*!< Select analog mode */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_OUTPUT Output Type + * @{ + */ +#define LL_GPIO_OUTPUT_PUSHPULL (0x00000000U) /*!< Select push-pull as output type */ +#define LL_GPIO_OUTPUT_OPENDRAIN GPIO_OTYPER_OT0 /*!< Select open-drain as output type */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_SPEED Output Speed + * @{ + */ +#define LL_GPIO_SPEED_FREQ_LOW (0x00000000U) /*!< Select I/O low output speed */ +#define LL_GPIO_SPEED_FREQ_MEDIUM GPIO_OSPEEDR_OSPEED0_0 /*!< Select I/O medium output speed */ +#define LL_GPIO_SPEED_FREQ_HIGH GPIO_OSPEEDR_OSPEED0_1 /*!< Select I/O fast output speed */ +#define LL_GPIO_SPEED_FREQ_VERY_HIGH GPIO_OSPEEDR_OSPEED0 /*!< Select I/O high output speed */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_PULL Pull Up Pull Down + * @{ + */ +#define LL_GPIO_PULL_NO (0x00000000U) /*!< Select I/O no pull */ +#define LL_GPIO_PULL_UP GPIO_PUPDR_PUPD0_0 /*!< Select I/O pull up */ +#define LL_GPIO_PULL_DOWN GPIO_PUPDR_PUPD0_1 /*!< Select I/O pull down */ +/** + * @} + */ + +/** @defgroup GPIO_LL_EC_AF Alternate Function + * @{ + */ +#define LL_GPIO_AF_0 (0x0000000U) /*!< Select alternate function 0 */ +#define LL_GPIO_AF_1 (0x0000001U) /*!< Select alternate function 1 */ +#define LL_GPIO_AF_2 (0x0000002U) /*!< Select alternate function 2 */ +#define LL_GPIO_AF_3 (0x0000003U) /*!< Select alternate function 3 */ +#define LL_GPIO_AF_4 (0x0000004U) /*!< Select alternate function 4 */ +#define LL_GPIO_AF_5 (0x0000005U) /*!< Select alternate function 5 */ +#define LL_GPIO_AF_6 (0x0000006U) /*!< Select alternate function 6 */ +#define LL_GPIO_AF_7 (0x0000007U) /*!< Select alternate function 7 */ +#define LL_GPIO_AF_8 (0x0000008U) /*!< Select alternate function 8 */ +#define LL_GPIO_AF_9 (0x0000009U) /*!< Select alternate function 9 */ +#define LL_GPIO_AF_10 (0x000000AU) /*!< Select alternate function 10 */ +#define LL_GPIO_AF_11 (0x000000BU) /*!< Select alternate function 11 */ +#define LL_GPIO_AF_12 (0x000000CU) /*!< Select alternate function 12 */ +#define LL_GPIO_AF_13 (0x000000DU) /*!< Select alternate function 13 */ +#define LL_GPIO_AF_14 (0x000000EU) /*!< Select alternate function 14 */ +#define LL_GPIO_AF_15 (0x000000FU) /*!< Select alternate function 15 */ + +/** + * @} + */ + +/** @defgroup GPIO_LL_Alternate_function_selection Alternate function selection + * @{ + */ + +/** + * @brief AF 0 selection + */ + +#define LL_GPIO_AF0_SWJ LL_GPIO_AF_0 /*!< SWJ (SWD) Alternate Function mapping */ +#define LL_GPIO_AF0_SPI1 LL_GPIO_AF_0 /*!< SPI1 Alternate Function mapping */ +#define LL_GPIO_AF0_SPI2 LL_GPIO_AF_0 /*!< SPI2 Alternate Function mapping */ +#define LL_GPIO_AF0_TIM14 LL_GPIO_AF_0 /*!< TIM14 Alternate Function mapping */ +#define LL_GPIO_AF0_USART1 LL_GPIO_AF_0 /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 1 selection + */ +#define LL_GPIO_AF1_IR LL_GPIO_AF_1 /*!< IR Alternate Function mapping */ +#define LL_GPIO_AF1_SPI2 LL_GPIO_AF_1 /*!< SPI2 Alternate Function mapping */ +#define LL_GPIO_AF1_TIM1 LL_GPIO_AF_1 /*!< TIM1 Alternate Function mapping */ +#define LL_GPIO_AF1_TIM3 LL_GPIO_AF_1 /*!< TIM3 Alternate Function mapping */ +#define LL_GPIO_AF1_USART1 LL_GPIO_AF_1 /*!< USART1 Alternate Function mapping */ + +/** + * @brief AF 2 selection + */ +#define LL_GPIO_AF2_SPI2 LL_GPIO_AF_2 /*!< SPI2 Alternate Function mapping */ +#define LL_GPIO_AF2_TIM1 LL_GPIO_AF_2 /*!< TIM1 Alternate Function mapping */ +#define LL_GPIO_AF2_TIM14 LL_GPIO_AF_2 /*!< TIM14 Alternate Function mapping */ +#define LL_GPIO_AF2_TIM16 LL_GPIO_AF_2 /*!< TIM16 Alternate Function mapping */ +#define LL_GPIO_AF2_TIM17 LL_GPIO_AF_2 /*!< TIM17 Alternate Function mapping */ + +/** + * @brief AF 3 selection + */ +#define LL_GPIO_AF3_LED LL_GPIO_AF_3 /*!< AF3: LED Alternate Function mapping*/ +#define LL_GPIO_AF3_USART1 LL_GPIO_AF_3 /*!< AF3: USART1 Alternate Function mapping*/ +#define LL_GPIO_AF3_USART2 LL_GPIO_AF_3 /*!< AF3: USART2 Alternate Function mapping*/ +#define LL_GPIO_AF3_SPI2 LL_GPIO_AF_3 /*!< AF3: SPI2 Alternate Function mapping*/ + +/** + * @brief AF 4 selection + */ +#define LL_GPIO_AF4_TIM14 LL_GPIO_AF_4 /*!< TIM14 Alternate Function mapping*/ +#define LL_GPIO_AF4_USART2 LL_GPIO_AF_4 /*!< USART2 Alternate Function mapping*/ + +/** + * @brief AF 5 selection + */ +#define LL_GPIO_AF5_LPTIM LL_GPIO_AF_5 /*!< LPTIM1 Alternate Function mapping*/ +#define LL_GPIO_AF5_USART2 LL_GPIO_AF_5 /*!< USART2 Alternate Function mapping*/ +#define LL_GPIO_AF5_EVENTOUT LL_GPIO_AF_5 /*!< EVENTOUT Alternate Function mapping*/ +#define LL_GPIO_AF5_TIM16 LL_GPIO_AF_5 /*!< TIM16 Alternate Function mapping*/ +#define LL_GPIO_AF5_TIM17 LL_GPIO_AF_5 /*!< TIM17 Alternate Function mapping*/ +#define LL_GPIO_AF5_MCO LL_GPIO_AF_5 /*!< MCO Alternate Function mapping*/ + +/** + * @brief AF 6 selection + */ +#define LL_GPIO_AF6_I2C LL_GPIO_AF_6 /*!< I2C1 Alternate Function mapping */ +#define LL_GPIO_AF6_LED LL_GPIO_AF_6 /*!< AF6: LED Alternate Function mapping*/ +#define LL_GPIO_AF6_MCO LL_GPIO_AF_6 /*!< MCO Alternate Function mapping */ +#define LL_GPIO_AF6_EVENTOUT LL_GPIO_AF_6 /*!< AF6: EVENTOUT Alternate Function mapping*/ + +/** + * @brief AF 7 selection + */ +#define LL_GPIO_AF7_EVENTOUT LL_GPIO_AF_7 /*!< EVENTOUT Alternate Function mapping */ +#define LL_GPIO_AF7_COMP1 LL_GPIO_AF_7 /*!< AF7: COMP1 Alternate Function mapping*/ +#define LL_GPIO_AF7_COMP2 LL_GPIO_AF_7 /*!< AF7: COMP2 Alternate Function mapping*/ + +/** + * @brief AF 8 selection + */ +#define LL_GPIO_AF8_USART1 LL_GPIO_AF_8 /*!< AF8: USART1 Alternate Function mapping*/ + +/** + * @brief AF 9 selection + */ +#define LL_GPIO_AF9_USART2 LL_GPIO_AF_9 /*!< USART2 Alternate Function mapping*/ + +/** + * @brief AF 10 selection + */ +#define LL_GPIO_AF10_SPI1 LL_GPIO_AF_10 /*!< SPI2 Alternate Function mapping*/ + +/** + * @brief AF 11 selection + */ +#define LL_GPIO_AF11_SPI2 LL_GPIO_AF_11 /*!< SPI2 Alternate Function mapping*/ + +/** + * @brief AF 12 selection + */ +#define LL_GPIO_AF12_I2C LL_GPIO_AF_12 /*!< I2C1 Alternate Function mapping*/ + +/** + * @brief AF 13 selection + */ +#define LL_GPIO_AF13_TIM1 LL_GPIO_AF_13 /*!< TIM1 Alternate Function mapping*/ +#define LL_GPIO_AF13_TIM3 LL_GPIO_AF_13 /*!< TIM3 Alternate Function mapping*/ +#define LL_GPIO_AF13_TIM14 LL_GPIO_AF_13 /*!< TIM14 Alternate Function mapping*/ +#define LL_GPIO_AF13_TIM17 LL_GPIO_AF_13 /*!< TIM17 Alternate Function mapping*/ + +/** + * @brief AF 14 selection + */ +#define LL_GPIO_AF14_TIM1 LL_GPIO_AF_14 /*!< TIM1 Alternate Function mapping*/ + +/** + * @brief AF 15 selection + */ +#define LL_GPIO_AF15_RTCOUT LL_GPIO_AF_15 +#define LL_GPIO_AF15_MCO LL_GPIO_AF_15 /*!< MCO Alternate Function mapping*/ +#define LL_GPIO_AF15_IR LL_GPIO_AF_15 /*!< IR Alternate Function mapping*/ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Macros GPIO Exported Macros + * @{ + */ + +/** @defgroup GPIO_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_GPIO_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in GPIO register + * @param __INSTANCE__ GPIO Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_GPIO_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup GPIO_LL_Exported_Functions GPIO Exported Functions + * @{ + */ + +/** @defgroup GPIO_LL_EF_Port_Configuration Port Configuration + * @{ + */ + +/** + * @brief Configure gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_SetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Mode) +{ + MODIFY_REG(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0), ((Pin * Pin) * Mode)); +} + +/** + * @brief Return gpio mode for a dedicated pin on dedicated port. + * @note I/O mode can be Input mode, General purpose output, Alternate function mode or Analog. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll MODER MODEy LL_GPIO_GetPinMode + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_MODE_INPUT + * @arg @ref LL_GPIO_MODE_OUTPUT + * @arg @ref LL_GPIO_MODE_ALTERNATE + * @arg @ref LL_GPIO_MODE_ANALOG + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinMode(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->MODER, ((Pin * Pin) * GPIO_MODER_MODE0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @rmtoll OTYPER OTy LL_GPIO_SetPinOutputType + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @param OutputType This parameter can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t PinMask, uint32_t OutputType) +{ + MODIFY_REG(GPIOx->OTYPER, PinMask, (PinMask * OutputType)); +} + +/** + * @brief Return gpio output type for several pins on dedicated port. + * @note Output type as to be set when gpio pin is in output or + * alternate modes. Possible type are Push-pull or Open-drain. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll OTYPER OTy LL_GPIO_GetPinOutputType + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_OUTPUT_PUSHPULL + * @arg @ref LL_GPIO_OUTPUT_OPENDRAIN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinOutputType(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OTYPER, Pin) / Pin); +} + +/** + * @brief Configure gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, High or Very High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_SetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Speed This parameter can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Speed) +{ + MODIFY_REG(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0), ((Pin * Pin) * Speed)); +} + +/** + * @brief Return gpio speed for a dedicated pin on dedicated port. + * @note I/O speed can be Low, Medium, High or Very High speed. + * @note Warning: only one pin can be passed as parameter. + * @note Refer to datasheet for frequency specifications and the power + * supply and load conditions for each speed. + * @rmtoll OSPEEDR OSPEEDy LL_GPIO_GetPinSpeed + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_SPEED_FREQ_LOW + * @arg @ref LL_GPIO_SPEED_FREQ_MEDIUM + * @arg @ref LL_GPIO_SPEED_FREQ_HIGH + * @arg @ref LL_GPIO_SPEED_FREQ_VERY_HIGH + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinSpeed(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->OSPEEDR, ((Pin * Pin) * GPIO_OSPEEDR_OSPEED0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio pull-up or pull-down for a dedicated pin on a dedicated port. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_SetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Pull This parameter can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Pull) +{ + MODIFY_REG(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0), ((Pin * Pin) * Pull)); +} + +/** + * @brief Return gpio pull-up or pull-down for a dedicated pin on a dedicated port + * @note Warning: only one pin can be passed as parameter. + * @rmtoll PUPDR PUPDy LL_GPIO_GetPinPull + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_PULL_NO + * @arg @ref LL_GPIO_PULL_UP + * @arg @ref LL_GPIO_PULL_DOWN + */ +__STATIC_INLINE uint32_t LL_GPIO_GetPinPull(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->PUPDR, ((Pin * Pin) * GPIO_PUPDR_PUPD0)) / (Pin * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRL AFSELy LL_GPIO_SetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[0], ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0), + ((((Pin * Pin) * Pin) * Pin) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 0 to 7 for a dedicated port. + * @rmtoll AFRL AFSELy LL_GPIO_GetAFPin_0_7 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_0_7(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[0], + ((((Pin * Pin) * Pin) * Pin) * GPIO_AFRL_AFSEL0)) / (((Pin * Pin) * Pin) * Pin)); +} + +/** + * @brief Configure gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @note Warning: only one pin can be passed as parameter. + * @rmtoll AFRH AFSELy LL_GPIO_SetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @param Alternate This parameter can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin, uint32_t Alternate) +{ + MODIFY_REG(GPIOx->AFR[1], (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8), + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * Alternate)); +} + +/** + * @brief Return gpio alternate function of a dedicated pin from 8 to 15 for a dedicated port. + * @note Possible values are from AF0 to AF7 depending on target. + * @rmtoll AFRH AFSELy LL_GPIO_GetAFPin_8_15 + * @param GPIOx GPIO Port + * @param Pin This parameter can be one of the following values: + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @retval Returned value can be one of the following values: + * @arg @ref LL_GPIO_AF_0 + * @arg @ref LL_GPIO_AF_1 + * @arg @ref LL_GPIO_AF_2 + * @arg @ref LL_GPIO_AF_3 + * @arg @ref LL_GPIO_AF_4 + * @arg @ref LL_GPIO_AF_5 + * @arg @ref LL_GPIO_AF_6 + * @arg @ref LL_GPIO_AF_7 + * @arg @ref LL_GPIO_AF_8 + * @arg @ref LL_GPIO_AF_9 + * @arg @ref LL_GPIO_AF_10 + * @arg @ref LL_GPIO_AF_11 + * @arg @ref LL_GPIO_AF_12 + * @arg @ref LL_GPIO_AF_13 + * @arg @ref LL_GPIO_AF_14 + * @arg @ref LL_GPIO_AF_15 + */ +__STATIC_INLINE uint32_t LL_GPIO_GetAFPin_8_15(GPIO_TypeDef *GPIOx, uint32_t Pin) +{ + return (uint32_t)(READ_BIT(GPIOx->AFR[1], + (((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U)) * GPIO_AFRH_AFSEL8)) / + ((((Pin >> 8U) * (Pin >> 8U)) * (Pin >> 8U)) * (Pin >> 8U))); +} + + +/** + * @brief Lock configuration of several pins for a dedicated port. + * @note When the lock sequence has been applied on a port bit, the + * value of this port bit can no longer be modified until the + * next reset. + * @note Each lock bit freezes a specific configuration register + * (control and alternate function registers). + * @rmtoll LCKR LCKK LL_GPIO_LockPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_LockPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + __IO uint32_t temp; + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + WRITE_REG(GPIOx->LCKR, PinMask); + WRITE_REG(GPIOx->LCKR, GPIO_LCKR_LCKK | PinMask); + /* Read LCKK register. This read is mandatory to complete key lock sequence */ + temp = READ_REG(GPIOx->LCKR); + (void) temp; +} + +/** + * @brief Return 1 if all pins passed as parameter, of a dedicated port, are locked. else Return 0. + * @rmtoll LCKR LCKy LL_GPIO_IsPinLocked + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsPinLocked(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->LCKR, PinMask) == (PinMask)); +} + +/** + * @brief Return 1 if one of the pin of a dedicated port is locked. else return 0. + * @rmtoll LCKR LCKK LL_GPIO_IsAnyPinLocked + * @param GPIOx GPIO Port + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsAnyPinLocked(GPIO_TypeDef *GPIOx) +{ + return (READ_BIT(GPIOx->LCKR, LL_GPIO_LCKR_LCKK) != 0U); +} + +/** + * @} + */ + +/** @defgroup GPIO_LL_EF_Data_Access Data Access + * @{ + */ + +/** + * @brief Return full input data register value for a dedicated port. + * @rmtoll IDR IDy LL_GPIO_ReadInputPort + * @param GPIOx GPIO Port + * @retval Input data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadInputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->IDR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll IDR IDy LL_GPIO_IsInputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsInputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->IDR, PinMask) == (PinMask)); +} + +/** + * @brief Write output data register for the port. + * @rmtoll ODR ODy LL_GPIO_WriteOutputPort + * @param GPIOx GPIO Port + * @param PortValue Level value for each pin of the port + * @retval None + */ +__STATIC_INLINE void LL_GPIO_WriteOutputPort(GPIO_TypeDef *GPIOx, uint32_t PortValue) +{ + WRITE_REG(GPIOx->ODR, PortValue); +} + +/** + * @brief Return full output data register value for a dedicated port. + * @rmtoll ODR ODy LL_GPIO_ReadOutputPort + * @param GPIOx GPIO Port + * @retval Output data register value of port + */ +__STATIC_INLINE uint32_t LL_GPIO_ReadOutputPort(GPIO_TypeDef *GPIOx) +{ + return (uint32_t)(READ_REG(GPIOx->ODR)); +} + +/** + * @brief Return if input data level for several pins of dedicated port is high or low. + * @rmtoll ODR ODy LL_GPIO_IsOutputPinSet + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_GPIO_IsOutputPinSet(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + return (READ_BIT(GPIOx->ODR, PinMask) == (PinMask)); +} + +/** + * @brief Set several pins to high level on dedicated gpio port. + * @rmtoll BSRR BSy LL_GPIO_SetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_SetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BSRR, PinMask); +} + +/** + * @brief Set several pins to low level on dedicated gpio port. + * @rmtoll BRR BRy LL_GPIO_ResetOutputPin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_ResetOutputPin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->BRR, PinMask); +} + +/** + * @brief Toggle data value for several pin of dedicated port. + * @rmtoll ODR ODy LL_GPIO_TogglePin + * @param GPIOx GPIO Port + * @param PinMask This parameter can be a combination of the following values: + * @arg @ref LL_GPIO_PIN_0 + * @arg @ref LL_GPIO_PIN_1 + * @arg @ref LL_GPIO_PIN_2 + * @arg @ref LL_GPIO_PIN_3 + * @arg @ref LL_GPIO_PIN_4 + * @arg @ref LL_GPIO_PIN_5 + * @arg @ref LL_GPIO_PIN_6 + * @arg @ref LL_GPIO_PIN_7 + * @arg @ref LL_GPIO_PIN_8 + * @arg @ref LL_GPIO_PIN_9 + * @arg @ref LL_GPIO_PIN_10 + * @arg @ref LL_GPIO_PIN_11 + * @arg @ref LL_GPIO_PIN_12 + * @arg @ref LL_GPIO_PIN_13 + * @arg @ref LL_GPIO_PIN_14 + * @arg @ref LL_GPIO_PIN_15 + * @arg @ref LL_GPIO_PIN_ALL + * @retval None + */ +__STATIC_INLINE void LL_GPIO_TogglePin(GPIO_TypeDef *GPIOx, uint32_t PinMask) +{ + WRITE_REG(GPIOx->ODR, READ_REG(GPIOx->ODR) ^ PinMask); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup GPIO_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx); +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct); +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOF) */ +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0xx_LL_GPIO_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_i2c.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_i2c.h similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_i2c.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_i2c.h index 0a844f7..47c715d 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_i2c.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_i2c.h @@ -1,1406 +1,1406 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_i2c.h - * @author MCU Application Team - * @brief Header file of I2C LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PY32F0xx_LL_I2C_H -#define __PY32F0xx_LL_I2C_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (I2C1) || defined (I2C2) - -/** @defgroup I2C_LL I2C - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2C_LL_Private_Constants I2C Private Constants - * @{ - */ - -/* Defines used to perform compute and check in the macros */ -#define LL_I2C_MAX_SPEED_STANDARD 100000U -#define LL_I2C_MAX_SPEED_FAST 400000U -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2C_LL_Private_Macros I2C Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure - * @{ - */ -typedef struct -{ - uint32_t ClockSpeed; /*!< Specifies the clock frequency. - This parameter must be set to a value lower than 400kHz (in Hz) - - This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod() - or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */ - - uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. - This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE - - This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */ - - uint32_t OwnAddress1; /*!< Specifies the device own address 1. - This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF - - This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ - - uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. - This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE - - This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ -} LL_I2C_InitTypeDef; -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants - * @{ - */ - -/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_I2C_ReadReg function - * @{ - */ -#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */ -#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or - Address matched flag (slave mode) */ -#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */ -#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */ -#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */ -#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */ -#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */ -#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */ -#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */ -#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */ -#define LL_I2C_SR1_PECERR I2C_SR1_PECERR /*!< PEC Error in reception (SMBus mode) */ -#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */ -#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */ -#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */ -#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions - * @{ - */ -#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */ -#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */ -#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle - * @{ - */ -#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */ -#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode - * @{ - */ -#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */ -#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation - * @{ - */ -#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */ -#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/ -/** - * @} - */ - -/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction - * @{ - */ -#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */ -#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros - * @{ - */ - -/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in I2C register - * @param __INSTANCE__ I2C Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in I2C register - * @param __INSTANCE__ I2C Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper - * @{ - */ - -/** - * @brief Convert Peripheral Clock Frequency in MHz. - * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). - * @retval Value of peripheral clock (in MHz) - */ -#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U) - -/** - * @brief Convert Peripheral Clock Frequency in Hz. - * @param __PCLK__ This parameter must be a value of peripheral clock (in MHz). - * @retval Value of peripheral clock (in Hz) - */ -#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U) - -/** - * @brief Compute I2C Clock rising time. - * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in MHz). - * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). - * @retval Value between Min_Data=0x02 and Max_Data=0x3F - */ -#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) - -/** - * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value. - * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). - * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). - * @param __DUTYCYCLE__ This parameter can be one of the following values: - * @arg @ref LL_I2C_DUTYCYCLE_2 - * @arg @ref LL_I2C_DUTYCYCLE_16_9 - * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. - */ -#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \ - (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \ - (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__)))) - -/** - * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value. - * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). - * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz). - * @retval Value between Min_Data=0x004 and Max_Data=0xFFF. - */ -#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) - -/** - * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value. - * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). - * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz). - * @param __DUTYCYCLE__ This parameter can be one of the following values: - * @arg @ref LL_I2C_DUTYCYCLE_2 - * @arg @ref LL_I2C_DUTYCYCLE_16_9 - * @retval Value between Min_Data=0x001 and Max_Data=0xFFF - */ -#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \ - (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \ - (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U)))) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions - * @{ - */ - -/** @defgroup I2C_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable I2C peripheral (PE = 1). - * @rmtoll CR1 PE LL_I2C_Enable - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_PE); -} - -/** - * @brief Disable I2C peripheral (PE = 0). - * @rmtoll CR1 PE LL_I2C_Disable - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); -} - -/** - * @brief Check if the I2C peripheral is enabled or disabled. - * @rmtoll CR1 PE LL_I2C_IsEnabled - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); -} - - -#if (defined(DMA1) || defined(DMA)) -/** - * @brief Enable DMA transmission requests. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); -} - -/** - * @brief Disable DMA transmission requests. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); -} - -/** - * @brief Check if DMA transmission requests are enabled or disabled. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); -} - -/** - * @brief Enable DMA reception requests. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); -} - -/** - * @brief Disable DMA reception requests. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); -} - -/** - * @brief Check if DMA reception requests are enabled or disabled. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); -} - -/** - * @brief Get the data register address used for DMA transfer. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll DR DR LL_I2C_DMA_GetRegAddr - * @param I2Cx I2C Instance. - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx) -{ - return (uint32_t) & (I2Cx->DR); -} -#endif /* DMA1 or DMA */ - -/** - * @brief Enable Clock stretching. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); -} - -/** - * @brief Disable Clock stretching. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); -} - -/** - * @brief Check if Clock stretching is enabled or disabled. - * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); -} - -/** - * @brief Enable General Call. - * @note When enabled the Address 0x00 is ACKed. - * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_ENGC); -} - -/** - * @brief Disable General Call. - * @note When disabled the Address 0x00 is NACKed. - * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC); -} - -/** - * @brief Check if General Call is enabled or disabled. - * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC)); -} - -/** - * @brief Set the Own Address1. - * @param I2Cx I2C Instance. - * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. - * @param OwnAddrSize This parameter is not used, can pass 0. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) -{ - (void)OwnAddrSize; - MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD1_7, OwnAddress1); -} - -/** - * @brief Configure the Peripheral clock frequency. - * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock - * @param I2Cx I2C Instance. - * @param PeriphClock Peripheral Clock (in Hz) - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock) -{ - MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock)); -} - -/** - * @brief Get the Peripheral clock frequency. - * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock - * @param I2Cx I2C Instance. - * @retval Value of Peripheral Clock (in Hz) - */ -__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ))); -} - -/** - * @brief Configure the Duty cycle (Fast mode only). - * @rmtoll CCR DUTY LL_I2C_SetDutyCycle - * @param I2Cx I2C Instance. - * @param DutyCycle This parameter can be one of the following values: - * @arg @ref LL_I2C_DUTYCYCLE_2 - * @arg @ref LL_I2C_DUTYCYCLE_16_9 - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle) -{ - MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle); -} - -/** - * @brief Get the Duty cycle (Fast mode only). - * @rmtoll CCR DUTY LL_I2C_GetDutyCycle - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_DUTYCYCLE_2 - * @arg @ref LL_I2C_DUTYCYCLE_16_9 - */ -__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY)); -} - -/** - * @brief Configure the I2C master clock speed mode. - * @rmtoll CCR FS LL_I2C_SetClockSpeedMode - * @param I2Cx I2C Instance. - * @param ClockSpeedMode This parameter can be one of the following values: - * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE - * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode) -{ - MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode); -} - -/** - * @brief Get the the I2C master speed mode. - * @rmtoll CCR FS LL_I2C_GetClockSpeedMode - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE - * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE - */ -__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS)); -} - -/** - * @brief Configure the SCL, SDA rising time. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll TRISE TRISE LL_I2C_SetRiseTime - * @param I2Cx I2C Instance. - * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime) -{ - MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime); -} - -/** - * @brief Get the SCL, SDA rising time. - * @rmtoll TRISE TRISE LL_I2C_GetRiseTime - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x02 and Max_Data=0x3F - */ -__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE)); -} - -/** - * @brief Configure the SCL high and low period. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CCR CCR LL_I2C_SetClockPeriod - * @param I2Cx I2C Instance. - * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. - * @retval None - */ -__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod) -{ - MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod); -} - -/** - * @brief Get the SCL high and low period. - * @rmtoll CCR CCR LL_I2C_GetClockPeriod - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. - */ -__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR)); -} - -/** - * @brief Configure the SCL speed. - * @note This bit can only be programmed when the I2C is disabled (PE = 0). - * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n - * TRISE TRISE LL_I2C_ConfigSpeed\n - * CCR FS LL_I2C_ConfigSpeed\n - * CCR DUTY LL_I2C_ConfigSpeed\n - * CCR CCR LL_I2C_ConfigSpeed - * @param I2Cx I2C Instance. - * @param PeriphClock Peripheral Clock (in Hz) - * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz). - * @param DutyCycle This parameter can be one of the following values: - * @arg @ref LL_I2C_DUTYCYCLE_2 - * @arg @ref LL_I2C_DUTYCYCLE_16_9 - * @retval None - */ -__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed, - uint32_t DutyCycle) -{ - register uint32_t freqrange = 0x0U; - register uint32_t clockconfig = 0x0U; - - /* Compute frequency range */ - freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock); - - /* Configure I2Cx: Frequency range register */ - MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange); - - /* Configure I2Cx: Rise Time register */ - MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed)); - - /* Configure Speed mode, Duty Cycle and Clock control register value */ - if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD) - { - /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */ - clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \ - __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \ - DutyCycle; - } - else - { - /* Set Speed mode at standard for Clock Speed request in standard clock range */ - clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \ - __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed); - } - - /* Configure I2Cx: Clock control register */ - MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig); -} - -/** - * @} - */ - -/** @defgroup I2C_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable TXE interrupt. - * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n - * CR2 ITBUFEN LL_I2C_EnableIT_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); -} - -/** - * @brief Disable TXE interrupt. - * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n - * CR2 ITBUFEN LL_I2C_DisableIT_TX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); -} - -/** - * @brief Check if the TXE Interrupt is enabled or disabled. - * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n - * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); -} - -/** - * @brief Enable RXNE interrupt. - * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n - * CR2 ITBUFEN LL_I2C_EnableIT_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); -} - -/** - * @brief Disable RXNE interrupt. - * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n - * CR2 ITBUFEN LL_I2C_DisableIT_RX - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); -} - -/** - * @brief Check if the RXNE Interrupt is enabled or disabled. - * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n - * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); -} - -/** - * @brief Enable Events interrupts. - * @note Any of these events will generate interrupt : - * Start Bit (SB) - * Address sent, Address matched (ADDR) - * Stop detection (STOPF) - * Byte transfer finished (BTF) - * - * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) : - * Receive buffer not empty (RXNE) - * Transmit buffer empty (TXE) - * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); -} - -/** - * @brief Disable Events interrupts. - * @note Any of these events will generate interrupt : - * Start Bit (SB) - * Address sent, Address matched (ADDR) - * Stop detection (STOPF) - * Byte transfer finished (BTF) - * Receive buffer not empty (RXNE) - * Transmit buffer empty (TXE) - * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); -} - -/** - * @brief Check if Events interrupts are enabled or disabled. - * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN)); -} - -/** - * @brief Enable Buffer interrupts. - * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) : - * Receive buffer not empty (RXNE) - * Transmit buffer empty (TXE) - * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); -} - -/** - * @brief Disable Buffer interrupts. - * @note Any of these Buffer events will generate interrupt : - * Receive buffer not empty (RXNE) - * Transmit buffer empty (TXE) - * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); -} - -/** - * @brief Check if Buffer interrupts are enabled or disabled. - * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN)); -} - -/** - * @brief Enable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note Any of these errors will generate interrupt : - * Bus Error detection (BERR) - * Arbitration Loss (ARLO) - * Acknowledge Failure(AF) - * Overrun/Underrun (OVR) - * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN); -} - -/** - * @brief Disable Error interrupts. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @note Any of these errors will generate interrupt : - * Bus Error detection (BERR) - * Arbitration Loss (ARLO) - * Acknowledge Failure(AF) - * Overrun/Underrun (OVR) - * SMBus Timeout detection (TIMEOUT) - * SMBus PEC error detection (PECERR) - * SMBus Alert pin event detection (SMBALERT) - * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN); -} - -/** - * @brief Check if Error interrupts are enabled or disabled. - * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN)); -} - -/** - * @} - */ - -/** @defgroup I2C_LL_EF_FLAG_management FLAG_management - * @{ - */ - -/** - * @brief Indicate the status of Transmit data register empty flag. - * @note RESET: When next data is written in Transmit data register. - * SET: When Transmit data register is empty. - * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE)); -} - -/** - * @brief Indicate the status of Byte Transfer Finished flag. - * RESET: When Data byte transfer not done. - * SET: When Data byte transfer succeeded. - * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF)); -} - -/** - * @brief Indicate the status of Receive data register not empty flag. - * @note RESET: When Receive data register is read. - * SET: When the received data is copied in Receive data register. - * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE)); -} - -/** - * @brief Indicate the status of Start Bit (master mode). - * @note RESET: When No Start condition. - * SET: When Start condition is generated. - * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB)); -} - -/** - * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode). - * @note RESET: Clear default value. - * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode). - * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR)); -} - -/** - * @brief Indicate the status of Acknowledge failure flag. - * @note RESET: No acknowledge failure. - * SET: When an acknowledge failure is received after a byte transmission. - * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF)); -} - -/** - * @brief Indicate the status of Stop detection flag (slave mode). - * @note RESET: Clear default value. - * SET: When a Stop condition is detected. - * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF)); -} - -/** - * @brief Indicate the status of Bus error flag. - * @note RESET: Clear default value. - * SET: When a misplaced Start or Stop condition is detected. - * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR)); -} - -/** - * @brief Indicate the status of Arbitration lost flag. - * @note RESET: Clear default value. - * SET: When arbitration lost. - * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO)); -} - -/** - * @brief Indicate the status of Overrun/Underrun flag. - * @note RESET: Clear default value. - * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). - * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR)); -} - -/** - * @brief Indicate the status of SMBus PEC error flag in reception. - * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not - * SMBus feature is supported by the I2Cx Instance. - * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR)); -} - -/** - * @brief Indicate the status of Bus Busy flag. - * @note RESET: Clear default value. - * SET: When a Start condition is detected. - * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY)); -} - -/** - * @brief Indicate the status of General call address reception (Slave mode). - * @note RESET: No Generall call address - * SET: General call address received. - * @note This status is cleared by hardware after a STOP condition or repeated START condition. - * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL)); -} - -/** - * @brief Indicate the status of Master/Slave flag. - * @note RESET: Slave Mode. - * SET: Master Mode. - * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL)); -} - -/** - * @brief Clear Address Matched flag. - * @note Clearing this flag is done by a read access to the I2Cx_SR1 - * register followed by a read access to the I2Cx_SR2 register. - * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) -{ - __IO uint32_t tmpreg; - tmpreg = I2Cx->SR1; - (void) tmpreg; - tmpreg = I2Cx->SR2; - (void) tmpreg; -} - -/** - * @brief Clear Acknowledge failure flag. - * @rmtoll SR1 AF LL_I2C_ClearFlag_AF - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF); -} - -/** - * @brief Clear Stop detection flag. - * @note Clearing this flag is done by a read access to the I2Cx_SR1 - * register followed by a write access to I2Cx_CR1 register. - * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n - * CR1 PE LL_I2C_ClearFlag_STOP - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) -{ - __IO uint32_t tmpreg; - tmpreg = I2Cx->SR1; - (void) tmpreg; - SET_BIT(I2Cx->CR1, I2C_CR1_PE); -} - -/** - * @brief Clear Bus error flag. - * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR); -} - -/** - * @brief Clear Arbitration lost flag. - * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO); -} - -/** - * @brief Clear Overrun/Underrun flag. - * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR); -} - -/** - * @brief Clear SMBus PEC error flag. - * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR); -} - -/** - * @} - */ - -/** @defgroup I2C_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Enable Reset of I2C peripheral. - * @rmtoll CR1 SWRST LL_I2C_EnableReset - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_SWRST); -} - -/** - * @brief Disable Reset of I2C peripheral. - * @rmtoll CR1 SWRST LL_I2C_DisableReset - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST); -} - -/** - * @brief Check if the I2C peripheral is under reset state or not. - * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST)); -} - -/** - * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. - * @note Usage in Slave or Master mode. - * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData - * @param I2Cx I2C Instance. - * @param TypeAcknowledge This parameter can be one of the following values: - * @arg @ref LL_I2C_ACK - * @arg @ref LL_I2C_NACK - * @retval None - */ -__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) -{ - MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge); -} - -/** - * @brief Generate a START or RESTART condition - * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. - * This action has no effect when RELOAD is set. - * @rmtoll CR1 START LL_I2C_GenerateStartCondition - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_START); -} - -/** - * @brief Generate a STOP condition after the current byte transfer (master mode). - * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_STOP); -} - -/** - * @brief Enable bit POS (master/host mode). - * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC. - * @rmtoll CR1 POS LL_I2C_EnableBitPOS - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR1, I2C_CR1_POS); -} - -/** - * @brief Disable bit POS (master/host mode). - * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC. - * @rmtoll CR1 POS LL_I2C_DisableBitPOS - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS); -} - -/** - * @brief Check if bit POS is enabled or disabled. - * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS)); -} - -/** - * @brief Indicate the value of transfer direction. - * @note RESET: Bus is in read transfer (peripheral point of view). - * SET: Bus is in write transfer (peripheral point of view). - * @rmtoll SR2 TRA LL_I2C_GetTransferDirection - * @param I2Cx I2C Instance. - * @retval Returned value can be one of the following values: - * @arg @ref LL_I2C_DIRECTION_WRITE - * @arg @ref LL_I2C_DIRECTION_READ - */ -__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) -{ - return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA)); -} - -#if (defined(DMA1) || defined(DMA)) -/** - * @brief Enable DMA last transfer. - * @note This action mean that next DMA EOT is the last transfer. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 LAST LL_I2C_EnableLastDMA - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx) -{ - SET_BIT(I2Cx->CR2, I2C_CR2_LAST); -} - -/** - * @brief Disable DMA last transfer. - * @note This action mean that next DMA EOT is not the last transfer. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 LAST LL_I2C_DisableLastDMA - * @param I2Cx I2C Instance. - * @retval None - */ -__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx) -{ - CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST); -} - -/** - * @brief Check if DMA last transfer is enabled or disabled. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA - * @param I2Cx I2C Instance. - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx) -{ - return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST)); -} -#endif /* DMA1 or DMA */ - -/** - * @brief Read Receive Data register. - * @rmtoll DR DR LL_I2C_ReceiveData8 - * @param I2Cx I2C Instance. - * @retval Value between Min_Data=0x0 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) -{ - return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR)); -} - -/** - * @brief Write in Transmit Data Register . - * @rmtoll DR DR LL_I2C_TransmitData8 - * @param I2Cx I2C Instance. - * @param Data Value between Min_Data=0x0 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) -{ - MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); -uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); -void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); - - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* I2C1 || I2C2 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PY32F0xx_LL_I2C_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_i2c.h + * @author MCU Application Team + * @brief Header file of I2C LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32F0xx_LL_I2C_H +#define __PY32F0xx_LL_I2C_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2C_LL_Private_Constants I2C Private Constants + * @{ + */ + +/* Defines used to perform compute and check in the macros */ +#define LL_I2C_MAX_SPEED_STANDARD 100000U +#define LL_I2C_MAX_SPEED_FAST 400000U +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_Private_Macros I2C Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_ES_INIT I2C Exported Init structure + * @{ + */ +typedef struct +{ + uint32_t ClockSpeed; /*!< Specifies the clock frequency. + This parameter must be set to a value lower than 400kHz (in Hz) + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetClockPeriod() + or @ref LL_I2C_SetDutyCycle() or @ref LL_I2C_SetClockSpeedMode() or @ref LL_I2C_ConfigSpeed(). */ + + uint32_t DutyCycle; /*!< Specifies the I2C fast mode duty cycle. + This parameter can be a value of @ref I2C_LL_EC_DUTYCYCLE + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetDutyCycle(). */ + + uint32_t OwnAddress1; /*!< Specifies the device own address 1. + This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF + + This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */ + + uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE + + This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */ +} LL_I2C_InitTypeDef; +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Constants I2C Exported Constants + * @{ + */ + +/** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_I2C_ReadReg function + * @{ + */ +#define LL_I2C_SR1_SB I2C_SR1_SB /*!< Start Bit (master mode) */ +#define LL_I2C_SR1_ADDR I2C_SR1_ADDR /*!< Address sent (master mode) or + Address matched flag (slave mode) */ +#define LL_I2C_SR1_BTF I2C_SR1_BTF /*!< Byte Transfer Finished flag */ +#define LL_I2C_SR1_STOPF I2C_SR1_STOPF /*!< Stop detection flag (slave mode) */ +#define LL_I2C_SR1_RXNE I2C_SR1_RXNE /*!< Data register not empty (receivers) */ +#define LL_I2C_SR1_TXE I2C_SR1_TXE /*!< Data register empty (transmitters) */ +#define LL_I2C_SR1_BERR I2C_SR1_BERR /*!< Bus error */ +#define LL_I2C_SR1_ARLO I2C_SR1_ARLO /*!< Arbitration lost */ +#define LL_I2C_SR1_AF I2C_SR1_AF /*!< Acknowledge failure flag */ +#define LL_I2C_SR1_OVR I2C_SR1_OVR /*!< Overrun/Underrun */ +#define LL_I2C_SR1_PECERR I2C_SR1_PECERR /*!< PEC Error in reception (SMBus mode) */ +#define LL_I2C_SR2_MSL I2C_SR2_MSL /*!< Master/Slave flag */ +#define LL_I2C_SR2_BUSY I2C_SR2_BUSY /*!< Bus busy flag */ +#define LL_I2C_SR2_TRA I2C_SR2_TRA /*!< Transmitter/receiver direction */ +#define LL_I2C_SR2_GENCALL I2C_SR2_GENCALL /*!< General call address (Slave mode) */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions + * @{ + */ +#define LL_I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN /*!< Events interrupts enable */ +#define LL_I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN /*!< Buffer interrupts enable */ +#define LL_I2C_CR2_ITERREN I2C_CR2_ITERREN /*!< Error interrupts enable */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DUTYCYCLE Fast Mode Duty Cycle + * @{ + */ +#define LL_I2C_DUTYCYCLE_2 0x00000000U /*!< I2C fast mode Tlow/Thigh = 2 */ +#define LL_I2C_DUTYCYCLE_16_9 I2C_CCR_DUTY /*!< I2C fast mode Tlow/Thigh = 16/9 */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_CLOCK_SPEED_MODE Master Clock Speed Mode + * @{ + */ +#define LL_I2C_CLOCK_SPEED_STANDARD_MODE 0x00000000U /*!< Master clock speed range is standard mode */ +#define LL_I2C_CLOCK_SPEED_FAST_MODE I2C_CCR_FS /*!< Master clock speed range is fast mode */ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation + * @{ + */ +#define LL_I2C_ACK I2C_CR1_ACK /*!< ACK is sent after current received byte. */ +#define LL_I2C_NACK 0x00000000U /*!< NACK is sent after current received byte.*/ +/** + * @} + */ + +/** @defgroup I2C_LL_EC_DIRECTION Read Write Direction + * @{ + */ +#define LL_I2C_DIRECTION_WRITE I2C_SR2_TRA /*!< Bus is in write transfer */ +#define LL_I2C_DIRECTION_READ 0x00000000U /*!< Bus is in read transfer */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup I2C_LL_Exported_Macros I2C Exported Macros + * @{ + */ + +/** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in I2C register + * @param __INSTANCE__ I2C Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup I2C_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Convert Peripheral Clock Frequency in MHz. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @retval Value of peripheral clock (in MHz) + */ +#define __LL_I2C_FREQ_HZ_TO_MHZ(__PCLK__) (uint32_t)((__PCLK__)/1000000U) + +/** + * @brief Convert Peripheral Clock Frequency in Hz. + * @param __PCLK__ This parameter must be a value of peripheral clock (in MHz). + * @retval Value of peripheral clock (in Hz) + */ +#define __LL_I2C_FREQ_MHZ_TO_HZ(__PCLK__) (uint32_t)((__PCLK__)*1000000U) + +/** + * @brief Compute I2C Clock rising time. + * @param __FREQRANGE__ This parameter must be a value of peripheral clock (in MHz). + * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). + * @retval Value between Min_Data=0x02 and Max_Data=0x3F + */ +#define __LL_I2C_RISE_TIME(__FREQRANGE__, __SPEED__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD) ? ((__FREQRANGE__) + 1U) : ((((__FREQRANGE__) * 300U) / 1000U) + 1U)) + +/** + * @brief Compute Speed clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value lower than 400kHz (in Hz). + * @param __DUTYCYCLE__ This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + */ +#define __LL_I2C_SPEED_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__SPEED__) <= LL_I2C_MAX_SPEED_STANDARD)? \ + (__LL_I2C_SPEED_STANDARD_TO_CCR((__PCLK__), (__SPEED__))) : \ + (__LL_I2C_SPEED_FAST_TO_CCR((__PCLK__), (__SPEED__), (__DUTYCYCLE__)))) + +/** + * @brief Compute Speed Standard clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value lower than 100kHz (in Hz). + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF. + */ +#define __LL_I2C_SPEED_STANDARD_TO_CCR(__PCLK__, __SPEED__) (uint32_t)(((((__PCLK__)/((__SPEED__) << 1U)) & I2C_CCR_CCR) < 4U)? 4U:((__PCLK__) / ((__SPEED__) << 1U))) + +/** + * @brief Compute Speed Fast clock range to a Clock Control Register (I2C_CCR_CCR) value. + * @param __PCLK__ This parameter must be a value of peripheral clock (in Hz). + * @param __SPEED__ This parameter must be a value between Min_Data=100Khz and Max_Data=400Khz (in Hz). + * @param __DUTYCYCLE__ This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval Value between Min_Data=0x001 and Max_Data=0xFFF + */ +#define __LL_I2C_SPEED_FAST_TO_CCR(__PCLK__, __SPEED__, __DUTYCYCLE__) (uint32_t)(((__DUTYCYCLE__) == LL_I2C_DUTYCYCLE_2)? \ + (((((__PCLK__) / ((__SPEED__) * 3U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 3U))) : \ + (((((__PCLK__) / ((__SPEED__) * 25U)) & I2C_CCR_CCR) == 0U)? 1U:((__PCLK__) / ((__SPEED__) * 25U)))) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup I2C_LL_Exported_Functions I2C Exported Functions + * @{ + */ + +/** @defgroup I2C_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable I2C peripheral (PE = 1). + * @rmtoll CR1 PE LL_I2C_Enable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Disable I2C peripheral (PE = 0). + * @rmtoll CR1 PE LL_I2C_Disable + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Check if the I2C peripheral is enabled or disabled. + * @rmtoll CR1 PE LL_I2C_IsEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE)); +} + + +#if (defined(DMA1) || defined(DMA)) +/** + * @brief Enable DMA transmission requests. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Disable DMA transmission requests. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Check if DMA transmission requests are enabled or disabled. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); +} + +/** + * @brief Enable DMA reception requests. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 DMAEN LL_I2C_EnableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Disable DMA reception requests. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 DMAEN LL_I2C_DisableDMAReq_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_DMAEN); +} + +/** + * @brief Check if DMA reception requests are enabled or disabled. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 DMAEN LL_I2C_IsEnabledDMAReq_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_DMAEN) == (I2C_CR2_DMAEN)); +} + +/** + * @brief Get the data register address used for DMA transfer. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll DR DR LL_I2C_DMA_GetRegAddr + * @param I2Cx I2C Instance. + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx) +{ + return (uint32_t) & (I2Cx->DR); +} +#endif /* DMA1 or DMA */ + +/** + * @brief Enable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Disable Clock stretching. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH); +} + +/** + * @brief Check if Clock stretching is enabled or disabled. + * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH)); +} + +/** + * @brief Enable General Call. + * @note When enabled the Address 0x00 is ACKed. + * @rmtoll CR1 ENGC LL_I2C_EnableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_ENGC); +} + +/** + * @brief Disable General Call. + * @note When disabled the Address 0x00 is NACKed. + * @rmtoll CR1 ENGC LL_I2C_DisableGeneralCall + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_ENGC); +} + +/** + * @brief Check if General Call is enabled or disabled. + * @rmtoll CR1 ENGC LL_I2C_IsEnabledGeneralCall + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_ENGC) == (I2C_CR1_ENGC)); +} + +/** + * @brief Set the Own Address1. + * @param I2Cx I2C Instance. + * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF. + * @param OwnAddrSize This parameter is not used, can pass 0. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize) +{ + (void)OwnAddrSize; + MODIFY_REG(I2Cx->OAR1, I2C_OAR1_ADD1_7, OwnAddress1); +} + +/** + * @brief Configure the Peripheral clock frequency. + * @rmtoll CR2 FREQ LL_I2C_SetPeriphClock + * @param I2Cx I2C Instance. + * @param PeriphClock Peripheral Clock (in Hz) + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetPeriphClock(I2C_TypeDef *I2Cx, uint32_t PeriphClock) +{ + MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock)); +} + +/** + * @brief Get the Peripheral clock frequency. + * @rmtoll CR2 FREQ LL_I2C_GetPeriphClock + * @param I2Cx I2C Instance. + * @retval Value of Peripheral Clock (in Hz) + */ +__STATIC_INLINE uint32_t LL_I2C_GetPeriphClock(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(__LL_I2C_FREQ_MHZ_TO_HZ(READ_BIT(I2Cx->CR2, I2C_CR2_FREQ))); +} + +/** + * @brief Configure the Duty cycle (Fast mode only). + * @rmtoll CCR DUTY LL_I2C_SetDutyCycle + * @param I2Cx I2C Instance. + * @param DutyCycle This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetDutyCycle(I2C_TypeDef *I2Cx, uint32_t DutyCycle) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_DUTY, DutyCycle); +} + +/** + * @brief Get the Duty cycle (Fast mode only). + * @rmtoll CCR DUTY LL_I2C_GetDutyCycle + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + */ +__STATIC_INLINE uint32_t LL_I2C_GetDutyCycle(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_DUTY)); +} + +/** + * @brief Configure the I2C master clock speed mode. + * @rmtoll CCR FS LL_I2C_SetClockSpeedMode + * @param I2Cx I2C Instance. + * @param ClockSpeedMode This parameter can be one of the following values: + * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE + * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetClockSpeedMode(I2C_TypeDef *I2Cx, uint32_t ClockSpeedMode) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_FS, ClockSpeedMode); +} + +/** + * @brief Get the the I2C master speed mode. + * @rmtoll CCR FS LL_I2C_GetClockSpeedMode + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_CLOCK_SPEED_STANDARD_MODE + * @arg @ref LL_I2C_CLOCK_SPEED_FAST_MODE + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockSpeedMode(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_FS)); +} + +/** + * @brief Configure the SCL, SDA rising time. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll TRISE TRISE LL_I2C_SetRiseTime + * @param I2Cx I2C Instance. + * @param RiseTime This parameter must be a value between Min_Data=0x02 and Max_Data=0x3F. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetRiseTime(I2C_TypeDef *I2Cx, uint32_t RiseTime) +{ + MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, RiseTime); +} + +/** + * @brief Get the SCL, SDA rising time. + * @rmtoll TRISE TRISE LL_I2C_GetRiseTime + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x02 and Max_Data=0x3F + */ +__STATIC_INLINE uint32_t LL_I2C_GetRiseTime(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->TRISE, I2C_TRISE_TRISE)); +} + +/** + * @brief Configure the SCL high and low period. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CCR CCR LL_I2C_SetClockPeriod + * @param I2Cx I2C Instance. + * @param ClockPeriod This parameter must be a value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + * @retval None + */ +__STATIC_INLINE void LL_I2C_SetClockPeriod(I2C_TypeDef *I2Cx, uint32_t ClockPeriod) +{ + MODIFY_REG(I2Cx->CCR, I2C_CCR_CCR, ClockPeriod); +} + +/** + * @brief Get the SCL high and low period. + * @rmtoll CCR CCR LL_I2C_GetClockPeriod + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x004 and Max_Data=0xFFF, except in FAST DUTY mode where Min_Data=0x001. + */ +__STATIC_INLINE uint32_t LL_I2C_GetClockPeriod(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->CCR, I2C_CCR_CCR)); +} + +/** + * @brief Configure the SCL speed. + * @note This bit can only be programmed when the I2C is disabled (PE = 0). + * @rmtoll CR2 FREQ LL_I2C_ConfigSpeed\n + * TRISE TRISE LL_I2C_ConfigSpeed\n + * CCR FS LL_I2C_ConfigSpeed\n + * CCR DUTY LL_I2C_ConfigSpeed\n + * CCR CCR LL_I2C_ConfigSpeed + * @param I2Cx I2C Instance. + * @param PeriphClock Peripheral Clock (in Hz) + * @param ClockSpeed This parameter must be a value lower than 400kHz (in Hz). + * @param DutyCycle This parameter can be one of the following values: + * @arg @ref LL_I2C_DUTYCYCLE_2 + * @arg @ref LL_I2C_DUTYCYCLE_16_9 + * @retval None + */ +__STATIC_INLINE void LL_I2C_ConfigSpeed(I2C_TypeDef *I2Cx, uint32_t PeriphClock, uint32_t ClockSpeed, + uint32_t DutyCycle) +{ + register uint32_t freqrange = 0x0U; + register uint32_t clockconfig = 0x0U; + + /* Compute frequency range */ + freqrange = __LL_I2C_FREQ_HZ_TO_MHZ(PeriphClock); + + /* Configure I2Cx: Frequency range register */ + MODIFY_REG(I2Cx->CR2, I2C_CR2_FREQ, freqrange); + + /* Configure I2Cx: Rise Time register */ + MODIFY_REG(I2Cx->TRISE, I2C_TRISE_TRISE, __LL_I2C_RISE_TIME(freqrange, ClockSpeed)); + + /* Configure Speed mode, Duty Cycle and Clock control register value */ + if (ClockSpeed > LL_I2C_MAX_SPEED_STANDARD) + { + /* Set Speed mode at fast and duty cycle for Clock Speed request in fast clock range */ + clockconfig = LL_I2C_CLOCK_SPEED_FAST_MODE | \ + __LL_I2C_SPEED_FAST_TO_CCR(PeriphClock, ClockSpeed, DutyCycle) | \ + DutyCycle; + } + else + { + /* Set Speed mode at standard for Clock Speed request in standard clock range */ + clockconfig = LL_I2C_CLOCK_SPEED_STANDARD_MODE | \ + __LL_I2C_SPEED_STANDARD_TO_CCR(PeriphClock, ClockSpeed); + } + + /* Configure I2Cx: Clock control register */ + MODIFY_REG(I2Cx->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), clockconfig); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable TXE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_TX\n + * CR2 ITBUFEN LL_I2C_EnableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable TXE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_TX\n + * CR2 ITBUFEN LL_I2C_DisableIT_TX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if the TXE Interrupt is enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_TX\n + * CR2 ITBUFEN LL_I2C_IsEnabledIT_TX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable RXNE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_RX\n + * CR2 ITBUFEN LL_I2C_EnableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable RXNE interrupt. + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_RX\n + * CR2 ITBUFEN LL_I2C_DisableIT_RX + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if the RXNE Interrupt is enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_RX\n + * CR2 ITBUFEN LL_I2C_IsEnabledIT_RX + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN) == (I2C_CR2_ITEVTEN | I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable Events interrupts. + * @note Any of these events will generate interrupt : + * Start Bit (SB) + * Address sent, Address matched (ADDR) + * Stop detection (STOPF) + * Byte transfer finished (BTF) + * + * @note Any of these events will generate interrupt if Buffer interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_BUF()) : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITEVTEN LL_I2C_EnableIT_EVT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_EVT(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); +} + +/** + * @brief Disable Events interrupts. + * @note Any of these events will generate interrupt : + * Start Bit (SB) + * Address sent, Address matched (ADDR) + * Stop detection (STOPF) + * Byte transfer finished (BTF) + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITEVTEN LL_I2C_DisableIT_EVT + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_EVT(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN); +} + +/** + * @brief Check if Events interrupts are enabled or disabled. + * @rmtoll CR2 ITEVTEN LL_I2C_IsEnabledIT_EVT + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_EVT(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITEVTEN) == (I2C_CR2_ITEVTEN)); +} + +/** + * @brief Enable Buffer interrupts. + * @note Any of these Buffer events will generate interrupt if Events interrupts are enabled too(using unitary function @ref LL_I2C_EnableIT_EVT()) : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITBUFEN LL_I2C_EnableIT_BUF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_BUF(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); +} + +/** + * @brief Disable Buffer interrupts. + * @note Any of these Buffer events will generate interrupt : + * Receive buffer not empty (RXNE) + * Transmit buffer empty (TXE) + * @rmtoll CR2 ITBUFEN LL_I2C_DisableIT_BUF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_BUF(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN); +} + +/** + * @brief Check if Buffer interrupts are enabled or disabled. + * @rmtoll CR2 ITBUFEN LL_I2C_IsEnabledIT_BUF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_BUF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITBUFEN) == (I2C_CR2_ITBUFEN)); +} + +/** + * @brief Enable Error interrupts. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Bus Error detection (BERR) + * Arbitration Loss (ARLO) + * Acknowledge Failure(AF) + * Overrun/Underrun (OVR) + * @rmtoll CR2 ITERREN LL_I2C_EnableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_ITERREN); +} + +/** + * @brief Disable Error interrupts. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @note Any of these errors will generate interrupt : + * Bus Error detection (BERR) + * Arbitration Loss (ARLO) + * Acknowledge Failure(AF) + * Overrun/Underrun (OVR) + * SMBus Timeout detection (TIMEOUT) + * SMBus PEC error detection (PECERR) + * SMBus Alert pin event detection (SMBALERT) + * @rmtoll CR2 ITERREN LL_I2C_DisableIT_ERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_ITERREN); +} + +/** + * @brief Check if Error interrupts are enabled or disabled. + * @rmtoll CR2 ITERREN LL_I2C_IsEnabledIT_ERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_ITERREN) == (I2C_CR2_ITERREN)); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_FLAG_management FLAG_management + * @{ + */ + +/** + * @brief Indicate the status of Transmit data register empty flag. + * @note RESET: When next data is written in Transmit data register. + * SET: When Transmit data register is empty. + * @rmtoll SR1 TXE LL_I2C_IsActiveFlag_TXE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_TXE) == (I2C_SR1_TXE)); +} + +/** + * @brief Indicate the status of Byte Transfer Finished flag. + * RESET: When Data byte transfer not done. + * SET: When Data byte transfer succeeded. + * @rmtoll SR1 BTF LL_I2C_IsActiveFlag_BTF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BTF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_BTF) == (I2C_SR1_BTF)); +} + +/** + * @brief Indicate the status of Receive data register not empty flag. + * @note RESET: When Receive data register is read. + * SET: When the received data is copied in Receive data register. + * @rmtoll SR1 RXNE LL_I2C_IsActiveFlag_RXNE + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_RXNE) == (I2C_SR1_RXNE)); +} + +/** + * @brief Indicate the status of Start Bit (master mode). + * @note RESET: When No Start condition. + * SET: When Start condition is generated. + * @rmtoll SR1 SB LL_I2C_IsActiveFlag_SB + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_SB(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_SB) == (I2C_SR1_SB)); +} + +/** + * @brief Indicate the status of Address sent (master mode) or Address matched flag (slave mode). + * @note RESET: Clear default value. + * SET: When the address is fully sent (master mode) or when the received slave address matched with one of the enabled slave address (slave mode). + * @rmtoll SR1 ADDR LL_I2C_IsActiveFlag_ADDR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ADDR) == (I2C_SR1_ADDR)); +} + +/** + * @brief Indicate the status of Acknowledge failure flag. + * @note RESET: No acknowledge failure. + * SET: When an acknowledge failure is received after a byte transmission. + * @rmtoll SR1 AF LL_I2C_IsActiveFlag_AF + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_AF(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_AF) == (I2C_SR1_AF)); +} + +/** + * @brief Indicate the status of Stop detection flag (slave mode). + * @note RESET: Clear default value. + * SET: When a Stop condition is detected. + * @rmtoll SR1 STOPF LL_I2C_IsActiveFlag_STOP + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_STOPF) == (I2C_SR1_STOPF)); +} + +/** + * @brief Indicate the status of Bus error flag. + * @note RESET: Clear default value. + * SET: When a misplaced Start or Stop condition is detected. + * @rmtoll SR1 BERR LL_I2C_IsActiveFlag_BERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_BERR) == (I2C_SR1_BERR)); +} + +/** + * @brief Indicate the status of Arbitration lost flag. + * @note RESET: Clear default value. + * SET: When arbitration lost. + * @rmtoll SR1 ARLO LL_I2C_IsActiveFlag_ARLO + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_ARLO) == (I2C_SR1_ARLO)); +} + +/** + * @brief Indicate the status of Overrun/Underrun flag. + * @note RESET: Clear default value. + * SET: When an overrun/underrun error occurs (Clock Stretching Disabled). + * @rmtoll SR1 OVR LL_I2C_IsActiveFlag_OVR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_OVR) == (I2C_SR1_OVR)); +} + +/** + * @brief Indicate the status of SMBus PEC error flag in reception. + * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not + * SMBus feature is supported by the I2Cx Instance. + * @rmtoll SR1 PECERR LL_I2C_IsActiveSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR1, I2C_SR1_PECERR) == (I2C_SR1_PECERR)); +} + +/** + * @brief Indicate the status of Bus Busy flag. + * @note RESET: Clear default value. + * SET: When a Start condition is detected. + * @rmtoll SR2 BUSY LL_I2C_IsActiveFlag_BUSY + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_BUSY) == (I2C_SR2_BUSY)); +} + +/** + * @brief Indicate the status of General call address reception (Slave mode). + * @note RESET: No Generall call address + * SET: General call address received. + * @note This status is cleared by hardware after a STOP condition or repeated START condition. + * @rmtoll SR2 GENCALL LL_I2C_IsActiveFlag_GENCALL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_GENCALL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_GENCALL) == (I2C_SR2_GENCALL)); +} + +/** + * @brief Indicate the status of Master/Slave flag. + * @note RESET: Slave Mode. + * SET: Master Mode. + * @rmtoll SR2 MSL LL_I2C_IsActiveFlag_MSL + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_MSL(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->SR2, I2C_SR2_MSL) == (I2C_SR2_MSL)); +} + +/** + * @brief Clear Address Matched flag. + * @note Clearing this flag is done by a read access to the I2Cx_SR1 + * register followed by a read access to the I2Cx_SR2 register. + * @rmtoll SR1 ADDR LL_I2C_ClearFlag_ADDR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx) +{ + __IO uint32_t tmpreg; + tmpreg = I2Cx->SR1; + (void) tmpreg; + tmpreg = I2Cx->SR2; + (void) tmpreg; +} + +/** + * @brief Clear Acknowledge failure flag. + * @rmtoll SR1 AF LL_I2C_ClearFlag_AF + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_AF(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_AF); +} + +/** + * @brief Clear Stop detection flag. + * @note Clearing this flag is done by a read access to the I2Cx_SR1 + * register followed by a write access to I2Cx_CR1 register. + * @rmtoll SR1 STOPF LL_I2C_ClearFlag_STOP\n + * CR1 PE LL_I2C_ClearFlag_STOP + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx) +{ + __IO uint32_t tmpreg; + tmpreg = I2Cx->SR1; + (void) tmpreg; + SET_BIT(I2Cx->CR1, I2C_CR1_PE); +} + +/** + * @brief Clear Bus error flag. + * @rmtoll SR1 BERR LL_I2C_ClearFlag_BERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_BERR); +} + +/** + * @brief Clear Arbitration lost flag. + * @rmtoll SR1 ARLO LL_I2C_ClearFlag_ARLO + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_ARLO); +} + +/** + * @brief Clear Overrun/Underrun flag. + * @rmtoll SR1 OVR LL_I2C_ClearFlag_OVR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_OVR); +} + +/** + * @brief Clear SMBus PEC error flag. + * @rmtoll SR1 PECERR LL_I2C_ClearSMBusFlag_PECERR + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->SR1, I2C_SR1_PECERR); +} + +/** + * @} + */ + +/** @defgroup I2C_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Enable Reset of I2C peripheral. + * @rmtoll CR1 SWRST LL_I2C_EnableReset + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableReset(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Disable Reset of I2C peripheral. + * @rmtoll CR1 SWRST LL_I2C_DisableReset + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableReset(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_SWRST); +} + +/** + * @brief Check if the I2C peripheral is under reset state or not. + * @rmtoll CR1 SWRST LL_I2C_IsResetEnabled + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsResetEnabled(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_SWRST) == (I2C_CR1_SWRST)); +} + +/** + * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte. + * @note Usage in Slave or Master mode. + * @rmtoll CR1 ACK LL_I2C_AcknowledgeNextData + * @param I2Cx I2C Instance. + * @param TypeAcknowledge This parameter can be one of the following values: + * @arg @ref LL_I2C_ACK + * @arg @ref LL_I2C_NACK + * @retval None + */ +__STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge) +{ + MODIFY_REG(I2Cx->CR1, I2C_CR1_ACK, TypeAcknowledge); +} + +/** + * @brief Generate a START or RESTART condition + * @note The START bit can be set even if bus is BUSY or I2C is in slave mode. + * This action has no effect when RELOAD is set. + * @rmtoll CR1 START LL_I2C_GenerateStartCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_START); +} + +/** + * @brief Generate a STOP condition after the current byte transfer (master mode). + * @rmtoll CR1 STOP LL_I2C_GenerateStopCondition + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_STOP); +} + +/** + * @brief Enable bit POS (master/host mode). + * @note In that case, the ACK bit controls the (N)ACK of the next byte received or the PEC bit indicates that the next byte in shift register is a PEC. + * @rmtoll CR1 POS LL_I2C_EnableBitPOS + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableBitPOS(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR1, I2C_CR1_POS); +} + +/** + * @brief Disable bit POS (master/host mode). + * @note In that case, the ACK bit controls the (N)ACK of the current byte received or the PEC bit indicates that the current byte in shift register is a PEC. + * @rmtoll CR1 POS LL_I2C_DisableBitPOS + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableBitPOS(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR1, I2C_CR1_POS); +} + +/** + * @brief Check if bit POS is enabled or disabled. + * @rmtoll CR1 POS LL_I2C_IsEnabledBitPOS + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledBitPOS(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR1, I2C_CR1_POS) == (I2C_CR1_POS)); +} + +/** + * @brief Indicate the value of transfer direction. + * @note RESET: Bus is in read transfer (peripheral point of view). + * SET: Bus is in write transfer (peripheral point of view). + * @rmtoll SR2 TRA LL_I2C_GetTransferDirection + * @param I2Cx I2C Instance. + * @retval Returned value can be one of the following values: + * @arg @ref LL_I2C_DIRECTION_WRITE + * @arg @ref LL_I2C_DIRECTION_READ + */ +__STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx) +{ + return (uint32_t)(READ_BIT(I2Cx->SR2, I2C_SR2_TRA)); +} + +#if (defined(DMA1) || defined(DMA)) +/** + * @brief Enable DMA last transfer. + * @note This action mean that next DMA EOT is the last transfer. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 LAST LL_I2C_EnableLastDMA + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_EnableLastDMA(I2C_TypeDef *I2Cx) +{ + SET_BIT(I2Cx->CR2, I2C_CR2_LAST); +} + +/** + * @brief Disable DMA last transfer. + * @note This action mean that next DMA EOT is not the last transfer. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 LAST LL_I2C_DisableLastDMA + * @param I2Cx I2C Instance. + * @retval None + */ +__STATIC_INLINE void LL_I2C_DisableLastDMA(I2C_TypeDef *I2Cx) +{ + CLEAR_BIT(I2Cx->CR2, I2C_CR2_LAST); +} + +/** + * @brief Check if DMA last transfer is enabled or disabled. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 LAST LL_I2C_IsEnabledLastDMA + * @param I2Cx I2C Instance. + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_I2C_IsEnabledLastDMA(I2C_TypeDef *I2Cx) +{ + return (READ_BIT(I2Cx->CR2, I2C_CR2_LAST) == (I2C_CR2_LAST)); +} +#endif /* DMA1 or DMA */ + +/** + * @brief Read Receive Data register. + * @rmtoll DR DR LL_I2C_ReceiveData8 + * @param I2Cx I2C Instance. + * @retval Value between Min_Data=0x0 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx) +{ + return (uint8_t)(READ_BIT(I2Cx->DR, I2C_DR_DR)); +} + +/** + * @brief Write in Transmit Data Register . + * @rmtoll DR DR LL_I2C_TransmitData8 + * @param I2Cx I2C Instance. + * @param Data Value between Min_Data=0x0 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data) +{ + MODIFY_REG(I2Cx->DR, I2C_DR_DR, Data); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct); +uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx); +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct); + + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0xx_LL_I2C_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_iwdg.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_iwdg.h similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_iwdg.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_iwdg.h index 9c1687d..dbace0b 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_iwdg.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_iwdg.h @@ -1,313 +1,313 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_iwdg.h - * @author MCU Application Team - * @brief Header file of IWDG LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef PY32F0XX_LL_IWDG_H -#define PY32F0XX_LL_IWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0XX_LL_Driver - * @{ - */ - -#if defined(IWDG) - -/** @defgroup IWDG_LL IWDG - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants - * @{ - */ - -#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ -#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ -#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ -#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants - * @{ - */ - -/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_IWDG_ReadReg function - * @{ - */ -#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ -#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ - -/** - * @} - */ - -/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider - * @{ - */ -#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ -#define LL_IWDG_PRESCALER_8 ( IWDG_PR_PR_0) /*!< Divider by 8 */ -#define LL_IWDG_PRESCALER_16 ( IWDG_PR_PR_1 ) /*!< Divider by 16 */ -#define LL_IWDG_PRESCALER_32 ( IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ -#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2 ) /*!< Divider by 64 */ -#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ -#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1 ) /*!< Divider by 256 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros - * @{ - */ - -/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in IWDG register - * @param __INSTANCE__ IWDG Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in IWDG register - * @param __INSTANCE__ IWDG Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions - * @{ - */ -/** @defgroup IWDG_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Start the Independent Watchdog - * @note Except if the hardware watchdog option is selected - * @rmtoll KR KEY LL_IWDG_Enable - * @param IWDGx IWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) -{ - WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); -} - -/** - * @brief Reloads IWDG counter with value defined in the reload register - * @rmtoll KR KEY LL_IWDG_ReloadCounter - * @param IWDGx IWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) -{ - WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); -} - -/** - * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers - * @rmtoll KR KEY LL_IWDG_EnableWriteAccess - * @param IWDGx IWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) -{ - WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); -} - -/** - * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers - * @rmtoll KR KEY LL_IWDG_DisableWriteAccess - * @param IWDGx IWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) -{ - WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); -} - -/** - * @brief Select the prescaler of the IWDG - * @rmtoll PR PR LL_IWDG_SetPrescaler - * @param IWDGx IWDG Instance - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_IWDG_PRESCALER_4 - * @arg @ref LL_IWDG_PRESCALER_8 - * @arg @ref LL_IWDG_PRESCALER_16 - * @arg @ref LL_IWDG_PRESCALER_32 - * @arg @ref LL_IWDG_PRESCALER_64 - * @arg @ref LL_IWDG_PRESCALER_128 - * @arg @ref LL_IWDG_PRESCALER_256 - * @retval None - */ -__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) -{ - WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); -} - -/** - * @brief Get the selected prescaler of the IWDG - * @rmtoll PR PR LL_IWDG_GetPrescaler - * @param IWDGx IWDG Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_IWDG_PRESCALER_4 - * @arg @ref LL_IWDG_PRESCALER_8 - * @arg @ref LL_IWDG_PRESCALER_16 - * @arg @ref LL_IWDG_PRESCALER_32 - * @arg @ref LL_IWDG_PRESCALER_64 - * @arg @ref LL_IWDG_PRESCALER_128 - * @arg @ref LL_IWDG_PRESCALER_256 - */ -__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) -{ - return (uint32_t)(READ_REG(IWDGx->PR)); -} - -/** - * @brief Specify the IWDG down-counter reload value - * @rmtoll RLR RL LL_IWDG_SetReloadCounter - * @param IWDGx IWDG Instance - * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF - * @retval None - */ -__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) -{ - WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); -} - -/** - * @brief Get the specified IWDG down-counter reload value - * @rmtoll RLR RL LL_IWDG_GetReloadCounter - * @param IWDGx IWDG Instance - * @retval Value between Min_Data=0 and Max_Data=0x0FFF - */ -__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) -{ - return (uint32_t)(READ_REG(IWDGx->RLR)); -} - - -/** - * @} - */ - -/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if flag Prescaler Value Update is set or not - * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU - * @param IWDGx IWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) -{ - return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)); -} - -/** - * @brief Check if flag Reload Value Update is set or not - * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU - * @param IWDGx IWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) -{ - return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)); -} - -/** - * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not - * @rmtoll SR PVU LL_IWDG_IsReady\n - * SR RVU LL_IWDG_IsReady - * @param IWDGx IWDG Instance - * @retval State of bits (1 or 0). - */ -__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) -{ - return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U); -} - -/** - * @} - */ - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* IWDG */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* PY32F0XX_LL_IWDG_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_iwdg.h + * @author MCU Application Team + * @brief Header file of IWDG LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef PY32F0XX_LL_IWDG_H +#define PY32F0XX_LL_IWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0XX_LL_Driver + * @{ + */ + +#if defined(IWDG) + +/** @defgroup IWDG_LL IWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup IWDG_LL_Private_Constants IWDG Private Constants + * @{ + */ + +#define LL_IWDG_KEY_RELOAD 0x0000AAAAU /*!< IWDG Reload Counter Enable */ +#define LL_IWDG_KEY_ENABLE 0x0000CCCCU /*!< IWDG Peripheral Enable */ +#define LL_IWDG_KEY_WR_ACCESS_ENABLE 0x00005555U /*!< IWDG KR Write Access Enable */ +#define LL_IWDG_KEY_WR_ACCESS_DISABLE 0x00000000U /*!< IWDG KR Write Access Disable */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Constants IWDG Exported Constants + * @{ + */ + +/** @defgroup IWDG_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_IWDG_ReadReg function + * @{ + */ +#define LL_IWDG_SR_PVU IWDG_SR_PVU /*!< Watchdog prescaler value update */ +#define LL_IWDG_SR_RVU IWDG_SR_RVU /*!< Watchdog counter reload value update */ + +/** + * @} + */ + +/** @defgroup IWDG_LL_EC_PRESCALER Prescaler Divider + * @{ + */ +#define LL_IWDG_PRESCALER_4 0x00000000U /*!< Divider by 4 */ +#define LL_IWDG_PRESCALER_8 ( IWDG_PR_PR_0) /*!< Divider by 8 */ +#define LL_IWDG_PRESCALER_16 ( IWDG_PR_PR_1 ) /*!< Divider by 16 */ +#define LL_IWDG_PRESCALER_32 ( IWDG_PR_PR_1 | IWDG_PR_PR_0) /*!< Divider by 32 */ +#define LL_IWDG_PRESCALER_64 (IWDG_PR_PR_2 ) /*!< Divider by 64 */ +#define LL_IWDG_PRESCALER_128 (IWDG_PR_PR_2 | IWDG_PR_PR_0) /*!< Divider by 128 */ +#define LL_IWDG_PRESCALER_256 (IWDG_PR_PR_2 | IWDG_PR_PR_1 ) /*!< Divider by 256 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Macros IWDG Exported Macros + * @{ + */ + +/** @defgroup IWDG_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_IWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in IWDG register + * @param __INSTANCE__ IWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_IWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup IWDG_LL_Exported_Functions IWDG Exported Functions + * @{ + */ +/** @defgroup IWDG_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Start the Independent Watchdog + * @note Except if the hardware watchdog option is selected + * @rmtoll KR KEY LL_IWDG_Enable + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_Enable(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_ENABLE); +} + +/** + * @brief Reloads IWDG counter with value defined in the reload register + * @rmtoll KR KEY LL_IWDG_ReloadCounter + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_ReloadCounter(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_RELOAD); +} + +/** + * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_EnableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_EnableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_ENABLE); +} + +/** + * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers + * @rmtoll KR KEY LL_IWDG_DisableWriteAccess + * @param IWDGx IWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_IWDG_DisableWriteAccess(IWDG_TypeDef *IWDGx) +{ + WRITE_REG(IWDGx->KR, LL_IWDG_KEY_WR_ACCESS_DISABLE); +} + +/** + * @brief Select the prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_SetPrescaler + * @param IWDGx IWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetPrescaler(IWDG_TypeDef *IWDGx, uint32_t Prescaler) +{ + WRITE_REG(IWDGx->PR, IWDG_PR_PR & Prescaler); +} + +/** + * @brief Get the selected prescaler of the IWDG + * @rmtoll PR PR LL_IWDG_GetPrescaler + * @param IWDGx IWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_IWDG_PRESCALER_4 + * @arg @ref LL_IWDG_PRESCALER_8 + * @arg @ref LL_IWDG_PRESCALER_16 + * @arg @ref LL_IWDG_PRESCALER_32 + * @arg @ref LL_IWDG_PRESCALER_64 + * @arg @ref LL_IWDG_PRESCALER_128 + * @arg @ref LL_IWDG_PRESCALER_256 + */ +__STATIC_INLINE uint32_t LL_IWDG_GetPrescaler(IWDG_TypeDef *IWDGx) +{ + return (uint32_t)(READ_REG(IWDGx->PR)); +} + +/** + * @brief Specify the IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_SetReloadCounter + * @param IWDGx IWDG Instance + * @param Counter Value between Min_Data=0 and Max_Data=0x0FFF + * @retval None + */ +__STATIC_INLINE void LL_IWDG_SetReloadCounter(IWDG_TypeDef *IWDGx, uint32_t Counter) +{ + WRITE_REG(IWDGx->RLR, IWDG_RLR_RL & Counter); +} + +/** + * @brief Get the specified IWDG down-counter reload value + * @rmtoll RLR RL LL_IWDG_GetReloadCounter + * @param IWDGx IWDG Instance + * @retval Value between Min_Data=0 and Max_Data=0x0FFF + */ +__STATIC_INLINE uint32_t LL_IWDG_GetReloadCounter(IWDG_TypeDef *IWDGx) +{ + return (uint32_t)(READ_REG(IWDGx->RLR)); +} + + +/** + * @} + */ + +/** @defgroup IWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if flag Prescaler Value Update is set or not + * @rmtoll SR PVU LL_IWDG_IsActiveFlag_PVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_PVU(IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->SR, IWDG_SR_PVU) == (IWDG_SR_PVU)); +} + +/** + * @brief Check if flag Reload Value Update is set or not + * @rmtoll SR RVU LL_IWDG_IsActiveFlag_RVU + * @param IWDGx IWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsActiveFlag_RVU(IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->SR, IWDG_SR_RVU) == (IWDG_SR_RVU)); +} + +/** + * @brief Check if all flags Prescaler, Reload & Window Value Update are reset or not + * @rmtoll SR PVU LL_IWDG_IsReady\n + * SR RVU LL_IWDG_IsReady + * @param IWDGx IWDG Instance + * @retval State of bits (1 or 0). + */ +__STATIC_INLINE uint32_t LL_IWDG_IsReady(IWDG_TypeDef *IWDGx) +{ + return (READ_BIT(IWDGx->SR, IWDG_SR_PVU | IWDG_SR_RVU) == 0U); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* IWDG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PY32F0XX_LL_IWDG_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_led.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_led.h similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_led.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_led.h index da94626..3e7c8e0 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_led.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_led.h @@ -1,475 +1,475 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_led.h - * @author MCU Application Team - * @brief Header file of LED LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef PY32F0XX_LL_LED_H -#define PY32F0XX_LL_LED_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0XX_LL_Driver - * @{ - */ - -#if defined (LED) -/** @defgroup LED_LL LED - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/** - * @brief LED Init Structure definition - */ -typedef struct -{ - uint32_t ComDrive; /*!< Specifies the LED COM drive capability. - This parameter can be a value of @ref LED_LL_EC_ComDrive */ - - uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the LED clock. - This parameter can be a number between Min_Data = 0x00(div1) and Max_Data = 0xFF(div256) */ - - uint32_t ComSelect; /*!< Specifies the number of COM open. - This parameter can be a value of @ref LED_LL_EC_ComSelct */ - - uint32_t LightTime; /*!< Specifies LED Lighting time. - This parameter can be a number between Min_Data = 1 and Max_Data = 0xFF */ - - uint32_t DeadTime; /*!< Specifies LED Dead time. - This parameter can be a number between Min_Data = 1 and Max_Data = 0xFF */ - -} LL_LED_InitTypeDef; - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup LED_LL_EC_ComDrive ComDrive - * @{ - */ -#define LL_LED_COMDRIVE_LOW 0x00000000U -#define LL_LED_COMDRIVE_HIGH LED_CR_EHS -/** - * @} - */ - - -/** @defgroup LED_LL_EC_ComSelct the number of COM open - * @{ - */ -#define LL_LED_COMSELECT_1COM 0x00000000U -#define LL_LED_COMSELECT_2COM LED_CR_LED_COM_SEL_0 -#define LL_LED_COMSELECT_3COM LED_CR_LED_COM_SEL_1 -#define LL_LED_COMSELECT_4COM (LED_CR_LED_COM_SEL_1 | LED_CR_LED_COM_SEL_0) -/** - * @} - */ - -/** @defgroup LED_LL_EC_DisplayValue LED display value - * @{ - */ -#define LL_LED_DISP_NONE 0x00U -#define LL_LED_DISP_FULL 0xFFU - -#define LL_LED_DISP_0 0x3FU -#define LL_LED_DISP_1 0x06U -#define LL_LED_DISP_2 0x5BU -#define LL_LED_DISP_3 0x4FU -#define LL_LED_DISP_4 0x66U -#define LL_LED_DISP_5 0x6DU -#define LL_LED_DISP_6 0x7DU -#define LL_LED_DISP_7 0x07U -#define LL_LED_DISP_8 0x7FU -#define LL_LED_DISP_9 0x6FU -#define LL_LED_DISP_A 0x77U -#define LL_LED_DISP_B 0x7CU -#define LL_LED_DISP_C 0x39U -#define LL_LED_DISP_D 0x5EU -#define LL_LED_DISP_E 0x79U -#define LL_LED_DISP_F 0x71U -#define LL_LED_DISP_H 0x76U -#define LL_LED_DISP_P 0x73U -#define LL_LED_DISP_U 0x3EU -#define LL_LED_DISP_DOT 0x80U -/** - * @} - */ - -/** @defgroup LED_LL_EC_ComDisplay LED COM Select - * @{ - */ -#define LL_LED_COM0 0x00000000U -#define LL_LED_COM1 0x00000004U -#define LL_LED_COM2 0x00000008U -#define LL_LED_COM3 0x0000000CU -/** - * @} - */ - -/** @defgroup LED_LL_EC_DataReg Data Register Mask and position - * @{ - */ -#define LL_LED_DR_DATA LED_DR0_DATA0 -#define LL_LED_DR_DATA_Pos LED_DR0_DATA0_Pos -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** - * @brief Set the LED COM drive capability. - * @param LEDx LED Instance - * @param ComDrive This parameter can be one of the following values: - * @arg @ref LL_LED_COMDRIVE_LOW - * @arg @ref LL_LED_COMDRIVE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_LED_SetComDrive(LED_TypeDef *LEDx, uint32_t ComDrive) -{ - MODIFY_REG(LEDx->CR, LED_CR_EHS, ComDrive); -} - -/** - * @brief Get the LED COM drive capability. - * @param LEDx LED Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LED_COMDRIVE_LOW - * @arg @ref LL_LED_COMDRIVE_HIGH - */ -__STATIC_INLINE uint32_t LL_LED_GetComDrive(LED_TypeDef *LEDx) -{ - return (READ_BIT(LEDx->CR, LED_CR_EHS)); -} - -/** - * @brief Enable LED Interrupt. - * @param LEDx LED Instance - * @retval None - */ -__STATIC_INLINE void LL_LED_EnableIT(LED_TypeDef *LEDx) -{ - SET_BIT(LEDx->CR, LED_CR_IE); -} - -/** - * @brief Disable LED Interrupt. - * @param LEDx LED Instance - * @retval None - */ -__STATIC_INLINE void LL_LED_DisableIT(LED_TypeDef *LEDx) -{ - CLEAR_BIT(LEDx->CR, LED_CR_IE); -} -/** - * @brief Check if LED Interrupt is enabled - * @param LEDx LED Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LED_IsEnabledIT(LED_TypeDef *LEDx) -{ - return ((READ_BIT(LEDx->CR, LED_CR_IE) == (LED_CR_IE)) ? 1UL : 0UL); -} - -/** - * @brief Set he number of COM open. - * @param LEDx LED Instance - * @param ComNum This parameter can be one of the following values: - * @arg @ref LL_LED_COMSELECT_1COM - * @arg @ref LL_LED_COMSELECT_2COM - * @arg @ref LL_LED_COMSELECT_3COM - * @arg @ref LL_LED_COMSELECT_4COM - * @retval None - */ -__STATIC_INLINE void LL_LED_SetComNum(LED_TypeDef *LEDx, uint32_t ComNum) -{ - MODIFY_REG(LEDx->CR, LED_CR_LED_COM_SEL, ComNum); -} - -/** - * @brief Get the number of COM open. - * @param LEDx LED Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_LED_COMSELECT_1COM - * @arg @ref LL_LED_COMSELECT_2COM - * @arg @ref LL_LED_COMSELECT_3COM - * @arg @ref LL_LED_COMSELECT_4COM - */ -__STATIC_INLINE uint32_t LL_LED_GetComNum(LED_TypeDef *LEDx) -{ - return (READ_BIT(LEDx->CR, LED_CR_LED_COM_SEL)); -} - - -/** - * @brief Enable LED. - * @param LEDx LED Instance - * @retval None - */ -__STATIC_INLINE void LL_LED_Enable(LED_TypeDef *LEDx) -{ - SET_BIT(LEDx->CR, LED_CR_LEDON); -} - -/** - * @brief Disable LED. - * @param LEDx LED Instance - * @retval None - */ -__STATIC_INLINE void LL_LED_Disable(LED_TypeDef *LEDx) -{ - CLEAR_BIT(LEDx->CR, LED_CR_LEDON); -} - -/** - * @brief Checks if LED is enabled - * @param LEDx LED Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LED_IsEnabled(LED_TypeDef *LEDx) -{ - return ((READ_BIT(LEDx->CR, LED_CR_LEDON) == (LED_CR_LEDON)) ? 1UL : 0UL); -} - -/** - * @brief Set the LED prescale Value. - * @param LEDx LED Instance - * @param Prescaler This parameter can be a number between Min_Data = 0x00(div1) - * and Max_Data = 0xFF(div256) - * @retval None - */ -__STATIC_INLINE void LL_LED_SetPrescaler(LED_TypeDef *LEDx, uint32_t Prescaler) -{ - MODIFY_REG(LEDx->PR, LED_PR_PR, (Prescaler << LED_PR_PR_Pos)); -} - -/** - * @brief Return LED Prescaler Value. - * @param LEDx LED Instance - * @retval Returned value can be a number between Min_Data = 0x00(div1) - * and Max_Data = 0xFF(div256) - */ -__STATIC_INLINE uint32_t LL_LED_GetPrescaler(LED_TypeDef *LEDx) -{ - return (READ_BIT(LEDx->PR, LED_PR_PR) >> LED_PR_PR_Pos); -} - -/** - * @brief Set the LED Lighting and Dead time. - * @param LEDx LED Instance - * @param LightTime This parameter can be a number between Min_Data = 1 and - * Max_Data = 0xFF - * @param DeadTime This parameter can be a number between Min_Data = 1 and - * Max_Data = 0xFF - * @retval None - */ -__STATIC_INLINE void LL_LED_SetLightAndDeadTime(LED_TypeDef *LEDx,\ - uint32_t LightTime, uint32_t DeadTime) -{ - MODIFY_REG(LEDx->TR, (LED_TR_T1 | LED_TR_T2), ((LightTime << LED_TR_T1_Pos) |\ - (DeadTime << LED_TR_T2_Pos))); -} - -/** - * @brief Set the LED Lighting time. - * @param LEDx LED Instance - * @param LightTime This parameter can be a number between Min_Data = 1 and - * Max_Data = 0xFF - * @retval None - */ -__STATIC_INLINE void LL_LED_SetLightTime(LED_TypeDef *LEDx, uint32_t LightTime) -{ - MODIFY_REG(LEDx->TR, LED_TR_T1, (LightTime << LED_TR_T1_Pos)); -} - -/** - * @brief Set the LED Dead time. - * @param LEDx LED Instance - * @param DeadTime This parameter can be a number between Min_Data = 1 and - * Max_Data = 0xFF - * @retval None - */ -__STATIC_INLINE void LL_LED_SetDeadTime(LED_TypeDef *LEDx, uint32_t DeadTime) -{ - MODIFY_REG(LEDx->TR, LED_TR_T2, (DeadTime << LED_TR_T2_Pos)); -} - -/** - * @brief Get the LED Lighting time. - * @param LEDx LED Instance - * @retval Returned value can be a number between Min_Data = 1 and - * Max_Data = 0xFF - */ -__STATIC_INLINE uint32_t LL_LED_GetLightTime(LED_TypeDef *LEDx) -{ - return (READ_BIT(LEDx->TR, LED_TR_T1) >> LED_TR_T1_Pos); -} - -/** - * @brief Get the LED Dead time. - * @param LEDx LED Instance - * @retval Returned value can be a number between Min_Data = 1 and - * Max_Data = 0xFF - */ -__STATIC_INLINE uint32_t LL_LED_GetDeadTime(LED_TypeDef *LEDx) -{ - return (READ_BIT(LEDx->TR, LED_TR_T2) >> LED_TR_T2_Pos); -} - -/** - * @brief Set the LED display value. - * @param LEDx LED Instance - * @param comCh Specify COM channels.This parameter can be one of the following values: - * @arg @ref LL_LED_COM0 - * @arg @ref LL_LED_COM1 - * @arg @ref LL_LED_COM2 - * @arg @ref LL_LED_COM3 - * @param data Specify display values.This parameter can be one of the following values: - * @arg @ref LL_LED_DISP_NONE - * @arg @ref LL_LED_DISP_FULL - * @arg @ref LL_LED_DISP_0 - * @arg @ref LL_LED_DISP_1 - * @arg @ref LL_LED_DISP_2 - * @arg @ref LL_LED_DISP_3 - * @arg @ref LL_LED_DISP_4 - * @arg @ref LL_LED_DISP_5 - * @arg @ref LL_LED_DISP_6 - * @arg @ref LL_LED_DISP_7 - * @arg @ref LL_LED_DISP_8 - * @arg @ref LL_LED_DISP_9 - * @arg @ref LL_LED_DISP_A - * @arg @ref LL_LED_DISP_B - * @arg @ref LL_LED_DISP_C - * @arg @ref LL_LED_DISP_D - * @arg @ref LL_LED_DISP_E - * @arg @ref LL_LED_DISP_F - * @arg @ref LL_LED_DISP_H - * @arg @ref LL_LED_DISP_P - * @arg @ref LL_LED_DISP_U - * @arg @ref LL_LED_DISP_DOT - * @retval None - */ -__STATIC_INLINE void LL_LED_SetDisplayValue(LED_TypeDef *LEDx,uint32_t comCh,\ - uint32_t data) -{ - MODIFY_REG((*((uint32_t *)((uint32_t)&(LEDx->DR0) + comCh))), LL_LED_DR_DATA,\ - (data << LL_LED_DR_DATA_Pos)); -} - -/** - * @brief Get the LED display value. - * @param LEDx LED Instance - * @param comCh Specify COM channels.This parameter can be one of the following values: - * @arg @ref LL_LED_COM0 - * @arg @ref LL_LED_COM1 - * @arg @ref LL_LED_COM2 - * @arg @ref LL_LED_COM3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_LED_DISP_NONE - * @arg @ref LL_LED_DISP_FULL - * @arg @ref LL_LED_DISP_0 - * @arg @ref LL_LED_DISP_1 - * @arg @ref LL_LED_DISP_2 - * @arg @ref LL_LED_DISP_3 - * @arg @ref LL_LED_DISP_4 - * @arg @ref LL_LED_DISP_5 - * @arg @ref LL_LED_DISP_6 - * @arg @ref LL_LED_DISP_7 - * @arg @ref LL_LED_DISP_8 - * @arg @ref LL_LED_DISP_9 - * @arg @ref LL_LED_DISP_A - * @arg @ref LL_LED_DISP_B - * @arg @ref LL_LED_DISP_C - * @arg @ref LL_LED_DISP_D - * @arg @ref LL_LED_DISP_E - * @arg @ref LL_LED_DISP_F - * @arg @ref LL_LED_DISP_H - * @arg @ref LL_LED_DISP_P - * @arg @ref LL_LED_DISP_U - * @arg @ref LL_LED_DISP_DOT - */ -__STATIC_INLINE uint32_t LL_LED_GetDisplayValue(LED_TypeDef *LEDx, uint32_t comCh) -{ - return ((READ_BIT((*((uint32_t *)((uint32_t)&(LEDx->DR0) + comCh))), LL_LED_DR_DATA))\ - >> LL_LED_DR_DATA_Pos); -} - - -/** - * @brief Get the LED interrupt flag. - * @param LEDx LED Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_LED_IsActiveFlag_IT(LED_TypeDef *LEDx) -{ - return ((READ_BIT(LEDx->IR, LED_IR_FLAG) == (LED_IR_FLAG)) ? 1UL : 0UL); -} - -/** - * @brief the LED interrupt flag. - * @param LEDx LED Instance - * @retval None - */ -__STATIC_INLINE void LL_LED_ClearFlag_IT(LED_TypeDef *LEDx) -{ - SET_BIT(LEDx->IR, LED_IR_FLAG); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup LED_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_LED_DeInit(LED_TypeDef *LEDx); -ErrorStatus LL_LED_Init(LED_TypeDef *LEDx, LL_LED_InitTypeDef *LED_InitStruct); -void LL_LED_StructInit(LL_LED_InitTypeDef *LED_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -#endif /* LED */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* PY32F0xx_LL_LED_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_led.h + * @author MCU Application Team + * @brief Header file of LED LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef PY32F0XX_LL_LED_H +#define PY32F0XX_LL_LED_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0XX_LL_Driver + * @{ + */ + +#if defined (LED) +/** @defgroup LED_LL LED + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/** + * @brief LED Init Structure definition + */ +typedef struct +{ + uint32_t ComDrive; /*!< Specifies the LED COM drive capability. + This parameter can be a value of @ref LED_LL_EC_ComDrive */ + + uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the LED clock. + This parameter can be a number between Min_Data = 0x00(div1) and Max_Data = 0xFF(div256) */ + + uint32_t ComSelect; /*!< Specifies the number of COM open. + This parameter can be a value of @ref LED_LL_EC_ComSelct */ + + uint32_t LightTime; /*!< Specifies LED Lighting time. + This parameter can be a number between Min_Data = 1 and Max_Data = 0xFF */ + + uint32_t DeadTime; /*!< Specifies LED Dead time. + This parameter can be a number between Min_Data = 1 and Max_Data = 0xFF */ + +} LL_LED_InitTypeDef; + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup LED_LL_EC_ComDrive ComDrive + * @{ + */ +#define LL_LED_COMDRIVE_LOW 0x00000000U +#define LL_LED_COMDRIVE_HIGH LED_CR_EHS +/** + * @} + */ + + +/** @defgroup LED_LL_EC_ComSelct the number of COM open + * @{ + */ +#define LL_LED_COMSELECT_1COM 0x00000000U +#define LL_LED_COMSELECT_2COM LED_CR_LED_COM_SEL_0 +#define LL_LED_COMSELECT_3COM LED_CR_LED_COM_SEL_1 +#define LL_LED_COMSELECT_4COM (LED_CR_LED_COM_SEL_1 | LED_CR_LED_COM_SEL_0) +/** + * @} + */ + +/** @defgroup LED_LL_EC_DisplayValue LED display value + * @{ + */ +#define LL_LED_DISP_NONE 0x00U +#define LL_LED_DISP_FULL 0xFFU + +#define LL_LED_DISP_0 0x3FU +#define LL_LED_DISP_1 0x06U +#define LL_LED_DISP_2 0x5BU +#define LL_LED_DISP_3 0x4FU +#define LL_LED_DISP_4 0x66U +#define LL_LED_DISP_5 0x6DU +#define LL_LED_DISP_6 0x7DU +#define LL_LED_DISP_7 0x07U +#define LL_LED_DISP_8 0x7FU +#define LL_LED_DISP_9 0x6FU +#define LL_LED_DISP_A 0x77U +#define LL_LED_DISP_B 0x7CU +#define LL_LED_DISP_C 0x39U +#define LL_LED_DISP_D 0x5EU +#define LL_LED_DISP_E 0x79U +#define LL_LED_DISP_F 0x71U +#define LL_LED_DISP_H 0x76U +#define LL_LED_DISP_P 0x73U +#define LL_LED_DISP_U 0x3EU +#define LL_LED_DISP_DOT 0x80U +/** + * @} + */ + +/** @defgroup LED_LL_EC_ComDisplay LED COM Select + * @{ + */ +#define LL_LED_COM0 0x00000000U +#define LL_LED_COM1 0x00000004U +#define LL_LED_COM2 0x00000008U +#define LL_LED_COM3 0x0000000CU +/** + * @} + */ + +/** @defgroup LED_LL_EC_DataReg Data Register Mask and position + * @{ + */ +#define LL_LED_DR_DATA LED_DR0_DATA0 +#define LL_LED_DR_DATA_Pos LED_DR0_DATA0_Pos +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** + * @brief Set the LED COM drive capability. + * @param LEDx LED Instance + * @param ComDrive This parameter can be one of the following values: + * @arg @ref LL_LED_COMDRIVE_LOW + * @arg @ref LL_LED_COMDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_LED_SetComDrive(LED_TypeDef *LEDx, uint32_t ComDrive) +{ + MODIFY_REG(LEDx->CR, LED_CR_EHS, ComDrive); +} + +/** + * @brief Get the LED COM drive capability. + * @param LEDx LED Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LED_COMDRIVE_LOW + * @arg @ref LL_LED_COMDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_LED_GetComDrive(LED_TypeDef *LEDx) +{ + return (READ_BIT(LEDx->CR, LED_CR_EHS)); +} + +/** + * @brief Enable LED Interrupt. + * @param LEDx LED Instance + * @retval None + */ +__STATIC_INLINE void LL_LED_EnableIT(LED_TypeDef *LEDx) +{ + SET_BIT(LEDx->CR, LED_CR_IE); +} + +/** + * @brief Disable LED Interrupt. + * @param LEDx LED Instance + * @retval None + */ +__STATIC_INLINE void LL_LED_DisableIT(LED_TypeDef *LEDx) +{ + CLEAR_BIT(LEDx->CR, LED_CR_IE); +} +/** + * @brief Check if LED Interrupt is enabled + * @param LEDx LED Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LED_IsEnabledIT(LED_TypeDef *LEDx) +{ + return ((READ_BIT(LEDx->CR, LED_CR_IE) == (LED_CR_IE)) ? 1UL : 0UL); +} + +/** + * @brief Set he number of COM open. + * @param LEDx LED Instance + * @param ComNum This parameter can be one of the following values: + * @arg @ref LL_LED_COMSELECT_1COM + * @arg @ref LL_LED_COMSELECT_2COM + * @arg @ref LL_LED_COMSELECT_3COM + * @arg @ref LL_LED_COMSELECT_4COM + * @retval None + */ +__STATIC_INLINE void LL_LED_SetComNum(LED_TypeDef *LEDx, uint32_t ComNum) +{ + MODIFY_REG(LEDx->CR, LED_CR_LED_COM_SEL, ComNum); +} + +/** + * @brief Get the number of COM open. + * @param LEDx LED Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_LED_COMSELECT_1COM + * @arg @ref LL_LED_COMSELECT_2COM + * @arg @ref LL_LED_COMSELECT_3COM + * @arg @ref LL_LED_COMSELECT_4COM + */ +__STATIC_INLINE uint32_t LL_LED_GetComNum(LED_TypeDef *LEDx) +{ + return (READ_BIT(LEDx->CR, LED_CR_LED_COM_SEL)); +} + + +/** + * @brief Enable LED. + * @param LEDx LED Instance + * @retval None + */ +__STATIC_INLINE void LL_LED_Enable(LED_TypeDef *LEDx) +{ + SET_BIT(LEDx->CR, LED_CR_LEDON); +} + +/** + * @brief Disable LED. + * @param LEDx LED Instance + * @retval None + */ +__STATIC_INLINE void LL_LED_Disable(LED_TypeDef *LEDx) +{ + CLEAR_BIT(LEDx->CR, LED_CR_LEDON); +} + +/** + * @brief Checks if LED is enabled + * @param LEDx LED Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LED_IsEnabled(LED_TypeDef *LEDx) +{ + return ((READ_BIT(LEDx->CR, LED_CR_LEDON) == (LED_CR_LEDON)) ? 1UL : 0UL); +} + +/** + * @brief Set the LED prescale Value. + * @param LEDx LED Instance + * @param Prescaler This parameter can be a number between Min_Data = 0x00(div1) + * and Max_Data = 0xFF(div256) + * @retval None + */ +__STATIC_INLINE void LL_LED_SetPrescaler(LED_TypeDef *LEDx, uint32_t Prescaler) +{ + MODIFY_REG(LEDx->PR, LED_PR_PR, (Prescaler << LED_PR_PR_Pos)); +} + +/** + * @brief Return LED Prescaler Value. + * @param LEDx LED Instance + * @retval Returned value can be a number between Min_Data = 0x00(div1) + * and Max_Data = 0xFF(div256) + */ +__STATIC_INLINE uint32_t LL_LED_GetPrescaler(LED_TypeDef *LEDx) +{ + return (READ_BIT(LEDx->PR, LED_PR_PR) >> LED_PR_PR_Pos); +} + +/** + * @brief Set the LED Lighting and Dead time. + * @param LEDx LED Instance + * @param LightTime This parameter can be a number between Min_Data = 1 and + * Max_Data = 0xFF + * @param DeadTime This parameter can be a number between Min_Data = 1 and + * Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void LL_LED_SetLightAndDeadTime(LED_TypeDef *LEDx,\ + uint32_t LightTime, uint32_t DeadTime) +{ + MODIFY_REG(LEDx->TR, (LED_TR_T1 | LED_TR_T2), ((LightTime << LED_TR_T1_Pos) |\ + (DeadTime << LED_TR_T2_Pos))); +} + +/** + * @brief Set the LED Lighting time. + * @param LEDx LED Instance + * @param LightTime This parameter can be a number between Min_Data = 1 and + * Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void LL_LED_SetLightTime(LED_TypeDef *LEDx, uint32_t LightTime) +{ + MODIFY_REG(LEDx->TR, LED_TR_T1, (LightTime << LED_TR_T1_Pos)); +} + +/** + * @brief Set the LED Dead time. + * @param LEDx LED Instance + * @param DeadTime This parameter can be a number between Min_Data = 1 and + * Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void LL_LED_SetDeadTime(LED_TypeDef *LEDx, uint32_t DeadTime) +{ + MODIFY_REG(LEDx->TR, LED_TR_T2, (DeadTime << LED_TR_T2_Pos)); +} + +/** + * @brief Get the LED Lighting time. + * @param LEDx LED Instance + * @retval Returned value can be a number between Min_Data = 1 and + * Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_LED_GetLightTime(LED_TypeDef *LEDx) +{ + return (READ_BIT(LEDx->TR, LED_TR_T1) >> LED_TR_T1_Pos); +} + +/** + * @brief Get the LED Dead time. + * @param LEDx LED Instance + * @retval Returned value can be a number between Min_Data = 1 and + * Max_Data = 0xFF + */ +__STATIC_INLINE uint32_t LL_LED_GetDeadTime(LED_TypeDef *LEDx) +{ + return (READ_BIT(LEDx->TR, LED_TR_T2) >> LED_TR_T2_Pos); +} + +/** + * @brief Set the LED display value. + * @param LEDx LED Instance + * @param comCh Specify COM channels.This parameter can be one of the following values: + * @arg @ref LL_LED_COM0 + * @arg @ref LL_LED_COM1 + * @arg @ref LL_LED_COM2 + * @arg @ref LL_LED_COM3 + * @param data Specify display values.This parameter can be one of the following values: + * @arg @ref LL_LED_DISP_NONE + * @arg @ref LL_LED_DISP_FULL + * @arg @ref LL_LED_DISP_0 + * @arg @ref LL_LED_DISP_1 + * @arg @ref LL_LED_DISP_2 + * @arg @ref LL_LED_DISP_3 + * @arg @ref LL_LED_DISP_4 + * @arg @ref LL_LED_DISP_5 + * @arg @ref LL_LED_DISP_6 + * @arg @ref LL_LED_DISP_7 + * @arg @ref LL_LED_DISP_8 + * @arg @ref LL_LED_DISP_9 + * @arg @ref LL_LED_DISP_A + * @arg @ref LL_LED_DISP_B + * @arg @ref LL_LED_DISP_C + * @arg @ref LL_LED_DISP_D + * @arg @ref LL_LED_DISP_E + * @arg @ref LL_LED_DISP_F + * @arg @ref LL_LED_DISP_H + * @arg @ref LL_LED_DISP_P + * @arg @ref LL_LED_DISP_U + * @arg @ref LL_LED_DISP_DOT + * @retval None + */ +__STATIC_INLINE void LL_LED_SetDisplayValue(LED_TypeDef *LEDx,uint32_t comCh,\ + uint32_t data) +{ + MODIFY_REG((*((uint32_t *)((uint32_t)&(LEDx->DR0) + comCh))), LL_LED_DR_DATA,\ + (data << LL_LED_DR_DATA_Pos)); +} + +/** + * @brief Get the LED display value. + * @param LEDx LED Instance + * @param comCh Specify COM channels.This parameter can be one of the following values: + * @arg @ref LL_LED_COM0 + * @arg @ref LL_LED_COM1 + * @arg @ref LL_LED_COM2 + * @arg @ref LL_LED_COM3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_LED_DISP_NONE + * @arg @ref LL_LED_DISP_FULL + * @arg @ref LL_LED_DISP_0 + * @arg @ref LL_LED_DISP_1 + * @arg @ref LL_LED_DISP_2 + * @arg @ref LL_LED_DISP_3 + * @arg @ref LL_LED_DISP_4 + * @arg @ref LL_LED_DISP_5 + * @arg @ref LL_LED_DISP_6 + * @arg @ref LL_LED_DISP_7 + * @arg @ref LL_LED_DISP_8 + * @arg @ref LL_LED_DISP_9 + * @arg @ref LL_LED_DISP_A + * @arg @ref LL_LED_DISP_B + * @arg @ref LL_LED_DISP_C + * @arg @ref LL_LED_DISP_D + * @arg @ref LL_LED_DISP_E + * @arg @ref LL_LED_DISP_F + * @arg @ref LL_LED_DISP_H + * @arg @ref LL_LED_DISP_P + * @arg @ref LL_LED_DISP_U + * @arg @ref LL_LED_DISP_DOT + */ +__STATIC_INLINE uint32_t LL_LED_GetDisplayValue(LED_TypeDef *LEDx, uint32_t comCh) +{ + return ((READ_BIT((*((uint32_t *)((uint32_t)&(LEDx->DR0) + comCh))), LL_LED_DR_DATA))\ + >> LL_LED_DR_DATA_Pos); +} + + +/** + * @brief Get the LED interrupt flag. + * @param LEDx LED Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_LED_IsActiveFlag_IT(LED_TypeDef *LEDx) +{ + return ((READ_BIT(LEDx->IR, LED_IR_FLAG) == (LED_IR_FLAG)) ? 1UL : 0UL); +} + +/** + * @brief the LED interrupt flag. + * @param LEDx LED Instance + * @retval None + */ +__STATIC_INLINE void LL_LED_ClearFlag_IT(LED_TypeDef *LEDx) +{ + SET_BIT(LEDx->IR, LED_IR_FLAG); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup LED_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_LED_DeInit(LED_TypeDef *LEDx); +ErrorStatus LL_LED_Init(LED_TypeDef *LEDx, LL_LED_InitTypeDef *LED_InitStruct); +void LL_LED_StructInit(LL_LED_InitTypeDef *LED_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +#endif /* LED */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PY32F0xx_LL_LED_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_lptim.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_lptim.h similarity index 99% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_lptim.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_lptim.h index 89006fe..60940a9 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_lptim.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_lptim.h @@ -4,18 +4,18 @@ * @author MCU Application Team * @brief Header file of LPTIM LL module. ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_pwr.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_pwr.h similarity index 100% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_pwr.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_pwr.h diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_rcc.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_rcc.h similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_rcc.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_rcc.h index 139a410..094bb3d 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_rcc.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_rcc.h @@ -1,1921 +1,1921 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_rcc.h - * @author MCU Application Team - * @brief Header file of RCC LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PY32F0XX_LL_RCC_H -#define __PY32F0XX_LL_RCC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0XX_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @defgroup RCC_LL RCC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup RCC_LL_Private_Variables RCC Private Variables - * @{ - */ - - -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Private_Macros RCC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_Exported_Types RCC Exported Types - * @{ - */ - -/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure - * @{ - */ - -/** - * @brief RCC Clocks Frequency Structure - */ -typedef struct -{ - uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ - uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ - uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ -} LL_RCC_ClocksTypeDef; - -/** - * @} - */ - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants - * @{ - */ - -/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation - * @brief Defines used to adapt values of different oscillators - * @note These values could be modified in the user environment according to - * HW set-up. - * @{ - */ -#if !defined (HSE_VALUE) -#define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */ -#endif /* HSE_VALUE */ - -#if !defined (HSI_VALUE) -#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ -#endif /* HSI_VALUE */ - -#if defined(RCC_LSE_SUPPORT) -#if !defined (LSE_VALUE) -#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ -#endif /* LSE_VALUE */ -#endif - -#if !defined (LSI_VALUE) -#define LSI_VALUE 32768U /*!< Value of the LSI oscillator in Hz */ -#endif /* LSI_VALUE */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines - * @brief Flags defines which can be used with LL_RCC_WriteReg function - * @{ - */ -#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ -#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ -#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ -#if defined(RCC_PLL_SUPPORT) -#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ -#endif -#if defined(RCC_LSE_SUPPORT) -#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ -#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ -#endif -#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ - -/** - * @} - */ - -/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_RCC_ReadReg function - * @{ - */ -#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ -#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ -#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ -#if defined(RCC_PLL_SUPPORT) -#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ -#endif -#if defined(RCC_LSE_SUPPORT) -#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ -#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ -#endif -#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ - -#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ -#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ -#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ -#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ -#if defined(WWDG) -#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ -#endif -#define LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions - * @{ - */ -#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ -#if defined(RCC_LSE_SUPPORT) -#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ -#endif -#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ -#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ -#if defined(RCC_PLL_SUPPORT) -#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ -#endif -/** - * @} - */ - -#if defined(RCC_LSE_SUPPORT) -/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability - * @{ - */ -#define LL_RCC_LSEDRIVE_CLOSE 0x00000000 /*!< Xtal mode driving capability closed */ -#define LL_RCC_LSEDRIVE_LOW RCC_ECSCR_LSE_DRIVER_0 /*!< Xtal mode lower driving capability */ -#define LL_RCC_LSEDRIVE_MEDIUM RCC_ECSCR_LSE_DRIVER_1 /*!< Xtal mode medium driving capability */ -#define LL_RCC_LSEDRIVE_HIGH RCC_ECSCR_LSE_DRIVER /*!< Xtal mode higher driving capability */ -/** - * @} - */ -#endif - - -#if defined(RCC_BDCR_LSCOSEL) -/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection - * @{ - */ -#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ -#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ -#endif -/** - * @} - */ - - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_HSISYS 0x00000000U /*!< HSISYS selection as system clock */ -#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ -#if defined(RCC_PLL_SUPPORT) -#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_1 /*!< PLL selection as system clock */ -#endif -#define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection used as system clock */ -#if defined(RCC_LSE_SUPPORT) -#define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection used as system clock */ -#endif -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status - * @{ - */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS 0x00000000U /*!< HSISYS used as system clock */ -#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ -#if defined(RCC_PLL_SUPPORT) -#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_1 /*!< PLL used as system clock */ -#endif -#define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ -#if defined(RCC_LSE_SUPPORT) -#define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ -#endif -/** - * @} - */ - -/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler - * @{ - */ -#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ -#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ -#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ -#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ -#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ -#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ -#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ -#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ -#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_APB1_DIV APB1 low-speed prescaler (APB1) - * @{ - */ -#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */ -#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */ -#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */ -#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */ -#define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_HSI_DIV HSI division factor - * @{ - */ -#define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI not divided */ -#define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI divided by 2 */ -#define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI divided by 4 */ -#define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) /*!< HSI divided by 8 */ -#define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2 /*!< HSI divided by 16 */ -#define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0) /*!< HSI divided by 32 */ -#define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1) /*!< HSI divided by 64 */ -#define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV /*!< HSI divided by 128 */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection - * @{ - */ -#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ -#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ -#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ -#if defined(RCC_PLL_SUPPORT) -#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ -#endif -#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ -#if defined(RCC_LSE_SUPPORT) -#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ -#endif -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCO Peripheral MCO get clock source - * @{ - */ -#define LL_RCC_MCO1_CLKSOURCE RCC_CFGR_MCOSEL /*!< MCO1 Clock source selection */ -/** - * @} - */ - -/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler - * @{ - */ -#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO1 not divided */ -#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO1 divided by 2 */ -#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO1 divided by 4 */ -#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 8 */ -#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO1 divided by 16 */ -#define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 32 */ -#define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 64 */ -#define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency - * @{ - */ -#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ -#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -#if defined(RCC_CCIPR_PVDSEL) -/** @defgroup RCC_LL_EC_PVD_CLKSOURCE Peripheral PVD clock source selection - * @{ - */ -#define LL_RCC_PVD_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as PVD clock */ -#define LL_RCC_PVD_CLKSOURCE_LSC RCC_CCIPR_PVDSEL /*!< LSC selected as PVD clock */ -/** - * @} - */ -#endif - -#if defined(COMP1) -/** @defgroup RCC_LL_EC_COMPx_CLKSOURCE Peripheral COMP clock source selection - * @{ - */ -#define LL_RCC_COMP1_CLKSOURCE_PCLK1 (RCC_CCIPR_COMP1SEL | (0x00000000U >> 8U)) /*!< PCLK1 selected as COMP1 clock */ -#define LL_RCC_COMP1_CLKSOURCE_LSC (RCC_CCIPR_COMP1SEL | (RCC_CCIPR_COMP1SEL >> 8U)) /*!< LSC selected as COMP1 clock */ -#if defined(COMP2) -#define LL_RCC_COMP2_CLKSOURCE_PCLK1 (RCC_CCIPR_COMP2SEL | (0x00000000U >> 8U)) /*!< PCLK1 selected as COMP2 clock */ -#define LL_RCC_COMP2_CLKSOURCE_LSC (RCC_CCIPR_COMP2SEL | (RCC_CCIPR_COMP2SEL >> 8U)) /*!< LSC selected as COMP2 clock */ -#endif -/** - * @} - */ -#endif /* COMP1 && COMP2 */ - -#if defined(RCC_CCIPR_LPTIMSEL) -/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection - * @{ - */ -#define LL_RCC_LPTIM1_CLKSOURCE_NONE (RCC_CCIPR_LPTIMSEL | (RCC_CCIPR_LPTIMSEL_1 >> 16U)) /*!< No clock used as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIMSEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM1 clock */ -#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIMSEL | (RCC_CCIPR_LPTIMSEL_0 >> 16U)) /*!< LSI selected as LPTIM1 clock */ -#if defined(RCC_LSE_SUPPORT) -#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIMSEL | (RCC_CCIPR_LPTIMSEL >> 16U)) /*!< LSE selected as LPTIM1 clock */ -#endif -/** - * @} - */ -#endif /* RCC_CCIPR_LPTIMSEL */ - -#if defined(RCC_BDCR_RTCSEL) -/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection - * @{ - */ -#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ -#if defined(RCC_LSE_SUPPORT) -#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ -#endif -#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ -#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */ -/** - * @} - */ -#endif - -#if defined(RCC_PLL_SUPPORT) -/** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source - * @{ - */ -#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ -#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ -#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ -/** - * @} - */ -#endif - -#if defined(COMP1) -/** @defgroup RCC_LL_EC_COMP Peripheral COMP get clock source - * @{ - */ -#define LL_RCC_COMP1_CLKSOURCE RCC_CCIPR_COMP1SEL /*!< COMP1 Clock source selection */ -#if defined(COMP2) -#define LL_RCC_COMP2_CLKSOURCE RCC_CCIPR_COMP2SEL /*!< COMP2 Clock source selection */ -#endif /* COMP2 */ -/** - * @} - */ -#endif /* COMP1 */ - -#if defined(RCC_CCIPR_LPTIMSEL) -/** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIM get clock source - * @{ - */ -#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIMSEL /*!< LPTIM1 Clock source selection */ -/** - * @} - */ -#endif /* RCC_CCIPR_LPTIMSEL */ - -/** @defgroup RCC_HSE_EC_Freq HSE Config - * @{ - */ -#define LL_RCC_HSE_STOP 0x00000000U -#define LL_RCC_HSE_4_8MHz RCC_ECSCR_HSE_FREQ_0 -#define LL_RCC_HSE_8_16MHz RCC_ECSCR_HSE_FREQ_1 -#if defined(PY32F002PRE) -#define LL_RCC_HSE_16_24MHz (RCC_ECSCR_HSE_FREQ_0 | RCC_ECSCR_HSE_FREQ_1) -#else -#define LL_RCC_HSE_16_32MHz (RCC_ECSCR_HSE_FREQ_0 | RCC_ECSCR_HSE_FREQ_1) -#endif -/** - * @} - */ - -/** @defgroup RCC_HSI_EC_Calibration HSI Calibration -* @{ -*/ -#if defined(PY32F002PRE) -#define LL_RCC_HSICALIBRATION_8MHz ((0x1<<13) | ((*(uint32_t *)(0x1FFF0F04)) & 0x1FFF)) /*!< 8MHz HSI calibration trimming value */ -#define LL_RCC_HSICALIBRATION_24MHz ((0x4<<13) | ((*(uint32_t *)(0x1FFF0F10)) & 0x1FFF)) /*!< 24MHz HSI calibration trimming value */ -#else -#define LL_RCC_HSICALIBRATION_4MHz ((0x0<<13) | ((*(uint32_t *)(0x1FFF0F00)) & 0x1FFF)) /*!< 4MHz HSI calibration trimming value */ -#define LL_RCC_HSICALIBRATION_8MHz ((0x1<<13) | ((*(uint32_t *)(0x1FFF0F04)) & 0x1FFF)) /*!< 8MHz HSI calibration trimming value */ -#define LL_RCC_HSICALIBRATION_16MHz ((0x2<<13) | ((*(uint32_t *)(0x1FFF0F08)) & 0x1FFF)) /*!< 16MHz HSI calibration trimming value */ -#define LL_RCC_HSICALIBRATION_22p12MHz ((0x3<<13) | ((*(uint32_t *)(0x1FFF0F0C)) & 0x1FFF)) /*!< 22.12MHz HSI calibration trimming value */ -#define LL_RCC_HSICALIBRATION_24MHz ((0x4<<13) | ((*(uint32_t *)(0x1FFF0F10)) & 0x1FFF)) /*!< 24MHz HSI calibration trimming value */ -#endif -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros - * @{ - */ - -/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RCC register - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__)) - -/** - * @brief Read a value in RCC register - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) -/** - * @} - */ - -/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies - * @{ - */ -#if defined(RCC_PLL_SUPPORT) -/** - * @brief Helper macro to calculate the PLLCLK frequency on system domain - * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) - - * @retval PLL clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__) ((__INPUTFREQ__) * 2) -#endif - -/** - * @brief Helper macro to calculate the HCLK frequency - * @param __SYSCLKFREQ__ SYSCLK frequency - * @param __AHBPRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval HCLK clock frequency (in Hz) - */ -#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) \ - ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU)) - -/** - * @brief Helper macro to calculate the PCLK1 frequency (APB1) - * @param __HCLKFREQ__ HCLK frequency - * @param __APB1PRESCALER__ This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval PCLK1 clock frequency (in Hz) - */ -#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \ - ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos] & 0x1FU)) - -/** - * @brief Helper macro to calculate the HSISYS frequency - * @param __HSIDIV__ This parameter can be one of the following values: - * @arg @ref LL_RCC_HSI_DIV_1 - * @arg @ref LL_RCC_HSI_DIV_2 - * @arg @ref LL_RCC_HSI_DIV_4 - * @arg @ref LL_RCC_HSI_DIV_8 - * @arg @ref LL_RCC_HSI_DIV_16 - * @arg @ref LL_RCC_HSI_DIV_32 - * @arg @ref LL_RCC_HSI_DIV_64 - * @arg @ref LL_RCC_HSI_DIV_128 - * @retval HSISYS clock frequency (in Hz) - */ -#define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) \ - (HSIFreqTable[(RCC->ICSCR & RCC_ICSCR_HSI_FS) >> RCC_ICSCR_HSI_FS_Pos] / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos))) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions - * @{ - */ - -/** @defgroup RCC_LL_EF_HSE HSE - * @{ - */ - -/** - * @brief Enable the Clock Security System. - * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) -{ - SET_BIT(RCC->CR, RCC_CR_CSSON); -} - -/** - * @brief Enable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Disable HSE external oscillator (HSE Bypass) - * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); -} - -/** - * @brief Enable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Disable HSE crystal oscillator (HSE ON) - * @rmtoll CR HSEON LL_RCC_HSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSEON); -} - -/** - * @brief Check if HSE oscillator Ready - * @rmtoll CR HSERDY LL_RCC_HSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); -} - -/** - * @brief Set HSE Crystal working frequency - * @param HSEFreq This parameter can be one of the following values: - * @arg @ref LL_RCC_HSE_STOP - * @arg @ref LL_RCC_HSE_4_8MHz - * @arg @ref LL_RCC_HSE_8_16MHz - * @arg @ref LL_RCC_HSE_16_32MHz or LL_RCC_HSE_16_24MHz - * @note The maximum working frequency varies depending on the devices. - * Refer to the devices data sheet for the maximum working frequency. - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSE_SetFreqRegion(uint32_t HSEFreq) -{ - MODIFY_REG(RCC->ECSCR, RCC_ECSCR_HSE_FREQ, HSEFreq); -} - - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_HSI HSI - * @{ - */ - -/** - * @brief Enable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Disable HSI oscillator - * @rmtoll CR HSION LL_RCC_HSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_HSION); -} - -/** - * @brief Check if HSI clock is ready - * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); -} - -/** - * @brief Set HSI Calibration trimming - * @param Value Between Min_Data = 0 and Max_Data = 0x1FFF - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) -{ - MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, Value << RCC_ICSCR_HSI_TRIM_Pos); -} - -/** - * @brief Get HSI Calibration trimming - * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming - * @retval Between Min_Data = 0 and Max_Data = 0x1FFF - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) -{ - return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_TRIM) >> RCC_ICSCR_HSI_TRIM_Pos); -} - -/** - * @brief Set HSI Calibration Frequency - * @param Value This parameter can be one of the following values: - * @arg @ref LL_RCC_HSICALIBRATION_4MHz - * @arg @ref LL_RCC_HSICALIBRATION_8MHz - * @arg @ref LL_RCC_HSICALIBRATION_16MHz - * @arg @ref LL_RCC_HSICALIBRATION_22p12MHz - * @arg @ref LL_RCC_HSICALIBRATION_24MHz - * @note Depending on devices and packages, some calibration values may not be available. - * Refer to device datasheet for calibration values availability. - * @retval None - */ -__STATIC_INLINE void LL_RCC_HSI_SetCalibFreq(uint32_t Value) -{ - MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_HSI_FS | RCC_ICSCR_HSI_TRIM), Value); -} - -/** - * @brief Get HSI Frequency - * @retval HSI clock frequency (in Hz) - */ -__STATIC_INLINE uint32_t LL_RCC_HSI_GetFreq(void) -{ - return (uint32_t)HSIFreqTable[(RCC->ICSCR & RCC_ICSCR_HSI_FS) >> RCC_ICSCR_HSI_FS_Pos]; -} - -/** - * @} - */ - -#if defined(RCC_LSE_SUPPORT) -/** @defgroup RCC_LL_EF_LSE LSE - * @{ - */ - -/** - * @brief Enable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Enable(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Disable Low Speed External (LSE) crystal. - * @rmtoll BDCR LSEON LL_RCC_LSE_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_Disable(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); -} - -/** - * @brief Enable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Disable external clock source (LSE bypass). - * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); -} - -/** - * @brief Set LSE oscillator drive capability - * @note The oscillator is in Xtal mode when it is not in bypass mode. - * @param LSEDrive This parameter can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_CLOSE - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUM - * @arg @ref LL_RCC_LSEDRIVE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) -{ - MODIFY_REG(RCC->ECSCR, RCC_ECSCR_LSE_DRIVER, LSEDrive); -} - -/** - * @brief Get LSE oscillator drive capability - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LSEDRIVE_CLOSE - * @arg @ref LL_RCC_LSEDRIVE_LOW - * @arg @ref LL_RCC_LSEDRIVE_MEDIUM - * @arg @ref LL_RCC_LSEDRIVE_HIGH - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) -{ - return (uint32_t)(READ_BIT(RCC->ECSCR, RCC_ECSCR_LSE_DRIVER)); -} - - -/** - * @brief Enable Clock security system on LSE. - * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); -} - -/** - * @brief Disable Clock security system on LSE. - * @note Clock security system can be disabled only after a LSE - * failure detection. In that case it MUST be disabled by software. - * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); -} - - -/** - * @brief Check if LSE oscillator Ready - * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) -{ - return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); -} - -/** - * @brief Check if CSS on LSE failure Detection - * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) -{ - return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL); -} - -/** - * @} - */ -#endif - -/** @defgroup RCC_LL_EF_LSI LSI - * @{ - */ - -/** - * @brief Enable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Enable(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Disable LSI Oscillator - * @rmtoll CSR LSION LL_RCC_LSI_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSI_Disable(void) -{ - CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); -} - -/** - * @brief Check if LSI is Ready - * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); -} - -/** - * @} - */ -#if defined(RCC_BDCR_LSCOEN) -/** @defgroup RCC_LL_EF_LSCO LSCO - * @{ - */ - -/** - * @brief Enable Low speed clock - * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSCO_Enable(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); -} - -/** - * @brief Disable Low speed clock - * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSCO_Disable(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); -} -#if defined(RCC_BDCR_LSCOSEL) -/** - * @brief Configure Low speed clock selection - * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI - * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); -} - -/** - * @brief Get Low speed clock selection - * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI - * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE - */ -__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); -} - -/** - * @} - */ -#endif -#endif -/** @defgroup RCC_LL_EF_System System - * @{ - */ - -/** - * @brief Configure the system clock source - * @rmtoll CFGR SW LL_RCC_SetSysClkSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSISYS - * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL - * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE - * @note Depending on devices and packages, some clocks may not be available. - * Refer to device datasheet for clocks availability. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); -} - -/** - * @brief Get the system clock source - * @rmtoll CFGR SWS LL_RCC_GetSysClkSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI - * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE - * @note Depending on devices and packages, some clocks may not be available. - * Refer to device datasheet for clocks availability. - */ -__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); -} - -/** - * @brief Set AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); -} - -/** - * @brief Set APB1 prescaler - * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); -} - -/** - * @brief Set HSI division factor - * @rmtoll CR HSIDIV LL_RCC_SetHSIDiv - * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as - * system clock source. - * @param HSIDiv This parameter can be one of the following values: - * @arg @ref LL_RCC_HSI_DIV_1 - * @arg @ref LL_RCC_HSI_DIV_2 - * @arg @ref LL_RCC_HSI_DIV_4 - * @arg @ref LL_RCC_HSI_DIV_8 - * @arg @ref LL_RCC_HSI_DIV_16 - * @arg @ref LL_RCC_HSI_DIV_32 - * @arg @ref LL_RCC_HSI_DIV_64 - * @arg @ref LL_RCC_HSI_DIV_128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv) -{ - MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv); -} -/** - * @brief Get AHB prescaler - * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_SYSCLK_DIV_1 - * @arg @ref LL_RCC_SYSCLK_DIV_2 - * @arg @ref LL_RCC_SYSCLK_DIV_4 - * @arg @ref LL_RCC_SYSCLK_DIV_8 - * @arg @ref LL_RCC_SYSCLK_DIV_16 - * @arg @ref LL_RCC_SYSCLK_DIV_64 - * @arg @ref LL_RCC_SYSCLK_DIV_128 - * @arg @ref LL_RCC_SYSCLK_DIV_256 - * @arg @ref LL_RCC_SYSCLK_DIV_512 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); -} - -/** - * @brief Get APB1 prescaler - * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_APB1_DIV_1 - * @arg @ref LL_RCC_APB1_DIV_2 - * @arg @ref LL_RCC_APB1_DIV_4 - * @arg @ref LL_RCC_APB1_DIV_8 - * @arg @ref LL_RCC_APB1_DIV_16 - */ -__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); -} - -/** - * @brief Get HSI division factor - * @rmtoll CR HSIDIV LL_RCC_GetHSIDiv - * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as - * system clock source. - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_HSI_DIV_1 - * @arg @ref LL_RCC_HSI_DIV_2 - * @arg @ref LL_RCC_HSI_DIV_4 - * @arg @ref LL_RCC_HSI_DIV_8 - * @arg @ref LL_RCC_HSI_DIV_16 - * @arg @ref LL_RCC_HSI_DIV_32 - * @arg @ref LL_RCC_HSI_DIV_64 - * @arg @ref LL_RCC_HSI_DIV_128 - */ -__STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void) -{ - return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)); -} -/** - * @} - */ - -/** @defgroup RCC_LL_EF_MCO MCO - * @{ - */ - -/** - * @brief Configure MCOx - * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n - * CFGR MCOPRE LL_RCC_ConfigMCO - * @param MCOxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK - * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK - * @arg @ref LL_RCC_MCO1SOURCE_HSI - * @arg @ref LL_RCC_MCO1SOURCE_HSE - * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK - * @arg @ref LL_RCC_MCO1SOURCE_LSI - * @arg @ref LL_RCC_MCO1SOURCE_LSE - * @note Depending on devices and packages, some clocks may not be available. - * Refer to device datasheet for clocks availability. - * @param MCOxPrescaler This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1_DIV_1 - * @arg @ref LL_RCC_MCO1_DIV_2 - * @arg @ref LL_RCC_MCO1_DIV_4 - * @arg @ref LL_RCC_MCO1_DIV_8 - * @arg @ref LL_RCC_MCO1_DIV_16 - * @arg @ref LL_RCC_MCO1_DIV_32 - * @arg @ref LL_RCC_MCO1_DIV_64 - * @arg @ref LL_RCC_MCO1_DIV_128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) -{ - MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); -} - -/** - * @brief Get MCO clock source - * @rmtoll CFGR MCOSEL LL_RCC_GetMCOClockSource - * @param MCOx This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK - * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK - * @arg @ref LL_RCC_MCO1SOURCE_HSI - * @arg @ref LL_RCC_MCO1SOURCE_HSE - * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK - * @arg @ref LL_RCC_MCO1SOURCE_LSI - * @arg @ref LL_RCC_MCO1SOURCE_LSE - * @note Depending on devices and packages, some clocks may not be available. - * Refer to device datasheet for clocks availability. - */ -__STATIC_INLINE uint32_t LL_RCC_GetMCOClockSource(uint32_t MCOx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, MCOx)); -} - -/** - * @brief Get MCO division factor - * @rmtoll CFGR MCOPRE LL_RCC_GetMCODiv - * @param MCOx This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_MCO1_DIV_1 - * @arg @ref LL_RCC_MCO1_DIV_2 - * @arg @ref LL_RCC_MCO1_DIV_4 - * @arg @ref LL_RCC_MCO1_DIV_8 - * @arg @ref LL_RCC_MCO1_DIV_16 - * @arg @ref LL_RCC_MCO1_DIV_32 - * @arg @ref LL_RCC_MCO1_DIV_64 - * @arg @ref LL_RCC_MCO1_DIV_128 - */ -__STATIC_INLINE uint32_t LL_RCC_GetMCODiv(uint32_t MCOx) -{ - return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_MCOPRE)); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source - * @{ - */ - -#if defined(RCC_CCIPR_PVDSEL) -/** - * @brief Configure PVD clock source - * @rmtoll CCIPR PVDSEL LL_RCC_SetCOMPClockSource - * @param PVDxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_PVD_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_PVD_CLKSOURCE_LSC - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetPVDClockSource(uint32_t PVDSource) -{ - MODIFY_REG(RCC->CCIPR, RCC_CCIPR_PVDSEL, PVDSource); -} - -/** - * @brief Get PVD clock source - * @rmtoll CCIPR PVDSEL LL_RCC_GetCOMPClockSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PVD_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_PVD_CLKSOURCE_LSC - */ -__STATIC_INLINE uint32_t LL_RCC_GetPVDClockSource(void) -{ - return (uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_PVDSEL)); -} -#endif - -#if defined(COMP1) -/** - * @brief Configure COMPx clock source - * @rmtoll CCIPR COMPxSEL LL_RCC_SetCOMPClockSource - * @param COMPxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_COMP1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_COMP1_CLKSOURCE_LSC - * @arg @ref LL_RCC_COMP2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_COMP2_CLKSOURCE_LSC - * @note Depending on devices and packages,some COMP may not be available. - * Refer to device datasheet for COMP availability. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetCOMPClockSource(uint32_t COMPxSource) -{ - MODIFY_REG(RCC->CCIPR, (COMPxSource & 0x0000FF00U), ((COMPxSource & 0xFFU) << 8U)); -} -#endif /* COMP1 */ - -#if defined(COMP1) -/** - * @brief Get COMPx clock source - * @rmtoll CCIPR COMPxSEL LL_RCC_GetCOMPClockSource - * @param COMPx This parameter can be one of the following values: - * @arg @ref LL_RCC_COMP1_CLKSOURCE - * @arg @ref LL_RCC_COMP2_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_COMP1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_COMP1_CLKSOURCE_LSC - * @arg @ref LL_RCC_COMP2_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_COMP2_CLKSOURCE_LSC - * @note Depending on devices and packages,some COMP may not be available. - * Refer to device datasheet for COMP availability. - */ -__STATIC_INLINE uint32_t LL_RCC_GetCOMPClockSource(uint32_t COMPx) -{ - return (uint32_t)((READ_BIT(RCC->CCIPR, COMPx) >> 8U) | COMPx); -} -#endif /* COMP1 */ - -#if defined(RCC_CCIPR_LPTIMSEL) -/** - * @brief Configure LPTIMx clock source - * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource - * @param LPTIMxSource This parameter can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_NONE - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE - * @note Depending on devices and packages, some clocks may not be available. - * Refer to device datasheet for clocks availability. - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) -{ - MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U)); -} - -/** - * @brief Get LPTIMx clock source - * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource - * @param LPTIMx This parameter can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_NONE - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE - * @note Depending on devices and packages, some clocks may not be available. - * Refer to device datasheet for clocks availability. - */ -__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) -{ - return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx); -} -#endif /* RCC_CCIPR_LPTIMSEL */ - -/** - * @} - */ -#if defined(RTC) -#if defined(RCC_BDCR_RTCSEL) -/** @defgroup RCC_LL_EF_RTC RTC - * @{ - */ - -/** - * @brief Set RTC Clock Source - * @note Once the RTC clock source has been selected, it cannot be changed anymore unless - * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is - * set). The BDRST bit can be used to reset them. - * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource - * @param Source This parameter can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 - * @retval None - */ -__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) -{ - MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); -} - -/** - * @brief Get RTC Clock Source - * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE - * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI - * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 - */ -__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) -{ - return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); -} -#endif -/** - * @brief Enable RTC - * @rmtoll BDCR RTCEN LL_RCC_EnableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableRTC(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Disable RTC - * @rmtoll BDCR RTCEN LL_RCC_DisableRTC - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableRTC(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); -} - -/** - * @brief Check if RTC has been enabled or not - * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) -{ - return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL); -} - -/** - * @brief Force the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) -{ - SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @brief Release the Backup domain reset - * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset - * @retval None - */ -__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) -{ - CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); -} - -/** - * @} - */ -#endif - -#if defined(RCC_PLL_SUPPORT) -/** @defgroup RCC_LL_EF_PLL PLL - * @{ - */ - -/** - * @brief Enable PLL - * @rmtoll CR PLLON LL_RCC_PLL_Enable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Enable(void) -{ - SET_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Disable PLL - * @note Cannot be disabled if the PLL clock is used as the system clock - * @rmtoll CR PLLON LL_RCC_PLL_Disable - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_Disable(void) -{ - CLEAR_BIT(RCC->CR, RCC_CR_PLLON); -} - -/** - * @brief Check if PLL Ready - * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) -{ - return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); -} - - -/** - * @brief Configure PLL clock source - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource - * @param PLLSource This parameter can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - * @retval None - */ -__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) -{ - MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); -} - -/** - * @brief Get the oscillator used as PLL clock source. - * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource - * @retval Returned value can be one of the following values: - * @arg @ref LL_RCC_PLLSOURCE_NONE - * @arg @ref LL_RCC_PLLSOURCE_HSI - * @arg @ref LL_RCC_PLLSOURCE_HSE - */ -__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) -{ - return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); -} -/** - * @} - */ -#endif - - -/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Clear LSI ready interrupt flag - * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); -} -#if defined(RCC_LSE_SUPPORT) -/** - * @brief Clear LSE ready interrupt flag - * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); -} -#endif -/** - * @brief Clear HSI ready interrupt flag - * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); -} - -/** - * @brief Clear HSE ready interrupt flag - * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); -} -#if defined(RCC_PLL_SUPPORT) -/** - * @brief Clear PLL ready interrupt flag - * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); -} -#endif -/** - * @brief Clear Clock security system interrupt flag - * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_CSSC); -} -#if defined(RCC_LSE_SUPPORT) -/** - * @brief Clear LSE Clock security system interrupt flag - * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) -{ - SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); -} -#endif - -/** - * @brief Check if LSI ready interrupt occurred or not - * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL); -} -#if defined(RCC_LSE_SUPPORT) -/** - * @brief Check if LSE ready interrupt occurred or not - * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL); -} -#endif -/** - * @brief Check if HSI ready interrupt occurred or not - * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL); -} - -/** - * @brief Check if HSE ready interrupt occurred or not - * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL); -} -#if defined(RCC_PLL_SUPPORT) -/** - * @brief Check if PLL ready interrupt occurred or not - * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL); -} -#endif -/** - * @brief Check if Clock security system interrupt occurred or not - * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL); -} -#if defined(RCC_LSE_SUPPORT) -/** - * @brief Check if LSE Clock security system interrupt occurred or not - * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) -{ - return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL); -} -#endif - -/** - * @brief Check if RCC flag Independent Watchdog reset is set or not. - * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL); -} - -/** - * @brief Check if RCC flag Option byte reset is set or not. - * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL); -} - -/** - * @brief Check if RCC flag Pin reset is set or not. - * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL); -} - -/** - * @brief Check if RCC flag Software reset is set or not. - * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL); -} - -#if defined(WWDG) -/** - * @brief Check if RCC flag Window Watchdog reset is set or not. - * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL); -} -#endif - -/** - * @brief Check if RCC flag BOR or POR/PDR reset is set or not. - * @rmtoll CSR PWRRSTF LL_RCC_IsActiveFlag_PWRRST - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_PWRRSTF) == (RCC_CSR_PWRRSTF)) ? 1UL : 0UL); -} - -/** - * @brief Set RMVF bit to clear the reset flags. - * @rmtoll CSR RMVF LL_RCC_ClearResetFlags - * @retval None - */ -__STATIC_INLINE void LL_RCC_ClearResetFlags(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_RMVF); -} - -/** - * @brief Enable NRST filter - * @rmtoll CSR NRST_FLTDIS LL_RCC_EnableNRSTFilter - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableNRSTFilter(void) -{ - CLEAR_BIT(RCC->CSR, RCC_CSR_NRST_FLTDIS); -} - -/** - * @brief Disable NRST filter - * @rmtoll CSR NRST_FLTDIS LL_RCC_DisableNRSTFilter - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableNRSTFilter(void) -{ - SET_BIT(RCC->CSR, RCC_CSR_NRST_FLTDIS); -} - -/** - * @brief Check if NRST filter is enable - * @rmtoll CSR NRST_FLTDIS LL_RCC_IsEnableNRSTFilter - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnableNRSTFilter(void) -{ - return ((READ_BIT(RCC->CSR, RCC_CSR_NRST_FLTDIS) == (RCC_CSR_NRST_FLTDIS)) ? 0UL : 1UL); -} - -/** - * @} - */ - -/** @defgroup RCC_LL_EF_IT_Management IT Management - * @{ - */ - -/** - * @brief Enable LSI ready interrupt - * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); -} -#if defined(RCC_LSE_SUPPORT) -/** - * @brief Enable LSE ready interrupt - * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); -} -#endif -/** - * @brief Enable HSI ready interrupt - * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); -} - -/** - * @brief Enable HSE ready interrupt - * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); -} -#if defined(RCC_PLL_SUPPORT) -/** - * @brief Enable PLL ready interrupt - * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) -{ - SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); -} -#endif -/** - * @brief Disable LSI ready interrupt - * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); -} -#if defined(RCC_LSE_SUPPORT) -/** - * @brief Disable LSE ready interrupt - * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); -} -#endif -/** - * @brief Disable HSI ready interrupt - * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); -} - -/** - * @brief Disable HSE ready interrupt - * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); -} -#if defined(RCC_PLL_SUPPORT) -/** - * @brief Disable PLL ready interrupt - * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY - * @retval None - */ -__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) -{ - CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); -} -#endif -/** - * @brief Checks if LSI ready interrupt source is enabled or disabled. - * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL); -} -#if defined(RCC_LSE_SUPPORT) -/** - * @brief Checks if LSE ready interrupt source is enabled or disabled. - * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL); -} -#endif -/** - * @brief Checks if HSI ready interrupt source is enabled or disabled. - * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL); -} - -/** - * @brief Checks if HSE ready interrupt source is enabled or disabled. - * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL); -} -#if defined(RCC_PLL_SUPPORT) -/** - * @brief Checks if PLL ready interrupt source is enabled or disabled. - * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) -{ - return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL); -} -#endif -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RCC_LL_EF_Init De-initialization function - * @{ - */ -ErrorStatus LL_RCC_DeInit(void); -/** - * @} - */ - -/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions - * @{ - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); -uint32_t LL_RCC_GetMCOClockFreq(uint32_t MCOx); -uint32_t LL_RCC_GetLSCClockFreq(void); -#if defined(PVD) -uint32_t LL_RCC_GetPVDClockFreq(void); -#endif -#if defined(COMP1) -uint32_t LL_RCC_GetCOMPClockFreq(uint32_t COMPx); -#endif -#if defined(LPTIM1) -uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMx); -#endif -#if defined(TRC) -uint32_t LL_RCC_GetRTCClockFreq(void); -#endif -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PY32F0XX_LL_RCC_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_rcc.h + * @author MCU Application Team + * @brief Header file of RCC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32F0XX_LL_RCC_H +#define __PY32F0XX_LL_RCC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0XX_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @defgroup RCC_LL RCC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup RCC_LL_Private_Variables RCC Private Variables + * @{ + */ + + +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Private_Macros RCC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_Exported_Types RCC Exported Types + * @{ + */ + +/** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure + * @{ + */ + +/** + * @brief RCC Clocks Frequency Structure + */ +typedef struct +{ + uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */ + uint32_t HCLK_Frequency; /*!< HCLK clock frequency */ + uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */ +} LL_RCC_ClocksTypeDef; + +/** + * @} + */ + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Constants RCC Exported Constants + * @{ + */ + +/** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation + * @brief Defines used to adapt values of different oscillators + * @note These values could be modified in the user environment according to + * HW set-up. + * @{ + */ +#if !defined (HSE_VALUE) +#define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) +#define HSI_VALUE 8000000U /*!< Value of the HSI oscillator in Hz */ +#endif /* HSI_VALUE */ + +#if defined(RCC_LSE_SUPPORT) +#if !defined (LSE_VALUE) +#define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */ +#endif /* LSE_VALUE */ +#endif + +#if !defined (LSI_VALUE) +#define LSI_VALUE 32768U /*!< Value of the LSI oscillator in Hz */ +#endif /* LSI_VALUE */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines + * @brief Flags defines which can be used with LL_RCC_WriteReg function + * @{ + */ +#define LL_RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC /*!< LSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC /*!< HSI Ready Interrupt Clear */ +#define LL_RCC_CICR_HSERDYC RCC_CICR_HSERDYC /*!< HSE Ready Interrupt Clear */ +#if defined(RCC_PLL_SUPPORT) +#define LL_RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC /*!< PLL Ready Interrupt Clear */ +#endif +#if defined(RCC_LSE_SUPPORT) +#define LL_RCC_CICR_LSERDYC RCC_CICR_LSERDYC /*!< LSE Ready Interrupt Clear */ +#define LL_RCC_CICR_LSECSSC RCC_CICR_LSECSSC /*!< LSE Clock Security System Interrupt Clear */ +#endif +#define LL_RCC_CICR_CSSC RCC_CICR_CSSC /*!< Clock Security System Interrupt Clear */ + +/** + * @} + */ + +/** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_RCC_ReadReg function + * @{ + */ +#define LL_RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF /*!< LSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF /*!< HSI Ready Interrupt flag */ +#define LL_RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF /*!< HSE Ready Interrupt flag */ +#if defined(RCC_PLL_SUPPORT) +#define LL_RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF /*!< PLL Ready Interrupt flag */ +#endif +#if defined(RCC_LSE_SUPPORT) +#define LL_RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF /*!< LSE Ready Interrupt flag */ +#define LL_RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF /*!< LSE Clock Security System Interrupt flag */ +#endif +#define LL_RCC_CIFR_CSSF RCC_CIFR_CSSF /*!< Clock Security System Interrupt flag */ + +#define LL_RCC_CSR_OBLRSTF RCC_CSR_OBLRSTF /*!< OBL reset flag */ +#define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */ +#define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */ +#define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */ +#if defined(WWDG) +#define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */ +#endif +#define LL_RCC_CSR_PWRRSTF RCC_CSR_PWRRSTF /*!< BOR or POR/PDR reset flag */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions + * @{ + */ +#define LL_RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE /*!< LSI Ready Interrupt Enable */ +#if defined(RCC_LSE_SUPPORT) +#define LL_RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE /*!< LSE Ready Interrupt Enable */ +#endif +#define LL_RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE /*!< HSI Ready Interrupt Enable */ +#define LL_RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE /*!< HSE Ready Interrupt Enable */ +#if defined(RCC_PLL_SUPPORT) +#define LL_RCC_CIER_PLLRDYIE RCC_CIER_PLLRDYIE /*!< PLL Ready Interrupt Enable */ +#endif +/** + * @} + */ + +#if defined(RCC_LSE_SUPPORT) +/** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability + * @{ + */ +#define LL_RCC_LSEDRIVE_CLOSE 0x00000000 /*!< Xtal mode driving capability closed */ +#define LL_RCC_LSEDRIVE_LOW RCC_ECSCR_LSE_DRIVER_0 /*!< Xtal mode lower driving capability */ +#define LL_RCC_LSEDRIVE_MEDIUM RCC_ECSCR_LSE_DRIVER_1 /*!< Xtal mode medium driving capability */ +#define LL_RCC_LSEDRIVE_HIGH RCC_ECSCR_LSE_DRIVER /*!< Xtal mode higher driving capability */ +/** + * @} + */ +#endif + + +#if defined(RCC_BDCR_LSCOSEL) +/** @defgroup RCC_LL_EC_LSCO_CLKSOURCE LSCO Selection + * @{ + */ +#define LL_RCC_LSCO_CLKSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock */ +#define LL_RCC_LSCO_CLKSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock */ +#endif +/** + * @} + */ + + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_HSISYS 0x00000000U /*!< HSISYS selection as system clock */ +#define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_0 /*!< HSE selection as system clock */ +#if defined(RCC_PLL_SUPPORT) +#define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_1 /*!< PLL selection as system clock */ +#endif +#define LL_RCC_SYS_CLKSOURCE_LSI (RCC_CFGR_SW_1 | RCC_CFGR_SW_0) /*!< LSI selection used as system clock */ +#if defined(RCC_LSE_SUPPORT) +#define LL_RCC_SYS_CLKSOURCE_LSE RCC_CFGR_SW_2 /*!< LSE selection used as system clock */ +#endif +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status + * @{ + */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS 0x00000000U /*!< HSISYS used as system clock */ +#define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_0 /*!< HSE used as system clock */ +#if defined(RCC_PLL_SUPPORT) +#define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_1 /*!< PLL used as system clock */ +#endif +#define LL_RCC_SYS_CLKSOURCE_STATUS_LSI (RCC_CFGR_SWS_1 | RCC_CFGR_SWS_0) /*!< LSI used as system clock */ +#if defined(RCC_LSE_SUPPORT) +#define LL_RCC_SYS_CLKSOURCE_STATUS_LSE RCC_CFGR_SWS_2 /*!< LSE used as system clock */ +#endif +/** + * @} + */ + +/** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler + * @{ + */ +#define LL_RCC_SYSCLK_DIV_1 0x00000000U /*!< SYSCLK not divided */ +#define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_3 /*!< SYSCLK divided by 2 */ +#define LL_RCC_SYSCLK_DIV_4 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 4 */ +#define LL_RCC_SYSCLK_DIV_8 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 8 */ +#define LL_RCC_SYSCLK_DIV_16 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 16 */ +#define LL_RCC_SYSCLK_DIV_64 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2) /*!< SYSCLK divided by 64 */ +#define LL_RCC_SYSCLK_DIV_128 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 128 */ +#define LL_RCC_SYSCLK_DIV_256 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1) /*!< SYSCLK divided by 256 */ +#define LL_RCC_SYSCLK_DIV_512 (RCC_CFGR_HPRE_3 | RCC_CFGR_HPRE_2 | RCC_CFGR_HPRE_1 | RCC_CFGR_HPRE_0) /*!< SYSCLK divided by 512 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_APB1_DIV APB1 low-speed prescaler (APB1) + * @{ + */ +#define LL_RCC_APB1_DIV_1 0x00000000U /*!< HCLK not divided */ +#define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE_2 /*!< HCLK divided by 2 */ +#define LL_RCC_APB1_DIV_4 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 4 */ +#define LL_RCC_APB1_DIV_8 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1) /*!< HCLK divided by 8 */ +#define LL_RCC_APB1_DIV_16 (RCC_CFGR_PPRE_2 | RCC_CFGR_PPRE_1 | RCC_CFGR_PPRE_0) /*!< HCLK divided by 16 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_HSI_DIV HSI division factor + * @{ + */ +#define LL_RCC_HSI_DIV_1 0x00000000U /*!< HSI not divided */ +#define LL_RCC_HSI_DIV_2 RCC_CR_HSIDIV_0 /*!< HSI divided by 2 */ +#define LL_RCC_HSI_DIV_4 RCC_CR_HSIDIV_1 /*!< HSI divided by 4 */ +#define LL_RCC_HSI_DIV_8 (RCC_CR_HSIDIV_1 | RCC_CR_HSIDIV_0) /*!< HSI divided by 8 */ +#define LL_RCC_HSI_DIV_16 RCC_CR_HSIDIV_2 /*!< HSI divided by 16 */ +#define LL_RCC_HSI_DIV_32 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_0) /*!< HSI divided by 32 */ +#define LL_RCC_HSI_DIV_64 (RCC_CR_HSIDIV_2 | RCC_CR_HSIDIV_1) /*!< HSI divided by 64 */ +#define LL_RCC_HSI_DIV_128 RCC_CR_HSIDIV /*!< HSI divided by 128 */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1SOURCE MCO1 SOURCE selection + * @{ + */ +#define LL_RCC_MCO1SOURCE_NOCLOCK 0x00000000U /*!< MCO output disabled, no clock on MCO */ +#define LL_RCC_MCO1SOURCE_SYSCLK RCC_CFGR_MCOSEL_0 /*!< SYSCLK selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSI (RCC_CFGR_MCOSEL_0| RCC_CFGR_MCOSEL_1) /*!< HSI selection as MCO1 source */ +#define LL_RCC_MCO1SOURCE_HSE RCC_CFGR_MCOSEL_2 /*!< HSE selection as MCO1 source */ +#if defined(RCC_PLL_SUPPORT) +#define LL_RCC_MCO1SOURCE_PLLCLK (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_2) /*!< Main PLL selection as MCO1 source */ +#endif +#define LL_RCC_MCO1SOURCE_LSI (RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSI selection as MCO1 source */ +#if defined(RCC_LSE_SUPPORT) +#define LL_RCC_MCO1SOURCE_LSE (RCC_CFGR_MCOSEL_0|RCC_CFGR_MCOSEL_1|RCC_CFGR_MCOSEL_2) /*!< LSE selection as MCO1 source */ +#endif +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO Peripheral MCO get clock source + * @{ + */ +#define LL_RCC_MCO1_CLKSOURCE RCC_CFGR_MCOSEL /*!< MCO1 Clock source selection */ +/** + * @} + */ + +/** @defgroup RCC_LL_EC_MCO1_DIV MCO1 prescaler + * @{ + */ +#define LL_RCC_MCO1_DIV_1 0x00000000U /*!< MCO1 not divided */ +#define LL_RCC_MCO1_DIV_2 RCC_CFGR_MCOPRE_0 /*!< MCO1 divided by 2 */ +#define LL_RCC_MCO1_DIV_4 RCC_CFGR_MCOPRE_1 /*!< MCO1 divided by 4 */ +#define LL_RCC_MCO1_DIV_8 (RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 8 */ +#define LL_RCC_MCO1_DIV_16 RCC_CFGR_MCOPRE_2 /*!< MCO1 divided by 16 */ +#define LL_RCC_MCO1_DIV_32 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 32 */ +#define LL_RCC_MCO1_DIV_64 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1) /*!< MCO1 divided by 64 */ +#define LL_RCC_MCO1_DIV_128 (RCC_CFGR_MCOPRE_2 | RCC_CFGR_MCOPRE_1 | RCC_CFGR_MCOPRE_0) /*!< MCO1 divided by 128 */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency + * @{ + */ +#define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */ +#define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +#if defined(RCC_CCIPR_PVDSEL) +/** @defgroup RCC_LL_EC_PVD_CLKSOURCE Peripheral PVD clock source selection + * @{ + */ +#define LL_RCC_PVD_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 selected as PVD clock */ +#define LL_RCC_PVD_CLKSOURCE_LSC RCC_CCIPR_PVDSEL /*!< LSC selected as PVD clock */ +/** + * @} + */ +#endif + +#if defined(COMP1) +/** @defgroup RCC_LL_EC_COMPx_CLKSOURCE Peripheral COMP clock source selection + * @{ + */ +#define LL_RCC_COMP1_CLKSOURCE_PCLK1 (RCC_CCIPR_COMP1SEL | (0x00000000U >> 8U)) /*!< PCLK1 selected as COMP1 clock */ +#define LL_RCC_COMP1_CLKSOURCE_LSC (RCC_CCIPR_COMP1SEL | (RCC_CCIPR_COMP1SEL >> 8U)) /*!< LSC selected as COMP1 clock */ +#if defined(COMP2) +#define LL_RCC_COMP2_CLKSOURCE_PCLK1 (RCC_CCIPR_COMP2SEL | (0x00000000U >> 8U)) /*!< PCLK1 selected as COMP2 clock */ +#define LL_RCC_COMP2_CLKSOURCE_LSC (RCC_CCIPR_COMP2SEL | (RCC_CCIPR_COMP2SEL >> 8U)) /*!< LSC selected as COMP2 clock */ +#endif +/** + * @} + */ +#endif /* COMP1 && COMP2 */ + +#if defined(RCC_CCIPR_LPTIMSEL) +/** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE_NONE (RCC_CCIPR_LPTIMSEL | (RCC_CCIPR_LPTIMSEL_1 >> 16U)) /*!< No clock used as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 (RCC_CCIPR_LPTIMSEL | (0x00000000U >> 16U)) /*!< PCLK1 selected as LPTIM1 clock */ +#define LL_RCC_LPTIM1_CLKSOURCE_LSI (RCC_CCIPR_LPTIMSEL | (RCC_CCIPR_LPTIMSEL_0 >> 16U)) /*!< LSI selected as LPTIM1 clock */ +#if defined(RCC_LSE_SUPPORT) +#define LL_RCC_LPTIM1_CLKSOURCE_LSE (RCC_CCIPR_LPTIMSEL | (RCC_CCIPR_LPTIMSEL >> 16U)) /*!< LSE selected as LPTIM1 clock */ +#endif +/** + * @} + */ +#endif /* RCC_CCIPR_LPTIMSEL */ + +#if defined(RCC_BDCR_RTCSEL) +/** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection + * @{ + */ +#define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */ +#if defined(RCC_LSE_SUPPORT) +#define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */ +#endif +#define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */ +#define LL_RCC_RTC_CLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by 128 used as RTC clock */ +/** + * @} + */ +#endif + +#if defined(RCC_PLL_SUPPORT) +/** @defgroup RCC_LL_EC_PLLSOURCE PLL entry clock source + * @{ + */ +#define LL_RCC_PLLSOURCE_NONE 0x00000000U /*!< No clock */ +#define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI clock selected as PLL entry clock source */ +#define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */ +/** + * @} + */ +#endif + +#if defined(COMP1) +/** @defgroup RCC_LL_EC_COMP Peripheral COMP get clock source + * @{ + */ +#define LL_RCC_COMP1_CLKSOURCE RCC_CCIPR_COMP1SEL /*!< COMP1 Clock source selection */ +#if defined(COMP2) +#define LL_RCC_COMP2_CLKSOURCE RCC_CCIPR_COMP2SEL /*!< COMP2 Clock source selection */ +#endif /* COMP2 */ +/** + * @} + */ +#endif /* COMP1 */ + +#if defined(RCC_CCIPR_LPTIMSEL) +/** @defgroup RCC_LL_EC_LPTIM Peripheral LPTIM get clock source + * @{ + */ +#define LL_RCC_LPTIM1_CLKSOURCE RCC_CCIPR_LPTIMSEL /*!< LPTIM1 Clock source selection */ +/** + * @} + */ +#endif /* RCC_CCIPR_LPTIMSEL */ + +/** @defgroup RCC_HSE_EC_Freq HSE Config + * @{ + */ +#define LL_RCC_HSE_STOP 0x00000000U +#define LL_RCC_HSE_4_8MHz RCC_ECSCR_HSE_FREQ_0 +#define LL_RCC_HSE_8_16MHz RCC_ECSCR_HSE_FREQ_1 +#if defined(PY32F002PRE) +#define LL_RCC_HSE_16_24MHz (RCC_ECSCR_HSE_FREQ_0 | RCC_ECSCR_HSE_FREQ_1) +#else +#define LL_RCC_HSE_16_32MHz (RCC_ECSCR_HSE_FREQ_0 | RCC_ECSCR_HSE_FREQ_1) +#endif +/** + * @} + */ + +/** @defgroup RCC_HSI_EC_Calibration HSI Calibration +* @{ +*/ +#if defined(PY32F002PRE) +#define LL_RCC_HSICALIBRATION_8MHz ((0x1<<13) | ((*(uint32_t *)(0x1FFF0F04)) & 0x1FFF)) /*!< 8MHz HSI calibration trimming value */ +#define LL_RCC_HSICALIBRATION_24MHz ((0x4<<13) | ((*(uint32_t *)(0x1FFF0F10)) & 0x1FFF)) /*!< 24MHz HSI calibration trimming value */ +#else +#define LL_RCC_HSICALIBRATION_4MHz ((0x0<<13) | ((*(uint32_t *)(0x1FFF0F00)) & 0x1FFF)) /*!< 4MHz HSI calibration trimming value */ +#define LL_RCC_HSICALIBRATION_8MHz ((0x1<<13) | ((*(uint32_t *)(0x1FFF0F04)) & 0x1FFF)) /*!< 8MHz HSI calibration trimming value */ +#define LL_RCC_HSICALIBRATION_16MHz ((0x2<<13) | ((*(uint32_t *)(0x1FFF0F08)) & 0x1FFF)) /*!< 16MHz HSI calibration trimming value */ +#define LL_RCC_HSICALIBRATION_22p12MHz ((0x3<<13) | ((*(uint32_t *)(0x1FFF0F0C)) & 0x1FFF)) /*!< 22.12MHz HSI calibration trimming value */ +#define LL_RCC_HSICALIBRATION_24MHz ((0x4<<13) | ((*(uint32_t *)(0x1FFF0F10)) & 0x1FFF)) /*!< 24MHz HSI calibration trimming value */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Macros RCC Exported Macros + * @{ + */ + +/** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RCC register + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG((RCC->__REG__), (__VALUE__)) + +/** + * @brief Read a value in RCC register + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__) +/** + * @} + */ + +/** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies + * @{ + */ +#if defined(RCC_PLL_SUPPORT) +/** + * @brief Helper macro to calculate the PLLCLK frequency on system domain + * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI) + + * @retval PLL clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__) ((__INPUTFREQ__) * 2) +#endif + +/** + * @brief Helper macro to calculate the HCLK frequency + * @param __SYSCLKFREQ__ SYSCLK frequency + * @param __AHBPRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval HCLK clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__,__AHBPRESCALER__) \ + ((__SYSCLKFREQ__) >> (AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos] & 0x1FU)) + +/** + * @brief Helper macro to calculate the PCLK1 frequency (APB1) + * @param __HCLKFREQ__ HCLK frequency + * @param __APB1PRESCALER__ This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval PCLK1 clock frequency (in Hz) + */ +#define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) \ + ((__HCLKFREQ__) >> (APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE_Pos] & 0x1FU)) + +/** + * @brief Helper macro to calculate the HSISYS frequency + * @param __HSIDIV__ This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + * @retval HSISYS clock frequency (in Hz) + */ +#define __LL_RCC_CALC_HSI_FREQ(__HSIDIV__) \ + (HSIFreqTable[(RCC->ICSCR & RCC_ICSCR_HSI_FS) >> RCC_ICSCR_HSI_FS_Pos] / (1U << ((__HSIDIV__)>> RCC_CR_HSIDIV_Pos))) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RCC_LL_Exported_Functions RCC Exported Functions + * @{ + */ + +/** @defgroup RCC_LL_EF_HSE HSE + * @{ + */ + +/** + * @brief Enable the Clock Security System. + * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableCSS(void) +{ + SET_BIT(RCC->CR, RCC_CR_CSSON); +} + +/** + * @brief Enable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_EnableBypass(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Disable HSE external oscillator (HSE Bypass) + * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); +} + +/** + * @brief Enable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Disable HSE crystal oscillator (HSE ON) + * @rmtoll CR HSEON LL_RCC_HSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSEON); +} + +/** + * @brief Check if HSE oscillator Ready + * @rmtoll CR HSERDY LL_RCC_HSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL); +} + +/** + * @brief Set HSE Crystal working frequency + * @param HSEFreq This parameter can be one of the following values: + * @arg @ref LL_RCC_HSE_STOP + * @arg @ref LL_RCC_HSE_4_8MHz + * @arg @ref LL_RCC_HSE_8_16MHz + * @arg @ref LL_RCC_HSE_16_32MHz or LL_RCC_HSE_16_24MHz + * @note The maximum working frequency varies depending on the devices. + * Refer to the devices data sheet for the maximum working frequency. + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSE_SetFreqRegion(uint32_t HSEFreq) +{ + MODIFY_REG(RCC->ECSCR, RCC_ECSCR_HSE_FREQ, HSEFreq); +} + + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_HSI HSI + * @{ + */ + +/** + * @brief Enable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Disable HSI oscillator + * @rmtoll CR HSION LL_RCC_HSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_HSION); +} + +/** + * @brief Check if HSI clock is ready + * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL); +} + +/** + * @brief Set HSI Calibration trimming + * @param Value Between Min_Data = 0 and Max_Data = 0x1FFF + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, Value << RCC_ICSCR_HSI_TRIM_Pos); +} + +/** + * @brief Get HSI Calibration trimming + * @rmtoll ICSCR HSITRIM LL_RCC_HSI_GetCalibTrimming + * @retval Between Min_Data = 0 and Max_Data = 0x1FFF + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void) +{ + return (uint32_t)(READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_TRIM) >> RCC_ICSCR_HSI_TRIM_Pos); +} + +/** + * @brief Set HSI Calibration Frequency + * @param Value This parameter can be one of the following values: + * @arg @ref LL_RCC_HSICALIBRATION_4MHz + * @arg @ref LL_RCC_HSICALIBRATION_8MHz + * @arg @ref LL_RCC_HSICALIBRATION_16MHz + * @arg @ref LL_RCC_HSICALIBRATION_22p12MHz + * @arg @ref LL_RCC_HSICALIBRATION_24MHz + * @note Depending on devices and packages, some calibration values may not be available. + * Refer to device datasheet for calibration values availability. + * @retval None + */ +__STATIC_INLINE void LL_RCC_HSI_SetCalibFreq(uint32_t Value) +{ + MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_HSI_FS | RCC_ICSCR_HSI_TRIM), Value); +} + +/** + * @brief Get HSI Frequency + * @retval HSI clock frequency (in Hz) + */ +__STATIC_INLINE uint32_t LL_RCC_HSI_GetFreq(void) +{ + return (uint32_t)HSIFreqTable[(RCC->ICSCR & RCC_ICSCR_HSI_FS) >> RCC_ICSCR_HSI_FS_Pos]; +} + +/** + * @} + */ + +#if defined(RCC_LSE_SUPPORT) +/** @defgroup RCC_LL_EF_LSE LSE + * @{ + */ + +/** + * @brief Enable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Disable Low Speed External (LSE) crystal. + * @rmtoll BDCR LSEON LL_RCC_LSE_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); +} + +/** + * @brief Enable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableBypass(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Disable external clock source (LSE bypass). + * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableBypass(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); +} + +/** + * @brief Set LSE oscillator drive capability + * @note The oscillator is in Xtal mode when it is not in bypass mode. + * @param LSEDrive This parameter can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_CLOSE + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUM + * @arg @ref LL_RCC_LSEDRIVE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive) +{ + MODIFY_REG(RCC->ECSCR, RCC_ECSCR_LSE_DRIVER, LSEDrive); +} + +/** + * @brief Get LSE oscillator drive capability + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSEDRIVE_CLOSE + * @arg @ref LL_RCC_LSEDRIVE_LOW + * @arg @ref LL_RCC_LSEDRIVE_MEDIUM + * @arg @ref LL_RCC_LSEDRIVE_HIGH + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void) +{ + return (uint32_t)(READ_BIT(RCC->ECSCR, RCC_ECSCR_LSE_DRIVER)); +} + + +/** + * @brief Enable Clock security system on LSE. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_EnableCSS(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + +/** + * @brief Disable Clock security system on LSE. + * @note Clock security system can be disabled only after a LSE + * failure detection. In that case it MUST be disabled by software. + * @rmtoll BDCR LSECSSON LL_RCC_LSE_DisableCSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSE_DisableCSS(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSECSSON); +} + + +/** + * @brief Check if LSE oscillator Ready + * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL); +} + +/** + * @brief Check if CSS on LSE failure Detection + * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsCSSDetected + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSE_IsCSSDetected(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif + +/** @defgroup RCC_LL_EF_LSI LSI + * @{ + */ + +/** + * @brief Enable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Enable(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Disable LSI Oscillator + * @rmtoll CSR LSION LL_RCC_LSI_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSI_Disable(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_LSION); +} + +/** + * @brief Check if LSI is Ready + * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL); +} + +/** + * @} + */ +#if defined(RCC_BDCR_LSCOEN) +/** @defgroup RCC_LL_EF_LSCO LSCO + * @{ + */ + +/** + * @brief Enable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Enable(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} + +/** + * @brief Disable Low speed clock + * @rmtoll BDCR LSCOEN LL_RCC_LSCO_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_Disable(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSCOEN); +} +#if defined(RCC_BDCR_LSCOSEL) +/** + * @brief Configure Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_SetSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_LSCO_SetSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_LSCOSEL, Source); +} + +/** + * @brief Get Low speed clock selection + * @rmtoll BDCR LSCOSEL LL_RCC_LSCO_GetSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSI + * @arg @ref LL_RCC_LSCO_CLKSOURCE_LSE + */ +__STATIC_INLINE uint32_t LL_RCC_LSCO_GetSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSCOSEL)); +} + +/** + * @} + */ +#endif +#endif +/** @defgroup RCC_LL_EF_System System + * @{ + */ + +/** + * @brief Configure the system clock source + * @rmtoll CFGR SW LL_RCC_SetSysClkSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSISYS + * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_LSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_LSE + * @note Depending on devices and packages, some clocks may not be available. + * Refer to device datasheet for clocks availability. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source); +} + +/** + * @brief Get the system clock source + * @rmtoll CFGR SWS LL_RCC_GetSysClkSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSI + * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_LSE + * @note Depending on devices and packages, some clocks may not be available. + * Refer to device datasheet for clocks availability. + */ +__STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)); +} + +/** + * @brief Set AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler); +} + +/** + * @brief Set APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_SetAPB1Prescaler + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE, Prescaler); +} + +/** + * @brief Set HSI division factor + * @rmtoll CR HSIDIV LL_RCC_SetHSIDiv + * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as + * system clock source. + * @param HSIDiv This parameter can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetHSIDiv(uint32_t HSIDiv) +{ + MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, HSIDiv); +} +/** + * @brief Get AHB prescaler + * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_SYSCLK_DIV_1 + * @arg @ref LL_RCC_SYSCLK_DIV_2 + * @arg @ref LL_RCC_SYSCLK_DIV_4 + * @arg @ref LL_RCC_SYSCLK_DIV_8 + * @arg @ref LL_RCC_SYSCLK_DIV_16 + * @arg @ref LL_RCC_SYSCLK_DIV_64 + * @arg @ref LL_RCC_SYSCLK_DIV_128 + * @arg @ref LL_RCC_SYSCLK_DIV_256 + * @arg @ref LL_RCC_SYSCLK_DIV_512 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE)); +} + +/** + * @brief Get APB1 prescaler + * @rmtoll CFGR PPRE LL_RCC_GetAPB1Prescaler + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_APB1_DIV_1 + * @arg @ref LL_RCC_APB1_DIV_2 + * @arg @ref LL_RCC_APB1_DIV_4 + * @arg @ref LL_RCC_APB1_DIV_8 + * @arg @ref LL_RCC_APB1_DIV_16 + */ +__STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE)); +} + +/** + * @brief Get HSI division factor + * @rmtoll CR HSIDIV LL_RCC_GetHSIDiv + * @note HSIDIV parameter is only applied to SYSCLK_Frequency when HSI is used as + * system clock source. + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_HSI_DIV_1 + * @arg @ref LL_RCC_HSI_DIV_2 + * @arg @ref LL_RCC_HSI_DIV_4 + * @arg @ref LL_RCC_HSI_DIV_8 + * @arg @ref LL_RCC_HSI_DIV_16 + * @arg @ref LL_RCC_HSI_DIV_32 + * @arg @ref LL_RCC_HSI_DIV_64 + * @arg @ref LL_RCC_HSI_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetHSIDiv(void) +{ + return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSIDIV)); +} +/** + * @} + */ + +/** @defgroup RCC_LL_EF_MCO MCO + * @{ + */ + +/** + * @brief Configure MCOx + * @rmtoll CFGR MCOSEL LL_RCC_ConfigMCO\n + * CFGR MCOPRE LL_RCC_ConfigMCO + * @param MCOxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @note Depending on devices and packages, some clocks may not be available. + * Refer to device datasheet for clocks availability. + * @param MCOxPrescaler This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_16 + * @arg @ref LL_RCC_MCO1_DIV_32 + * @arg @ref LL_RCC_MCO1_DIV_64 + * @arg @ref LL_RCC_MCO1_DIV_128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler) +{ + MODIFY_REG(RCC->CFGR, RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE, MCOxSource | MCOxPrescaler); +} + +/** + * @brief Get MCO clock source + * @rmtoll CFGR MCOSEL LL_RCC_GetMCOClockSource + * @param MCOx This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MCO1SOURCE_NOCLOCK + * @arg @ref LL_RCC_MCO1SOURCE_SYSCLK + * @arg @ref LL_RCC_MCO1SOURCE_HSI + * @arg @ref LL_RCC_MCO1SOURCE_HSE + * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK + * @arg @ref LL_RCC_MCO1SOURCE_LSI + * @arg @ref LL_RCC_MCO1SOURCE_LSE + * @note Depending on devices and packages, some clocks may not be available. + * Refer to device datasheet for clocks availability. + */ +__STATIC_INLINE uint32_t LL_RCC_GetMCOClockSource(uint32_t MCOx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, MCOx)); +} + +/** + * @brief Get MCO division factor + * @rmtoll CFGR MCOPRE LL_RCC_GetMCODiv + * @param MCOx This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_MCO1_DIV_1 + * @arg @ref LL_RCC_MCO1_DIV_2 + * @arg @ref LL_RCC_MCO1_DIV_4 + * @arg @ref LL_RCC_MCO1_DIV_8 + * @arg @ref LL_RCC_MCO1_DIV_16 + * @arg @ref LL_RCC_MCO1_DIV_32 + * @arg @ref LL_RCC_MCO1_DIV_64 + * @arg @ref LL_RCC_MCO1_DIV_128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetMCODiv(uint32_t MCOx) +{ + return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_MCOPRE)); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source + * @{ + */ + +#if defined(RCC_CCIPR_PVDSEL) +/** + * @brief Configure PVD clock source + * @rmtoll CCIPR PVDSEL LL_RCC_SetCOMPClockSource + * @param PVDxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PVD_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_PVD_CLKSOURCE_LSC + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetPVDClockSource(uint32_t PVDSource) +{ + MODIFY_REG(RCC->CCIPR, RCC_CCIPR_PVDSEL, PVDSource); +} + +/** + * @brief Get PVD clock source + * @rmtoll CCIPR PVDSEL LL_RCC_GetCOMPClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PVD_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_PVD_CLKSOURCE_LSC + */ +__STATIC_INLINE uint32_t LL_RCC_GetPVDClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_PVDSEL)); +} +#endif + +#if defined(COMP1) +/** + * @brief Configure COMPx clock source + * @rmtoll CCIPR COMPxSEL LL_RCC_SetCOMPClockSource + * @param COMPxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_COMP1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_COMP1_CLKSOURCE_LSC + * @arg @ref LL_RCC_COMP2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_COMP2_CLKSOURCE_LSC + * @note Depending on devices and packages,some COMP may not be available. + * Refer to device datasheet for COMP availability. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetCOMPClockSource(uint32_t COMPxSource) +{ + MODIFY_REG(RCC->CCIPR, (COMPxSource & 0x0000FF00U), ((COMPxSource & 0xFFU) << 8U)); +} +#endif /* COMP1 */ + +#if defined(COMP1) +/** + * @brief Get COMPx clock source + * @rmtoll CCIPR COMPxSEL LL_RCC_GetCOMPClockSource + * @param COMPx This parameter can be one of the following values: + * @arg @ref LL_RCC_COMP1_CLKSOURCE + * @arg @ref LL_RCC_COMP2_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_COMP1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_COMP1_CLKSOURCE_LSC + * @arg @ref LL_RCC_COMP2_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_COMP2_CLKSOURCE_LSC + * @note Depending on devices and packages,some COMP may not be available. + * Refer to device datasheet for COMP availability. + */ +__STATIC_INLINE uint32_t LL_RCC_GetCOMPClockSource(uint32_t COMPx) +{ + return (uint32_t)((READ_BIT(RCC->CCIPR, COMPx) >> 8U) | COMPx); +} +#endif /* COMP1 */ + +#if defined(RCC_CCIPR_LPTIMSEL) +/** + * @brief Configure LPTIMx clock source + * @rmtoll CCIPR LPTIMxSEL LL_RCC_SetLPTIMClockSource + * @param LPTIMxSource This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_NONE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @note Depending on devices and packages, some clocks may not be available. + * Refer to device datasheet for clocks availability. + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource) +{ + MODIFY_REG(RCC->CCIPR, (LPTIMxSource & 0xFFFF0000U), (LPTIMxSource << 16U)); +} + +/** + * @brief Get LPTIMx clock source + * @rmtoll CCIPR LPTIMxSEL LL_RCC_GetLPTIMClockSource + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1 + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_NONE + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE + * @note Depending on devices and packages, some clocks may not be available. + * Refer to device datasheet for clocks availability. + */ +__STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx) +{ + return (uint32_t)((READ_BIT(RCC->CCIPR, LPTIMx) >> 16U) | LPTIMx); +} +#endif /* RCC_CCIPR_LPTIMSEL */ + +/** + * @} + */ +#if defined(RTC) +#if defined(RCC_BDCR_RTCSEL) +/** @defgroup RCC_LL_EF_RTC RTC + * @{ + */ + +/** + * @brief Set RTC Clock Source + * @note Once the RTC clock source has been selected, it cannot be changed anymore unless + * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is + * set). The BDRST bit can be used to reset them. + * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource + * @param Source This parameter can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 + * @retval None + */ +__STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source) +{ + MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source); +} + +/** + * @brief Get RTC Clock Source + * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE + * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI + * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE_DIV128 + */ +__STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void) +{ + return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)); +} +#endif +/** + * @brief Enable RTC + * @rmtoll BDCR RTCEN LL_RCC_EnableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableRTC(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Disable RTC + * @rmtoll BDCR RTCEN LL_RCC_DisableRTC + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableRTC(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN); +} + +/** + * @brief Check if RTC has been enabled or not + * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void) +{ + return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL); +} + +/** + * @brief Force the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void) +{ + SET_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @brief Release the Backup domain reset + * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset + * @retval None + */ +__STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void) +{ + CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST); +} + +/** + * @} + */ +#endif + +#if defined(RCC_PLL_SUPPORT) +/** @defgroup RCC_LL_EF_PLL PLL + * @{ + */ + +/** + * @brief Enable PLL + * @rmtoll CR PLLON LL_RCC_PLL_Enable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Enable(void) +{ + SET_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Disable PLL + * @note Cannot be disabled if the PLL clock is used as the system clock + * @rmtoll CR PLLON LL_RCC_PLL_Disable + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_Disable(void) +{ + CLEAR_BIT(RCC->CR, RCC_CR_PLLON); +} + +/** + * @brief Check if PLL Ready + * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void) +{ + return ((READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY)) ? 1UL : 0UL); +} + + +/** + * @brief Configure PLL clock source + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource + * @param PLLSource This parameter can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + * @retval None + */ +__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource) +{ + MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource); +} + +/** + * @brief Get the oscillator used as PLL clock source. + * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource + * @retval Returned value can be one of the following values: + * @arg @ref LL_RCC_PLLSOURCE_NONE + * @arg @ref LL_RCC_PLLSOURCE_HSI + * @arg @ref LL_RCC_PLLSOURCE_HSE + */ +__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void) +{ + return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC)); +} +/** + * @} + */ +#endif + + +/** @defgroup RCC_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Clear LSI ready interrupt flag + * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC); +} +#if defined(RCC_LSE_SUPPORT) +/** + * @brief Clear LSE ready interrupt flag + * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSERDYC); +} +#endif +/** + * @brief Clear HSI ready interrupt flag + * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC); +} + +/** + * @brief Clear HSE ready interrupt flag + * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_HSERDYC); +} +#if defined(RCC_PLL_SUPPORT) +/** + * @brief Clear PLL ready interrupt flag + * @rmtoll CICR PLLRDYC LL_RCC_ClearFlag_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC); +} +#endif +/** + * @brief Clear Clock security system interrupt flag + * @rmtoll CICR CSSC LL_RCC_ClearFlag_HSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_CSSC); +} +#if defined(RCC_LSE_SUPPORT) +/** + * @brief Clear LSE Clock security system interrupt flag + * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void) +{ + SET_BIT(RCC->CICR, RCC_CICR_LSECSSC); +} +#endif + +/** + * @brief Check if LSI ready interrupt occurred or not + * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL); +} +#if defined(RCC_LSE_SUPPORT) +/** + * @brief Check if LSE ready interrupt occurred or not + * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL); +} +#endif +/** + * @brief Check if HSI ready interrupt occurred or not + * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL); +} + +/** + * @brief Check if HSE ready interrupt occurred or not + * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL); +} +#if defined(RCC_PLL_SUPPORT) +/** + * @brief Check if PLL ready interrupt occurred or not + * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL); +} +#endif +/** + * @brief Check if Clock security system interrupt occurred or not + * @rmtoll CIFR CSSF LL_RCC_IsActiveFlag_HSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSSF) == (RCC_CIFR_CSSF)) ? 1UL : 0UL); +} +#if defined(RCC_LSE_SUPPORT) +/** + * @brief Check if LSE Clock security system interrupt occurred or not + * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void) +{ + return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL); +} +#endif + +/** + * @brief Check if RCC flag Independent Watchdog reset is set or not. + * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Option byte reset is set or not. + * @rmtoll CSR OBLRSTF LL_RCC_IsActiveFlag_OBLRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_OBLRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_OBLRSTF) == (RCC_CSR_OBLRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Pin reset is set or not. + * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Check if RCC flag Software reset is set or not. + * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF)) ? 1UL : 0UL); +} + +#if defined(WWDG) +/** + * @brief Check if RCC flag Window Watchdog reset is set or not. + * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF)) ? 1UL : 0UL); +} +#endif + +/** + * @brief Check if RCC flag BOR or POR/PDR reset is set or not. + * @rmtoll CSR PWRRSTF LL_RCC_IsActiveFlag_PWRRST + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PWRRST(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_PWRRSTF) == (RCC_CSR_PWRRSTF)) ? 1UL : 0UL); +} + +/** + * @brief Set RMVF bit to clear the reset flags. + * @rmtoll CSR RMVF LL_RCC_ClearResetFlags + * @retval None + */ +__STATIC_INLINE void LL_RCC_ClearResetFlags(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_RMVF); +} + +/** + * @brief Enable NRST filter + * @rmtoll CSR NRST_FLTDIS LL_RCC_EnableNRSTFilter + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableNRSTFilter(void) +{ + CLEAR_BIT(RCC->CSR, RCC_CSR_NRST_FLTDIS); +} + +/** + * @brief Disable NRST filter + * @rmtoll CSR NRST_FLTDIS LL_RCC_DisableNRSTFilter + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableNRSTFilter(void) +{ + SET_BIT(RCC->CSR, RCC_CSR_NRST_FLTDIS); +} + +/** + * @brief Check if NRST filter is enable + * @rmtoll CSR NRST_FLTDIS LL_RCC_IsEnableNRSTFilter + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnableNRSTFilter(void) +{ + return ((READ_BIT(RCC->CSR, RCC_CSR_NRST_FLTDIS) == (RCC_CSR_NRST_FLTDIS)) ? 0UL : 1UL); +} + +/** + * @} + */ + +/** @defgroup RCC_LL_EF_IT_Management IT Management + * @{ + */ + +/** + * @brief Enable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} +#if defined(RCC_LSE_SUPPORT) +/** + * @brief Enable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} +#endif +/** + * @brief Enable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Enable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} +#if defined(RCC_PLL_SUPPORT) +/** + * @brief Enable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_EnableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void) +{ + SET_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} +#endif +/** + * @brief Disable LSI ready interrupt + * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE); +} +#if defined(RCC_LSE_SUPPORT) +/** + * @brief Disable LSE ready interrupt + * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE); +} +#endif +/** + * @brief Disable HSI ready interrupt + * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE); +} + +/** + * @brief Disable HSE ready interrupt + * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE); +} +#if defined(RCC_PLL_SUPPORT) +/** + * @brief Disable PLL ready interrupt + * @rmtoll CIER PLLRDYIE LL_RCC_DisableIT_PLLRDY + * @retval None + */ +__STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void) +{ + CLEAR_BIT(RCC->CIER, RCC_CIER_PLLRDYIE); +} +#endif +/** + * @brief Checks if LSI ready interrupt source is enabled or disabled. + * @rmtoll CIER LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == (RCC_CIER_LSIRDYIE)) ? 1UL : 0UL); +} +#if defined(RCC_LSE_SUPPORT) +/** + * @brief Checks if LSE ready interrupt source is enabled or disabled. + * @rmtoll CIER LSERDYIE LL_RCC_IsEnabledIT_LSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == (RCC_CIER_LSERDYIE)) ? 1UL : 0UL); +} +#endif +/** + * @brief Checks if HSI ready interrupt source is enabled or disabled. + * @rmtoll CIER HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == (RCC_CIER_HSIRDYIE)) ? 1UL : 0UL); +} + +/** + * @brief Checks if HSE ready interrupt source is enabled or disabled. + * @rmtoll CIER HSERDYIE LL_RCC_IsEnabledIT_HSERDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == (RCC_CIER_HSERDYIE)) ? 1UL : 0UL); +} +#if defined(RCC_PLL_SUPPORT) +/** + * @brief Checks if PLL ready interrupt source is enabled or disabled. + * @rmtoll CIER PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void) +{ + return ((READ_BIT(RCC->CIER, RCC_CIER_PLLRDYIE) == (RCC_CIER_PLLRDYIE)) ? 1UL : 0UL); +} +#endif +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RCC_LL_EF_Init De-initialization function + * @{ + */ +ErrorStatus LL_RCC_DeInit(void); +/** + * @} + */ + +/** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions + * @{ + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks); +uint32_t LL_RCC_GetMCOClockFreq(uint32_t MCOx); +uint32_t LL_RCC_GetLSCClockFreq(void); +#if defined(PVD) +uint32_t LL_RCC_GetPVDClockFreq(void); +#endif +#if defined(COMP1) +uint32_t LL_RCC_GetCOMPClockFreq(uint32_t COMPx); +#endif +#if defined(LPTIM1) +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMx); +#endif +#if defined(TRC) +uint32_t LL_RCC_GetRTCClockFreq(void); +#endif +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_LL_RCC_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_rtc.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_rtc.h similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_rtc.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_rtc.h index dbc2894..0fded17 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_rtc.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_rtc.h @@ -1,660 +1,660 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_rtc.h - * @author MCU Application Team - * @brief Header file of RTC LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PY32F0xx_LL_RTC_H -#define __PY32F0xx_LL_RTC_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined(RTC) - -/** @defgroup RTC_LL RTC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_Private_Macros RTC Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure - * @{ - */ - -/** - * @brief RTC Init structures definition - */ -typedef struct -{ - uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF - - This feature can be modified afterwards using unitary function - @ref LL_RTC_SetAsynchPrescaler(). */ - - uint32_t OutPutSource; /*!< Specifies which signal will be routed to the RTC Tamper pin. - This parameter can be a value of @ref LL_RTC_Output_Source - - This feature can be modified afterwards using unitary function - @ref LL_RTC_SetOutputSource(). */ - -} LL_RTC_InitTypeDef; - -/** - * @brief RTC Time structure definition - */ -typedef struct -{ - uint8_t Hours; /*!< Specifies the RTC Time Hours. - This parameter must be a number between Min_Data = 0 and Max_Data = 23 */ - - uint8_t Minutes; /*!< Specifies the RTC Time Minutes. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ - - uint8_t Seconds; /*!< Specifies the RTC Time Seconds. - This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ -} LL_RTC_TimeTypeDef; - - -/** - * @brief RTC Alarm structure definition - */ -typedef struct -{ - LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ - -} LL_RTC_AlarmTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants - * @{ - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_EC_FORMAT FORMAT - * @{ - */ -#define LL_RTC_FORMAT_BIN (0x000000000U) /*!< Binary data format */ -#define LL_RTC_FORMAT_BCD (0x000000001U) /*!< BCD data format */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup LL_RTC_Output_Source Clock Source to output on the Tamper Pin - * @{ - */ -#define LL_RTC_CALIB_OUTPUT_NONE (0x00000000U) /*!< Calibration output disabled */ -#define LL_RTC_CALIB_OUTPUT_RTCCLOCK BKP_RTCCR_CCO /*!< Calibration output is RTC Clock with a frequency divided by 64 on the TAMPER Pin */ -#define LL_RTC_CALIB_OUTPUT_ALARM BKP_RTCCR_ASOE /*!< Calibration output is Alarm pulse signal on the TAMPER pin */ -#define LL_RTC_CALIB_OUTPUT_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Calibration output is Second pulse signal on the TAMPER pin*/ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros - * @{ - */ - -/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in RTC register - * @param __INSTANCE__ RTC Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in RTC register - * @param __INSTANCE__ RTC Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup RTC_LL_EM_Convert Convert helper Macros - * @{ - */ - -/** - * @brief Helper macro to convert a value from 2 digit decimal format to BCD format - * @param __VALUE__ Byte to be converted - * @retval Converted byte - */ -#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)) - -/** - * @brief Helper macro to convert a value from BCD format to 2 digit decimal format - * @param __VALUE__ BCD value to be converted - * @retval Converted byte - */ -#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions - * @{ - */ - -/** @defgroup RTC_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Set Asynchronous prescaler factor - * @rmtoll PRLH PRL LL_RTC_SetAsynchPrescaler\n - * @rmtoll PRLL PRL LL_RTC_SetAsynchPrescaler\n - * @param RTCx RTC Instance - * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0xFFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) -{ - MODIFY_REG(RTCx->PRLH, RTC_PRLH_PRL, (AsynchPrescaler >> 16)); - MODIFY_REG(RTCx->PRLL, RTC_PRLL_PRL, (AsynchPrescaler & RTC_PRLL_PRL)); -} - -/** - * @brief Get Asynchronous prescaler factor - * @rmtoll DIVH DIV LL_RTC_GetDivider\n - * @rmtoll DIVL DIV LL_RTC_GetDivider\n - * @param RTCx RTC Instance - * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF - */ -__STATIC_INLINE uint32_t LL_RTC_GetDivider(RTC_TypeDef *RTCx) -{ - register uint16_t Highprescaler = 0, Lowprescaler = 0; - Highprescaler = READ_REG(RTCx->DIVH & RTC_DIVH_RTC_DIV); - Lowprescaler = READ_REG(RTCx->DIVL & RTC_DIVL_RTC_DIV); - - return (((uint32_t) Highprescaler << 16U) | Lowprescaler); -} - -/** - * @brief Set Output Source - * @rmtoll RTCCR CCO LL_RTC_SetOutputSource - * @rmtoll RTCCR ASOE LL_RTC_SetOutputSource - * @rmtoll RTCCR ASOS LL_RTC_SetOutputSource - * @param RTCx RTC Instance - * @param OutputSource This parameter can be one of the following values: - * @arg @ref LL_RTC_CALIB_OUTPUT_NONE - * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK - * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM - * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND - * @retval None - */ -__STATIC_INLINE void LL_RTC_SetOutputSource(RTC_TypeDef *RTCx, uint32_t OutputSource) -{ - MODIFY_REG(RTCx->BKP_RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), OutputSource); -} - -/** - * @brief Get Output Source - * @rmtoll RTCCR CCO LL_RTC_GetOutPutSource - * @rmtoll RTCCR ASOE LL_RTC_GetOutPutSource - * @rmtoll RTCCR ASOS LL_RTC_GetOutPutSource - * @param RTCx RTC Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_RTC_CALIB_OUTPUT_NONE - * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK - * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM - * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND - */ -__STATIC_INLINE uint32_t LL_RTC_GetOutPutSource(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->BKP_RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS))); -} - -/** - * @brief Enable the write protection for RTC registers. - * @rmtoll CRL CNF LL_RTC_EnableWriteProtection - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRL, RTC_CRL_CNF); -} - -/** - * @brief Disable the write protection for RTC registers. - * @rmtoll CRL RTC_CRL_CNF LL_RTC_DisableWriteProtection - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CRL, RTC_CRL_CNF); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_Time Time - * @{ - */ - -/** - * @brief Set time counter in BCD format - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function) - * @rmtoll CNTH CNT LL_RTC_TIME_Set\n - * CNTL CNT LL_RTC_TIME_Set\n - * @param RTCx RTC Instance - * @param TimeCounter Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_TIME_Set(RTC_TypeDef *RTCx, uint32_t TimeCounter) -{ - /* Set RTC COUNTER MSB word */ - WRITE_REG(RTCx->CNTH, (TimeCounter >> 16U)); - /* Set RTC COUNTER LSB word */ - WRITE_REG(RTCx->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); -} - -/** - * @brief Get time counter in BCD format - * @rmtoll CNTH CNT LL_RTC_TIME_Get\n - * CNTL CNT LL_RTC_TIME_Get\n - * @param RTCx RTC Instance - * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFFFFF - */ -__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) -{ - register uint16_t high = 0, low = 0; - - high = READ_REG(RTCx->CNTH & RTC_CNTH_RTC_CNT); - low = READ_REG(RTCx->CNTL & RTC_CNTL_RTC_CNT); - return ((uint32_t)(((uint32_t) high << 16U) | low)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_ALARM ALARM - * @{ - */ - -/** - * @brief Set Alarm Counter - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll ALRH ALR LL_RTC_ALARM_Set\n - * @rmtoll ALRL ALR LL_RTC_ALARM_Set\n - * @param RTCx RTC Instance - * @param AlarmCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF - * @retval None - */ -__STATIC_INLINE void LL_RTC_ALARM_Set(RTC_TypeDef *RTCx, uint32_t AlarmCounter) -{ - /* Set RTC COUNTER MSB word */ - WRITE_REG(RTCx->ALRH, (AlarmCounter >> 16)); - /* Set RTC COUNTER LSB word */ - WRITE_REG(RTCx->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR)); -} - - -/** @defgroup RTC_LL_EF_Calibration Calibration - * @{ - */ - -/** - * @brief Set the coarse digital calibration - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function) - * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n - * @param RTCx RTC Instance - * @param Value value of coarse calibration expressed in ppm - * @retval None - */ -__STATIC_INLINE void LL_RTC_CAL_SetCoarseDigital(RTC_TypeDef *RTCx, uint32_t Value) -{ - MODIFY_REG(RTCx->BKP_RTCCR, BKP_RTCCR_CAL, Value); -} - -/** - * @brief Get the coarse digital calibration value - * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n - * @param RTCx RTC Instance - * @retval value of coarse calibration expressed in ppm - */ -__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigital(RTC_TypeDef *RTCx) -{ - return (uint32_t)(READ_BIT(RTCx->BKP_RTCCR, BKP_RTCCR_CAL)); -} -/** - * @} - */ - -/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Get Alarm flag - * @rmtoll CRL ALRF LL_RTC_IsActiveFlag_ALR - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALR(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRL, RTC_CRL_ALRF) == (RTC_CRL_ALRF)); -} - -/** - * @brief Clear Alarm flag - * @rmtoll CRL ALRF LL_RTC_ClearFlag_ALR - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_ALR(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRL, RTC_CRL_ALRF); -} - -/** - * @brief Get Registers synchronization flag - * @rmtoll CRL RSF LL_RTC_IsActiveFlag_RS - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRL, RTC_CRL_RSF) == (RTC_CRL_RSF)); -} - -/** - * @brief Clear Registers synchronization flag - * @rmtoll CRL RSF LL_RTC_ClearFlag_RS - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRL, RTC_CRL_RSF); -} - -/** - * @brief Get Registers OverFlow flag - * @rmtoll CRL OWF LL_RTC_IsActiveFlag_OW - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_OW(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRL, RTC_CRL_OWF) == (RTC_CRL_OWF)); -} - -/** - * @brief Clear Registers OverFlow flag - * @rmtoll CRL OWF LL_RTC_ClearFlag_OW - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_OW(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRL, RTC_CRL_OWF); -} - -/** - * @brief Get Registers synchronization flag - * @rmtoll CRL SECF LL_RTC_IsActiveFlag_SEC - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SEC(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRL, RTC_CRL_SECF) == (RTC_CRL_SECF)); -} - -/** - * @brief Clear Registers synchronization flag - * @rmtoll CRL SECF LL_RTC_ClearFlag_SEC - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_ClearFlag_SEC(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRL, RTC_CRL_SECF); -} - -/** - * @brief Get RTC Operation OFF status flag - * @rmtoll CRL RTOFF LL_RTC_IsActiveFlag_RTOF - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RTOF(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRL, RTC_CRL_RTOFF) == (RTC_CRL_RTOFF)); -} - -/** - * @} - */ - -/** @defgroup RTC_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable Alarm interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH ALRIE LL_RTC_EnableIT_ALR - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_ALR(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CRH, RTC_CRH_ALRIE); -} - -/** - * @brief Disable Alarm interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH ALRIE LL_RTC_DisableIT_ALR - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_ALR(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRH, RTC_CRH_ALRIE); -} - -/** - * @brief Check if Alarm interrupt is enabled or not - * @rmtoll CRH ALRIE LL_RTC_IsEnabledIT_ALR - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALR(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRH, RTC_CRH_ALRIE) == (RTC_CRH_ALRIE)); -} - -/** - * @brief Enable Second Interrupt interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH SECIE LL_RTC_EnableIT_SEC - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_SEC(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CRH, RTC_CRH_SECIE); -} - -/** - * @brief Disable Second interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH SECIE LL_RTC_DisableIT_SEC - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_SEC(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRH, RTC_CRH_SECIE); -} - -/** - * @brief Check if Second interrupt is enabled or not - * @rmtoll CRH SECIE LL_RTC_IsEnabledIT_SEC - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SEC(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRH, RTC_CRH_SECIE) == (RTC_CRH_SECIE)); -} - -/** - * @brief Enable OverFlow interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH OWIE LL_RTC_EnableIT_OW - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_EnableIT_OW(RTC_TypeDef *RTCx) -{ - SET_BIT(RTCx->CRH, RTC_CRH_OWIE); -} - -/** - * @brief Disable OverFlow interrupt - * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. - * @rmtoll CRH OWIE LL_RTC_DisableIT_OW - * @param RTCx RTC Instance - * @retval None - */ -__STATIC_INLINE void LL_RTC_DisableIT_OW(RTC_TypeDef *RTCx) -{ - CLEAR_BIT(RTCx->CRH, RTC_CRH_OWIE); -} - -/** - * @brief Check if OverFlow interrupt is enabled or not - * @rmtoll CRH OWIE LL_RTC_IsEnabledIT_OW - * @param RTCx RTC Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_OW(RTC_TypeDef *RTCx) -{ - return (READ_BIT(RTCx->CRH, RTC_CRH_OWIE) == (RTC_CRH_OWIE)); -} -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); -void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); -ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); -void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); -ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); -void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); -ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); -ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter); -ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RTC) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PY32F0xx_LL_RTC_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_rtc.h + * @author MCU Application Team + * @brief Header file of RTC LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32F0xx_LL_RTC_H +#define __PY32F0xx_LL_RTC_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @defgroup RTC_LL RTC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_Private_Macros RTC Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_ES_INIT RTC Exported Init structure + * @{ + */ + +/** + * @brief RTC Init structures definition + */ +typedef struct +{ + uint32_t AsynchPrescaler; /*!< Specifies the RTC Asynchronous Predivider value. + This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFFFFF + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetAsynchPrescaler(). */ + + uint32_t OutPutSource; /*!< Specifies which signal will be routed to the RTC Tamper pin. + This parameter can be a value of @ref LL_RTC_Output_Source + + This feature can be modified afterwards using unitary function + @ref LL_RTC_SetOutputSource(). */ + +} LL_RTC_InitTypeDef; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t Hours; /*!< Specifies the RTC Time Hours. + This parameter must be a number between Min_Data = 0 and Max_Data = 23 */ + + uint8_t Minutes; /*!< Specifies the RTC Time Minutes. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t Seconds; /*!< Specifies the RTC Time Seconds. + This parameter must be a number between Min_Data = 0 and Max_Data = 59 */ +} LL_RTC_TimeTypeDef; + + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + LL_RTC_TimeTypeDef AlarmTime; /*!< Specifies the RTC Alarm Time members. */ + +} LL_RTC_AlarmTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Constants RTC Exported Constants + * @{ + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EC_FORMAT FORMAT + * @{ + */ +#define LL_RTC_FORMAT_BIN (0x000000000U) /*!< Binary data format */ +#define LL_RTC_FORMAT_BCD (0x000000001U) /*!< BCD data format */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup LL_RTC_Output_Source Clock Source to output on the Tamper Pin + * @{ + */ +#define LL_RTC_CALIB_OUTPUT_NONE (0x00000000U) /*!< Calibration output disabled */ +#define LL_RTC_CALIB_OUTPUT_RTCCLOCK BKP_RTCCR_CCO /*!< Calibration output is RTC Clock with a frequency divided by 64 on the TAMPER Pin */ +#define LL_RTC_CALIB_OUTPUT_ALARM BKP_RTCCR_ASOE /*!< Calibration output is Alarm pulse signal on the TAMPER pin */ +#define LL_RTC_CALIB_OUTPUT_SECOND (BKP_RTCCR_ASOS | BKP_RTCCR_ASOE) /*!< Calibration output is Second pulse signal on the TAMPER pin*/ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Macros RTC Exported Macros + * @{ + */ + +/** @defgroup RTC_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_RTC_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in RTC register + * @param __INSTANCE__ RTC Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_RTC_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup RTC_LL_EM_Convert Convert helper Macros + * @{ + */ + +/** + * @brief Helper macro to convert a value from 2 digit decimal format to BCD format + * @param __VALUE__ Byte to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BIN2BCD(__VALUE__) (uint8_t)((((__VALUE__) / 10U) << 4U) | ((__VALUE__) % 10U)) + +/** + * @brief Helper macro to convert a value from BCD format to 2 digit decimal format + * @param __VALUE__ BCD value to be converted + * @retval Converted byte + */ +#define __LL_RTC_CONVERT_BCD2BIN(__VALUE__) (uint8_t)(((uint8_t)((__VALUE__) & (uint8_t)0xF0U) >> (uint8_t)0x4U) * 10U + ((__VALUE__) & (uint8_t)0x0FU)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup RTC_LL_Exported_Functions RTC Exported Functions + * @{ + */ + +/** @defgroup RTC_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Set Asynchronous prescaler factor + * @rmtoll PRLH PRL LL_RTC_SetAsynchPrescaler\n + * @rmtoll PRLL PRL LL_RTC_SetAsynchPrescaler\n + * @param RTCx RTC Instance + * @param AsynchPrescaler Value between Min_Data = 0 and Max_Data = 0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetAsynchPrescaler(RTC_TypeDef *RTCx, uint32_t AsynchPrescaler) +{ + MODIFY_REG(RTCx->PRLH, RTC_PRLH_PRL, (AsynchPrescaler >> 16)); + MODIFY_REG(RTCx->PRLL, RTC_PRLL_PRL, (AsynchPrescaler & RTC_PRLL_PRL)); +} + +/** + * @brief Get Asynchronous prescaler factor + * @rmtoll DIVH DIV LL_RTC_GetDivider\n + * @rmtoll DIVL DIV LL_RTC_GetDivider\n + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_GetDivider(RTC_TypeDef *RTCx) +{ + register uint16_t Highprescaler = 0, Lowprescaler = 0; + Highprescaler = READ_REG(RTCx->DIVH & RTC_DIVH_RTC_DIV); + Lowprescaler = READ_REG(RTCx->DIVL & RTC_DIVL_RTC_DIV); + + return (((uint32_t) Highprescaler << 16U) | Lowprescaler); +} + +/** + * @brief Set Output Source + * @rmtoll RTCCR CCO LL_RTC_SetOutputSource + * @rmtoll RTCCR ASOE LL_RTC_SetOutputSource + * @rmtoll RTCCR ASOS LL_RTC_SetOutputSource + * @param RTCx RTC Instance + * @param OutputSource This parameter can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK + * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM + * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND + * @retval None + */ +__STATIC_INLINE void LL_RTC_SetOutputSource(RTC_TypeDef *RTCx, uint32_t OutputSource) +{ + MODIFY_REG(RTCx->BKP_RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS), OutputSource); +} + +/** + * @brief Get Output Source + * @rmtoll RTCCR CCO LL_RTC_GetOutPutSource + * @rmtoll RTCCR ASOE LL_RTC_GetOutPutSource + * @rmtoll RTCCR ASOS LL_RTC_GetOutPutSource + * @param RTCx RTC Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_RTC_CALIB_OUTPUT_NONE + * @arg @ref LL_RTC_CALIB_OUTPUT_RTCCLOCK + * @arg @ref LL_RTC_CALIB_OUTPUT_ALARM + * @arg @ref LL_RTC_CALIB_OUTPUT_SECOND + */ +__STATIC_INLINE uint32_t LL_RTC_GetOutPutSource(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->BKP_RTCCR, (BKP_RTCCR_CCO | BKP_RTCCR_ASOE | BKP_RTCCR_ASOS))); +} + +/** + * @brief Enable the write protection for RTC registers. + * @rmtoll CRL CNF LL_RTC_EnableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableWriteProtection(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_CNF); +} + +/** + * @brief Disable the write protection for RTC registers. + * @rmtoll CRL RTC_CRL_CNF LL_RTC_DisableWriteProtection + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableWriteProtection(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRL, RTC_CRL_CNF); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_Time Time + * @{ + */ + +/** + * @brief Set time counter in BCD format + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function) + * @rmtoll CNTH CNT LL_RTC_TIME_Set\n + * CNTL CNT LL_RTC_TIME_Set\n + * @param RTCx RTC Instance + * @param TimeCounter Value between Min_Data=0x00 and Max_Data=0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_TIME_Set(RTC_TypeDef *RTCx, uint32_t TimeCounter) +{ + /* Set RTC COUNTER MSB word */ + WRITE_REG(RTCx->CNTH, (TimeCounter >> 16U)); + /* Set RTC COUNTER LSB word */ + WRITE_REG(RTCx->CNTL, (TimeCounter & RTC_CNTL_RTC_CNT)); +} + +/** + * @brief Get time counter in BCD format + * @rmtoll CNTH CNT LL_RTC_TIME_Get\n + * CNTL CNT LL_RTC_TIME_Get\n + * @param RTCx RTC Instance + * @retval Value between Min_Data = 0 and Max_Data = 0xFFFFFFFF + */ +__STATIC_INLINE uint32_t LL_RTC_TIME_Get(RTC_TypeDef *RTCx) +{ + register uint16_t high = 0, low = 0; + + high = READ_REG(RTCx->CNTH & RTC_CNTH_RTC_CNT); + low = READ_REG(RTCx->CNTL & RTC_CNTL_RTC_CNT); + return ((uint32_t)(((uint32_t) high << 16U) | low)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_ALARM ALARM + * @{ + */ + +/** + * @brief Set Alarm Counter + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll ALRH ALR LL_RTC_ALARM_Set\n + * @rmtoll ALRL ALR LL_RTC_ALARM_Set\n + * @param RTCx RTC Instance + * @param AlarmCounter Value between Min_Data=0x00 and Max_Data=0xFFFFF + * @retval None + */ +__STATIC_INLINE void LL_RTC_ALARM_Set(RTC_TypeDef *RTCx, uint32_t AlarmCounter) +{ + /* Set RTC COUNTER MSB word */ + WRITE_REG(RTCx->ALRH, (AlarmCounter >> 16)); + /* Set RTC COUNTER LSB word */ + WRITE_REG(RTCx->ALRL, (AlarmCounter & RTC_ALRL_RTC_ALR)); +} + + +/** @defgroup RTC_LL_EF_Calibration Calibration + * @{ + */ + +/** + * @brief Set the coarse digital calibration + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @note It can be written in initialization mode only (@ref LL_RTC_EnterInitMode function) + * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n + * @param RTCx RTC Instance + * @param Value value of coarse calibration expressed in ppm + * @retval None + */ +__STATIC_INLINE void LL_RTC_CAL_SetCoarseDigital(RTC_TypeDef *RTCx, uint32_t Value) +{ + MODIFY_REG(RTCx->BKP_RTCCR, BKP_RTCCR_CAL, Value); +} + +/** + * @brief Get the coarse digital calibration value + * @rmtoll RTCCR CAL LL_RTC_CAL_SetCoarseDigital\n + * @param RTCx RTC Instance + * @retval value of coarse calibration expressed in ppm + */ +__STATIC_INLINE uint32_t LL_RTC_CAL_GetCoarseDigital(RTC_TypeDef *RTCx) +{ + return (uint32_t)(READ_BIT(RTCx->BKP_RTCCR, BKP_RTCCR_CAL)); +} +/** + * @} + */ + +/** @defgroup RTC_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Get Alarm flag + * @rmtoll CRL ALRF LL_RTC_IsActiveFlag_ALR + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_ALR(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_ALRF) == (RTC_CRL_ALRF)); +} + +/** + * @brief Clear Alarm flag + * @rmtoll CRL ALRF LL_RTC_ClearFlag_ALR + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_ALR(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_ALRF); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll CRL RSF LL_RTC_IsActiveFlag_RS + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RS(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_RSF) == (RTC_CRL_RSF)); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll CRL RSF LL_RTC_ClearFlag_RS + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_RS(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_RSF); +} + +/** + * @brief Get Registers OverFlow flag + * @rmtoll CRL OWF LL_RTC_IsActiveFlag_OW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_OW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_OWF) == (RTC_CRL_OWF)); +} + +/** + * @brief Clear Registers OverFlow flag + * @rmtoll CRL OWF LL_RTC_ClearFlag_OW + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_OW(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_OWF); +} + +/** + * @brief Get Registers synchronization flag + * @rmtoll CRL SECF LL_RTC_IsActiveFlag_SEC + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_SEC(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_SECF) == (RTC_CRL_SECF)); +} + +/** + * @brief Clear Registers synchronization flag + * @rmtoll CRL SECF LL_RTC_ClearFlag_SEC + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_ClearFlag_SEC(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRL, RTC_CRL_SECF); +} + +/** + * @brief Get RTC Operation OFF status flag + * @rmtoll CRL RTOFF LL_RTC_IsActiveFlag_RTOF + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsActiveFlag_RTOF(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRL, RTC_CRL_RTOFF) == (RTC_CRL_RTOFF)); +} + +/** + * @} + */ + +/** @defgroup RTC_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable Alarm interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH ALRIE LL_RTC_EnableIT_ALR + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_ALR(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRH, RTC_CRH_ALRIE); +} + +/** + * @brief Disable Alarm interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH ALRIE LL_RTC_DisableIT_ALR + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_ALR(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRH, RTC_CRH_ALRIE); +} + +/** + * @brief Check if Alarm interrupt is enabled or not + * @rmtoll CRH ALRIE LL_RTC_IsEnabledIT_ALR + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_ALR(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRH, RTC_CRH_ALRIE) == (RTC_CRH_ALRIE)); +} + +/** + * @brief Enable Second Interrupt interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH SECIE LL_RTC_EnableIT_SEC + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_SEC(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRH, RTC_CRH_SECIE); +} + +/** + * @brief Disable Second interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH SECIE LL_RTC_DisableIT_SEC + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_SEC(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRH, RTC_CRH_SECIE); +} + +/** + * @brief Check if Second interrupt is enabled or not + * @rmtoll CRH SECIE LL_RTC_IsEnabledIT_SEC + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_SEC(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRH, RTC_CRH_SECIE) == (RTC_CRH_SECIE)); +} + +/** + * @brief Enable OverFlow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH OWIE LL_RTC_EnableIT_OW + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_EnableIT_OW(RTC_TypeDef *RTCx) +{ + SET_BIT(RTCx->CRH, RTC_CRH_OWIE); +} + +/** + * @brief Disable OverFlow interrupt + * @note Bit is write-protected. @ref LL_RTC_DisableWriteProtection function should be called before. + * @rmtoll CRH OWIE LL_RTC_DisableIT_OW + * @param RTCx RTC Instance + * @retval None + */ +__STATIC_INLINE void LL_RTC_DisableIT_OW(RTC_TypeDef *RTCx) +{ + CLEAR_BIT(RTCx->CRH, RTC_CRH_OWIE); +} + +/** + * @brief Check if OverFlow interrupt is enabled or not + * @rmtoll CRH OWIE LL_RTC_IsEnabledIT_OW + * @param RTCx RTC Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_RTC_IsEnabledIT_OW(RTC_TypeDef *RTCx) +{ + return (READ_BIT(RTCx->CRH, RTC_CRH_OWIE) == (RTC_CRH_OWIE)); +} +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup RTC_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct); +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct); +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct); +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct); +ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct); +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx); +ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter); +ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0xx_LL_RTC_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_spi.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_spi.h similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_spi.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_spi.h index c315c9b..ade346b 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_spi.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_spi.h @@ -1,1175 +1,1175 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_spi.h - * @author MCU Application Team - * @brief Header file of SPI LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef PY32F0xx_LL_SPI_H -#define PY32F0xx_LL_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - - - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (SPI1) || defined (SPI2) - -/** @defgroup SPI_LL SPI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure - * @{ - */ - -/** - * @brief SPI Init structures definition - */ -typedef struct -{ - uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. - This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ - - uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). - This parameter can be a value of @ref SPI_LL_EC_MODE. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ - - uint32_t DataWidth; /*!< Specifies the SPI data width. - This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ - - uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. - This parameter can be a value of @ref SPI_LL_EC_POLARITY. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ - - uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. - This parameter can be a value of @ref SPI_LL_EC_PHASE. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ - - uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. - This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ - - uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. - This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. - @note The communication clock is derived from the master clock. The slave clock does not need to be set. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ - - uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. - This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. - - This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ - - uint32_t SlaveSpeedMode; /*!< Specifies the Slave speed mode. - This parameter can be a value of @ref SPI_LL_EC_SLAVE_SPEED_MODE */ - -} LL_SPI_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants - * @{ - */ - -/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_SPI_ReadReg function - * @{ - */ -#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ -#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ -#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ -#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ -#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions - * @{ - */ -#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ -#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ -#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_MODE Operation Mode - * @{ - */ -#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ -#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_PHASE Clock Phase - * @{ - */ -#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ -#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_POLARITY Clock Polarity - * @{ - */ -#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ -#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler - * @{ - */ -#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ -#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order - * @{ - */ -#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ -#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode - * @{ - */ -#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ -#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ -#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ -#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode - * @{ - */ -#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ -#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ -#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth - * @{ - */ -#define LL_SPI_DATAWIDTH_8BIT 0x0 /*!< Data length for SPI transfer: 8 bits */ -#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS) /*!< Data length for SPI transfer: 16 bits */ -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) - -#endif /* USE_FULL_LL_DRIVER */ - - -/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold - * @{ - */ -#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */ -#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level - * @{ - */ -#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ -#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ -#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ -#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ -/** - * @} - */ - -/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level - * @{ - */ -#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ -#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ -#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ -#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ - -#if (defined(DMA1) || defined(DMA)) -/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity - * @{ - */ -#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ -#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ -#endif /* DMA1 or DMA */ - -/** - * @} - */ - -/** @defgroup SPI_LL_EC_SLAVE_SPEED_MODE SLAVE SPEED MODE - * @{ - */ -#define LL_SPI_SLAVE_SPEED_NORMAL 0x00000000U /* Slave normal mode */ -#define LL_SPI_SLAVE_SPEED_FAST SPI_CR2_SLVFM /* Slave fast mode */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros - * @{ - */ - -/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in SPI register - * @param __INSTANCE__ SPI Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in SPI register - * @param __INSTANCE__ SPI Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions - * @{ - */ - -/** @defgroup SPI_LL_EF_Configuration Configuration - * @{ - */ - -/** - * @brief Enable SPI peripheral - * @rmtoll CR1 SPE LL_SPI_Enable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR1, SPI_CR1_SPE); -} - -/** - * @brief Disable SPI peripheral - * @note When disabling the SPI, follow the procedure described in the Reference Manual. - * @rmtoll CR1 SPE LL_SPI_Disable - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); -} - -/** - * @brief Check if SPI peripheral is enabled - * @rmtoll CR1 SPE LL_SPI_IsEnabled - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); -} - -/** - * @brief Set SPI operation mode to Master or Slave - * @note This bit should not be changed when communication is ongoing. - * @rmtoll CR1 MSTR LL_SPI_SetMode\n - * CR1 SSI LL_SPI_SetMode - * @param SPIx SPI Instance - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_SPI_MODE_MASTER - * @arg @ref LL_SPI_MODE_SLAVE - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); -} - -/** - * @brief Get SPI operation mode (Master or Slave) - * @rmtoll CR1 MSTR LL_SPI_GetMode\n - * CR1 SSI LL_SPI_GetMode - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_MODE_MASTER - * @arg @ref LL_SPI_MODE_SLAVE - */ -__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); -} - -/** - * @brief Set clock phase - * @note This bit should not be changed when communication is ongoing. - * This bit is not used in SPI TI mode. - * @rmtoll CR1 CPHA LL_SPI_SetClockPhase - * @param SPIx SPI Instance - * @param ClockPhase This parameter can be one of the following values: - * @arg @ref LL_SPI_PHASE_1EDGE - * @arg @ref LL_SPI_PHASE_2EDGE - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); -} - -/** - * @brief Get clock phase - * @rmtoll CR1 CPHA LL_SPI_GetClockPhase - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_PHASE_1EDGE - * @arg @ref LL_SPI_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); -} - -/** - * @brief Set clock polarity - * @note This bit should not be changed when communication is ongoing. - * This bit is not used in SPI TI mode. - * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity - * @param SPIx SPI Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_SPI_POLARITY_LOW - * @arg @ref LL_SPI_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); -} - -/** - * @brief Get clock polarity - * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_POLARITY_LOW - * @arg @ref LL_SPI_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); -} - -/** - * @brief Set baud rate prescaler - * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. - * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler - * @param SPIx SPI Instance - * @param BaudRate This parameter can be one of the following values: - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); -} - -/** - * @brief Get baud rate prescaler - * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 - * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 - */ -__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); -} - -/** - * @brief Set transfer bit order - * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. - * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder - * @param SPIx SPI Instance - * @param BitOrder This parameter can be one of the following values: - * @arg @ref LL_SPI_LSB_FIRST - * @arg @ref LL_SPI_MSB_FIRST - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); -} - -/** - * @brief Get transfer bit order - * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_LSB_FIRST - * @arg @ref LL_SPI_MSB_FIRST - */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); -} - -/** - * @brief Set transfer direction mode - * @note For Half-Duplex mode, Rx Direction is set by default. - * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. - * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n - * CR1 BIDIMODE LL_SPI_SetTransferDirection\n - * CR1 BIDIOE LL_SPI_SetTransferDirection - * @param SPIx SPI Instance - * @param TransferDirection This parameter can be one of the following values: - * @arg @ref LL_SPI_FULL_DUPLEX - * @arg @ref LL_SPI_SIMPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_TX - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); -} - -/** - * @brief Get transfer direction mode - * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n - * CR1 BIDIMODE LL_SPI_GetTransferDirection\n - * CR1 BIDIOE LL_SPI_GetTransferDirection - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_FULL_DUPLEX - * @arg @ref LL_SPI_SIMPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_RX - * @arg @ref LL_SPI_HALF_DUPLEX_TX - */ -__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); -} - -/** - * @brief Set frame data width - * @rmtoll CR2 DS LL_SPI_SetDataWidth - * @param SPIx SPI Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_SPI_DATAWIDTH_8BIT - * @arg @ref LL_SPI_DATAWIDTH_16BIT - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); -} - -/** - * @brief Get frame data width - * @rmtoll CR2 DS LL_SPI_GetDataWidth - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_DATAWIDTH_8BIT - * @arg @ref LL_SPI_DATAWIDTH_16BIT - */ -__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); -} - -/** - * @brief Set threshold of RXFIFO that triggers an RXNE event - * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold - * @param SPIx SPI Instance - * @param Threshold This parameter can be one of the following values: - * @arg @ref LL_SPI_RX_FIFO_TH_HALF - * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); -} - -/** - * @brief Get threshold of RXFIFO that triggers an RXNE event - * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_RX_FIFO_TH_HALF - * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER - */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management - * @{ - */ - -/** - * @brief Set NSS mode - * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n - * @rmtoll CR2 SSOE LL_SPI_SetNSSMode - * @param SPIx SPI Instance - * @param NSS This parameter can be one of the following values: - * @arg @ref LL_SPI_NSS_SOFT - * @arg @ref LL_SPI_NSS_HARD_INPUT - * @arg @ref LL_SPI_NSS_HARD_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) -{ - MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); - MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); -} - -/** - * @brief Get NSS mode - * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n - * @rmtoll CR2 SSOE LL_SPI_GetNSSMode - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_NSS_SOFT - * @arg @ref LL_SPI_NSS_HARD_INPUT - * @arg @ref LL_SPI_NSS_HARD_OUTPUT - */ -__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) -{ - uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); - uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); - return (Ssm | Ssoe); -} -/** - * @} - */ - -/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management - * @{ - */ - -/** - * @brief Check if Rx buffer is not empty - * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx buffer is empty - * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); -} - - -/** - * @brief Get mode fault error flag - * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); -} - -/** - * @brief Get overrun error flag - * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); -} - -/** - * @brief Get busy flag - * @note The BSY flag is cleared under any one of the following conditions: - * -When the SPI is correctly disabled - * -When a fault is detected in Master mode (MODF bit set to 1) - * -In Master mode, when it finishes a data transmission and no new data is ready to be - * sent - * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between - * each data transfer. - * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); -} - -/** - * @brief Get FIFO reception Level - * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_RX_FIFO_EMPTY - * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL - * @arg @ref LL_SPI_RX_FIFO_HALF_FULL - * @arg @ref LL_SPI_RX_FIFO_FULL - */ -__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); -} - -/** - * @brief Get FIFO Transmission Level - * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_TX_FIFO_EMPTY - * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL - * @arg @ref LL_SPI_TX_FIFO_HALF_FULL - * @arg @ref LL_SPI_TX_FIFO_FULL - */ -__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); -} - -/** - * @brief Clear mode fault error flag - * @note Clearing this flag is done by a read access to the SPIx_SR - * register followed by a write access to the SPIx_CR1 register - * @rmtoll SR MODF LL_SPI_ClearFlag_MODF - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) -{ - __IO uint32_t tmpreg_sr; - tmpreg_sr = SPIx->SR; - (void) tmpreg_sr; - CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); -} - -/** - * @brief Clear overrun error flag - * @note Clearing this flag is done by a read access to the SPIx_DR - * register followed by a read access to the SPIx_SR register - * @rmtoll SR OVR LL_SPI_ClearFlag_OVR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) -{ - __IO uint32_t tmpreg; - tmpreg = SPIx->DR; - (void) tmpreg; - tmpreg = SPIx->SR; - (void) tmpreg; -} - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_IT_Management Interrupt Management - * @{ - */ - -/** - * @brief Enable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). - * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); -} - -/** - * @brief Enable Rx buffer not empty interrupt - * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); -} - -/** - * @brief Enable Tx buffer empty interrupt - * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); -} - -/** - * @brief Disable error interrupt - * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). - * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); -} - -/** - * @brief Disable Rx buffer not empty interrupt - * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); -} - -/** - * @brief Disable Tx buffer empty interrupt - * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); -} - -/** - * @brief Check if error interrupt is enabled - * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Rx buffer not empty interrupt is enabled - * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); -} - -/** - * @brief Check if Tx buffer empty interrupt - * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); -} - -/** - * @} - */ - -#if (defined(DMA1) || defined(DMA)) -/** @defgroup SPI_LL_EF_DMA_Management DMA Management - * @{ - */ - -/** - * @brief Enable DMA Rx - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); -} - -/** - * @brief Disable DMA Rx - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); -} - -/** - * @brief Check if DMA Rx is enabled - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable DMA Tx - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) -{ - SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); -} - -/** - * @brief Disable DMA Tx - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX - * @param SPIx SPI Instance - * @retval None - */ -__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) -{ - CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); -} - -/** - * @brief Check if DMA Tx is enabled - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX - * @param SPIx SPI Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) -{ - return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); -} - -/** - * @brief Set parity of Last DMA reception - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX - * @param SPIx SPI Instance - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_SPI_DMA_PARITY_ODD - * @arg @ref LL_SPI_DMA_PARITY_EVEN - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_LDMA_RX, (Parity << SPI_CR2_LDMA_RX_Pos)); -} - -/** - * @brief Get parity configuration for Last DMA reception - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_DMA_PARITY_ODD - * @arg @ref LL_SPI_DMA_PARITY_EVEN - */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMA_RX) >> SPI_CR2_LDMA_RX_Pos); -} - -/** - * @brief Set parity of Last DMA transmission - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX - * @param SPIx SPI Instance - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_SPI_DMA_PARITY_ODD - * @arg @ref LL_SPI_DMA_PARITY_EVEN - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_LDMA_TX, (Parity << SPI_CR2_LDMA_TX_Pos)); -} - -/** - * @brief Get parity configuration for Last DMA transmission - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_DMA_PARITY_ODD - * @arg @ref LL_SPI_DMA_PARITY_EVEN - */ -__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMA_TX) >> SPI_CR2_LDMA_TX_Pos); -} - -/** - * @brief Get the data register address used for DMA transfer - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll DR DR LL_SPI_DMA_GetRegAddr - * @param SPIx SPI Instance - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) -{ - return (uint32_t) & (SPIx->DR); -} -#endif /* DMA1 or DMA */ - -/** - * @} - */ - -/** @defgroup SPI_LL_EF_DATA_Management DATA Management - * @{ - */ - -/** - * @brief Read 8-Bits in the data register - * @rmtoll DR DR LL_SPI_ReceiveData8 - * @param SPIx SPI Instance - * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) -{ - return (*((__IO uint8_t *)&SPIx->DR)); -} - -/** - * @brief Read 16-Bits in the data register - * @rmtoll DR DR LL_SPI_ReceiveData16 - * @param SPIx SPI Instance - * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) -{ - return (uint16_t)(READ_REG(SPIx->DR)); -} - -/** - * @brief Write 8-Bits in the data register - * @rmtoll DR DR LL_SPI_TransmitData8 - * @param SPIx SPI Instance - * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) -{ -#if defined (__GNUC__) - __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); - *spidr = TxData; -#else - *((__IO uint8_t *)&SPIx->DR) = TxData; -#endif /* __GNUC__ */ -} - -/** - * @brief Write 16-Bits in the data register - * @rmtoll DR DR LL_SPI_TransmitData16 - * @param SPIx SPI Instance - * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF - * @retval None - */ -__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) -{ -#if defined (__GNUC__) - __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); - *spidr = TxData; -#else - SPIx->DR = TxData; -#endif /* __GNUC__ */ -} - -/** - * @brief Set Slave Speed Mode - * @rmtoll CR2 SLVFM LL_SPI_SetSlaveSpeedMode - * @param SPIx SPI Instance - * @param SlaveSpeedMode This parameter can be one of the following values: - * @arg @ref LL_SPI_SLAVE_SPEED_NORMAL - * @arg @ref LL_SPI_SLAVE_SPEED_FAST - * @retval None - */ -__STATIC_INLINE void LL_SPI_SetSlaveSpeedMode(SPI_TypeDef *SPIx, uint32_t SlaveSpeedMode) -{ - MODIFY_REG(SPIx->CR2, SPI_CR2_SLVFM, SlaveSpeedMode); -} - -/** - * @brief Get Slave Speed Mode - * @rmtoll CR2 SLVFM LL_SPI_GetSlaveSpeedMode - * @param SPIx SPI Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_SPI_SLAVE_SPEED_NORMAL - * @arg @ref LL_SPI_SLAVE_SPEED_FAST - */ -__STATIC_INLINE uint32_t LL_SPI_GetSlaveSpeedMode(SPI_TypeDef *SPIx) -{ - return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_SLVFM)); -} - -/** - * @} - */ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions - * @{ - */ - -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); -ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); -void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ -/** - * @} - */ - -/** - * @} - */ -#endif /* defined (SPI1) || defined (SPI2) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* PY32F0xx_LL_SPI_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_spi.h + * @author MCU Application Team + * @brief Header file of SPI LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef PY32F0xx_LL_SPI_H +#define PY32F0xx_LL_SPI_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + + + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) + +/** @defgroup SPI_LL SPI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_ES_INIT SPI Exported Init structure + * @{ + */ + +/** + * @brief SPI Init structures definition + */ +typedef struct +{ + uint32_t TransferDirection; /*!< Specifies the SPI unidirectional or bidirectional data mode. + This parameter can be a value of @ref SPI_LL_EC_TRANSFER_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferDirection().*/ + + uint32_t Mode; /*!< Specifies the SPI mode (Master/Slave). + This parameter can be a value of @ref SPI_LL_EC_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetMode().*/ + + uint32_t DataWidth; /*!< Specifies the SPI data width. + This parameter can be a value of @ref SPI_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetDataWidth().*/ + + uint32_t ClockPolarity; /*!< Specifies the serial clock steady state. + This parameter can be a value of @ref SPI_LL_EC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPolarity().*/ + + uint32_t ClockPhase; /*!< Specifies the clock active edge for the bit capture. + This parameter can be a value of @ref SPI_LL_EC_PHASE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetClockPhase().*/ + + uint32_t NSS; /*!< Specifies whether the NSS signal is managed by hardware (NSS pin) or by software using the SSI bit. + This parameter can be a value of @ref SPI_LL_EC_NSS_MODE. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetNSSMode().*/ + + uint32_t BaudRate; /*!< Specifies the BaudRate prescaler value which will be used to configure the transmit and receive SCK clock. + This parameter can be a value of @ref SPI_LL_EC_BAUDRATEPRESCALER. + @note The communication clock is derived from the master clock. The slave clock does not need to be set. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetBaudRatePrescaler().*/ + + uint32_t BitOrder; /*!< Specifies whether data transfers start from MSB or LSB bit. + This parameter can be a value of @ref SPI_LL_EC_BIT_ORDER. + + This feature can be modified afterwards using unitary function @ref LL_SPI_SetTransferBitOrder().*/ + + uint32_t SlaveSpeedMode; /*!< Specifies the Slave speed mode. + This parameter can be a value of @ref SPI_LL_EC_SLAVE_SPEED_MODE */ + +} LL_SPI_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Constants SPI Exported Constants + * @{ + */ + +/** @defgroup SPI_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_SPI_ReadReg function + * @{ + */ +#define LL_SPI_SR_RXNE SPI_SR_RXNE /*!< Rx buffer not empty flag */ +#define LL_SPI_SR_TXE SPI_SR_TXE /*!< Tx buffer empty flag */ +#define LL_SPI_SR_BSY SPI_SR_BSY /*!< Busy flag */ +#define LL_SPI_SR_MODF SPI_SR_MODF /*!< Mode fault flag */ +#define LL_SPI_SR_OVR SPI_SR_OVR /*!< Overrun flag */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_SPI_ReadReg and LL_SPI_WriteReg functions + * @{ + */ +#define LL_SPI_CR2_RXNEIE SPI_CR2_RXNEIE /*!< Rx buffer not empty interrupt enable */ +#define LL_SPI_CR2_TXEIE SPI_CR2_TXEIE /*!< Tx buffer empty interrupt enable */ +#define LL_SPI_CR2_ERRIE SPI_CR2_ERRIE /*!< Error interrupt enable */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_MODE Operation Mode + * @{ + */ +#define LL_SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI) /*!< Master configuration */ +#define LL_SPI_MODE_SLAVE 0x00000000U /*!< Slave configuration */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_SPI_PHASE_1EDGE 0x00000000U /*!< First clock transition is the first data capture edge */ +#define LL_SPI_PHASE_2EDGE (SPI_CR1_CPHA) /*!< Second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_SPI_POLARITY_LOW 0x00000000U /*!< Clock to 0 when idle */ +#define LL_SPI_POLARITY_HIGH (SPI_CR1_CPOL) /*!< Clock to 1 when idle */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BAUDRATEPRESCALER Baud Rate Prescaler + * @{ + */ +#define LL_SPI_BAUDRATEPRESCALER_DIV2 0x00000000U /*!< BaudRate control equal to fPCLK/2 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV4 (SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/4 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV8 (SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/8 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV16 (SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/16 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV32 (SPI_CR1_BR_2) /*!< BaudRate control equal to fPCLK/32 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV64 (SPI_CR1_BR_2 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/64 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV128 (SPI_CR1_BR_2 | SPI_CR1_BR_1) /*!< BaudRate control equal to fPCLK/128 */ +#define LL_SPI_BAUDRATEPRESCALER_DIV256 (SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0) /*!< BaudRate control equal to fPCLK/256 */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_BIT_ORDER Transmission Bit Order + * @{ + */ +#define LL_SPI_LSB_FIRST (SPI_CR1_LSBFIRST) /*!< Data is transmitted/received with the LSB first */ +#define LL_SPI_MSB_FIRST 0x00000000U /*!< Data is transmitted/received with the MSB first */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TRANSFER_MODE Transfer Mode + * @{ + */ +#define LL_SPI_FULL_DUPLEX 0x00000000U /*!< Full-Duplex mode. Rx and Tx transfer on 2 lines */ +#define LL_SPI_SIMPLEX_RX (SPI_CR1_RXONLY) /*!< Simplex Rx mode. Rx transfer only on 1 line */ +#define LL_SPI_HALF_DUPLEX_RX (SPI_CR1_BIDIMODE) /*!< Half-Duplex Rx mode. Rx transfer on 1 line */ +#define LL_SPI_HALF_DUPLEX_TX (SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE) /*!< Half-Duplex Tx mode. Tx transfer on 1 line */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_NSS_MODE Slave Select Pin Mode + * @{ + */ +#define LL_SPI_NSS_SOFT (SPI_CR1_SSM) /*!< NSS managed internally. NSS pin not used and free */ +#define LL_SPI_NSS_HARD_INPUT 0x00000000U /*!< NSS pin used in Input. Only used in Master mode */ +#define LL_SPI_NSS_HARD_OUTPUT (((uint32_t)SPI_CR2_SSOE << 16U)) /*!< NSS pin used in Output. Only used in Slave mode as chip select */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_SPI_DATAWIDTH_8BIT 0x0 /*!< Data length for SPI transfer: 8 bits */ +#define LL_SPI_DATAWIDTH_16BIT (SPI_CR2_DS) /*!< Data length for SPI transfer: 16 bits */ +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) + +#endif /* USE_FULL_LL_DRIVER */ + + +/** @defgroup SPI_LL_EC_RX_FIFO_TH RX FIFO Threshold + * @{ + */ +#define LL_SPI_RX_FIFO_TH_HALF 0x00000000U /*!< RXNE event is generated if FIFO level is greater than or equal to 1/2 (16-bit) */ +#define LL_SPI_RX_FIFO_TH_QUARTER (SPI_CR2_FRXTH) /*!< RXNE event is generated if FIFO level is greater than or equal to 1/4 (8-bit) */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_RX_FIFO RX FIFO Level + * @{ + */ +#define LL_SPI_RX_FIFO_EMPTY 0x00000000U /*!< FIFO reception empty */ +#define LL_SPI_RX_FIFO_QUARTER_FULL (SPI_SR_FRLVL_0) /*!< FIFO reception 1/4 */ +#define LL_SPI_RX_FIFO_HALF_FULL (SPI_SR_FRLVL_1) /*!< FIFO reception 1/2 */ +#define LL_SPI_RX_FIFO_FULL (SPI_SR_FRLVL_1 | SPI_SR_FRLVL_0) /*!< FIFO reception full */ +/** + * @} + */ + +/** @defgroup SPI_LL_EC_TX_FIFO TX FIFO Level + * @{ + */ +#define LL_SPI_TX_FIFO_EMPTY 0x00000000U /*!< FIFO transmission empty */ +#define LL_SPI_TX_FIFO_QUARTER_FULL (SPI_SR_FTLVL_0) /*!< FIFO transmission 1/4 */ +#define LL_SPI_TX_FIFO_HALF_FULL (SPI_SR_FTLVL_1) /*!< FIFO transmission 1/2 */ +#define LL_SPI_TX_FIFO_FULL (SPI_SR_FTLVL_1 | SPI_SR_FTLVL_0) /*!< FIFO transmission full */ + +#if (defined(DMA1) || defined(DMA)) +/** @defgroup SPI_LL_EC_DMA_PARITY DMA Parity + * @{ + */ +#define LL_SPI_DMA_PARITY_EVEN 0x00000000U /*!< Select DMA parity Even */ +#define LL_SPI_DMA_PARITY_ODD 0x00000001U /*!< Select DMA parity Odd */ +#endif /* DMA1 or DMA */ + +/** + * @} + */ + +/** @defgroup SPI_LL_EC_SLAVE_SPEED_MODE SLAVE SPEED MODE + * @{ + */ +#define LL_SPI_SLAVE_SPEED_NORMAL 0x00000000U /* Slave normal mode */ +#define LL_SPI_SLAVE_SPEED_FAST SPI_CR2_SLVFM /* Slave fast mode */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Macros SPI Exported Macros + * @{ + */ + +/** @defgroup SPI_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_SPI_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in SPI register + * @param __INSTANCE__ SPI Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_SPI_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SPI_LL_Exported_Functions SPI Exported Functions + * @{ + */ + +/** @defgroup SPI_LL_EF_Configuration Configuration + * @{ + */ + +/** + * @brief Enable SPI peripheral + * @rmtoll CR1 SPE LL_SPI_Enable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Enable(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Disable SPI peripheral + * @note When disabling the SPI, follow the procedure described in the Reference Manual. + * @rmtoll CR1 SPE LL_SPI_Disable + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_Disable(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Check if SPI peripheral is enabled + * @rmtoll CR1 SPE LL_SPI_IsEnabled + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabled(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR1, SPI_CR1_SPE) == (SPI_CR1_SPE)) ? 1UL : 0UL); +} + +/** + * @brief Set SPI operation mode to Master or Slave + * @note This bit should not be changed when communication is ongoing. + * @rmtoll CR1 MSTR LL_SPI_SetMode\n + * CR1 SSI LL_SPI_SetMode + * @param SPIx SPI Instance + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetMode(SPI_TypeDef *SPIx, uint32_t Mode) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI, Mode); +} + +/** + * @brief Get SPI operation mode (Master or Slave) + * @rmtoll CR1 MSTR LL_SPI_GetMode\n + * CR1 SSI LL_SPI_GetMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_MODE_MASTER + * @arg @ref LL_SPI_MODE_SLAVE + */ +__STATIC_INLINE uint32_t LL_SPI_GetMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_MSTR | SPI_CR1_SSI)); +} + +/** + * @brief Set clock phase + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPHA LL_SPI_SetClockPhase + * @param SPIx SPI Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPhase(SPI_TypeDef *SPIx, uint32_t ClockPhase) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPHA, ClockPhase); +} + +/** + * @brief Get clock phase + * @rmtoll CR1 CPHA LL_SPI_GetClockPhase + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_PHASE_1EDGE + * @arg @ref LL_SPI_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPhase(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPHA)); +} + +/** + * @brief Set clock polarity + * @note This bit should not be changed when communication is ongoing. + * This bit is not used in SPI TI mode. + * @rmtoll CR1 CPOL LL_SPI_SetClockPolarity + * @param SPIx SPI Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetClockPolarity(SPI_TypeDef *SPIx, uint32_t ClockPolarity) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_CPOL, ClockPolarity); +} + +/** + * @brief Get clock polarity + * @rmtoll CR1 CPOL LL_SPI_GetClockPolarity + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_POLARITY_LOW + * @arg @ref LL_SPI_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_SPI_GetClockPolarity(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_CPOL)); +} + +/** + * @brief Set baud rate prescaler + * @note These bits should not be changed when communication is ongoing. SPI BaudRate = fPCLK/Prescaler. + * @rmtoll CR1 BR LL_SPI_SetBaudRatePrescaler + * @param SPIx SPI Instance + * @param BaudRate This parameter can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetBaudRatePrescaler(SPI_TypeDef *SPIx, uint32_t BaudRate) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_BR, BaudRate); +} + +/** + * @brief Get baud rate prescaler + * @rmtoll CR1 BR LL_SPI_GetBaudRatePrescaler + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV2 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV4 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV8 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV16 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV32 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV64 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV128 + * @arg @ref LL_SPI_BAUDRATEPRESCALER_DIV256 + */ +__STATIC_INLINE uint32_t LL_SPI_GetBaudRatePrescaler(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_BR)); +} + +/** + * @brief Set transfer bit order + * @note This bit should not be changed when communication is ongoing. This bit is not used in SPI TI mode. + * @rmtoll CR1 LSBFIRST LL_SPI_SetTransferBitOrder + * @param SPIx SPI Instance + * @param BitOrder This parameter can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferBitOrder(SPI_TypeDef *SPIx, uint32_t BitOrder) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_LSBFIRST, BitOrder); +} + +/** + * @brief Get transfer bit order + * @rmtoll CR1 LSBFIRST LL_SPI_GetTransferBitOrder + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_LSB_FIRST + * @arg @ref LL_SPI_MSB_FIRST + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferBitOrder(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_LSBFIRST)); +} + +/** + * @brief Set transfer direction mode + * @note For Half-Duplex mode, Rx Direction is set by default. + * In master mode, the MOSI pin is used and in slave mode, the MISO pin is used for Half-Duplex. + * @rmtoll CR1 RXONLY LL_SPI_SetTransferDirection\n + * CR1 BIDIMODE LL_SPI_SetTransferDirection\n + * CR1 BIDIOE LL_SPI_SetTransferDirection + * @param SPIx SPI Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetTransferDirection(SPI_TypeDef *SPIx, uint32_t TransferDirection) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE, TransferDirection); +} + +/** + * @brief Get transfer direction mode + * @rmtoll CR1 RXONLY LL_SPI_GetTransferDirection\n + * CR1 BIDIMODE LL_SPI_GetTransferDirection\n + * CR1 BIDIOE LL_SPI_GetTransferDirection + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_FULL_DUPLEX + * @arg @ref LL_SPI_SIMPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_RX + * @arg @ref LL_SPI_HALF_DUPLEX_TX + */ +__STATIC_INLINE uint32_t LL_SPI_GetTransferDirection(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR1, SPI_CR1_RXONLY | SPI_CR1_BIDIMODE | SPI_CR1_BIDIOE)); +} + +/** + * @brief Set frame data width + * @rmtoll CR2 DS LL_SPI_SetDataWidth + * @param SPIx SPI Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDataWidth(SPI_TypeDef *SPIx, uint32_t DataWidth) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_DS, DataWidth); +} + +/** + * @brief Get frame data width + * @rmtoll CR2 DS LL_SPI_GetDataWidth + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DATAWIDTH_8BIT + * @arg @ref LL_SPI_DATAWIDTH_16BIT + */ +__STATIC_INLINE uint32_t LL_SPI_GetDataWidth(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_DS)); +} + +/** + * @brief Set threshold of RXFIFO that triggers an RXNE event + * @rmtoll CR2 FRXTH LL_SPI_SetRxFIFOThreshold + * @param SPIx SPI Instance + * @param Threshold This parameter can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_TH_HALF + * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetRxFIFOThreshold(SPI_TypeDef *SPIx, uint32_t Threshold) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_FRXTH, Threshold); +} + +/** + * @brief Get threshold of RXFIFO that triggers an RXNE event + * @rmtoll CR2 FRXTH LL_SPI_GetRxFIFOThreshold + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_TH_HALF + * @arg @ref LL_SPI_RX_FIFO_TH_QUARTER + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOThreshold(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_FRXTH)); +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_NSS_Management Slave Select Pin Management + * @{ + */ + +/** + * @brief Set NSS mode + * @rmtoll CR1 SSM LL_SPI_SetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_SetNSSMode + * @param SPIx SPI Instance + * @param NSS This parameter can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetNSSMode(SPI_TypeDef *SPIx, uint32_t NSS) +{ + MODIFY_REG(SPIx->CR1, SPI_CR1_SSM, NSS); + MODIFY_REG(SPIx->CR2, SPI_CR2_SSOE, ((uint32_t)(NSS >> 16U))); +} + +/** + * @brief Get NSS mode + * @rmtoll CR1 SSM LL_SPI_GetNSSMode\n + * @rmtoll CR2 SSOE LL_SPI_GetNSSMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_NSS_SOFT + * @arg @ref LL_SPI_NSS_HARD_INPUT + * @arg @ref LL_SPI_NSS_HARD_OUTPUT + */ +__STATIC_INLINE uint32_t LL_SPI_GetNSSMode(SPI_TypeDef *SPIx) +{ + uint32_t Ssm = (READ_BIT(SPIx->CR1, SPI_CR1_SSM)); + uint32_t Ssoe = (READ_BIT(SPIx->CR2, SPI_CR2_SSOE) << 16U); + return (Ssm | Ssoe); +} +/** + * @} + */ + +/** @defgroup SPI_LL_EF_FLAG_Management FLAG Management + * @{ + */ + +/** + * @brief Check if Rx buffer is not empty + * @rmtoll SR RXNE LL_SPI_IsActiveFlag_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_RXNE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_RXNE) == (SPI_SR_RXNE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer is empty + * @rmtoll SR TXE LL_SPI_IsActiveFlag_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_TXE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_TXE) == (SPI_SR_TXE)) ? 1UL : 0UL); +} + + +/** + * @brief Get mode fault error flag + * @rmtoll SR MODF LL_SPI_IsActiveFlag_MODF + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_MODF(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_MODF) == (SPI_SR_MODF)) ? 1UL : 0UL); +} + +/** + * @brief Get overrun error flag + * @rmtoll SR OVR LL_SPI_IsActiveFlag_OVR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_OVR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_OVR) == (SPI_SR_OVR)) ? 1UL : 0UL); +} + +/** + * @brief Get busy flag + * @note The BSY flag is cleared under any one of the following conditions: + * -When the SPI is correctly disabled + * -When a fault is detected in Master mode (MODF bit set to 1) + * -In Master mode, when it finishes a data transmission and no new data is ready to be + * sent + * -In Slave mode, when the BSY flag is set to '0' for at least one SPI clock cycle between + * each data transfer. + * @rmtoll SR BSY LL_SPI_IsActiveFlag_BSY + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsActiveFlag_BSY(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->SR, SPI_SR_BSY) == (SPI_SR_BSY)) ? 1UL : 0UL); +} + +/** + * @brief Get FIFO reception Level + * @rmtoll SR FRLVL LL_SPI_GetRxFIFOLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_RX_FIFO_EMPTY + * @arg @ref LL_SPI_RX_FIFO_QUARTER_FULL + * @arg @ref LL_SPI_RX_FIFO_HALF_FULL + * @arg @ref LL_SPI_RX_FIFO_FULL + */ +__STATIC_INLINE uint32_t LL_SPI_GetRxFIFOLevel(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FRLVL)); +} + +/** + * @brief Get FIFO Transmission Level + * @rmtoll SR FTLVL LL_SPI_GetTxFIFOLevel + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_TX_FIFO_EMPTY + * @arg @ref LL_SPI_TX_FIFO_QUARTER_FULL + * @arg @ref LL_SPI_TX_FIFO_HALF_FULL + * @arg @ref LL_SPI_TX_FIFO_FULL + */ +__STATIC_INLINE uint32_t LL_SPI_GetTxFIFOLevel(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->SR, SPI_SR_FTLVL)); +} + +/** + * @brief Clear mode fault error flag + * @note Clearing this flag is done by a read access to the SPIx_SR + * register followed by a write access to the SPIx_CR1 register + * @rmtoll SR MODF LL_SPI_ClearFlag_MODF + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_MODF(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg_sr; + tmpreg_sr = SPIx->SR; + (void) tmpreg_sr; + CLEAR_BIT(SPIx->CR1, SPI_CR1_SPE); +} + +/** + * @brief Clear overrun error flag + * @note Clearing this flag is done by a read access to the SPIx_DR + * register followed by a read access to the SPIx_SR register + * @rmtoll SR OVR LL_SPI_ClearFlag_OVR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_ClearFlag_OVR(SPI_TypeDef *SPIx) +{ + __IO uint32_t tmpreg; + tmpreg = SPIx->DR; + (void) tmpreg; + tmpreg = SPIx->SR; + (void) tmpreg; +} + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_IT_Management Interrupt Management + * @{ + */ + +/** + * @brief Enable error interrupt + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_EnableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_ERR(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Enable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_EnableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_RXNE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Enable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_EnableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableIT_TXE(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Disable error interrupt + * @note This bit controls the generation of an interrupt when an error condition occurs (CRCERR, OVR, MODF in SPI mode, FRE at TI mode). + * @rmtoll CR2 ERRIE LL_SPI_DisableIT_ERR + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_ERR(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_ERRIE); +} + +/** + * @brief Disable Rx buffer not empty interrupt + * @rmtoll CR2 RXNEIE LL_SPI_DisableIT_RXNE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_RXNE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXNEIE); +} + +/** + * @brief Disable Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_DisableIT_TXE + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableIT_TXE(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXEIE); +} + +/** + * @brief Check if error interrupt is enabled + * @rmtoll CR2 ERRIE LL_SPI_IsEnabledIT_ERR + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_ERR(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_ERRIE) == (SPI_CR2_ERRIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Rx buffer not empty interrupt is enabled + * @rmtoll CR2 RXNEIE LL_SPI_IsEnabledIT_RXNE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_RXNE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXNEIE) == (SPI_CR2_RXNEIE)) ? 1UL : 0UL); +} + +/** + * @brief Check if Tx buffer empty interrupt + * @rmtoll CR2 TXEIE LL_SPI_IsEnabledIT_TXE + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledIT_TXE(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXEIE) == (SPI_CR2_TXEIE)) ? 1UL : 0UL); +} + +/** + * @} + */ + +#if (defined(DMA1) || defined(DMA)) +/** @defgroup SPI_LL_EF_DMA_Management DMA Management + * @{ + */ + +/** + * @brief Enable DMA Rx + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 RXDMAEN LL_SPI_EnableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_RX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Disable DMA Rx + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 RXDMAEN LL_SPI_DisableDMAReq_RX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_RX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_RXDMAEN); +} + +/** + * @brief Check if DMA Rx is enabled + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 RXDMAEN LL_SPI_IsEnabledDMAReq_RX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_RX(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_RXDMAEN) == (SPI_CR2_RXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable DMA Tx + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 TXDMAEN LL_SPI_EnableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_EnableDMAReq_TX(SPI_TypeDef *SPIx) +{ + SET_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Disable DMA Tx + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 TXDMAEN LL_SPI_DisableDMAReq_TX + * @param SPIx SPI Instance + * @retval None + */ +__STATIC_INLINE void LL_SPI_DisableDMAReq_TX(SPI_TypeDef *SPIx) +{ + CLEAR_BIT(SPIx->CR2, SPI_CR2_TXDMAEN); +} + +/** + * @brief Check if DMA Tx is enabled + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 TXDMAEN LL_SPI_IsEnabledDMAReq_TX + * @param SPIx SPI Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SPI_IsEnabledDMAReq_TX(SPI_TypeDef *SPIx) +{ + return ((READ_BIT(SPIx->CR2, SPI_CR2_TXDMAEN) == (SPI_CR2_TXDMAEN)) ? 1UL : 0UL); +} + +/** + * @brief Set parity of Last DMA reception + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 LDMARX LL_SPI_SetDMAParity_RX + * @param SPIx SPI Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDMAParity_RX(SPI_TypeDef *SPIx, uint32_t Parity) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMA_RX, (Parity << SPI_CR2_LDMA_RX_Pos)); +} + +/** + * @brief Get parity configuration for Last DMA reception + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 LDMARX LL_SPI_GetDMAParity_RX + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + */ +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_RX(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMA_RX) >> SPI_CR2_LDMA_RX_Pos); +} + +/** + * @brief Set parity of Last DMA transmission + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 LDMATX LL_SPI_SetDMAParity_TX + * @param SPIx SPI Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetDMAParity_TX(SPI_TypeDef *SPIx, uint32_t Parity) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_LDMA_TX, (Parity << SPI_CR2_LDMA_TX_Pos)); +} + +/** + * @brief Get parity configuration for Last DMA transmission + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR2 LDMATX LL_SPI_GetDMAParity_TX + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_DMA_PARITY_ODD + * @arg @ref LL_SPI_DMA_PARITY_EVEN + */ +__STATIC_INLINE uint32_t LL_SPI_GetDMAParity_TX(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_LDMA_TX) >> SPI_CR2_LDMA_TX_Pos); +} + +/** + * @brief Get the data register address used for DMA transfer + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll DR DR LL_SPI_DMA_GetRegAddr + * @param SPIx SPI Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_SPI_DMA_GetRegAddr(SPI_TypeDef *SPIx) +{ + return (uint32_t) & (SPIx->DR); +} +#endif /* DMA1 or DMA */ + +/** + * @} + */ + +/** @defgroup SPI_LL_EF_DATA_Management DATA Management + * @{ + */ + +/** + * @brief Read 8-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData8 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_SPI_ReceiveData8(SPI_TypeDef *SPIx) +{ + return (*((__IO uint8_t *)&SPIx->DR)); +} + +/** + * @brief Read 16-Bits in the data register + * @rmtoll DR DR LL_SPI_ReceiveData16 + * @param SPIx SPI Instance + * @retval RxData Value between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint16_t LL_SPI_ReceiveData16(SPI_TypeDef *SPIx) +{ + return (uint16_t)(READ_REG(SPIx->DR)); +} + +/** + * @brief Write 8-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData8 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData8(SPI_TypeDef *SPIx, uint8_t TxData) +{ +#if defined (__GNUC__) + __IO uint8_t *spidr = ((__IO uint8_t *)&SPIx->DR); + *spidr = TxData; +#else + *((__IO uint8_t *)&SPIx->DR) = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Write 16-Bits in the data register + * @rmtoll DR DR LL_SPI_TransmitData16 + * @param SPIx SPI Instance + * @param TxData Value between Min_Data=0x00 and Max_Data=0xFFFF + * @retval None + */ +__STATIC_INLINE void LL_SPI_TransmitData16(SPI_TypeDef *SPIx, uint16_t TxData) +{ +#if defined (__GNUC__) + __IO uint16_t *spidr = ((__IO uint16_t *)&SPIx->DR); + *spidr = TxData; +#else + SPIx->DR = TxData; +#endif /* __GNUC__ */ +} + +/** + * @brief Set Slave Speed Mode + * @rmtoll CR2 SLVFM LL_SPI_SetSlaveSpeedMode + * @param SPIx SPI Instance + * @param SlaveSpeedMode This parameter can be one of the following values: + * @arg @ref LL_SPI_SLAVE_SPEED_NORMAL + * @arg @ref LL_SPI_SLAVE_SPEED_FAST + * @retval None + */ +__STATIC_INLINE void LL_SPI_SetSlaveSpeedMode(SPI_TypeDef *SPIx, uint32_t SlaveSpeedMode) +{ + MODIFY_REG(SPIx->CR2, SPI_CR2_SLVFM, SlaveSpeedMode); +} + +/** + * @brief Get Slave Speed Mode + * @rmtoll CR2 SLVFM LL_SPI_GetSlaveSpeedMode + * @param SPIx SPI Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_SPI_SLAVE_SPEED_NORMAL + * @arg @ref LL_SPI_SLAVE_SPEED_FAST + */ +__STATIC_INLINE uint32_t LL_SPI_GetSlaveSpeedMode(SPI_TypeDef *SPIx) +{ + return (uint32_t)(READ_BIT(SPIx->CR2, SPI_CR2_SLVFM)); +} + +/** + * @} + */ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup SPI_LL_EF_Init Initialization and de-initialization functions + * @{ + */ + +ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx); +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct); +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct); + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ +/** + * @} + */ + +/** + * @} + */ +#endif /* defined (SPI1) || defined (SPI2) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PY32F0xx_LL_SPI_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_system.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_system.h similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_system.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_system.h index 4237215..94fb79f 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_system.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_system.h @@ -1,968 +1,968 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_system.h - * @author MCU Application Team - * @brief Header file of SYSTEM LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef PY32F0XX_LL_SYSTEM_H -#define PY32F0XX_LL_SYSTEM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0XX_LL_Driver - * @{ - */ - -#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) - -/** @defgroup SYSTEM_LL SYSTEM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants - * @{ - */ - -/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP - * @{ - */ -#define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ -#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ -#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */ -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_I2C_ANF I2C ANALOG FILTER ENABLE CONTORL - * @{ - */ -#if defined(SYSCFG_CFGR1_I2C_PA2_ANF) -#define LL_SYSCFG_I2C_ANF_PA2 SYSCFG_CFGR1_I2C_PA2_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PA3_ANF) -#define LL_SYSCFG_I2C_ANF_PA3 SYSCFG_CFGR1_I2C_PA3_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PA7_ANF) -#define LL_SYSCFG_I2C_ANF_PA7 SYSCFG_CFGR1_I2C_PA7_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PA8_ANF) -#define LL_SYSCFG_I2C_ANF_PA8 SYSCFG_CFGR1_I2C_PA8_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PA9_ANF) -#define LL_SYSCFG_I2C_ANF_PA9 SYSCFG_CFGR1_I2C_PA9_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PA10_ANF) -#define LL_SYSCFG_I2C_ANF_PA10 SYSCFG_CFGR1_I2C_PA10_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PA11_ANF) -#define LL_SYSCFG_I2C_ANF_PA11 SYSCFG_CFGR1_I2C_PA11_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PA12_ANF) -#define LL_SYSCFG_I2C_ANF_PA12 SYSCFG_CFGR1_I2C_PA12_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PB6_ANF) -#define LL_SYSCFG_I2C_ANF_PB6 SYSCFG_CFGR1_I2C_PB6_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PB7_ANF) -#define LL_SYSCFG_I2C_ANF_PB7 SYSCFG_CFGR1_I2C_PB7_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PB8_ANF) -#define LL_SYSCFG_I2C_ANF_PB8 SYSCFG_CFGR1_I2C_PB8_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PF0_ANF) -#define LL_SYSCFG_I2C_ANF_PF0 SYSCFG_CFGR1_I2C_PF0_ANF -#endif -#if defined(SYSCFG_CFGR1_I2C_PF1_ANF) -#define LL_SYSCFG_I2C_ANF_PF1 SYSCFG_CFGR1_I2C_PF1_ANF -#endif -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_TIMBREAK TIMER BREAK INPUT - * @{ - */ -#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) -#define LL_SYSCFG_TIMBREAK_LOCKUP_TO_ALL SYSCFG_CFGR2_LOCKUP_LOCK -#endif -#if defined(SYSCFG_CFGR2_PVD_LOCK) -#define LL_SYSCFG_TIMBREAK_PVD_TO_ALL SYSCFG_CFGR2_PVD_LOCK -#endif -#if defined(SYSCFG_CFGR2_COMP1_BRK_TIM1) -#define LL_SYSCFG_TIMBREAK_COMP1_TO_TIM1 SYSCFG_CFGR2_COMP1_BRK_TIM1 -#endif -#if defined(SYSCFG_CFGR2_COMP2_BRK_TIM1) -#define LL_SYSCFG_TIMBREAK_COMP2_TO_TIM1 SYSCFG_CFGR2_COMP2_BRK_TIM1 -#endif -#if defined(SYSCFG_CFGR2_COMP1_BRK_TIM16) -#define LL_SYSCFG_TIMBREAK_COMP1_TO_TIM16 SYSCFG_CFGR2_COMP1_BRK_TIM16 -#endif -#if defined(SYSCFG_CFGR2_COMP2_BRK_TIM16) -#define LL_SYSCFG_TIMBREAK_COMP2_TO_TIM16 SYSCFG_CFGR2_COMP2_BRK_TIM16 -#endif -#if defined(SYSCFG_CFGR2_COMP1_BRK_TIM17) -#define LL_SYSCFG_TIMBREAK_COMP1_TO_TIM17 SYSCFG_CFGR2_COMP1_BRK_TIM17 -#endif -#if defined(SYSCFG_CFGR2_COMP2_BRK_TIM17) -#define LL_SYSCFG_TIMBREAK_COMP2_TO_TIM17 SYSCFG_CFGR2_COMP2_BRK_TIM17 -#endif -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_ETR_SRC ETR SOURCE - */ -#define LL_SYSCFG_ETR_SRC_TIM1_GPIO 0x00000000U -#if defined(COMP1) -#define LL_SYSCFG_ETR_SRC_TIM1_COMP1 SYSCFG_CFGR2_ETR_SRC_TIM1_0 -#endif -#if defined(COMP2) -#define LL_SYSCFG_ETR_SRC_TIM1_COMP2 SYSCFG_CFGR2_ETR_SRC_TIM1_1 -#endif -#define LL_SYSCFG_ETR_SRC_TIM1_ADC (SYSCFG_CFGR2_ETR_SRC_TIM1_1 | SYSCFG_CFGR2_ETR_SRC_TIM1_0) -/** - * @} - */ - -#if (defined(DMA) || defined(DMA1)) -/** @defgroup SYSTEM_LL_EC_DMA_MAP DMA MAP - */ -#define LL_SYSCFG_DMA_MAP_ADC 0x00000000U -#define LL_SYSCFG_DMA_MAP_SPI1_TX SYSCFG_CFGR3_DMA1_MAP_0 -#define LL_SYSCFG_DMA_MAP_SPI1_RX SYSCFG_CFGR3_DMA1_MAP_1 -#define LL_SYSCFG_DMA_MAP_SPI2_TX (SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_SPI2_RX SYSCFG_CFGR3_DMA1_MAP_2 -#define LL_SYSCFG_DMA_MAP_USART1_TX (SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_USART1_RX (SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_1) -#define LL_SYSCFG_DMA_MAP_USART2_TX (SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_USART2_RX SYSCFG_CFGR3_DMA1_MAP_3 -#define LL_SYSCFG_DMA_MAP_I2C_TX (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_I2C_RX (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_1) -#define LL_SYSCFG_DMA_MAP_TIM1_CH1 (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_TIM1_CH2 (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_2) -#define LL_SYSCFG_DMA_MAP_TIM1_CH3 (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_TIM1_CH4 (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_1) -#define LL_SYSCFG_DMA_MAP_TIM1_COM (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_TIM1_UP SYSCFG_CFGR3_DMA1_MAP_4 -#define LL_SYSCFG_DMA_MAP_TIM1_TRIG (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_TIM3_CH1 (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_1) -#define LL_SYSCFG_DMA_MAP_TIM3_CH3 (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_TIM3_CH4 (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_2) -#define LL_SYSCFG_DMA_MAP_TIM3_TRG (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_TIM3_UP (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_1) -#define LL_SYSCFG_DMA_MAP_TIM16_CH1 (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_3) -#define LL_SYSCFG_DMA_MAP_TIM16_UP (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_0) -#define LL_SYSCFG_DMA_MAP_TIM17_CH1 (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_1) -#define LL_SYSCFG_DMA_MAP_TIM17_UP (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_DMA_ACKLVL DMA SPEED ENABLE - */ -#define LL_SYSCFG_DMA_ACKLVL_NORM 0x00000000U -#define LL_SYSCFG_DMA_ACKLVL_FAST SYSCFG_CFGR3_DMA1_ACKLVL -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_DMA_CHNNEL_SHIFT DMA CHNNEL SHIFT ADDRESS - */ -#define LL_SYSCFG_DMA_CH2_SHIFT (8U) -#define LL_SYSCFG_DMA_CH3_SHIFT (16U) -/** - * @} - */ -#endif - -/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY - * @{ - */ -#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ -#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ -/** - * @} - */ - - -/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP - * @{ - */ -#if defined(DBGMCU_APB_FZ1_DBG_TIM3_STOP) -#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB_FZ1_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ -#endif -#if defined(DBGMCU_APB_FZ1_DBG_RTC_STOP) -#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB_FZ1_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */ -#endif -#if defined(DBGMCU_APB_FZ1_DBG_WWDG_STOP) -#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB_FZ1_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ -#endif -#if defined(DBGMCU_APB_FZ1_DBG_IWDG_STOP) -#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB_FZ1_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ -#endif -#if defined(DBGMCU_APB_FZ1_DBG_LPTIM_STOP) -#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB_FZ1_DBG_LPTIM_STOP /*!< LPTIM1 counter stopped when Core is halted */ -#endif -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP - * @{ - */ -#if defined(DBGMCU_APB_FZ2_DBG_TIM1_STOP) -#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB_FZ2_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ -#endif -#if defined(DBGMCU_APB_FZ2_DBG_TIM14_STOP) -#define LL_DBGMCU_APB1_GRP2_TIM14_STOP DBGMCU_APB_FZ2_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ -#endif -#if defined(DBGMCU_APB_FZ2_DBG_TIM16_STOP) -#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB_FZ2_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ -#endif -#if defined(DBGMCU_APB_FZ2_DBG_TIM17_STOP) -#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB_FZ2_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ -#endif -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions - * @{ - */ - -/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG - * @{ - */ - -/** - * @brief Set memory mapping at address 0x00000000 - * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory - * @param Memory This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_REMAP_FLASH - * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH - * @arg @ref LL_SYSCFG_REMAP_SRAM - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) -{ - MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); -} - -/** - * @brief Get memory mapping at address 0x00000000 - * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_REMAP_FLASH - * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH - * @arg @ref LL_SYSCFG_REMAP_SRAM - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); -} - -/** - * @brief Enable analog filtering of I2C related IO - * @note Depending on devices and packages, some IOs may not be available. - * Refer to device datasheet for IOs availability. - * @param I2CAnalogFilter This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_ANF_PA2 - * @arg @ref LL_SYSCFG_I2C_ANF_PA3 - * @arg @ref LL_SYSCFG_I2C_ANF_PA7 - * @arg @ref LL_SYSCFG_I2C_ANF_PA8 - * @arg @ref LL_SYSCFG_I2C_ANF_PA9 - * @arg @ref LL_SYSCFG_I2C_ANF_PA10 - * @arg @ref LL_SYSCFG_I2C_ANF_PA11 - * @arg @ref LL_SYSCFG_I2C_ANF_PA12 - * @arg @ref LL_SYSCFG_I2C_ANF_PB6 - * @arg @ref LL_SYSCFG_I2C_ANF_PB7 - * @arg @ref LL_SYSCFG_I2C_ANF_PB8 - * @arg @ref LL_SYSCFG_I2C_ANF_PF0 - * @arg @ref LL_SYSCFG_I2C_ANF_PF1 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableI2CAnalogFilter(uint32_t I2CAnalogFilter) -{ - SET_BIT(SYSCFG->CFGR1, I2CAnalogFilter); -} - -/** - * @brief Disable analog filtering of I2C related IO - * @note Depending on devices and packages, some IOs may not be available. - * Refer to device datasheet for IOs availability. - * @param I2CAnalogFilter This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_I2C_ANF_PA2 - * @arg @ref LL_SYSCFG_I2C_ANF_PA3 - * @arg @ref LL_SYSCFG_I2C_ANF_PA7 - * @arg @ref LL_SYSCFG_I2C_ANF_PA8 - * @arg @ref LL_SYSCFG_I2C_ANF_PA9 - * @arg @ref LL_SYSCFG_I2C_ANF_PA10 - * @arg @ref LL_SYSCFG_I2C_ANF_PA11 - * @arg @ref LL_SYSCFG_I2C_ANF_PA12 - * @arg @ref LL_SYSCFG_I2C_ANF_PB6 - * @arg @ref LL_SYSCFG_I2C_ANF_PB7 - * @arg @ref LL_SYSCFG_I2C_ANF_PB8 - * @arg @ref LL_SYSCFG_I2C_ANF_PF0 - * @arg @ref LL_SYSCFG_I2C_ANF_PF1 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableI2CAnalogFilter(uint32_t I2CAnalogFilter) -{ - CLEAR_BIT(SYSCFG->CFGR1, I2CAnalogFilter); -} - -/** - * @brief Indicate if enable analog filtering of I2C related IO - * @note Depending on devices and packages, some IOs may not be available. - * Refer to device datasheet for IOs availability. - * @param I2CAnalogFilter This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_I2C_ANF_PA2 - * @arg @ref LL_SYSCFG_I2C_ANF_PA3 - * @arg @ref LL_SYSCFG_I2C_ANF_PA7 - * @arg @ref LL_SYSCFG_I2C_ANF_PA8 - * @arg @ref LL_SYSCFG_I2C_ANF_PA9 - * @arg @ref LL_SYSCFG_I2C_ANF_PA10 - * @arg @ref LL_SYSCFG_I2C_ANF_PA11 - * @arg @ref LL_SYSCFG_I2C_ANF_PA12 - * @arg @ref LL_SYSCFG_I2C_ANF_PB6 - * @arg @ref LL_SYSCFG_I2C_ANF_PB7 - * @arg @ref LL_SYSCFG_I2C_ANF_PB8 - * @arg @ref LL_SYSCFG_I2C_ANF_PF0 - * @arg @ref LL_SYSCFG_I2C_ANF_PF1 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledI2CAnalogFilter(uint32_t I2CAnalogFilter) -{ - return ((READ_BIT(SYSCFG->CFGR1, I2CAnalogFilter) == (I2CAnalogFilter)) ? 1UL : 0UL); -} - -/** - * @brief Enables COMPx as TIMx break input - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @param TIMBreakInputs This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP_TO_ALL - * @arg @ref LL_SYSCFG_TIMBREAK_PVD_TO_ALL - * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM1 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM1 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM16 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM16 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM17 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM17 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_EnableTIMBreakInputs(uint32_t TIMBreakInputs) -{ - SET_BIT(SYSCFG->CFGR2, TIMBreakInputs); -} - -/** - * @brief Disables COMPx as TIMx break input - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @param TIMBreakInputs This parameter can be a combination of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP_TO_ALL - * @arg @ref LL_SYSCFG_TIMBREAK_PVD_TO_ALL - * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM1 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM1 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM16 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM16 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM17 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM17 - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_DisableTIMBreakInputs(uint32_t TIMBreakInputs) -{ - CLEAR_BIT(SYSCFG->CFGR2, TIMBreakInputs); -} - -/** - * @brief Indicate if COMPx as TIMx break input - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @param TIMBreakInputs This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP_TO_ALL - * @arg @ref LL_SYSCFG_TIMBREAK_PVD_TO_ALL - * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM1 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM1 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM16 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM16 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM17 - * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM17 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledTIMBreakInputs(uint32_t TIMBreakInputs) -{ - return ((READ_BIT(SYSCFG->CFGR2, TIMBreakInputs) == (TIMBreakInputs)) ? 1UL : 0UL); -} - -/** - * @brief Set the TIMER1 ETR input source - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @param source This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_GPIO - * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_COMP1 - * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_COMP2 - * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_ADC - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetTIM1ETRSource(uint32_t source) -{ - MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_ETR_SRC_TIM1, source); -} - -/** - * @brief Get the TIMER1 ETR input source - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_GPIO - * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_COMP1 - * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_COMP2 - * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_ADC - * @retval None - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetTIM1ETRSource(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ETR_SRC_TIM1)); -} - -#if (defined(DMA) || defined(DMA1)) -/** - * @brief Set the request image for DMA channel 1 - * @param Requset This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_MAP_ADC - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetDMARemap_CH1(uint32_t Requset) -{ - MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA1_MAP_Msk, Requset); -} - -/** - * @brief Gett the request image for DMA channel 1 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_MAP_ADC - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetDMARemap_CH1(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA1_MAP_Msk)); -} - -/** - * @brief Set the response speed of DMA channel 1 - * @param Requset This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM - * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetDMAResponseSpeed_CH1(uint32_t ResponseSpeed) -{ - MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA1_ACKLVL, ResponseSpeed); -} - -/** - * @brief Get the response speed of DMA channel 1 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM - * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetDMAResponseSpeed_CH1(void) -{ - return (uint32_t)(READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA1_ACKLVL)); -} - - -/** - * @brief Set the request image for DMA channel 2 - * @param Requset This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_MAP_ADC - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetDMARemap_CH2(uint32_t Requset) -{ - MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA2_MAP_Msk, (Requset << LL_SYSCFG_DMA_CH2_SHIFT)); -} - -/** - * @brief Gett the request image for DMA channel 2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_MAP_ADC - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetDMARemap_CH2(void) -{ - return (uint32_t)((READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA2_MAP_Msk)) >> LL_SYSCFG_DMA_CH2_SHIFT); -} - -/** - * @brief Set the response speed of DMA channel 2 - * @param Requset This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM - * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetDMAResponseSpeed_CH2(uint32_t ResponseSpeed) -{ - MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA2_ACKLVL, (ResponseSpeed << LL_SYSCFG_DMA_CH2_SHIFT)); -} - -/** - * @brief Get the response speed of DMA channel 2 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM - * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetDMAResponseSpeed_CH2(void) -{ - return (uint32_t)((READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA2_ACKLVL)) >> LL_SYSCFG_DMA_CH2_SHIFT); -} - -/** - * @brief Set the request image for DMA channel 3 - * @param Requset This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_MAP_ADC - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetDMARemap_CH3(uint32_t Requset) -{ - MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA3_MAP_Msk, (Requset << LL_SYSCFG_DMA_CH3_SHIFT)); -} - -/** - * @brief Gett the request image for DMA channel 3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_MAP_ADC - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX - * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX - * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG - * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 - * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetDMARemap_CH3(void) -{ - return (uint32_t)((READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA3_MAP_Msk)) >> LL_SYSCFG_DMA_CH3_SHIFT); -} - -/** - * @brief Set the response speed of DMA channel 3 - * @param Requset This parameter can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM - * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST - * @retval None - */ -__STATIC_INLINE void LL_SYSCFG_SetDMAResponseSpeed_CH3(uint32_t ResponseSpeed) -{ - MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA3_ACKLVL, (ResponseSpeed << LL_SYSCFG_DMA_CH3_SHIFT)); -} - -/** - * @brief Get the response speed of DMA channel 3 - * @retval Returned value can be one of the following values: - * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM - * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST - */ -__STATIC_INLINE uint32_t LL_SYSCFG_GetDMAResponseSpeed_CH3(void) -{ - return (uint32_t)((READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA3_ACKLVL)) >> LL_SYSCFG_DMA_CH3_SHIFT); -} -#endif - -/** - * @} - */ - -/** @defgroup SYSTEM_LL_EF_FLASH FLASH - * @{ - */ - -/** - * @brief Set FLASH Latency - * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_SetLatency - * @param Latency This parameter can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - * @retval None - */ -__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) -{ - MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); -} - -/** - * @brief Get FLASH Latency - * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_GetLatency - * @retval Returned value can be one of the following values: - * @arg @ref LL_FLASH_LATENCY_0 - * @arg @ref LL_FLASH_LATENCY_1 - */ -__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) -{ - return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); -} - -/** - * @} - */ - -/** - * @} - */ - - -/** - * @brief Return the device identifier - * @retval Values between Min_Data=0x00 and Max_Data=0xFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); -} - -/** - * @brief Return the device revision identifier - * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF - */ -__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) -{ - return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); -} - - -/** - * @brief Enable the Debug Module during STOP mode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) -{ - SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Disable the Debug Module during STOP mode - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) -{ - CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); -} - -/** - * @brief Indicate if enable the Debug Module during STOP mode - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGStopMode(void) -{ - return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP) == (DBGMCU_CR_DBG_STOP)) ? 1UL : 0UL); -} -/** - * @brief Freeze APB1 peripherals (group1 peripherals) - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APBFZ1, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals (group1 peripherals) - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APBFZ1, Periphs); -} - -/** - * @brief Indicate if Freeze APB1 peripherals (group1 peripherals) - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @param Periphs This parameter can be one of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP - * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DBGMCU_APB1_GRP1_IsFreezePeriph(uint32_t Periphs) -{ - return ((READ_BIT(DBGMCU->APBFZ1, Periphs) == (Periphs)) ? 1UL : 0UL); -} - -/** - * @brief Freeze APB1 peripherals(group2 peripherals) - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) -{ - SET_BIT(DBGMCU->APBFZ2, Periphs); -} - -/** - * @brief Unfreeze APB1 peripherals(group2 peripherals) - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @param Periphs This parameter can be a combination of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP - * @retval None - */ -__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) -{ - CLEAR_BIT(DBGMCU->APBFZ2, Periphs); -} - -/** - * @brief Indicate if Freeze APB1 peripherals (group2 peripherals) - * @note Depending on devices and packages, some Peripherals may not be available. - * Refer to device datasheet for Peripherals availability. - * @param Periphs This parameter can be one of the following values: - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP - * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_DBGMCU_APB1_GRP2_IsFreezePeriph(uint32_t Periphs) -{ - return ((READ_BIT(DBGMCU->APBFZ2, Periphs) == (Periphs)) ? 1UL : 0UL); -} -/** - * @} - */ - -#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* PY32F0XX_LL_SYSTEM_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_system.h + * @author MCU Application Team + * @brief Header file of SYSTEM LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef PY32F0XX_LL_SYSTEM_H +#define PY32F0XX_LL_SYSTEM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0XX_LL_Driver + * @{ + */ + +#if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) + +/** @defgroup SYSTEM_LL SYSTEM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants + * @{ + */ + +/** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP + * @{ + */ +#define LL_SYSCFG_REMAP_FLASH 0x00000000U /*!< Main Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_CFGR1_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SRAM (SYSCFG_CFGR1_MEM_MODE_1 | SYSCFG_CFGR1_MEM_MODE_0) /*!< Embedded SRAM mapped at 0x00000000 */ +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_I2C_ANF I2C ANALOG FILTER ENABLE CONTORL + * @{ + */ +#if defined(SYSCFG_CFGR1_I2C_PA2_ANF) +#define LL_SYSCFG_I2C_ANF_PA2 SYSCFG_CFGR1_I2C_PA2_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PA3_ANF) +#define LL_SYSCFG_I2C_ANF_PA3 SYSCFG_CFGR1_I2C_PA3_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PA7_ANF) +#define LL_SYSCFG_I2C_ANF_PA7 SYSCFG_CFGR1_I2C_PA7_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PA8_ANF) +#define LL_SYSCFG_I2C_ANF_PA8 SYSCFG_CFGR1_I2C_PA8_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PA9_ANF) +#define LL_SYSCFG_I2C_ANF_PA9 SYSCFG_CFGR1_I2C_PA9_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PA10_ANF) +#define LL_SYSCFG_I2C_ANF_PA10 SYSCFG_CFGR1_I2C_PA10_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PA11_ANF) +#define LL_SYSCFG_I2C_ANF_PA11 SYSCFG_CFGR1_I2C_PA11_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PA12_ANF) +#define LL_SYSCFG_I2C_ANF_PA12 SYSCFG_CFGR1_I2C_PA12_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PB6_ANF) +#define LL_SYSCFG_I2C_ANF_PB6 SYSCFG_CFGR1_I2C_PB6_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PB7_ANF) +#define LL_SYSCFG_I2C_ANF_PB7 SYSCFG_CFGR1_I2C_PB7_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PB8_ANF) +#define LL_SYSCFG_I2C_ANF_PB8 SYSCFG_CFGR1_I2C_PB8_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PF0_ANF) +#define LL_SYSCFG_I2C_ANF_PF0 SYSCFG_CFGR1_I2C_PF0_ANF +#endif +#if defined(SYSCFG_CFGR1_I2C_PF1_ANF) +#define LL_SYSCFG_I2C_ANF_PF1 SYSCFG_CFGR1_I2C_PF1_ANF +#endif +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_TIMBREAK TIMER BREAK INPUT + * @{ + */ +#if defined(SYSCFG_CFGR2_LOCKUP_LOCK) +#define LL_SYSCFG_TIMBREAK_LOCKUP_TO_ALL SYSCFG_CFGR2_LOCKUP_LOCK +#endif +#if defined(SYSCFG_CFGR2_PVD_LOCK) +#define LL_SYSCFG_TIMBREAK_PVD_TO_ALL SYSCFG_CFGR2_PVD_LOCK +#endif +#if defined(SYSCFG_CFGR2_COMP1_BRK_TIM1) +#define LL_SYSCFG_TIMBREAK_COMP1_TO_TIM1 SYSCFG_CFGR2_COMP1_BRK_TIM1 +#endif +#if defined(SYSCFG_CFGR2_COMP2_BRK_TIM1) +#define LL_SYSCFG_TIMBREAK_COMP2_TO_TIM1 SYSCFG_CFGR2_COMP2_BRK_TIM1 +#endif +#if defined(SYSCFG_CFGR2_COMP1_BRK_TIM16) +#define LL_SYSCFG_TIMBREAK_COMP1_TO_TIM16 SYSCFG_CFGR2_COMP1_BRK_TIM16 +#endif +#if defined(SYSCFG_CFGR2_COMP2_BRK_TIM16) +#define LL_SYSCFG_TIMBREAK_COMP2_TO_TIM16 SYSCFG_CFGR2_COMP2_BRK_TIM16 +#endif +#if defined(SYSCFG_CFGR2_COMP1_BRK_TIM17) +#define LL_SYSCFG_TIMBREAK_COMP1_TO_TIM17 SYSCFG_CFGR2_COMP1_BRK_TIM17 +#endif +#if defined(SYSCFG_CFGR2_COMP2_BRK_TIM17) +#define LL_SYSCFG_TIMBREAK_COMP2_TO_TIM17 SYSCFG_CFGR2_COMP2_BRK_TIM17 +#endif +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_ETR_SRC ETR SOURCE + */ +#define LL_SYSCFG_ETR_SRC_TIM1_GPIO 0x00000000U +#if defined(COMP1) +#define LL_SYSCFG_ETR_SRC_TIM1_COMP1 SYSCFG_CFGR2_ETR_SRC_TIM1_0 +#endif +#if defined(COMP2) +#define LL_SYSCFG_ETR_SRC_TIM1_COMP2 SYSCFG_CFGR2_ETR_SRC_TIM1_1 +#endif +#define LL_SYSCFG_ETR_SRC_TIM1_ADC (SYSCFG_CFGR2_ETR_SRC_TIM1_1 | SYSCFG_CFGR2_ETR_SRC_TIM1_0) +/** + * @} + */ + +#if (defined(DMA) || defined(DMA1)) +/** @defgroup SYSTEM_LL_EC_DMA_MAP DMA MAP + */ +#define LL_SYSCFG_DMA_MAP_ADC 0x00000000U +#define LL_SYSCFG_DMA_MAP_SPI1_TX SYSCFG_CFGR3_DMA1_MAP_0 +#define LL_SYSCFG_DMA_MAP_SPI1_RX SYSCFG_CFGR3_DMA1_MAP_1 +#define LL_SYSCFG_DMA_MAP_SPI2_TX (SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_SPI2_RX SYSCFG_CFGR3_DMA1_MAP_2 +#define LL_SYSCFG_DMA_MAP_USART1_TX (SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_USART1_RX (SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_1) +#define LL_SYSCFG_DMA_MAP_USART2_TX (SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_USART2_RX SYSCFG_CFGR3_DMA1_MAP_3 +#define LL_SYSCFG_DMA_MAP_I2C_TX (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_I2C_RX (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_1) +#define LL_SYSCFG_DMA_MAP_TIM1_CH1 (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_TIM1_CH2 (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_2) +#define LL_SYSCFG_DMA_MAP_TIM1_CH3 (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_TIM1_CH4 (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_1) +#define LL_SYSCFG_DMA_MAP_TIM1_COM (SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_TIM1_UP SYSCFG_CFGR3_DMA1_MAP_4 +#define LL_SYSCFG_DMA_MAP_TIM1_TRIG (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_TIM3_CH1 (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_1) +#define LL_SYSCFG_DMA_MAP_TIM3_CH3 (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_TIM3_CH4 (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_2) +#define LL_SYSCFG_DMA_MAP_TIM3_TRG (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_TIM3_UP (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_2 | SYSCFG_CFGR3_DMA1_MAP_1) +#define LL_SYSCFG_DMA_MAP_TIM16_CH1 (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_3) +#define LL_SYSCFG_DMA_MAP_TIM16_UP (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_0) +#define LL_SYSCFG_DMA_MAP_TIM17_CH1 (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_1) +#define LL_SYSCFG_DMA_MAP_TIM17_UP (SYSCFG_CFGR3_DMA1_MAP_4 | SYSCFG_CFGR3_DMA1_MAP_3 | SYSCFG_CFGR3_DMA1_MAP_1 | SYSCFG_CFGR3_DMA1_MAP_0) +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_DMA_ACKLVL DMA SPEED ENABLE + */ +#define LL_SYSCFG_DMA_ACKLVL_NORM 0x00000000U +#define LL_SYSCFG_DMA_ACKLVL_FAST SYSCFG_CFGR3_DMA1_ACKLVL +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_DMA_CHNNEL_SHIFT DMA CHNNEL SHIFT ADDRESS + */ +#define LL_SYSCFG_DMA_CH2_SHIFT (8U) +#define LL_SYSCFG_DMA_CH3_SHIFT (16U) +/** + * @} + */ +#endif + +/** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY + * @{ + */ +#define LL_FLASH_LATENCY_0 0x00000000U /*!< FLASH Zero Latency cycle */ +#define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY /*!< FLASH One Latency cycle */ +/** + * @} + */ + + +/** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP + * @{ + */ +#if defined(DBGMCU_APB_FZ1_DBG_TIM3_STOP) +#define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB_FZ1_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */ +#endif +#if defined(DBGMCU_APB_FZ1_DBG_RTC_STOP) +#define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB_FZ1_DBG_RTC_STOP /*!< RTC Calendar frozen when core is halted */ +#endif +#if defined(DBGMCU_APB_FZ1_DBG_WWDG_STOP) +#define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB_FZ1_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */ +#endif +#if defined(DBGMCU_APB_FZ1_DBG_IWDG_STOP) +#define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB_FZ1_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */ +#endif +#if defined(DBGMCU_APB_FZ1_DBG_LPTIM_STOP) +#define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB_FZ1_DBG_LPTIM_STOP /*!< LPTIM1 counter stopped when Core is halted */ +#endif +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP + * @{ + */ +#if defined(DBGMCU_APB_FZ2_DBG_TIM1_STOP) +#define LL_DBGMCU_APB1_GRP2_TIM1_STOP DBGMCU_APB_FZ2_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */ +#endif +#if defined(DBGMCU_APB_FZ2_DBG_TIM14_STOP) +#define LL_DBGMCU_APB1_GRP2_TIM14_STOP DBGMCU_APB_FZ2_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */ +#endif +#if defined(DBGMCU_APB_FZ2_DBG_TIM16_STOP) +#define LL_DBGMCU_APB1_GRP2_TIM16_STOP DBGMCU_APB_FZ2_DBG_TIM16_STOP /*!< TIM16 counter stopped when core is halted */ +#endif +#if defined(DBGMCU_APB_FZ2_DBG_TIM17_STOP) +#define LL_DBGMCU_APB1_GRP2_TIM17_STOP DBGMCU_APB_FZ2_DBG_TIM17_STOP /*!< TIM17 counter stopped when core is halted */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions + * @{ + */ + +/** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG + * @{ + */ + +/** + * @brief Set memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_SetRemapMemory + * @param Memory This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetRemapMemory(uint32_t Memory) +{ + MODIFY_REG(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE, Memory); +} + +/** + * @brief Get memory mapping at address 0x00000000 + * @rmtoll SYSCFG_CFGR1 MEM_MODE LL_SYSCFG_GetRemapMemory + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_REMAP_FLASH + * @arg @ref LL_SYSCFG_REMAP_SYSTEMFLASH + * @arg @ref LL_SYSCFG_REMAP_SRAM + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetRemapMemory(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR1, SYSCFG_CFGR1_MEM_MODE)); +} + +/** + * @brief Enable analog filtering of I2C related IO + * @note Depending on devices and packages, some IOs may not be available. + * Refer to device datasheet for IOs availability. + * @param I2CAnalogFilter This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_ANF_PA2 + * @arg @ref LL_SYSCFG_I2C_ANF_PA3 + * @arg @ref LL_SYSCFG_I2C_ANF_PA7 + * @arg @ref LL_SYSCFG_I2C_ANF_PA8 + * @arg @ref LL_SYSCFG_I2C_ANF_PA9 + * @arg @ref LL_SYSCFG_I2C_ANF_PA10 + * @arg @ref LL_SYSCFG_I2C_ANF_PA11 + * @arg @ref LL_SYSCFG_I2C_ANF_PA12 + * @arg @ref LL_SYSCFG_I2C_ANF_PB6 + * @arg @ref LL_SYSCFG_I2C_ANF_PB7 + * @arg @ref LL_SYSCFG_I2C_ANF_PB8 + * @arg @ref LL_SYSCFG_I2C_ANF_PF0 + * @arg @ref LL_SYSCFG_I2C_ANF_PF1 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableI2CAnalogFilter(uint32_t I2CAnalogFilter) +{ + SET_BIT(SYSCFG->CFGR1, I2CAnalogFilter); +} + +/** + * @brief Disable analog filtering of I2C related IO + * @note Depending on devices and packages, some IOs may not be available. + * Refer to device datasheet for IOs availability. + * @param I2CAnalogFilter This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_I2C_ANF_PA2 + * @arg @ref LL_SYSCFG_I2C_ANF_PA3 + * @arg @ref LL_SYSCFG_I2C_ANF_PA7 + * @arg @ref LL_SYSCFG_I2C_ANF_PA8 + * @arg @ref LL_SYSCFG_I2C_ANF_PA9 + * @arg @ref LL_SYSCFG_I2C_ANF_PA10 + * @arg @ref LL_SYSCFG_I2C_ANF_PA11 + * @arg @ref LL_SYSCFG_I2C_ANF_PA12 + * @arg @ref LL_SYSCFG_I2C_ANF_PB6 + * @arg @ref LL_SYSCFG_I2C_ANF_PB7 + * @arg @ref LL_SYSCFG_I2C_ANF_PB8 + * @arg @ref LL_SYSCFG_I2C_ANF_PF0 + * @arg @ref LL_SYSCFG_I2C_ANF_PF1 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableI2CAnalogFilter(uint32_t I2CAnalogFilter) +{ + CLEAR_BIT(SYSCFG->CFGR1, I2CAnalogFilter); +} + +/** + * @brief Indicate if enable analog filtering of I2C related IO + * @note Depending on devices and packages, some IOs may not be available. + * Refer to device datasheet for IOs availability. + * @param I2CAnalogFilter This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_I2C_ANF_PA2 + * @arg @ref LL_SYSCFG_I2C_ANF_PA3 + * @arg @ref LL_SYSCFG_I2C_ANF_PA7 + * @arg @ref LL_SYSCFG_I2C_ANF_PA8 + * @arg @ref LL_SYSCFG_I2C_ANF_PA9 + * @arg @ref LL_SYSCFG_I2C_ANF_PA10 + * @arg @ref LL_SYSCFG_I2C_ANF_PA11 + * @arg @ref LL_SYSCFG_I2C_ANF_PA12 + * @arg @ref LL_SYSCFG_I2C_ANF_PB6 + * @arg @ref LL_SYSCFG_I2C_ANF_PB7 + * @arg @ref LL_SYSCFG_I2C_ANF_PB8 + * @arg @ref LL_SYSCFG_I2C_ANF_PF0 + * @arg @ref LL_SYSCFG_I2C_ANF_PF1 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledI2CAnalogFilter(uint32_t I2CAnalogFilter) +{ + return ((READ_BIT(SYSCFG->CFGR1, I2CAnalogFilter) == (I2CAnalogFilter)) ? 1UL : 0UL); +} + +/** + * @brief Enables COMPx as TIMx break input + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @param TIMBreakInputs This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP_TO_ALL + * @arg @ref LL_SYSCFG_TIMBREAK_PVD_TO_ALL + * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM1 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM1 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM16 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM16 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM17 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_EnableTIMBreakInputs(uint32_t TIMBreakInputs) +{ + SET_BIT(SYSCFG->CFGR2, TIMBreakInputs); +} + +/** + * @brief Disables COMPx as TIMx break input + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @param TIMBreakInputs This parameter can be a combination of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP_TO_ALL + * @arg @ref LL_SYSCFG_TIMBREAK_PVD_TO_ALL + * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM1 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM1 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM16 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM16 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM17 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM17 + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_DisableTIMBreakInputs(uint32_t TIMBreakInputs) +{ + CLEAR_BIT(SYSCFG->CFGR2, TIMBreakInputs); +} + +/** + * @brief Indicate if COMPx as TIMx break input + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @param TIMBreakInputs This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP_TO_ALL + * @arg @ref LL_SYSCFG_TIMBREAK_PVD_TO_ALL + * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM1 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM1 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM16 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM16 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP1_TO_TIM17 + * @arg @ref LL_SYSCFG_TIMBREAK_COMP2_TO_TIM17 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_SYSCFG_IsEnabledTIMBreakInputs(uint32_t TIMBreakInputs) +{ + return ((READ_BIT(SYSCFG->CFGR2, TIMBreakInputs) == (TIMBreakInputs)) ? 1UL : 0UL); +} + +/** + * @brief Set the TIMER1 ETR input source + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @param source This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_GPIO + * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_COMP1 + * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_COMP2 + * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_ADC + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetTIM1ETRSource(uint32_t source) +{ + MODIFY_REG(SYSCFG->CFGR2, SYSCFG_CFGR2_ETR_SRC_TIM1, source); +} + +/** + * @brief Get the TIMER1 ETR input source + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_GPIO + * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_COMP1 + * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_COMP2 + * @arg @ref LL_SYSCFG_ETR_SRC_TIM1_ADC + * @retval None + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetTIM1ETRSource(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR2, SYSCFG_CFGR2_ETR_SRC_TIM1)); +} + +#if (defined(DMA) || defined(DMA1)) +/** + * @brief Set the request image for DMA channel 1 + * @param Requset This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_MAP_ADC + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetDMARemap_CH1(uint32_t Requset) +{ + MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA1_MAP_Msk, Requset); +} + +/** + * @brief Gett the request image for DMA channel 1 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_MAP_ADC + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetDMARemap_CH1(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA1_MAP_Msk)); +} + +/** + * @brief Set the response speed of DMA channel 1 + * @param Requset This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM + * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetDMAResponseSpeed_CH1(uint32_t ResponseSpeed) +{ + MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA1_ACKLVL, ResponseSpeed); +} + +/** + * @brief Get the response speed of DMA channel 1 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM + * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetDMAResponseSpeed_CH1(void) +{ + return (uint32_t)(READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA1_ACKLVL)); +} + + +/** + * @brief Set the request image for DMA channel 2 + * @param Requset This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_MAP_ADC + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetDMARemap_CH2(uint32_t Requset) +{ + MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA2_MAP_Msk, (Requset << LL_SYSCFG_DMA_CH2_SHIFT)); +} + +/** + * @brief Gett the request image for DMA channel 2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_MAP_ADC + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetDMARemap_CH2(void) +{ + return (uint32_t)((READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA2_MAP_Msk)) >> LL_SYSCFG_DMA_CH2_SHIFT); +} + +/** + * @brief Set the response speed of DMA channel 2 + * @param Requset This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM + * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetDMAResponseSpeed_CH2(uint32_t ResponseSpeed) +{ + MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA2_ACKLVL, (ResponseSpeed << LL_SYSCFG_DMA_CH2_SHIFT)); +} + +/** + * @brief Get the response speed of DMA channel 2 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM + * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetDMAResponseSpeed_CH2(void) +{ + return (uint32_t)((READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA2_ACKLVL)) >> LL_SYSCFG_DMA_CH2_SHIFT); +} + +/** + * @brief Set the request image for DMA channel 3 + * @param Requset This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_MAP_ADC + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetDMARemap_CH3(uint32_t Requset) +{ + MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA3_MAP_Msk, (Requset << LL_SYSCFG_DMA_CH3_SHIFT)); +} + +/** + * @brief Gett the request image for DMA channel 3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_MAP_ADC + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_SPI2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART1_RX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_TX + * @arg @ref LL_SYSCFG_DMA_MAP_USART2_RX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_TX + * @arg @ref LL_SYSCFG_DMA_MAP_I2C_RX + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH2 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_COM + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM1_TRIG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH3 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_CH4 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_TRG + * @arg @ref LL_SYSCFG_DMA_MAP_TIM3_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM16_UP + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_CH1 + * @arg @ref LL_SYSCFG_DMA_MAP_TIM17_UP + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetDMARemap_CH3(void) +{ + return (uint32_t)((READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA3_MAP_Msk)) >> LL_SYSCFG_DMA_CH3_SHIFT); +} + +/** + * @brief Set the response speed of DMA channel 3 + * @param Requset This parameter can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM + * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST + * @retval None + */ +__STATIC_INLINE void LL_SYSCFG_SetDMAResponseSpeed_CH3(uint32_t ResponseSpeed) +{ + MODIFY_REG(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA3_ACKLVL, (ResponseSpeed << LL_SYSCFG_DMA_CH3_SHIFT)); +} + +/** + * @brief Get the response speed of DMA channel 3 + * @retval Returned value can be one of the following values: + * @arg @ref LL_SYSCFG_DMA_ACKLVL_NORM + * @arg @ref LL_SYSCFG_DMA_ACKLVL_FAST + */ +__STATIC_INLINE uint32_t LL_SYSCFG_GetDMAResponseSpeed_CH3(void) +{ + return (uint32_t)((READ_BIT(SYSCFG->CFGR3, SYSCFG_CFGR3_DMA3_ACKLVL)) >> LL_SYSCFG_DMA_CH3_SHIFT); +} +#endif + +/** + * @} + */ + +/** @defgroup SYSTEM_LL_EF_FLASH FLASH + * @{ + */ + +/** + * @brief Set FLASH Latency + * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_SetLatency + * @param Latency This parameter can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + * @retval None + */ +__STATIC_INLINE void LL_FLASH_SetLatency(uint32_t Latency) +{ + MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, Latency); +} + +/** + * @brief Get FLASH Latency + * @rmtoll FLASH_ACR FLASH_ACR_LATENCY LL_FLASH_GetLatency + * @retval Returned value can be one of the following values: + * @arg @ref LL_FLASH_LATENCY_0 + * @arg @ref LL_FLASH_LATENCY_1 + */ +__STATIC_INLINE uint32_t LL_FLASH_GetLatency(void) +{ + return (uint32_t)(READ_BIT(FLASH->ACR, FLASH_ACR_LATENCY)); +} + +/** + * @} + */ + +/** + * @} + */ + + +/** + * @brief Return the device identifier + * @retval Values between Min_Data=0x00 and Max_Data=0xFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetDeviceID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_DEV_ID)); +} + +/** + * @brief Return the device revision identifier + * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF + */ +__STATIC_INLINE uint32_t LL_DBGMCU_GetRevisionID(void) +{ + return (uint32_t)(READ_BIT(DBGMCU->IDCODE, DBGMCU_IDCODE_REV_ID) >> DBGMCU_IDCODE_REV_ID_Pos); +} + + +/** + * @brief Enable the Debug Module during STOP mode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_EnableDBGStopMode(void) +{ + SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Disable the Debug Module during STOP mode + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_DisableDBGStopMode(void) +{ + CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP); +} + +/** + * @brief Indicate if enable the Debug Module during STOP mode + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_IsEnabledDBGStopMode(void) +{ + return ((READ_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP) == (DBGMCU_CR_DBG_STOP)) ? 1UL : 0UL); +} +/** + * @brief Freeze APB1 peripherals (group1 peripherals) + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APBFZ1, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals (group1 peripherals) + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APBFZ1, Periphs); +} + +/** + * @brief Indicate if Freeze APB1 peripherals (group1 peripherals) + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @param Periphs This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP + * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_APB1_GRP1_IsFreezePeriph(uint32_t Periphs) +{ + return ((READ_BIT(DBGMCU->APBFZ1, Periphs) == (Periphs)) ? 1UL : 0UL); +} + +/** + * @brief Freeze APB1 peripherals(group2 peripherals) + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_FreezePeriph(uint32_t Periphs) +{ + SET_BIT(DBGMCU->APBFZ2, Periphs); +} + +/** + * @brief Unfreeze APB1 peripherals(group2 peripherals) + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @param Periphs This parameter can be a combination of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * @retval None + */ +__STATIC_INLINE void LL_DBGMCU_APB1_GRP2_UnFreezePeriph(uint32_t Periphs) +{ + CLEAR_BIT(DBGMCU->APBFZ2, Periphs); +} + +/** + * @brief Indicate if Freeze APB1 peripherals (group2 peripherals) + * @note Depending on devices and packages, some Peripherals may not be available. + * Refer to device datasheet for Peripherals availability. + * @param Periphs This parameter can be one of the following values: + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM1_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM14_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM16_STOP + * @arg @ref LL_DBGMCU_APB1_GRP2_TIM17_STOP + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_DBGMCU_APB1_GRP2_IsFreezePeriph(uint32_t Periphs) +{ + return ((READ_BIT(DBGMCU->APBFZ2, Periphs) == (Periphs)) ? 1UL : 0UL); +} +/** + * @} + */ + +#endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PY32F0XX_LL_SYSTEM_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_tim.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_tim.h similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_tim.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_tim.h index 70de580..3471a26 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_tim.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_tim.h @@ -1,3871 +1,3871 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_tim.h - * @author MCU Application Team - * @brief Header file of TIM LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PY32F0XX_LL_TIM_H -#define __PY32F0XX_LL_TIM_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0XX_LL_Driver - * @{ - */ - -#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) - -/** @defgroup TIM_LL TIM - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/** @defgroup TIM_LL_Private_Variables TIM Private Variables - * @{ - */ -static const uint8_t OFFSET_TAB_CCMRx[] = -{ - 0x00U, /* 0: TIMx_CH1 */ - 0x00U, /* 1: TIMx_CH1N */ - 0x00U, /* 2: TIMx_CH2 */ - 0x00U, /* 3: TIMx_CH2N */ - 0x04U, /* 4: TIMx_CH3 */ - 0x04U, /* 5: TIMx_CH3N */ - 0x04U /* 6: TIMx_CH4 */ -}; - -static const uint8_t SHIFT_TAB_OCxx[] = -{ - 0U, /* 0: OC1M, OC1FE, OC1PE */ - 0U, /* 1: - NA */ - 8U, /* 2: OC2M, OC2FE, OC2PE */ - 0U, /* 3: - NA */ - 0U, /* 4: OC3M, OC3FE, OC3PE */ - 0U, /* 5: - NA */ - 8U /* 6: OC4M, OC4FE, OC4PE */ -}; - -static const uint8_t SHIFT_TAB_ICxx[] = -{ - 0U, /* 0: CC1S, IC1PSC, IC1F */ - 0U, /* 1: - NA */ - 8U, /* 2: CC2S, IC2PSC, IC2F */ - 0U, /* 3: - NA */ - 0U, /* 4: CC3S, IC3PSC, IC3F */ - 0U, /* 5: - NA */ - 8U /* 6: CC4S, IC4PSC, IC4F */ -}; - -static const uint8_t SHIFT_TAB_CCxP[] = -{ - 0U, /* 0: CC1P */ - 2U, /* 1: CC1NP */ - 4U, /* 2: CC2P */ - 6U, /* 3: CC2NP */ - 8U, /* 4: CC3P */ - 10U, /* 5: CC3NP */ - 12U /* 6: CC4P */ -}; - -static const uint8_t SHIFT_TAB_OISx[] = -{ - 0U, /* 0: OIS1 */ - 1U, /* 1: OIS1N */ - 2U, /* 2: OIS2 */ - 3U, /* 3: OIS2N */ - 4U, /* 4: OIS3 */ - 5U, /* 5: OIS3N */ - 6U /* 6: OIS4 */ -}; -/** - * @} - */ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup TIM_LL_Private_Constants TIM Private Constants - * @{ - */ - - - -/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ -#define DT_DELAY_1 ((uint8_t)0x7F) -#define DT_DELAY_2 ((uint8_t)0x3F) -#define DT_DELAY_3 ((uint8_t)0x1F) -#define DT_DELAY_4 ((uint8_t)0x1F) - -/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ -#define DT_RANGE_1 ((uint8_t)0x00) -#define DT_RANGE_2 ((uint8_t)0x80) -#define DT_RANGE_3 ((uint8_t)0xC0) -#define DT_RANGE_4 ((uint8_t)0xE0) - - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup TIM_LL_Private_Macros TIM Private Macros - * @{ - */ -/** @brief Convert channel id into channel index. - * @param __CHANNEL__ This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval none - */ -#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ - (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ - ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) - -/** @brief Calculate the deadtime sampling period(in ps). - * @param __TIMCLK__ timer input clock frequency (in Hz). - * @param __CKD__ This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - * @retval none - */ -#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ - (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ - ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ - ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) -/** - * @} - */ - - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure - * @{ - */ - -/** - * @brief TIM Time Base configuration structure definition. - */ -typedef struct -{ - uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. - This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ - - uint32_t CounterMode; /*!< Specifies the counter mode. - This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ - - uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active - Auto-Reload Register at the next update event. - This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ - - uint32_t ClockDivision; /*!< Specifies the clock division. - This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ - - uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter - reaches zero, an update event is generated and counting restarts - from the RCR value (N). - This means in PWM mode that (N+1) corresponds to: - - the number of PWM periods in edge-aligned mode - - the number of half PWM period in center-aligned mode - This parameter must be a number between 0x00 and 0xFF. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ -} LL_TIM_InitTypeDef; - -/** - * @brief TIM Output Compare configuration structure definition. - */ -typedef struct -{ - uint32_t OCMode; /*!< Specifies the output mode. - This parameter can be a value of @ref TIM_LL_EC_OCMODE. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ - - uint32_t OCState; /*!< Specifies the TIM Output Compare state. - This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ - - uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. - This parameter can be a value of @ref TIM_LL_EC_OCSTATE. - - This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ - - uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. - This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. - - This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ - - uint32_t OCPolarity; /*!< Specifies the output polarity. - This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ - - uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. - This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ - - - uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ - - uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. - This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ -} LL_TIM_OC_InitTypeDef; - -/** - * @brief TIM Input Capture configuration structure definition. - */ - -typedef struct -{ - - uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t ICActiveInput; /*!< Specifies the input. - This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ - - uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t ICFilter; /*!< Specifies the input capture filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ -} LL_TIM_IC_InitTypeDef; - - -/** - * @brief TIM Encoder interface configuration structure definition. - */ -typedef struct -{ - uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). - This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ - - uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source - This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ - - uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ - - uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source - This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ - - uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t IC2Filter; /*!< Specifies the TI2 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ - -} LL_TIM_ENCODER_InitTypeDef; - -/** - * @brief TIM Hall sensor interface configuration structure definition. - */ -typedef struct -{ - - uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. - This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ - - uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. - Prescaler must be set to get a maximum counter period longer than the - time interval between 2 consecutive changes on the Hall inputs. - This parameter can be a value of @ref TIM_LL_EC_ICPSC. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ - - uint32_t IC1Filter; /*!< Specifies the TI1 input filter. - This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. - - This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ - - uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. - A positive pulse (TRGO event) is generated with a programmable delay every time - a change occurs on the Hall inputs. - This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ -} LL_TIM_HALLSENSOR_InitTypeDef; - -/** - * @brief BDTR (Break and Dead Time) structure definition - */ -typedef struct -{ - uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. - This parameter can be a value of @ref TIM_LL_EC_OSSR - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() - - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ - - uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. - This parameter can be a value of @ref TIM_LL_EC_OSSI - - This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() - - @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ - - uint32_t LockLevel; /*!< Specifies the LOCK level parameters. - This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL - - @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register - has been written, their content is frozen until the next reset.*/ - - uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the - switching-on of the outputs. - This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. - - This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() - - @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ - - uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. - This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE - - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - - uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. - This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY - - This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ - - uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. - This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE - - This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() - - @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ -} LL_TIM_BDTR_InitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants - * @{ - */ - -/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_TIM_ReadReg function. - * @{ - */ -#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ -#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ -#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ -#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ -#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ -#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ -#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ -#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ -#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ -#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ -#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ -#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable - * @{ - */ -#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ -#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable - * @{ - */ -#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ -#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** @defgroup TIM_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. - * @{ - */ -#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ -#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ -#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ -#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ -#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ -#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ -#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ -#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source - * @{ - */ -#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ -#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode - * @{ - */ -#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ -#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode - * @{ - */ -#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!TIMx_CCRy else active.*/ -#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity - * @{ - */ -#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ -#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ -/** - * @} - */ - -/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State - * @{ - */ -#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VALUE__)) - -/** - * @brief Read a value in TIM register. - * @param __INSTANCE__ TIM Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) -/** - * @} - */ - -/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros - * @{ - */ - -/** - * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. - * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __CKD__ This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - * @param __DT__ deadtime duration (in ns) - * @retval DTG[0:7] - */ -#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ - ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ - (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ - (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ - 0U) - -/** - * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. - * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __CNTCLK__ counter clock frequency (in Hz) - * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ - (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) - -/** - * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. - * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __FREQ__ output signal frequency (in Hz) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ - ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) - -/** - * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. - * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @retval Compare value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ - ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ - / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) - -/** - * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). - * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); - * @param __TIMCLK__ timer input clock frequency (in Hz) - * @param __PSC__ prescaler - * @param __DELAY__ timer output compare active/inactive delay (in us) - * @param __PULSE__ pulse duration (in us) - * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) - */ -#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ - ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ - + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) - -/** - * @brief HELPER macro retrieving the ratio of the input capture prescaler - * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); - * @param __ICPSC__ This parameter can be one of the following values: - * @arg @ref LL_TIM_ICPSC_DIV1 - * @arg @ref LL_TIM_ICPSC_DIV2 - * @arg @ref LL_TIM_ICPSC_DIV4 - * @arg @ref LL_TIM_ICPSC_DIV8 - * @retval Input capture prescaler ratio (1, 2, 4 or 8) - */ -#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ - ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) - - -/** - * @} - */ - - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions - * @{ - */ - -/** @defgroup TIM_LL_EF_Time_Base Time Base configuration - * @{ - */ -/** - * @brief Enable timer counter. - * @rmtoll CR1 CEN LL_TIM_EnableCounter - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_CEN); -} - -/** - * @brief Disable timer counter. - * @rmtoll CR1 CEN LL_TIM_DisableCounter - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); -} - -/** - * @brief Indicates whether the timer counter is enabled. - * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); -} - -/** - * @brief Enable update event generation. - * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); -} - -/** - * @brief Disable update event generation. - * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_UDIS); -} - -/** - * @brief Indicates whether update event generation is enabled. - * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent - * @param TIMx Timer instance - * @retval Inverted state of bit (0 or 1). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); -} - -/** - * @brief Set update event source - * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events - * generate an update interrupt or DMA request if enabled: - * - Counter overflow/underflow - * - Setting the UG bit - * - Update generation through the slave mode controller - * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter - * overflow/underflow generates an update interrupt or DMA request if enabled. - * @note Depending on devices and packages,DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR1 URS LL_TIM_SetUpdateSource - * @param TIMx Timer instance - * @param UpdateSource This parameter can be one of the following values: - * @arg @ref LL_TIM_UPDATESOURCE_REGULAR - * @arg @ref LL_TIM_UPDATESOURCE_COUNTER - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) -{ - MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); -} - -/** - * @brief Get actual event update source - * @rmtoll CR1 URS LL_TIM_GetUpdateSource - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_UPDATESOURCE_REGULAR - * @arg @ref LL_TIM_UPDATESOURCE_COUNTER - */ -__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); -} - -/** - * @brief Set one pulse mode (one shot v.s. repetitive). - * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode - * @param TIMx Timer instance - * @param OnePulseMode This parameter can be one of the following values: - * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE - * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) -{ - MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); -} - -/** - * @brief Get actual one pulse mode. - * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE - * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE - */ -__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); -} - -/** - * @brief Set the timer counter counting mode. - * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to - * check whether or not the counter mode selection feature is supported - * by a timer instance. - * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) - * requires a timer reset to avoid unexpected direction - * due to DIR bit readonly in center aligned mode. - * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n - * CR1 CMS LL_TIM_SetCounterMode - * @param TIMx Timer instance - * @param CounterMode This parameter can be one of the following values: - * @arg @ref LL_TIM_COUNTERMODE_UP - * @arg @ref LL_TIM_COUNTERMODE_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP - * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) -{ - MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); -} - -/** - * @brief Get actual counter mode. - * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to - * check whether or not the counter mode selection feature is supported - * by a timer instance. - * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n - * CR1 CMS LL_TIM_GetCounterMode - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_COUNTERMODE_UP - * @arg @ref LL_TIM_COUNTERMODE_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP - * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN - * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN - */ -__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); -} - -/** - * @brief Enable auto-reload (ARR) preload. - * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR1, TIM_CR1_ARPE); -} - -/** - * @brief Disable auto-reload (ARR) preload. - * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); -} - -/** - * @brief Indicates whether auto-reload (ARR) preload is enabled. - * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); -} - -/** - * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check - * whether or not the clock division feature is supported by the timer - * instance. - * @rmtoll CR1 CKD LL_TIM_SetClockDivision - * @param TIMx Timer instance - * @param ClockDivision This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) -{ - MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); -} - -/** - * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. - * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check - * whether or not the clock division feature is supported by the timer - * instance. - * @rmtoll CR1 CKD LL_TIM_GetClockDivision - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 - * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 - */ -__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); -} - -/** - * @brief Set the counter value. - * @rmtoll CNT CNT LL_TIM_SetCounter - * @param TIMx Timer instance - * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) -{ - WRITE_REG(TIMx->CNT, Counter); -} - -/** - * @brief Get the counter value. - * @rmtoll CNT CNT LL_TIM_GetCounter - * @param TIMx Timer instance - * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF) - */ -__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CNT)); -} - -/** - * @brief Get the current direction of the counter - * @rmtoll CR1 DIR LL_TIM_GetDirection - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_COUNTERDIRECTION_UP - * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN - */ -__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); -} - -/** - * @brief Set the prescaler value. - * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). - * @note The prescaler can be changed on the fly as this control register is buffered. The new - * prescaler ratio is taken into account at the next update event. - * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter - * @rmtoll PSC PSC LL_TIM_SetPrescaler - * @param TIMx Timer instance - * @param Prescaler between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) -{ - WRITE_REG(TIMx->PSC, Prescaler); -} - -/** - * @brief Get the prescaler value. - * @rmtoll PSC PSC LL_TIM_GetPrescaler - * @param TIMx Timer instance - * @retval Prescaler value between Min_Data=0 and Max_Data=65535 - */ -__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->PSC)); -} - -/** - * @brief Set the auto-reload value. - * @note The counter is blocked while the auto-reload value is null. - * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter - * @rmtoll ARR ARR LL_TIM_SetAutoReload - * @param TIMx Timer instance - * @param AutoReload between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) -{ - WRITE_REG(TIMx->ARR, AutoReload); -} - -/** - * @brief Get the auto-reload value. - * @rmtoll ARR ARR LL_TIM_GetAutoReload - * @param TIMx Timer instance - * @retval Auto-reload value - */ -__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->ARR)); -} - -/** - * @brief Set the repetition counter value. - * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a repetition counter. - * @rmtoll RCR REP LL_TIM_SetRepetitionCounter - * @param TIMx Timer instance - * @param RepetitionCounter between Min_Data=0 and Max_Data=255 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) -{ - WRITE_REG(TIMx->RCR, RepetitionCounter); -} - -/** - * @brief Get the repetition counter value. - * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports a repetition counter. - * @rmtoll RCR REP LL_TIM_GetRepetitionCounter - * @param TIMx Timer instance - * @retval Repetition counter value - */ -__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->RCR)); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration - * @{ - */ -/** - * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. - * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, - * they are updated only when a commutation event (COM) occurs. - * @note Only on channels that have a complementary output. - * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check - * whether or not a timer instance is able to generate a commutation event. - * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR2, TIM_CR2_CCPC); -} - -/** - * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. - * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check - * whether or not a timer instance is able to generate a commutation event. - * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); -} - -/** - * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). - * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check - * whether or not a timer instance is able to generate a commutation event. - * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate - * @param TIMx Timer instance - * @param CCUpdateSource This parameter can be one of the following values: - * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY - * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); -} - -#if (defined(DMA) || defined(DMA1)) -/** - * @brief Set the trigger of the capture/compare DMA request. - * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger - * @param TIMx Timer instance - * @param DMAReqTrigger This parameter can be one of the following values: - * @arg @ref LL_TIM_CCDMAREQUEST_CC - * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); -} - -/** - * @brief Get actual trigger of the capture/compare DMA request. - * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger - * @param TIMx Timer instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_CCDMAREQUEST_CC - * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE - */ -__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); -} -#endif -/** - * @brief Set the lock level to freeze the - * configuration of several capture/compare parameters. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * the lock mechanism is supported by a timer instance. - * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel - * @param TIMx Timer instance - * @param LockLevel This parameter can be one of the following values: - * @arg @ref LL_TIM_LOCKLEVEL_OFF - * @arg @ref LL_TIM_LOCKLEVEL_1 - * @arg @ref LL_TIM_LOCKLEVEL_2 - * @arg @ref LL_TIM_LOCKLEVEL_3 - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); -} - -/** - * @brief Enable capture/compare channels. - * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n - * CCER CC1NE LL_TIM_CC_EnableChannel\n - * CCER CC2E LL_TIM_CC_EnableChannel\n - * CCER CC2NE LL_TIM_CC_EnableChannel\n - * CCER CC3E LL_TIM_CC_EnableChannel\n - * CCER CC3NE LL_TIM_CC_EnableChannel\n - * CCER CC4E LL_TIM_CC_EnableChannel - * @param TIMx Timer instance - * @param Channels This parameter can be a combination of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) -{ - SET_BIT(TIMx->CCER, Channels); -} - -/** - * @brief Disable capture/compare channels. - * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n - * CCER CC1NE LL_TIM_CC_DisableChannel\n - * CCER CC2E LL_TIM_CC_DisableChannel\n - * CCER CC2NE LL_TIM_CC_DisableChannel\n - * CCER CC3E LL_TIM_CC_DisableChannel\n - * CCER CC3NE LL_TIM_CC_DisableChannel\n - * CCER CC4E LL_TIM_CC_DisableChannel - * @param TIMx Timer instance - * @param Channels This parameter can be a combination of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) -{ - CLEAR_BIT(TIMx->CCER, Channels); -} - -/** - * @brief Indicate whether channel(s) is(are) enabled. - * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n - * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n - * CCER CC2E LL_TIM_CC_IsEnabledChannel\n - * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n - * CCER CC3E LL_TIM_CC_IsEnabledChannel\n - * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n - * CCER CC4E LL_TIM_CC_IsEnabledChannel - * @param TIMx Timer instance - * @param Channels This parameter can be a combination of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) -{ - return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration - * @{ - */ -/** - * @brief Configure an output channel. - * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n - * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n - * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n - * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n - * CCER CC1P LL_TIM_OC_ConfigOutput\n - * CCER CC2P LL_TIM_OC_ConfigOutput\n - * CCER CC3P LL_TIM_OC_ConfigOutput\n - * CCER CC4P LL_TIM_OC_ConfigOutput\n - * CR2 OIS1 LL_TIM_OC_ConfigOutput\n - * CR2 OIS2 LL_TIM_OC_ConfigOutput\n - * CR2 OIS3 LL_TIM_OC_ConfigOutput\n - * CR2 OIS4 LL_TIM_OC_ConfigOutput - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW - * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); - MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), - (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); - MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), - (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); -} - -/** - * @brief Define the behavior of the output reference signal OCxREF from which - * OCx and OCxN (when relevant) are derived. - * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n - * CCMR1 OC2M LL_TIM_OC_SetMode\n - * CCMR2 OC3M LL_TIM_OC_SetMode\n - * CCMR2 OC4M LL_TIM_OC_SetMode - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param Mode This parameter can be one of the following values: - * @arg @ref LL_TIM_OCMODE_FROZEN - * @arg @ref LL_TIM_OCMODE_ACTIVE - * @arg @ref LL_TIM_OCMODE_INACTIVE - * @arg @ref LL_TIM_OCMODE_TOGGLE - * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE - * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE - * @arg @ref LL_TIM_OCMODE_PWM1 - * @arg @ref LL_TIM_OCMODE_PWM2 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); -} - -/** - * @brief Get the output compare mode of an output channel. - * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n - * CCMR1 OC2M LL_TIM_OC_GetMode\n - * CCMR2 OC3M LL_TIM_OC_GetMode\n - * CCMR2 OC4M LL_TIM_OC_GetMode - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_OCMODE_FROZEN - * @arg @ref LL_TIM_OCMODE_ACTIVE - * @arg @ref LL_TIM_OCMODE_INACTIVE - * @arg @ref LL_TIM_OCMODE_TOGGLE - * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE - * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE - * @arg @ref LL_TIM_OCMODE_PWM1 - * @arg @ref LL_TIM_OCMODE_PWM2 - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); -} - -/** - * @brief Set the polarity of an output channel. - * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n - * CCER CC1NP LL_TIM_OC_SetPolarity\n - * CCER CC2P LL_TIM_OC_SetPolarity\n - * CCER CC2NP LL_TIM_OC_SetPolarity\n - * CCER CC3P LL_TIM_OC_SetPolarity\n - * CCER CC3NP LL_TIM_OC_SetPolarity\n - * CCER CC4P LL_TIM_OC_SetPolarity - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_TIM_OCPOLARITY_HIGH - * @arg @ref LL_TIM_OCPOLARITY_LOW - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Get the polarity of an output channel. - * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n - * CCER CC1NP LL_TIM_OC_GetPolarity\n - * CCER CC2P LL_TIM_OC_GetPolarity\n - * CCER CC2NP LL_TIM_OC_GetPolarity\n - * CCER CC3P LL_TIM_OC_GetPolarity\n - * CCER CC3NP LL_TIM_OC_GetPolarity\n - * CCER CC4P LL_TIM_OC_GetPolarity - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_OCPOLARITY_HIGH - * @arg @ref LL_TIM_OCPOLARITY_LOW - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Set the IDLE state of an output channel - * @note This function is significant only for the timer instances - * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) - * can be used to check whether or not a timer instance provides - * a break input. - * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n - * CR2 OIS1N LL_TIM_OC_SetIdleState\n - * CR2 OIS2 LL_TIM_OC_SetIdleState\n - * CR2 OIS2N LL_TIM_OC_SetIdleState\n - * CR2 OIS3 LL_TIM_OC_SetIdleState\n - * CR2 OIS3N LL_TIM_OC_SetIdleState\n - * CR2 OIS4 LL_TIM_OC_SetIdleState - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param IdleState This parameter can be one of the following values: - * @arg @ref LL_TIM_OCIDLESTATE_LOW - * @arg @ref LL_TIM_OCIDLESTATE_HIGH - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); -} - -/** - * @brief Get the IDLE state of an output channel - * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n - * CR2 OIS1N LL_TIM_OC_GetIdleState\n - * CR2 OIS2 LL_TIM_OC_GetIdleState\n - * CR2 OIS2N LL_TIM_OC_GetIdleState\n - * CR2 OIS3 LL_TIM_OC_GetIdleState\n - * CR2 OIS3N LL_TIM_OC_GetIdleState\n - * CR2 OIS4 LL_TIM_OC_GetIdleState - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH1N - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH2N - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH3N - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_OCIDLESTATE_LOW - * @arg @ref LL_TIM_OCIDLESTATE_HIGH - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); -} - -/** - * @brief Enable fast mode for the output channel. - * @note Acts only if the channel is configured in PWM1 or PWM2 mode. - * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n - * CCMR1 OC2FE LL_TIM_OC_EnableFast\n - * CCMR2 OC3FE LL_TIM_OC_EnableFast\n - * CCMR2 OC4FE LL_TIM_OC_EnableFast - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); - -} - -/** - * @brief Disable fast mode for the output channel. - * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n - * CCMR1 OC2FE LL_TIM_OC_DisableFast\n - * CCMR2 OC3FE LL_TIM_OC_DisableFast\n - * CCMR2 OC4FE LL_TIM_OC_DisableFast - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); - -} - -/** - * @brief Indicates whether fast mode is enabled for the output channel. - * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n - * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n - * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n - * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; - return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); -} - -/** - * @brief Enable compare register (TIMx_CCRx) preload for the output channel. - * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n - * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n - * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n - * CCMR2 OC4PE LL_TIM_OC_EnablePreload - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Disable compare register (TIMx_CCRx) preload for the output channel. - * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n - * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n - * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n - * CCMR2 OC4PE LL_TIM_OC_DisablePreload - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. - * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n - * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n - * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n - * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; - return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); -} - -/** - * @brief Enable clearing the output channel on an external event. - * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether - * or not a timer instance can clear the OCxREF signal on an external event. - * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n - * CCMR1 OC2CE LL_TIM_OC_EnableClear\n - * CCMR2 OC3CE LL_TIM_OC_EnableClear\n - * CCMR2 OC4CE LL_TIM_OC_EnableClear - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Disable clearing the output channel on an external event. - * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether - * or not a timer instance can clear the OCxREF signal on an external event. - * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n - * CCMR1 OC2CE LL_TIM_OC_DisableClear\n - * CCMR2 OC3CE LL_TIM_OC_DisableClear\n - * CCMR2 OC4CE LL_TIM_OC_DisableClear - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); -} - -/** - * @brief Indicates clearing the output channel on an external event is enabled for the output channel. - * @note This function enables clearing the output channel on an external event. - * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. - * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether - * or not a timer instance can clear the OCxREF signal on an external event. - * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n - * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n - * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n - * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; - return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); -} - -/** - * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * dead-time insertion feature is supported by a timer instance. - * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter - * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime - * @param TIMx Timer instance - * @param DeadTime between Min_Data=0 and Max_Data=255 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); -} - -/** - * @brief Set compare value for output channel 1 (TIMx_CCR1). - * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not - * output channel 1 is supported by a timer instance. - * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR1, CompareValue); -} - -/** - * @brief Set compare value for output channel 2 (TIMx_CCR2). - * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not - * output channel 2 is supported by a timer instance. - * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR2, CompareValue); -} - -/** - * @brief Set compare value for output channel 3 (TIMx_CCR3). - * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not - * output channel is supported by a timer instance. - * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR3, CompareValue); -} - -/** - * @brief Set compare value for output channel 4 (TIMx_CCR4). - * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not - * output channel 4 is supported by a timer instance. - * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 - * @param TIMx Timer instance - * @param CompareValue between Min_Data=0 and Max_Data=65535 - * @retval None - */ -__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) -{ - WRITE_REG(TIMx->CCR4, CompareValue); -} - -/** - * @brief Get compare value (TIMx_CCR1) set for output channel 1. - * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not - * output channel 1 is supported by a timer instance. - * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR1)); -} - -/** - * @brief Get compare value (TIMx_CCR2) set for output channel 2. - * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not - * output channel 2 is supported by a timer instance. - * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR2)); -} - -/** - * @brief Get compare value (TIMx_CCR3) set for output channel 3. - * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not - * output channel 3 is supported by a timer instance. - * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR3)); -} - -/** - * @brief Get compare value (TIMx_CCR4) set for output channel 4. - * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not - * output channel 4 is supported by a timer instance. - * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 - * @param TIMx Timer instance - * @retval CompareValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR4)); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration - * @{ - */ -/** - * @brief Configure input channel. - * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n - * CCMR1 IC1PSC LL_TIM_IC_Config\n - * CCMR1 IC1F LL_TIM_IC_Config\n - * CCMR1 CC2S LL_TIM_IC_Config\n - * CCMR1 IC2PSC LL_TIM_IC_Config\n - * CCMR1 IC2F LL_TIM_IC_Config\n - * CCMR2 CC3S LL_TIM_IC_Config\n - * CCMR2 IC3PSC LL_TIM_IC_Config\n - * CCMR2 IC3F LL_TIM_IC_Config\n - * CCMR2 CC4S LL_TIM_IC_Config\n - * CCMR2 IC4PSC LL_TIM_IC_Config\n - * CCMR2 IC4F LL_TIM_IC_Config\n - * CCER CC1P LL_TIM_IC_Config\n - * CCER CC1NP LL_TIM_IC_Config\n - * CCER CC2P LL_TIM_IC_Config\n - * CCER CC2NP LL_TIM_IC_Config\n - * CCER CC3P LL_TIM_IC_Config\n - * CCER CC3NP LL_TIM_IC_Config\n - * CCER CC4P LL_TIM_IC_Config\n - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param Configuration This parameter must be a combination of all the following values: - * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC - * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 - * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 - * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), - ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); - MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), - (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Set the active input. - * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n - * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n - * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n - * CCMR2 CC4S LL_TIM_IC_SetActiveInput - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICActiveInput This parameter can be one of the following values: - * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_TRC - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); -} - -/** - * @brief Get the current active input. - * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n - * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n - * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n - * CCMR2 CC4S LL_TIM_IC_GetActiveInput - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI - * @arg @ref LL_TIM_ACTIVEINPUT_TRC - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); -} - -/** - * @brief Set the prescaler of input channel. - * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n - * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n - * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n - * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICPrescaler This parameter can be one of the following values: - * @arg @ref LL_TIM_ICPSC_DIV1 - * @arg @ref LL_TIM_ICPSC_DIV2 - * @arg @ref LL_TIM_ICPSC_DIV4 - * @arg @ref LL_TIM_ICPSC_DIV8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); -} - -/** - * @brief Get the current prescaler value acting on an input channel. - * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n - * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n - * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n - * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_ICPSC_DIV1 - * @arg @ref LL_TIM_ICPSC_DIV2 - * @arg @ref LL_TIM_ICPSC_DIV4 - * @arg @ref LL_TIM_ICPSC_DIV8 - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); -} - -/** - * @brief Set the input filter duration. - * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n - * CCMR1 IC2F LL_TIM_IC_SetFilter\n - * CCMR2 IC3F LL_TIM_IC_SetFilter\n - * CCMR2 IC4F LL_TIM_IC_SetFilter - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICFilter This parameter can be one of the following values: - * @arg @ref LL_TIM_IC_FILTER_FDIV1 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); -} - -/** - * @brief Get the input filter duration. - * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n - * CCMR1 IC2F LL_TIM_IC_GetFilter\n - * CCMR2 IC3F LL_TIM_IC_GetFilter\n - * CCMR2 IC4F LL_TIM_IC_GetFilter - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_IC_FILTER_FDIV1 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); - return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); -} - -/** - * @brief Set the input channel polarity. - * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n - * CCER CC1NP LL_TIM_IC_SetPolarity\n - * CCER CC2P LL_TIM_IC_SetPolarity\n - * CCER CC2NP LL_TIM_IC_SetPolarity\n - * CCER CC3P LL_TIM_IC_SetPolarity\n - * CCER CC3NP LL_TIM_IC_SetPolarity\n - * CCER CC4P LL_TIM_IC_SetPolarity\n - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param ICPolarity This parameter can be one of the following values: - * @arg @ref LL_TIM_IC_POLARITY_RISING - * @arg @ref LL_TIM_IC_POLARITY_FALLING - * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), - ICPolarity << SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Get the current input channel polarity. - * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n - * CCER CC1NP LL_TIM_IC_GetPolarity\n - * CCER CC2P LL_TIM_IC_GetPolarity\n - * CCER CC2NP LL_TIM_IC_GetPolarity\n - * CCER CC3P LL_TIM_IC_GetPolarity\n - * CCER CC3NP LL_TIM_IC_GetPolarity\n - * CCER CC4P LL_TIM_IC_GetPolarity\n - * @param TIMx Timer instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @retval Returned value can be one of the following values: - * @arg @ref LL_TIM_IC_POLARITY_RISING - * @arg @ref LL_TIM_IC_POLARITY_FALLING - * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) -{ - register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); - return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> - SHIFT_TAB_CCxP[iChannel]); -} - -/** - * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). - * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an XOR input. - * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->CR2, TIM_CR2_TI1S); -} - -/** - * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. - * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an XOR input. - * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); -} - -/** - * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. - * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an XOR input. - * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); -} - -/** - * @brief Get captured value for input channel 1. - * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not - * input channel 1 is supported by a timer instance. - * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR1)); -} - -/** - * @brief Get captured value for input channel 2. - * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not - * input channel 2 is supported by a timer instance. - * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR2)); -} - -/** - * @brief Get captured value for input channel 3. - * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not - * input channel 3 is supported by a timer instance. - * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR3)); -} - -/** - * @brief Get captured value for input channel 4. - * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not - * input channel 4 is supported by a timer instance. - * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 - * @param TIMx Timer instance - * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) - */ -__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) -{ - return (uint32_t)(READ_REG(TIMx->CCR4)); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection - * @{ - */ -/** - * @brief Enable external clock mode 2. - * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. - * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR ECE LL_TIM_EnableExternalClock - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); -} - -/** - * @brief Disable external clock mode 2. - * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR ECE LL_TIM_DisableExternalClock - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); -} - -/** - * @brief Indicate whether external clock mode 2 is enabled. - * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); -} - -/** - * @brief Set the clock source of the counter clock. - * @note when selected clock source is external clock mode 1, the timer input - * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() - * function. This timer input must be configured by calling - * the @ref LL_TIM_IC_Config() function. - * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode1. - * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports external clock mode2. - * @rmtoll SMCR SMS LL_TIM_SetClockSource\n - * SMCR ECE LL_TIM_SetClockSource - * @param TIMx Timer instance - * @param ClockSource This parameter can be one of the following values: - * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL - * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 - * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); -} - -/** - * @brief Set the encoder interface mode. - * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check - * whether or not a timer instance supports the encoder mode. - * @rmtoll SMCR SMS LL_TIM_SetEncoderMode - * @param TIMx Timer instance - * @param EncoderMode This parameter can be one of the following values: - * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 - * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 - * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration - * @{ - */ -/** - * @brief Set the trigger output (TRGO) used for timer synchronization . - * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check - * whether or not a timer instance can operate as a master timer. - * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput - * @param TIMx Timer instance - * @param TimerSynchronization This parameter can be one of the following values: - * @arg @ref LL_TIM_TRGO_RESET - * @arg @ref LL_TIM_TRGO_ENABLE - * @arg @ref LL_TIM_TRGO_UPDATE - * @arg @ref LL_TIM_TRGO_CC1IF - * @arg @ref LL_TIM_TRGO_OC1REF - * @arg @ref LL_TIM_TRGO_OC2REF - * @arg @ref LL_TIM_TRGO_OC3REF - * @arg @ref LL_TIM_TRGO_OC4REF - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) -{ - MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); -} - -/** - * @brief Set the synchronization mode of a slave timer. - * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR SMS LL_TIM_SetSlaveMode - * @param TIMx Timer instance - * @param SlaveMode This parameter can be one of the following values: - * @arg @ref LL_TIM_SLAVEMODE_DISABLED - * @arg @ref LL_TIM_SLAVEMODE_RESET - * @arg @ref LL_TIM_SLAVEMODE_GATED - * @arg @ref LL_TIM_SLAVEMODE_TRIGGER - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); -} - -/** - * @brief Set the selects the trigger input to be used to synchronize the counter. - * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR TS LL_TIM_SetTriggerInput - * @param TIMx Timer instance - * @param TriggerInput This parameter can be one of the following values: - * @arg @ref LL_TIM_TS_ITR0 - * @arg @ref LL_TIM_TS_ITR1 - * @arg @ref LL_TIM_TS_ITR2 - * @arg @ref LL_TIM_TS_ITR3 - * @arg @ref LL_TIM_TS_TI1F_ED - * @arg @ref LL_TIM_TS_TI1FP1 - * @arg @ref LL_TIM_TS_TI2FP2 - * @arg @ref LL_TIM_TS_ETRF - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); -} - -/** - * @brief Enable the Master/Slave mode. - * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); -} - -/** - * @brief Disable the Master/Slave mode. - * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); -} - -/** - * @brief Indicates whether the Master/Slave mode is enabled. - * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not - * a timer instance can operate as a slave timer. - * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); -} - -/** - * @brief Configure the external trigger (ETR) input. - * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides an external trigger input. - * @rmtoll SMCR ETP LL_TIM_ConfigETR\n - * SMCR ETPS LL_TIM_ConfigETR\n - * SMCR ETF LL_TIM_ConfigETR - * @param TIMx Timer instance - * @param ETRPolarity This parameter can be one of the following values: - * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED - * @arg @ref LL_TIM_ETR_POLARITY_INVERTED - * @param ETRPrescaler This parameter can be one of the following values: - * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 - * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 - * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 - * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 - * @param ETRFilter This parameter can be one of the following values: - * @arg @ref LL_TIM_ETR_FILTER_FDIV1 - * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 - * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 - * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 - * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 - * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 - * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 - * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, - uint32_t ETRFilter) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_Break_Function Break function configuration - * @{ - */ -/** - * @brief Enable the break function. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR BKE LL_TIM_EnableBRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) -{ - __IO uint32_t tmpreg; - SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); - /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ - tmpreg = READ_REG(TIMx->BDTR); - (void)(tmpreg); -} - -/** - * @brief Disable the break function. - * @rmtoll BDTR BKE LL_TIM_DisableBRK - * @param TIMx Timer instance - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) -{ - __IO uint32_t tmpreg; - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); - /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ - tmpreg = READ_REG(TIMx->BDTR); - (void)(tmpreg); -} - -/** - * @brief Configure the break input. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR BKP LL_TIM_ConfigBRK - * @param TIMx Timer instance - * @param BreakPolarity This parameter can be one of the following values: - * @arg @ref LL_TIM_BREAK_POLARITY_LOW - * @arg @ref LL_TIM_BREAK_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) -{ - __IO uint32_t tmpreg; - MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); - /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ - tmpreg = READ_REG(TIMx->BDTR); - (void)(tmpreg); -} - -/** - * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n - * BDTR OSSR LL_TIM_SetOffStates - * @param TIMx Timer instance - * @param OffStateIdle This parameter can be one of the following values: - * @arg @ref LL_TIM_OSSI_DISABLE - * @arg @ref LL_TIM_OSSI_ENABLE - * @param OffStateRun This parameter can be one of the following values: - * @arg @ref LL_TIM_OSSR_DISABLE - * @arg @ref LL_TIM_OSSR_ENABLE - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) -{ - MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); -} - -/** - * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); -} - -/** - * @brief Disable automatic output (MOE can be set only by software). - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); -} - -/** - * @brief Indicate whether automatic output is enabled. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); -} - -/** - * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). - * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by - * software and is reset in case of break or break2 event - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); -} - -/** - * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). - * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by - * software and is reset in case of break or break2 event. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); -} - -/** - * @brief Indicates whether outputs are enabled. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); -} - -/** - * @} - */ -#if (defined(DMA) || defined(DMA1)) -/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration - * @{ - */ -/** - * @brief Configures the timer DMA burst feature. - * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or - * not a timer instance supports the DMA burst mode. - * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n - * DCR DBA LL_TIM_ConfigDMABurst - * @param TIMx Timer instance - * @param DMABurstBaseAddress This parameter can be one of the following values: - * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR - * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER - * @arg @ref LL_TIM_DMABURST_BASEADDR_SR - * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER - * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT - * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC - * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR - * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 - * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 - * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR - * @param DMABurstLength This parameter can be one of the following values: - * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER - * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS - * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS - * @retval None - */ -__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) -{ - MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); -} -#endif -/** - * @} - */ - -/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management - * @{ - */ -/** - * @brief Set the OCREF clear input source - * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT - * @note This function can only be used in Output compare and PWM modes. - * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource - * @param TIMx Timer instance - * @param OCRefClearInputSource This parameter can be one of the following values: - * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR - * @arg @ref LL_TIM_OCREF_CLR_INT_ETR - * @retval None - */ -__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) -{ - MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); -} -/** - * @} - */ - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management - * @{ - */ -/** - * @brief Clear the update interrupt flag (UIF). - * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); -} - -/** - * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). - * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). - * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); -} - -/** - * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). - * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). - * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); -} - -/** - * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). - * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). - * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); -} - -/** - * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). - * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). - * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); -} - -/** - * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). - * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the commutation interrupt flag (COMIF). - * @rmtoll SR COMIF LL_TIM_ClearFlag_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); -} - -/** - * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). - * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the trigger interrupt flag (TIF). - * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); -} - -/** - * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). - * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the break interrupt flag (BIF). - * @rmtoll SR BIF LL_TIM_ClearFlag_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); -} - -/** - * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). - * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). - * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); -} - -/** - * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). - * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). - * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); -} - -/** - * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). - * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). - * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); -} - -/** - * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). - * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); -} - -/** - * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). - * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) -{ - WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); -} - -/** - * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). - * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); -} - -/** - * @} - */ - -/** @defgroup TIM_LL_EF_IT_Management IT-Management - * @{ - */ -/** - * @brief Enable update interrupt (UIE). - * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_UIE); -} - -/** - * @brief Disable update interrupt (UIE). - * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); -} - -/** - * @brief Indicates whether the update interrupt (UIE) is enabled. - * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 1 interrupt (CC1IE). - * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); -} - -/** - * @brief Disable capture/compare 1 interrupt (CC1IE). - * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); -} - -/** - * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. - * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 2 interrupt (CC2IE). - * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); -} - -/** - * @brief Disable capture/compare 2 interrupt (CC2IE). - * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); -} - -/** - * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. - * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 3 interrupt (CC3IE). - * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); -} - -/** - * @brief Disable capture/compare 3 interrupt (CC3IE). - * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); -} - -/** - * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. - * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 4 interrupt (CC4IE). - * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); -} - -/** - * @brief Disable capture/compare 4 interrupt (CC4IE). - * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); -} - -/** - * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. - * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); -} - -/** - * @brief Enable commutation interrupt (COMIE). - * @rmtoll DIER COMIE LL_TIM_EnableIT_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_COMIE); -} - -/** - * @brief Disable commutation interrupt (COMIE). - * @rmtoll DIER COMIE LL_TIM_DisableIT_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); -} - -/** - * @brief Indicates whether the commutation interrupt (COMIE) is enabled. - * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable trigger interrupt (TIE). - * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_TIE); -} - -/** - * @brief Disable trigger interrupt (TIE). - * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); -} - -/** - * @brief Indicates whether the trigger interrupt (TIE) is enabled. - * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); -} - -/** - * @brief Enable break interrupt (BIE). - * @rmtoll DIER BIE LL_TIM_EnableIT_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_BIE); -} - -/** - * @brief Disable break interrupt (BIE). - * @rmtoll DIER BIE LL_TIM_DisableIT_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); -} - -/** - * @brief Indicates whether the break interrupt (BIE) is enabled. - * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); -} - -/** - * @} - */ -#if (defined(DMA) || defined(DMA1)) -/** @defgroup TIM_LL_EF_DMA_Management DMA-Management - * @{ - */ -/** - * @brief Enable update DMA request (UDE). - * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_UDE); -} - -/** - * @brief Disable update DMA request (UDE). - * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); -} - -/** - * @brief Indicates whether the update DMA request (UDE) is enabled. - * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 1 DMA request (CC1DE). - * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); -} - -/** - * @brief Disable capture/compare 1 DMA request (CC1DE). - * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); -} - -/** - * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. - * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 2 DMA request (CC2DE). - * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); -} - -/** - * @brief Disable capture/compare 2 DMA request (CC2DE). - * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); -} - -/** - * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. - * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 3 DMA request (CC3DE). - * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); -} - -/** - * @brief Disable capture/compare 3 DMA request (CC3DE). - * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); -} - -/** - * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. - * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable capture/compare 4 DMA request (CC4DE). - * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); -} - -/** - * @brief Disable capture/compare 4 DMA request (CC4DE). - * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); -} - -/** - * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. - * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); -} - -/** - * @brief Enable commutation DMA request (COMDE). - * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_COMDE); -} - -/** - * @brief Disable commutation DMA request (COMDE). - * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); -} - -/** - * @brief Indicates whether the commutation DMA request (COMDE) is enabled. - * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); -} - -/** - * @brief Enable trigger interrupt (TDE). - * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->DIER, TIM_DIER_TDE); -} - -/** - * @brief Disable trigger interrupt (TDE). - * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) -{ - CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); -} - -/** - * @brief Indicates whether the trigger interrupt (TDE) is enabled. - * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG - * @param TIMx Timer instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) -{ - return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); -} - -/** - * @} - */ -#endif - -/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management - * @{ - */ -/** - * @brief Generate an update event. - * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_UG); -} - -/** - * @brief Generate Capture/Compare 1 event. - * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC1G); -} - -/** - * @brief Generate Capture/Compare 2 event. - * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC2G); -} - -/** - * @brief Generate Capture/Compare 3 event. - * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC3G); -} - -/** - * @brief Generate Capture/Compare 4 event. - * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_CC4G); -} - -/** - * @brief Generate commutation event. - * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_COMG); -} - -/** - * @brief Generate trigger event. - * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_TG); -} - -/** - * @brief Generate break event. - * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK - * @param TIMx Timer instance - * @retval None - */ -__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) -{ - SET_BIT(TIMx->EGR, TIM_EGR_BG); -} - -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions - * @{ - */ - -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); -void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); -void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); -void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); -void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); -void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); -void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PY32F0XX_LL_TIM_H */ -/************************ (C) COPYRIGHT PY *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_tim.h + * @author MCU Application Team + * @brief Header file of TIM LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32F0XX_LL_TIM_H +#define __PY32F0XX_LL_TIM_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0XX_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) + +/** @defgroup TIM_LL TIM + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Variables TIM Private Variables + * @{ + */ +static const uint8_t OFFSET_TAB_CCMRx[] = +{ + 0x00U, /* 0: TIMx_CH1 */ + 0x00U, /* 1: TIMx_CH1N */ + 0x00U, /* 2: TIMx_CH2 */ + 0x00U, /* 3: TIMx_CH2N */ + 0x04U, /* 4: TIMx_CH3 */ + 0x04U, /* 5: TIMx_CH3N */ + 0x04U /* 6: TIMx_CH4 */ +}; + +static const uint8_t SHIFT_TAB_OCxx[] = +{ + 0U, /* 0: OC1M, OC1FE, OC1PE */ + 0U, /* 1: - NA */ + 8U, /* 2: OC2M, OC2FE, OC2PE */ + 0U, /* 3: - NA */ + 0U, /* 4: OC3M, OC3FE, OC3PE */ + 0U, /* 5: - NA */ + 8U /* 6: OC4M, OC4FE, OC4PE */ +}; + +static const uint8_t SHIFT_TAB_ICxx[] = +{ + 0U, /* 0: CC1S, IC1PSC, IC1F */ + 0U, /* 1: - NA */ + 8U, /* 2: CC2S, IC2PSC, IC2F */ + 0U, /* 3: - NA */ + 0U, /* 4: CC3S, IC3PSC, IC3F */ + 0U, /* 5: - NA */ + 8U /* 6: CC4S, IC4PSC, IC4F */ +}; + +static const uint8_t SHIFT_TAB_CCxP[] = +{ + 0U, /* 0: CC1P */ + 2U, /* 1: CC1NP */ + 4U, /* 2: CC2P */ + 6U, /* 3: CC2NP */ + 8U, /* 4: CC3P */ + 10U, /* 5: CC3NP */ + 12U /* 6: CC4P */ +}; + +static const uint8_t SHIFT_TAB_OISx[] = +{ + 0U, /* 0: OIS1 */ + 1U, /* 1: OIS1N */ + 2U, /* 2: OIS2 */ + 3U, /* 3: OIS2N */ + 4U, /* 4: OIS3 */ + 5U, /* 5: OIS3N */ + 6U /* 6: OIS4 */ +}; +/** + * @} + */ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Constants TIM Private Constants + * @{ + */ + + + +/* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */ +#define DT_DELAY_1 ((uint8_t)0x7F) +#define DT_DELAY_2 ((uint8_t)0x3F) +#define DT_DELAY_3 ((uint8_t)0x1F) +#define DT_DELAY_4 ((uint8_t)0x1F) + +/* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */ +#define DT_RANGE_1 ((uint8_t)0x00) +#define DT_RANGE_2 ((uint8_t)0x80) +#define DT_RANGE_3 ((uint8_t)0xC0) +#define DT_RANGE_4 ((uint8_t)0xE0) + + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup TIM_LL_Private_Macros TIM Private Macros + * @{ + */ +/** @brief Convert channel id into channel index. + * @param __CHANNEL__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval none + */ +#define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \ + (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\ + ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U : 6U) + +/** @brief Calculate the deadtime sampling period(in ps). + * @param __TIMCLK__ timer input clock frequency (in Hz). + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval none + */ +#define TIM_CALC_DTS(__TIMCLK__, __CKD__) \ + (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \ + ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \ + ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U))) +/** + * @} + */ + + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_ES_INIT TIM Exported Init structure + * @{ + */ + +/** + * @brief TIM Time Base configuration structure definition. + */ +typedef struct +{ + uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/ + + uint32_t CounterMode; /*!< Specifies the counter mode. + This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/ + + uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active + Auto-Reload Register at the next update event. + This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/ + + uint32_t ClockDivision; /*!< Specifies the clock division. + This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/ + + uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter + reaches zero, an update event is generated and counting restarts + from the RCR value (N). + This means in PWM mode that (N+1) corresponds to: + - the number of PWM periods in edge-aligned mode + - the number of half PWM period in center-aligned mode + This parameter must be a number between 0x00 and 0xFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/ +} LL_TIM_InitTypeDef; + +/** + * @brief TIM Output Compare configuration structure definition. + */ +typedef struct +{ + uint32_t OCMode; /*!< Specifies the output mode. + This parameter can be a value of @ref TIM_LL_EC_OCMODE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/ + + uint32_t OCState; /*!< Specifies the TIM Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state. + This parameter can be a value of @ref TIM_LL_EC_OCSTATE. + + This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/ + + uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register. + This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF. + + This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/ + + uint32_t OCPolarity; /*!< Specifies the output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + + uint32_t OCNPolarity; /*!< Specifies the complementary output polarity. + This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/ + + + uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ + + uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state. + This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/ +} LL_TIM_OC_InitTypeDef; + +/** + * @brief TIM Input Capture configuration structure definition. + */ + +typedef struct +{ + + uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t ICActiveInput; /*!< Specifies the input. + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t ICFilter; /*!< Specifies the input capture filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ +} LL_TIM_IC_InitTypeDef; + + +/** + * @brief TIM Encoder interface configuration structure definition. + */ +typedef struct +{ + uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4). + This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE. + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + + uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source + This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/ + + uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC2Filter; /*!< Specifies the TI2 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + +} LL_TIM_ENCODER_InitTypeDef; + +/** + * @brief TIM Hall sensor interface configuration structure definition. + */ +typedef struct +{ + + uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input. + This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/ + + uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value. + Prescaler must be set to get a maximum counter period longer than the + time interval between 2 consecutive changes on the Hall inputs. + This parameter can be a value of @ref TIM_LL_EC_ICPSC. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/ + + uint32_t IC1Filter; /*!< Specifies the TI1 input filter. + This parameter can be a value of @ref TIM_LL_EC_IC_FILTER. + + This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/ + + uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register. + A positive pulse (TRGO event) is generated with a programmable delay every time + a change occurs on the Hall inputs. + This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/ +} LL_TIM_HALLSENSOR_InitTypeDef; + +/** + * @brief BDTR (Break and Dead Time) structure definition + */ +typedef struct +{ + uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode. + This parameter can be a value of @ref TIM_LL_EC_OSSR + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state. + This parameter can be a value of @ref TIM_LL_EC_OSSI + + This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates() + + @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */ + + uint32_t LockLevel; /*!< Specifies the LOCK level parameters. + This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL + + @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register + has been written, their content is frozen until the next reset.*/ + + uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the + switching-on of the outputs. + This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF. + + This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime() + + @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */ + + uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity. + This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY + + This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ + + uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not. + This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE + + This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput() + + @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */ +} LL_TIM_BDTR_InitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Constants TIM Exported Constants + * @{ + */ + +/** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_TIM_ReadReg function. + * @{ + */ +#define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */ +#define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */ +#define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */ +#define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */ +#define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */ +#define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */ +#define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */ +#define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */ +#define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */ +#define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */ +#define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */ +#define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable + * @{ + */ +#define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */ +#define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable + * @{ + */ +#define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */ +#define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */ +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** @defgroup TIM_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions. + * @{ + */ +#define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */ +#define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */ +#define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */ +#define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */ +#define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */ +#define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */ +#define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */ +#define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_UPDATESOURCE Update Source + * @{ + */ +#define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */ +#define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode + * @{ + */ +#define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */ +#define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode + * @{ + */ +#define LL_TIM_COUNTERMODE_UP 0x00000000U /*!TIMx_CCRy else active.*/ +#define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!TIMx_CCRy else inactive*/ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity + * @{ + */ +#define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/ +#define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/ +/** + * @} + */ + +/** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State + * @{ + */ +#define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!__REG__, (__VALUE__)) + +/** + * @brief Read a value in TIM register. + * @param __INSTANCE__ TIM Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__) +/** + * @} + */ + +/** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros + * @{ + */ + +/** + * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration. + * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CKD__ This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @param __DT__ deadtime duration (in ns) + * @retval DTG[0:7] + */ +#define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \ + ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \ + (((uint64_t)((__DT__)*1000U)) < ((64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64) & DT_DELAY_2)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32) & DT_DELAY_3)) :\ + (((uint64_t)((__DT__)*1000U)) < ((32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32) & DT_DELAY_4)) :\ + 0U) + +/** + * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency. + * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __CNTCLK__ counter clock frequency (in Hz) + * @retval Prescaler value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \ + (((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)(((__TIMCLK__)/(__CNTCLK__)) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency. + * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __FREQ__ output signal frequency (in Hz) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \ + ((((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? (((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U))) - 1U) : 0U) + +/** + * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay. + * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @retval Compare value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \ + ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \ + / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U)))) + +/** + * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode). + * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20); + * @param __TIMCLK__ timer input clock frequency (in Hz) + * @param __PSC__ prescaler + * @param __DELAY__ timer output compare active/inactive delay (in us) + * @param __PULSE__ pulse duration (in us) + * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535) + */ +#define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \ + ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \ + + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__)))) + +/** + * @brief HELPER macro retrieving the ratio of the input capture prescaler + * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ()); + * @param __ICPSC__ This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval Input capture prescaler ratio (1, 2, 4 or 8) + */ +#define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \ + ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos))) + + +/** + * @} + */ + + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup TIM_LL_Exported_Functions TIM Exported Functions + * @{ + */ + +/** @defgroup TIM_LL_EF_Time_Base Time Base configuration + * @{ + */ +/** + * @brief Enable timer counter. + * @rmtoll CR1 CEN LL_TIM_EnableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Disable timer counter. + * @rmtoll CR1 CEN LL_TIM_DisableCounter + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN); +} + +/** + * @brief Indicates whether the timer counter is enabled. + * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN)) ? 1UL : 0UL); +} + +/** + * @brief Enable update event generation. + * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Disable update event generation. + * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_UDIS); +} + +/** + * @brief Indicates whether update event generation is enabled. + * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent + * @param TIMx Timer instance + * @retval Inverted state of bit (0 or 1). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (uint32_t)RESET) ? 1UL : 0UL); +} + +/** + * @brief Set update event source + * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events + * generate an update interrupt or DMA request if enabled: + * - Counter overflow/underflow + * - Setting the UG bit + * - Update generation through the slave mode controller + * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter + * overflow/underflow generates an update interrupt or DMA request if enabled. + * @note Depending on devices and packages,DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR1 URS LL_TIM_SetUpdateSource + * @param TIMx Timer instance + * @param UpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource); +} + +/** + * @brief Get actual event update source + * @rmtoll CR1 URS LL_TIM_GetUpdateSource + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_UPDATESOURCE_REGULAR + * @arg @ref LL_TIM_UPDATESOURCE_COUNTER + */ +__STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS)); +} + +/** + * @brief Set one pulse mode (one shot v.s. repetitive). + * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode + * @param TIMx Timer instance + * @param OnePulseMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode); +} + +/** + * @brief Get actual one pulse mode. + * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE + * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE + */ +__STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM)); +} + +/** + * @brief Set the timer counter counting mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @note Switching from Center Aligned counter mode to Edge counter mode (or reverse) + * requires a timer reset to avoid unexpected direction + * due to DIR bit readonly in center aligned mode. + * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n + * CR1 CMS LL_TIM_SetCounterMode + * @param TIMx Timer instance + * @param CounterMode This parameter can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode) +{ + MODIFY_REG(TIMx->CR1, (TIM_CR1_DIR | TIM_CR1_CMS), CounterMode); +} + +/** + * @brief Get actual counter mode. + * @note Macro IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to + * check whether or not the counter mode selection feature is supported + * by a timer instance. + * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n + * CR1 CMS LL_TIM_GetCounterMode + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERMODE_UP + * @arg @ref LL_TIM_COUNTERMODE_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP + * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN + * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS)); +} + +/** + * @brief Enable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Disable auto-reload (ARR) preload. + * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE); +} + +/** + * @brief Indicates whether auto-reload (ARR) preload is enabled. + * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE)) ? 1UL : 0UL); +} + +/** + * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_SetClockDivision + * @param TIMx Timer instance + * @param ClockDivision This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision) +{ + MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision); +} + +/** + * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters. + * @note Macro IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check + * whether or not the clock division feature is supported by the timer + * instance. + * @rmtoll CR1 CKD LL_TIM_GetClockDivision + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CLOCKDIVISION_DIV1 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV2 + * @arg @ref LL_TIM_CLOCKDIVISION_DIV4 + */ +__STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD)); +} + +/** + * @brief Set the counter value. + * @rmtoll CNT CNT LL_TIM_SetCounter + * @param TIMx Timer instance + * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF) + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter) +{ + WRITE_REG(TIMx->CNT, Counter); +} + +/** + * @brief Get the counter value. + * @rmtoll CNT CNT LL_TIM_GetCounter + * @param TIMx Timer instance + * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF) + */ +__STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CNT)); +} + +/** + * @brief Get the current direction of the counter + * @rmtoll CR1 DIR LL_TIM_GetDirection + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_COUNTERDIRECTION_UP + * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN + */ +__STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR)); +} + +/** + * @brief Set the prescaler value. + * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1). + * @note The prescaler can be changed on the fly as this control register is buffered. The new + * prescaler ratio is taken into account at the next update event. + * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter + * @rmtoll PSC PSC LL_TIM_SetPrescaler + * @param TIMx Timer instance + * @param Prescaler between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler) +{ + WRITE_REG(TIMx->PSC, Prescaler); +} + +/** + * @brief Get the prescaler value. + * @rmtoll PSC PSC LL_TIM_GetPrescaler + * @param TIMx Timer instance + * @retval Prescaler value between Min_Data=0 and Max_Data=65535 + */ +__STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->PSC)); +} + +/** + * @brief Set the auto-reload value. + * @note The counter is blocked while the auto-reload value is null. + * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter + * @rmtoll ARR ARR LL_TIM_SetAutoReload + * @param TIMx Timer instance + * @param AutoReload between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload) +{ + WRITE_REG(TIMx->ARR, AutoReload); +} + +/** + * @brief Get the auto-reload value. + * @rmtoll ARR ARR LL_TIM_GetAutoReload + * @param TIMx Timer instance + * @retval Auto-reload value + */ +__STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->ARR)); +} + +/** + * @brief Set the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_SetRepetitionCounter + * @param TIMx Timer instance + * @param RepetitionCounter between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter) +{ + WRITE_REG(TIMx->RCR, RepetitionCounter); +} + +/** + * @brief Get the repetition counter value. + * @note Macro IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports a repetition counter. + * @rmtoll RCR REP LL_TIM_GetRepetitionCounter + * @param TIMx Timer instance + * @retval Repetition counter value + */ +__STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->RCR)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration + * @{ + */ +/** + * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written, + * they are updated only when a commutation event (COM) occurs. + * @note Only on channels that have a complementary output. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload. + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC); +} + +/** + * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM). + * @note Macro IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check + * whether or not a timer instance is able to generate a commutation event. + * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate + * @param TIMx Timer instance + * @param CCUpdateSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY + * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource); +} + +#if (defined(DMA) || defined(DMA1)) +/** + * @brief Set the trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger + * @param TIMx Timer instance + * @param DMAReqTrigger This parameter can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger); +} + +/** + * @brief Get actual trigger of the capture/compare DMA request. + * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger + * @param TIMx Timer instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_CCDMAREQUEST_CC + * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE + */ +__STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS)); +} +#endif +/** + * @brief Set the lock level to freeze the + * configuration of several capture/compare parameters. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * the lock mechanism is supported by a timer instance. + * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel + * @param TIMx Timer instance + * @param LockLevel This parameter can be one of the following values: + * @arg @ref LL_TIM_LOCKLEVEL_OFF + * @arg @ref LL_TIM_LOCKLEVEL_1 + * @arg @ref LL_TIM_LOCKLEVEL_2 + * @arg @ref LL_TIM_LOCKLEVEL_3 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel); +} + +/** + * @brief Enable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n + * CCER CC1NE LL_TIM_CC_EnableChannel\n + * CCER CC2E LL_TIM_CC_EnableChannel\n + * CCER CC2NE LL_TIM_CC_EnableChannel\n + * CCER CC3E LL_TIM_CC_EnableChannel\n + * CCER CC3NE LL_TIM_CC_EnableChannel\n + * CCER CC4E LL_TIM_CC_EnableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + SET_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Disable capture/compare channels. + * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n + * CCER CC1NE LL_TIM_CC_DisableChannel\n + * CCER CC2E LL_TIM_CC_DisableChannel\n + * CCER CC2NE LL_TIM_CC_DisableChannel\n + * CCER CC3E LL_TIM_CC_DisableChannel\n + * CCER CC3NE LL_TIM_CC_DisableChannel\n + * CCER CC4E LL_TIM_CC_DisableChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + CLEAR_BIT(TIMx->CCER, Channels); +} + +/** + * @brief Indicate whether channel(s) is(are) enabled. + * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n + * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC2E LL_TIM_CC_IsEnabledChannel\n + * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC3E LL_TIM_CC_IsEnabledChannel\n + * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n + * CCER CC4E LL_TIM_CC_IsEnabledChannel + * @param TIMx Timer instance + * @param Channels This parameter can be a combination of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels) +{ + return ((READ_BIT(TIMx->CCER, Channels) == (Channels)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Output_Channel Output channel configuration + * @{ + */ +/** + * @brief Configure an output channel. + * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n + * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n + * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n + * CCER CC1P LL_TIM_OC_ConfigOutput\n + * CCER CC2P LL_TIM_OC_ConfigOutput\n + * CCER CC3P LL_TIM_OC_ConfigOutput\n + * CCER CC4P LL_TIM_OC_ConfigOutput\n + * CR2 OIS1 LL_TIM_OC_ConfigOutput\n + * CR2 OIS2 LL_TIM_OC_ConfigOutput\n + * CR2 OIS3 LL_TIM_OC_ConfigOutput\n + * CR2 OIS4 LL_TIM_OC_ConfigOutput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW + * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel])); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), + (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), + (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Define the behavior of the output reference signal OCxREF from which + * OCx and OCxN (when relevant) are derived. + * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n + * CCMR1 OC2M LL_TIM_OC_SetMode\n + * CCMR2 OC3M LL_TIM_OC_SetMode\n + * CCMR2 OC4M LL_TIM_OC_SetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Mode This parameter can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Get the output compare mode of an output channel. + * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n + * CCMR1 OC2M LL_TIM_OC_GetMode\n + * CCMR2 OC3M LL_TIM_OC_GetMode\n + * CCMR2 OC4M LL_TIM_OC_GetMode + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCMODE_FROZEN + * @arg @ref LL_TIM_OCMODE_ACTIVE + * @arg @ref LL_TIM_OCMODE_INACTIVE + * @arg @ref LL_TIM_OCMODE_TOGGLE + * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE + * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE + * @arg @ref LL_TIM_OCMODE_PWM1 + * @arg @ref LL_TIM_OCMODE_PWM2 + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]); +} + +/** + * @brief Set the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n + * CCER CC1NP LL_TIM_OC_SetPolarity\n + * CCER CC2P LL_TIM_OC_SetPolarity\n + * CCER CC2NP LL_TIM_OC_SetPolarity\n + * CCER CC3P LL_TIM_OC_SetPolarity\n + * CCER CC3NP LL_TIM_OC_SetPolarity\n + * CCER CC4P LL_TIM_OC_SetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the polarity of an output channel. + * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n + * CCER CC1NP LL_TIM_OC_GetPolarity\n + * CCER CC2P LL_TIM_OC_GetPolarity\n + * CCER CC2NP LL_TIM_OC_GetPolarity\n + * CCER CC3P LL_TIM_OC_GetPolarity\n + * CCER CC3NP LL_TIM_OC_GetPolarity\n + * CCER CC4P LL_TIM_OC_GetPolarity + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCPOLARITY_HIGH + * @arg @ref LL_TIM_OCPOLARITY_LOW + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the IDLE state of an output channel + * @note This function is significant only for the timer instances + * supporting the break feature. Macro IS_TIM_BREAK_INSTANCE(TIMx) + * can be used to check whether or not a timer instance provides + * a break input. + * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n + * CR2 OIS1N LL_TIM_OC_SetIdleState\n + * CR2 OIS2 LL_TIM_OC_SetIdleState\n + * CR2 OIS2N LL_TIM_OC_SetIdleState\n + * CR2 OIS3 LL_TIM_OC_SetIdleState\n + * CR2 OIS3N LL_TIM_OC_SetIdleState\n + * CR2 OIS4 LL_TIM_OC_SetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param IdleState This parameter can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Get the IDLE state of an output channel + * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n + * CR2 OIS1N LL_TIM_OC_GetIdleState\n + * CR2 OIS2 LL_TIM_OC_GetIdleState\n + * CR2 OIS2N LL_TIM_OC_GetIdleState\n + * CR2 OIS3 LL_TIM_OC_GetIdleState\n + * CR2 OIS3N LL_TIM_OC_GetIdleState\n + * CR2 OIS4 LL_TIM_OC_GetIdleState + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH1N + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH2N + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH3N + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_OCIDLESTATE_LOW + * @arg @ref LL_TIM_OCIDLESTATE_HIGH + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]); +} + +/** + * @brief Enable fast mode for the output channel. + * @note Acts only if the channel is configured in PWM1 or PWM2 mode. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n + * CCMR1 OC2FE LL_TIM_OC_EnableFast\n + * CCMR2 OC3FE LL_TIM_OC_EnableFast\n + * CCMR2 OC4FE LL_TIM_OC_EnableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Disable fast mode for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n + * CCMR1 OC2FE LL_TIM_OC_DisableFast\n + * CCMR2 OC3FE LL_TIM_OC_DisableFast\n + * CCMR2 OC4FE LL_TIM_OC_DisableFast + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel])); + +} + +/** + * @brief Indicates whether fast mode is enabled for the output channel. + * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n + * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n + * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n + * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n + * CCMR2 OC4PE LL_TIM_OC_EnablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable compare register (TIMx_CCRx) preload for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n + * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n + * CCMR2 OC4PE LL_TIM_OC_DisablePreload + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel. + * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n + * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n + * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Enable clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n + * CCMR1 OC2CE LL_TIM_OC_EnableClear\n + * CCMR2 OC3CE LL_TIM_OC_EnableClear\n + * CCMR2 OC4CE LL_TIM_OC_EnableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Disable clearing the output channel on an external event. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n + * CCMR1 OC2CE LL_TIM_OC_DisableClear\n + * CCMR2 OC3CE LL_TIM_OC_DisableClear\n + * CCMR2 OC4CE LL_TIM_OC_DisableClear + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel])); +} + +/** + * @brief Indicates clearing the output channel on an external event is enabled for the output channel. + * @note This function enables clearing the output channel on an external event. + * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode. + * @note Macro IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether + * or not a timer instance can clear the OCxREF signal on an external event. + * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n + * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n + * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]; + return ((READ_BIT(*pReg, bitfield) == bitfield) ? 1UL : 0UL); +} + +/** + * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge of the Ocx and OCxN signals). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * dead-time insertion feature is supported by a timer instance. + * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter + * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime + * @param TIMx Timer instance + * @param DeadTime between Min_Data=0 and Max_Data=255 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime); +} + +/** + * @brief Set compare value for output channel 1 (TIMx_CCR1). + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR1, CompareValue); +} + +/** + * @brief Set compare value for output channel 2 (TIMx_CCR2). + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR2, CompareValue); +} + +/** + * @brief Set compare value for output channel 3 (TIMx_CCR3). + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR3, CompareValue); +} + +/** + * @brief Set compare value for output channel 4 (TIMx_CCR4). + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4 + * @param TIMx Timer instance + * @param CompareValue between Min_Data=0 and Max_Data=65535 + * @retval None + */ +__STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue) +{ + WRITE_REG(TIMx->CCR4, CompareValue); +} + +/** + * @brief Get compare value (TIMx_CCR1) set for output channel 1. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * output channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get compare value (TIMx_CCR2) set for output channel 2. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * output channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get compare value (TIMx_CCR3) set for output channel 3. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * output channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get compare value (TIMx_CCR4) set for output channel 4. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * output channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4 + * @param TIMx Timer instance + * @retval CompareValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Input_Channel Input channel configuration + * @{ + */ +/** + * @brief Configure input channel. + * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n + * CCMR1 IC1PSC LL_TIM_IC_Config\n + * CCMR1 IC1F LL_TIM_IC_Config\n + * CCMR1 CC2S LL_TIM_IC_Config\n + * CCMR1 IC2PSC LL_TIM_IC_Config\n + * CCMR1 IC2F LL_TIM_IC_Config\n + * CCMR2 CC3S LL_TIM_IC_Config\n + * CCMR2 IC3PSC LL_TIM_IC_Config\n + * CCMR2 IC3F LL_TIM_IC_Config\n + * CCMR2 CC4S LL_TIM_IC_Config\n + * CCMR2 IC4PSC LL_TIM_IC_Config\n + * CCMR2 IC4F LL_TIM_IC_Config\n + * CCER CC1P LL_TIM_IC_Config\n + * CCER CC1NP LL_TIM_IC_Config\n + * CCER CC2P LL_TIM_IC_Config\n + * CCER CC2NP LL_TIM_IC_Config\n + * CCER CC3P LL_TIM_IC_Config\n + * CCER CC3NP LL_TIM_IC_Config\n + * CCER CC4P LL_TIM_IC_Config\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param Configuration This parameter must be a combination of all the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC + * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8 + * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), + ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Set the active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_SetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICActiveInput This parameter can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current active input. + * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n + * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n + * CCMR2 CC4S LL_TIM_IC_GetActiveInput + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI + * @arg @ref LL_TIM_ACTIVEINPUT_TRC + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the prescaler of input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the current prescaler value acting on an input channel. + * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n + * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n + * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_ICPSC_DIV1 + * @arg @ref LL_TIM_ICPSC_DIV2 + * @arg @ref LL_TIM_ICPSC_DIV4 + * @arg @ref LL_TIM_ICPSC_DIV8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n + * CCMR1 IC2F LL_TIM_IC_SetFilter\n + * CCMR2 IC3F LL_TIM_IC_SetFilter\n + * CCMR2 IC4F LL_TIM_IC_SetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]); +} + +/** + * @brief Get the input filter duration. + * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n + * CCMR1 IC2F LL_TIM_IC_GetFilter\n + * CCMR2 IC3F LL_TIM_IC_GetFilter\n + * CCMR2 IC4F LL_TIM_IC_GetFilter + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_FILTER_FDIV1 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8 + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + register const __IO uint32_t *pReg = (__IO uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel])); + return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U); +} + +/** + * @brief Set the input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n + * CCER CC1NP LL_TIM_IC_SetPolarity\n + * CCER CC2P LL_TIM_IC_SetPolarity\n + * CCER CC2NP LL_TIM_IC_SetPolarity\n + * CCER CC3P LL_TIM_IC_SetPolarity\n + * CCER CC3NP LL_TIM_IC_SetPolarity\n + * CCER CC4P LL_TIM_IC_SetPolarity\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param ICPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]), + ICPolarity << SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Get the current input channel polarity. + * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n + * CCER CC1NP LL_TIM_IC_GetPolarity\n + * CCER CC2P LL_TIM_IC_GetPolarity\n + * CCER CC2NP LL_TIM_IC_GetPolarity\n + * CCER CC3P LL_TIM_IC_GetPolarity\n + * CCER CC3NP LL_TIM_IC_GetPolarity\n + * CCER CC4P LL_TIM_IC_GetPolarity\n + * @param TIMx Timer instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @retval Returned value can be one of the following values: + * @arg @ref LL_TIM_IC_POLARITY_RISING + * @arg @ref LL_TIM_IC_POLARITY_FALLING + * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel) +{ + register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel); + return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >> + SHIFT_TAB_CCxP[iChannel]); +} + +/** + * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination). + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S); +} + +/** + * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input. + * @note Macro IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an XOR input. + * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S)) ? 1UL : 0UL); +} + +/** + * @brief Get captured value for input channel 1. + * @note Macro IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not + * input channel 1 is supported by a timer instance. + * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR1)); +} + +/** + * @brief Get captured value for input channel 2. + * @note Macro IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not + * input channel 2 is supported by a timer instance. + * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR2)); +} + +/** + * @brief Get captured value for input channel 3. + * @note Macro IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not + * input channel 3 is supported by a timer instance. + * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR3)); +} + +/** + * @brief Get captured value for input channel 4. + * @note Macro IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not + * input channel 4 is supported by a timer instance. + * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4 + * @param TIMx Timer instance + * @retval CapturedValue (between Min_Data=0 and Max_Data=65535) + */ +__STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx) +{ + return (uint32_t)(READ_REG(TIMx->CCR4)); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection + * @{ + */ +/** + * @brief Enable external clock mode 2. + * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_EnableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Disable external clock mode 2. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_DisableExternalClock + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE); +} + +/** + * @brief Indicate whether external clock mode 2 is enabled. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE)) ? 1UL : 0UL); +} + +/** + * @brief Set the clock source of the counter clock. + * @note when selected clock source is external clock mode 1, the timer input + * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput() + * function. This timer input must be configured by calling + * the @ref LL_TIM_IC_Config() function. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode1. + * @note Macro IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports external clock mode2. + * @rmtoll SMCR SMS LL_TIM_SetClockSource\n + * SMCR ECE LL_TIM_SetClockSource + * @param TIMx Timer instance + * @param ClockSource This parameter can be one of the following values: + * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1 + * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource); +} + +/** + * @brief Set the encoder interface mode. + * @note Macro IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check + * whether or not a timer instance supports the encoder mode. + * @rmtoll SMCR SMS LL_TIM_SetEncoderMode + * @param TIMx Timer instance + * @param EncoderMode This parameter can be one of the following values: + * @arg @ref LL_TIM_ENCODERMODE_X2_TI1 + * @arg @ref LL_TIM_ENCODERMODE_X2_TI2 + * @arg @ref LL_TIM_ENCODERMODE_X4_TI12 + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration + * @{ + */ +/** + * @brief Set the trigger output (TRGO) used for timer synchronization . + * @note Macro IS_TIM_MASTER_INSTANCE(TIMx) can be used to check + * whether or not a timer instance can operate as a master timer. + * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput + * @param TIMx Timer instance + * @param TimerSynchronization This parameter can be one of the following values: + * @arg @ref LL_TIM_TRGO_RESET + * @arg @ref LL_TIM_TRGO_ENABLE + * @arg @ref LL_TIM_TRGO_UPDATE + * @arg @ref LL_TIM_TRGO_CC1IF + * @arg @ref LL_TIM_TRGO_OC1REF + * @arg @ref LL_TIM_TRGO_OC2REF + * @arg @ref LL_TIM_TRGO_OC3REF + * @arg @ref LL_TIM_TRGO_OC4REF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization) +{ + MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization); +} + +/** + * @brief Set the synchronization mode of a slave timer. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR SMS LL_TIM_SetSlaveMode + * @param TIMx Timer instance + * @param SlaveMode This parameter can be one of the following values: + * @arg @ref LL_TIM_SLAVEMODE_DISABLED + * @arg @ref LL_TIM_SLAVEMODE_RESET + * @arg @ref LL_TIM_SLAVEMODE_GATED + * @arg @ref LL_TIM_SLAVEMODE_TRIGGER + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode); +} + +/** + * @brief Set the selects the trigger input to be used to synchronize the counter. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR TS LL_TIM_SetTriggerInput + * @param TIMx Timer instance + * @param TriggerInput This parameter can be one of the following values: + * @arg @ref LL_TIM_TS_ITR0 + * @arg @ref LL_TIM_TS_ITR1 + * @arg @ref LL_TIM_TS_ITR2 + * @arg @ref LL_TIM_TS_ITR3 + * @arg @ref LL_TIM_TS_TI1F_ED + * @arg @ref LL_TIM_TS_TI1FP1 + * @arg @ref LL_TIM_TS_TI2FP2 + * @arg @ref LL_TIM_TS_ETRF + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput); +} + +/** + * @brief Enable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Disable the Master/Slave mode. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM); +} + +/** + * @brief Indicates whether the Master/Slave mode is enabled. + * @note Macro IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not + * a timer instance can operate as a slave timer. + * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM)) ? 1UL : 0UL); +} + +/** + * @brief Configure the external trigger (ETR) input. + * @note Macro IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides an external trigger input. + * @rmtoll SMCR ETP LL_TIM_ConfigETR\n + * SMCR ETPS LL_TIM_ConfigETR\n + * SMCR ETF LL_TIM_ConfigETR + * @param TIMx Timer instance + * @param ETRPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED + * @arg @ref LL_TIM_ETR_POLARITY_INVERTED + * @param ETRPrescaler This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_PRESCALER_DIV1 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV2 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV4 + * @arg @ref LL_TIM_ETR_PRESCALER_DIV8 + * @param ETRFilter This parameter can be one of the following values: + * @arg @ref LL_TIM_ETR_FILTER_FDIV1 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4 + * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6 + * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8 + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler, + uint32_t ETRFilter) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_Break_Function Break function configuration + * @{ + */ +/** + * @brief Enable the break function. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKE LL_TIM_EnableBRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + SET_BIT(TIMx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Disable the break function. + * @rmtoll BDTR BKE LL_TIM_DisableBRK + * @param TIMx Timer instance + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx) +{ + __IO uint32_t tmpreg; + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE); + /* Note: Any write operation to this bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Configure the break input. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR BKP LL_TIM_ConfigBRK + * @param TIMx Timer instance + * @param BreakPolarity This parameter can be one of the following values: + * @arg @ref LL_TIM_BREAK_POLARITY_LOW + * @arg @ref LL_TIM_BREAK_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity) +{ + __IO uint32_t tmpreg; + MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP, BreakPolarity); + /* Note: Any write operation to BKP bit takes a delay of 1 APB clock cycle to become effective. */ + tmpreg = READ_REG(TIMx->BDTR); + (void)(tmpreg); +} + +/** + * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n + * BDTR OSSR LL_TIM_SetOffStates + * @param TIMx Timer instance + * @param OffStateIdle This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSI_DISABLE + * @arg @ref LL_TIM_OSSI_ENABLE + * @param OffStateRun This parameter can be one of the following values: + * @arg @ref LL_TIM_OSSR_DISABLE + * @arg @ref LL_TIM_OSSR_ENABLE + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun) +{ + MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun); +} + +/** + * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Disable automatic output (MOE can be set only by software). + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE); +} + +/** + * @brief Indicate whether automatic output is enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE)) ? 1UL : 0UL); +} + +/** + * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register). + * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by + * software and is reset in case of break or break2 event. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE); +} + +/** + * @brief Indicates whether outputs are enabled. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE)) ? 1UL : 0UL); +} + +/** + * @} + */ +#if (defined(DMA) || defined(DMA1)) +/** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration + * @{ + */ +/** + * @brief Configures the timer DMA burst feature. + * @note Macro IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or + * not a timer instance supports the DMA burst mode. + * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n + * DCR DBA LL_TIM_ConfigDMABurst + * @param TIMx Timer instance + * @param DMABurstBaseAddress This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER + * @arg @ref LL_TIM_DMABURST_BASEADDR_SR + * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER + * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT + * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC + * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR + * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3 + * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4 + * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR + * @param DMABurstLength This parameter can be one of the following values: + * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER + * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS + * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS + * @retval None + */ +__STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength) +{ + MODIFY_REG(TIMx->DCR, (TIM_DCR_DBL | TIM_DCR_DBA), (DMABurstBaseAddress | DMABurstLength)); +} +#endif +/** + * @} + */ + +/** @defgroup TIM_LL_EF_OCREF_Clear OCREF_Clear_Management + * @{ + */ +/** + * @brief Set the OCREF clear input source + * @note The OCxREF signal of a given channel can be cleared when a high level is applied on the OCREF_CLR_INPUT + * @note This function can only be used in Output compare and PWM modes. + * @rmtoll SMCR OCCS LL_TIM_SetOCRefClearInputSource + * @param TIMx Timer instance + * @param OCRefClearInputSource This parameter can be one of the following values: + * @arg @ref LL_TIM_OCREF_CLR_INT_OCREF_CLR + * @arg @ref LL_TIM_OCREF_CLR_INT_ETR + * @retval None + */ +__STATIC_INLINE void LL_TIM_SetOCRefClearInputSource(TIM_TypeDef *TIMx, uint32_t OCRefClearInputSource) +{ + MODIFY_REG(TIMx->SMCR, TIM_SMCR_OCCS, OCRefClearInputSource); +} +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management + * @{ + */ +/** + * @brief Clear the update interrupt flag (UIF). + * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_UIF)); +} + +/** + * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending). + * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 interrupt flag (CC1F). + * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 interrupt flag (CC2F). + * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending). + * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 interrupt flag (CC3F). + * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending). + * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 interrupt flag (CC4F). + * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending). + * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the commutation interrupt flag (COMIF). + * @rmtoll SR COMIF LL_TIM_ClearFlag_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF)); +} + +/** + * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending). + * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the trigger interrupt flag (TIF). + * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_TIF)); +} + +/** + * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending). + * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the break interrupt flag (BIF). + * @rmtoll SR BIF LL_TIM_ClearFlag_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_BIF)); +} + +/** + * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending). + * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF). + * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF)); +} + +/** + * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending). + * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF). + * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF)); +} + +/** + * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending). + * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF). + * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF)); +} + +/** + * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending). + * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF)) ? 1UL : 0UL); +} + +/** + * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF). + * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF)); +} + +/** + * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending). + * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF)) ? 1UL : 0UL); +} + +/** + * @} + */ + +/** @defgroup TIM_LL_EF_IT_Management IT-Management + * @{ + */ +/** + * @brief Enable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Disable update interrupt (UIE). + * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE); +} + +/** + * @brief Indicates whether the update interrupt (UIE) is enabled. + * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Disable capture/compare 1 interrupt (CC1IE). + * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE); +} + +/** + * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled. + * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Disable capture/compare 2 interrupt (CC2IE). + * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE); +} + +/** + * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled. + * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Disable capture/compare 3 interrupt (CC3IE). + * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE); +} + +/** + * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled. + * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Disable capture/compare 4 interrupt (CC4IE). + * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE); +} + +/** + * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled. + * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_EnableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Disable commutation interrupt (COMIE). + * @rmtoll DIER COMIE LL_TIM_DisableIT_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE); +} + +/** + * @brief Indicates whether the commutation interrupt (COMIE) is enabled. + * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Disable trigger interrupt (TIE). + * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE); +} + +/** + * @brief Indicates whether the trigger interrupt (TIE) is enabled. + * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE)) ? 1UL : 0UL); +} + +/** + * @brief Enable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_EnableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Disable break interrupt (BIE). + * @rmtoll DIER BIE LL_TIM_DisableIT_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE); +} + +/** + * @brief Indicates whether the break interrupt (BIE) is enabled. + * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE)) ? 1UL : 0UL); +} + +/** + * @} + */ +#if (defined(DMA) || defined(DMA1)) +/** @defgroup TIM_LL_EF_DMA_Management DMA-Management + * @{ + */ +/** + * @brief Enable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Disable update DMA request (UDE). + * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE); +} + +/** + * @brief Indicates whether the update DMA request (UDE) is enabled. + * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Disable capture/compare 1 DMA request (CC1DE). + * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE); +} + +/** + * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled. + * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Disable capture/compare 2 DMA request (CC2DE). + * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE); +} + +/** + * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled. + * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Disable capture/compare 3 DMA request (CC3DE). + * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE); +} + +/** + * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled. + * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Disable capture/compare 4 DMA request (CC4DE). + * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE); +} + +/** + * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled. + * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4 + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE)) ? 1UL : 0UL); +} + +/** + * @brief Enable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Disable commutation DMA request (COMDE). + * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE); +} + +/** + * @brief Indicates whether the commutation DMA request (COMDE) is enabled. + * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE)) ? 1UL : 0UL); +} + +/** + * @brief Enable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Disable trigger interrupt (TDE). + * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE); +} + +/** + * @brief Indicates whether the trigger interrupt (TDE) is enabled. + * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG + * @param TIMx Timer instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx) +{ + return ((READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE)) ? 1UL : 0UL); +} + +/** + * @} + */ +#endif + +/** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management + * @{ + */ +/** + * @brief Generate an update event. + * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_UG); +} + +/** + * @brief Generate Capture/Compare 1 event. + * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC1G); +} + +/** + * @brief Generate Capture/Compare 2 event. + * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC2G); +} + +/** + * @brief Generate Capture/Compare 3 event. + * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC3G); +} + +/** + * @brief Generate Capture/Compare 4 event. + * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4 + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_CC4G); +} + +/** + * @brief Generate commutation event. + * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_COMG); +} + +/** + * @brief Generate trigger event. + * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_TG); +} + +/** + * @brief Generate break event. + * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK + * @param TIMx Timer instance + * @retval None + */ +__STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx) +{ + SET_BIT(TIMx->EGR, TIM_EGR_BG); +} + +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions + * @{ + */ + +ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx); +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct); +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct); +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct); +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct); +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct); +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct); +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_LL_TIM_H */ +/************************ (C) COPYRIGHT PY *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_usart.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_usart.h similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_usart.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_usart.h index ac611bc..8773bc6 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_usart.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_usart.h @@ -1,2071 +1,2071 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_usart.h - * @author MCU Application Team - * @brief Header file of USART LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef __PY32F0xx_LL_USART_H -#define __PY32F0xx_LL_USART_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0XX_LL_Driver - * @{ - */ - -#if defined (USART1) || defined (USART2) - -/** @defgroup USART_LL USART - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup USART_LL_Private_Constants USART Private Constants - * @{ - */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_Private_Macros USART Private Macros - * @{ - */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/* Exported types ------------------------------------------------------------*/ -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_ES_INIT USART Exported Init structures - * @{ - */ - -/** - * @brief LL USART Init Structure definition - */ -typedef struct -{ - uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ - - uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. - This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ - - uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. - This parameter can be a value of @ref USART_LL_EC_STOPBITS. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ - - uint32_t Parity; /*!< Specifies the parity mode. - This parameter can be a value of @ref USART_LL_EC_PARITY. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ - - uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_DIRECTION. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ - - uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_HWCONTROL. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ - - uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. - This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. - - This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ - -} LL_USART_InitTypeDef; - -/** - * @brief LL USART Clock Init Structure definition - */ -typedef struct -{ - uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. - This parameter can be a value of @ref USART_LL_EC_CLOCK. - - USART HW configuration can be modified afterwards using unitary functions - @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). - For more details, refer to description of this function. */ - - uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. - This parameter can be a value of @ref USART_LL_EC_POLARITY. - - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). - For more details, refer to description of this function. */ - - uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. - This parameter can be a value of @ref USART_LL_EC_PHASE. - - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). - For more details, refer to description of this function. */ - - uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted - data bit (MSB) has to be output on the SCLK pin in synchronous mode. - This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. - - USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). - For more details, refer to description of this function. */ - -} LL_USART_ClockInitTypeDef; - -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/* Exported constants --------------------------------------------------------*/ -/** @defgroup USART_LL_Exported_Constants USART Exported Constants - * @{ - */ - -/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines - * @brief Flags defines which can be used with LL_USART_ReadReg function - * @{ - */ -#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */ -#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */ -#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */ -#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */ -#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */ -#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */ -#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */ -#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */ -#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions - * @{ - */ -#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ -#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ -#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ -#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ -#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ -#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ -#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DIRECTION Communication Direction - * @{ - */ -#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ -#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ -#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ -#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PARITY Parity Control - * @{ - */ -#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ -#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ -#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_WAKEUP Wakeup - * @{ - */ -#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ -#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_DATAWIDTH Datawidth - * @{ - */ -#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ -#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling - * @{ - */ -#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ -#if defined(USART_CR3_OVER8) -#define LL_USART_OVERSAMPLING_8 USART_CR3_OVER8 /*!< Oversampling by 8 */ -#endif /* USART_OverSampling_Feature */ -/** - * @} - */ - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_EC_CLOCK Clock Signal - * @{ - */ - -#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ -#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ -/** - * @} - */ -#endif /*USE_FULL_LL_DRIVER*/ - -/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse - * @{ - */ -#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ -#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_PHASE Clock Phase - * @{ - */ -#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ -#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_POLARITY Clock Polarity - * @{ - */ -#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ -#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_STOPBITS Stop Bits - * @{ - */ -#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ -#define LL_USART_STOPBITS_2 USART_CR2_STOP /*!< 2 stop bits */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_HWCONTROL Hardware Control - * @{ - */ -#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ -#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ -#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ -#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ -/** - * @} - */ - -/** @defgroup USART_LL_EC_AUTOBAUNDMODE Auto baud rate detection mode - * @{ - */ -#define LL_USART_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ -#define LL_USART_AUTOBAUDRATE_ONFALLINGEDGE USART_CR3_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup USART_LL_Exported_Macros USART Exported Macros - * @{ - */ - -/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros - * @{ - */ - -/** - * @brief Write a value in USART register - * @param __INSTANCE__ USART Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in USART register - * @param __INSTANCE__ USART Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper - * @{ - */ - -/** - * @brief Compute USARTDIV value according to Peripheral Clock and - * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance - * @param __BAUDRATE__ Baud rate value to achieve - * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case - */ -#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__))) -#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100) -#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100) -/* UART BRR = mantissa + overflow + fraction - = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ -#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ - ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ - (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07)) - -/** - * @brief Compute USARTDIV value according to Peripheral Clock and - * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) - * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance - * @param __BAUDRATE__ Baud rate value to achieve - * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case - */ -#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__))) -#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) -#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100) -/* USART BRR = mantissa + overflow + fraction - = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ -#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ - (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ - (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F)) - -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ - -/** @defgroup USART_LL_Exported_Functions USART Exported Functions - * @{ - */ - -/** @defgroup USART_LL_EF_Configuration Configuration functions - * @{ - */ - -/** - * @brief USART Enable - * @rmtoll CR1 UE LL_USART_Enable - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_UE); -} - -/** - * @brief USART Disable (all USART prescalers and outputs are disabled) - * @note When USART is disabled, USART prescalers and outputs are stopped immediately, - * and current operations are discarded. The configuration of the USART is kept, but all the status - * flags, in the USARTx_SR are set to their default values. - * @rmtoll CR1 UE LL_USART_Disable - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_UE); -} - -/** - * @brief Indicate if USART is enabled - * @rmtoll CR1 UE LL_USART_IsEnabled - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); -} - -/** - * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) - * @rmtoll CR1 RE LL_USART_EnableDirectionRx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Receiver Disable - * @rmtoll CR1 RE LL_USART_DisableDirectionRx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_RE); -} - -/** - * @brief Transmitter Enable - * @rmtoll CR1 TE LL_USART_EnableDirectionTx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Transmitter Disable - * @rmtoll CR1 TE LL_USART_DisableDirectionTx - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_TE); -} - -/** - * @brief Configure simultaneously enabled/disabled states - * of Transmitter and Receiver - * @rmtoll CR1 RE LL_USART_SetTransferDirection\n - * CR1 TE LL_USART_SetTransferDirection - * @param USARTx USART Instance - * @param TransferDirection This parameter can be one of the following values: - * @arg @ref LL_USART_DIRECTION_NONE - * @arg @ref LL_USART_DIRECTION_RX - * @arg @ref LL_USART_DIRECTION_TX - * @arg @ref LL_USART_DIRECTION_TX_RX - * @retval None - */ -__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); -} - -/** - * @brief Return enabled/disabled states of Transmitter and Receiver - * @rmtoll CR1 RE LL_USART_GetTransferDirection\n - * CR1 TE LL_USART_GetTransferDirection - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DIRECTION_NONE - * @arg @ref LL_USART_DIRECTION_RX - * @arg @ref LL_USART_DIRECTION_TX - * @arg @ref LL_USART_DIRECTION_TX_RX - */ -__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); -} - -/** - * @brief Configure Parity (enabled/disabled and parity mode if enabled). - * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. - * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position - * (9th or 8th bit depending on data width) and parity is checked on the received data. - * @rmtoll CR1 PS LL_USART_SetParity\n - * CR1 PCE LL_USART_SetParity - * @param USARTx USART Instance - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - * @retval None - */ -__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); -} - -/** - * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) - * @rmtoll CR1 PS LL_USART_GetParity\n - * CR1 PCE LL_USART_GetParity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - */ -__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); -} - -/** - * @brief Set Receiver Wake Up method from Mute mode. - * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod - * @param USARTx USART Instance - * @param Method This parameter can be one of the following values: - * @arg @ref LL_USART_WAKEUP_IDLELINE - * @arg @ref LL_USART_WAKEUP_ADDRESSMARK - * @retval None - */ -__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); -} - -/** - * @brief Return Receiver Wake Up method from Mute mode - * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_WAKEUP_IDLELINE - * @arg @ref LL_USART_WAKEUP_ADDRESSMARK - */ -__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); -} - -/** - * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M LL_USART_SetDataWidth - * @param USARTx USART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * @retval None - */ -__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); -} - -/** - * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) - * @rmtoll CR1 M LL_USART_GetDataWidth - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - */ -__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); -} - -#if defined(USART_CR3_OVER8) -/** - * @brief Set Oversampling to 8-bit or 16-bit mode - * @rmtoll CR1 OVER8 LL_USART_SetOverSampling - * @param USARTx USART Instance - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_OVER8, OverSampling); -} - -/** - * @brief Return Oversampling mode - * @rmtoll CR1 OVER8 LL_USART_GetOverSampling - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - */ -__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_OVER8)); -} -#endif /* USART_OverSampling_Feature */ - -/** - * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput - * @param USARTx USART Instance - * @param LastBitClockPulse This parameter can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); -} - -/** - * @brief Retrieve Clock pulse of the last data bit output configuration - * (Last bit Clock pulse output to the SCLK pin or not) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - */ -__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); -} - -/** - * @brief Select the phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPHA LL_USART_SetClockPhase - * @param USARTx USART Instance - * @param ClockPhase This parameter can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); -} - -/** - * @brief Return phase of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPHA LL_USART_GetClockPhase - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - */ -__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); -} - -/** - * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPOL LL_USART_SetClockPolarity - * @param USARTx USART Instance - * @param ClockPolarity This parameter can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - * @retval None - */ -__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); -} - -/** - * @brief Return polarity of the clock output on the SCLK pin in synchronous mode - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CPOL LL_USART_GetClockPolarity - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - */ -__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); -} - -/** - * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function - * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function - * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function - * @rmtoll CR2 CPHA LL_USART_ConfigClock\n - * CR2 CPOL LL_USART_ConfigClock\n - * CR2 LBCL LL_USART_ConfigClock - * @param USARTx USART Instance - * @param Phase This parameter can be one of the following values: - * @arg @ref LL_USART_PHASE_1EDGE - * @arg @ref LL_USART_PHASE_2EDGE - * @param Polarity This parameter can be one of the following values: - * @arg @ref LL_USART_POLARITY_LOW - * @arg @ref LL_USART_POLARITY_HIGH - * @param LBCPOutput This parameter can be one of the following values: - * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT - * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); -} - -/** - * @brief Enable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Disable Clock output on SCLK pin - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Indicate if Clock output on SCLK pin is enabled - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); -} - -/** - * @brief Set the length of the stop bits - * @rmtoll CR2 STOP LL_USART_SetStopBitsLength - * @param USARTx USART Instance - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_2 - * @retval None - */ -__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Retrieve the length of the stop bits - * @rmtoll CR2 STOP LL_USART_GetStopBitsLength - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_2 - */ -__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); -} - -/** - * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) - * @note Call of this function is equivalent to following function call sequence : - * - Data Width configuration using @ref LL_USART_SetDataWidth() function - * - Parity Control and mode configuration using @ref LL_USART_SetParity() function - * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function - * @rmtoll CR1 PS LL_USART_ConfigCharacter\n - * CR1 PCE LL_USART_ConfigCharacter\n - * CR1 M LL_USART_ConfigCharacter\n - * CR2 STOP LL_USART_ConfigCharacter - * @param USARTx USART Instance - * @param DataWidth This parameter can be one of the following values: - * @arg @ref LL_USART_DATAWIDTH_8B - * @arg @ref LL_USART_DATAWIDTH_9B - * @param Parity This parameter can be one of the following values: - * @arg @ref LL_USART_PARITY_NONE - * @arg @ref LL_USART_PARITY_EVEN - * @arg @ref LL_USART_PARITY_ODD - * @param StopBits This parameter can be one of the following values: - * @arg @ref LL_USART_STOPBITS_1 - * @arg @ref LL_USART_STOPBITS_2 - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, - uint32_t StopBits) -{ - MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); - MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); -} - -/** - * @brief Set Address of the USART node. - * @note This is used in multiprocessor communication during Mute mode or Stop mode, - * for wake up with address mark detection. - * @rmtoll CR2 ADD LL_USART_SetNodeAddress - * @param USARTx USART Instance - * @param NodeAddress 4 bit Address of the USART node. - * @retval None - */ -__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress) -{ - MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD)); -} - -/** - * @brief Return 4 bit Address of the USART node as set in ADD field of CR2. - * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) - * @rmtoll CR2 ADD LL_USART_GetNodeAddress - * @param USARTx USART Instance - * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) - */ -__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD)); -} - -/** - * @brief Enable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Disable RTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); -} - -/** - * @brief Enable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Disable CTS HW Flow Control - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); -} - -/** - * @brief Configure HW Flow Control mode (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n - * CR3 CTSE LL_USART_SetHWFlowCtrl - * @param USARTx USART Instance - * @param HardwareFlowControl This parameter can be one of the following values: - * @arg @ref LL_USART_HWCONTROL_NONE - * @arg @ref LL_USART_HWCONTROL_RTS - * @arg @ref LL_USART_HWCONTROL_CTS - * @arg @ref LL_USART_HWCONTROL_RTS_CTS - * @retval None - */ -__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); -} - -/** - * @brief Return HW Flow Control configuration (both CTS and RTS) - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n - * CR3 CTSE LL_USART_GetHWFlowCtrl - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_HWCONTROL_NONE - * @arg @ref LL_USART_HWCONTROL_RTS - * @arg @ref LL_USART_HWCONTROL_CTS - * @arg @ref LL_USART_HWCONTROL_RTS_CTS - */ -__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); -} - - -#if defined(USART_CR3_OVER8) -/** - * @brief Configure USART BRR register for achieving expected Baud Rate value. - * @note Compute and set USARTDIV value in BRR Register (full BRR content) - * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values - * @note Peripheral clock and Baud rate values provided as function parameters should be valid - * (Baud rate value != 0) - * @rmtoll BRR BRR LL_USART_SetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @param BaudRate Baud Rate - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, - uint32_t BaudRate) -{ - if (OverSampling == LL_USART_OVERSAMPLING_8) - { - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); - } - else - { - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); - } -} - -/** - * @brief Return current Baud Rate value, according to USARTDIV present in BRR register - * (full BRR content), and to used Peripheral Clock and Oversampling mode values - * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. - * @rmtoll BRR BRR LL_USART_GetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param OverSampling This parameter can be one of the following values: - * @arg @ref LL_USART_OVERSAMPLING_16 - * @arg @ref LL_USART_OVERSAMPLING_8 - * @retval Baud Rate - */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) -{ - register uint32_t usartdiv = 0x0U; - register uint32_t brrresult = 0x0U; - - usartdiv = USARTx->BRR; - - if (OverSampling == LL_USART_OVERSAMPLING_8) - { - if ((usartdiv & 0xFFF7U) != 0U) - { - usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; - brrresult = (PeriphClk * 2U) / usartdiv; - } - } - else - { - if ((usartdiv & 0xFFFFU) != 0U) - { - brrresult = PeriphClk / usartdiv; - } - } - return (brrresult); -} -#else -/** - * @brief Configure USART BRR register for achieving expected Baud Rate value. - * @note Compute and set USARTDIV value in BRR Register (full BRR content) - * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values - * @note Peripheral clock and Baud rate values provided as function parameters should be valid - * (Baud rate value != 0) - * @rmtoll BRR BRR LL_USART_SetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @param BaudRate Baud Rate - * @retval None - */ -__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaudRate) -{ - USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); -} - -/** - * @brief Return current Baud Rate value, according to USARTDIV present in BRR register - * (full BRR content), and to used Peripheral Clock and Oversampling mode values - * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. - * @rmtoll BRR BRR LL_USART_GetBaudRate - * @param USARTx USART Instance - * @param PeriphClk Peripheral Clock - * @retval Baud Rate - */ -__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk) -{ - register uint32_t usartdiv = 0x0U; - register uint32_t brrresult = 0x0U; - - usartdiv = USARTx->BRR; - - if ((usartdiv & 0xFFFFU) != 0U) - { - brrresult = PeriphClk / usartdiv; - } - return (brrresult); -} -#endif /* USART_OverSampling_Feature */ - -/** - * @} - */ - - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature - * @{ - */ - -/** - * @brief Enable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Disable Single Wire Half-Duplex mode - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Indicate if Single Wire Half-Duplex mode is enabled - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); -} - -/** - * @} - */ - - -/** - * @} - */ - -/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services - * @{ - */ - -/** - * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) - * @note In UART mode, the following bits must be kept cleared: - * - CLKEN bit in the USART_CR2 register, - * - HDSEL bit in the USART_CR3 register. - * @note Call of this function is equivalent to following function call sequence : - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * @note Other remaining configurations items related to Asynchronous Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 CLKEN LL_USART_ConfigAsyncMode\n - * CR3 HDSEL LL_USART_ConfigAsyncMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) -{ - /* In Asynchronous mode, the following bits must be kept cleared: - - CLKEN bits in the USART_CR2 register, - - HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Synchronous Mode - * @note In Synchronous mode, the following bits must be kept cleared: - * - HDSEL bit in the USART_CR3 register. - * This function also sets the USART in Synchronous mode. - * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not - * Synchronous mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function - * @note Other remaining configurations items related to Synchronous Mode - * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using - * dedicated functions - * @rmtoll CR2 CLKEN LL_USART_ConfigSyncMode\n - * CR3 HDSEL LL_USART_ConfigSyncMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) -{ - /* In Synchronous mode, the following bits must be kept cleared: - - HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); - /* set the UART/USART in Synchronous mode */ - SET_BIT(USARTx->CR2, USART_CR2_CLKEN); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode - * @note In Half Duplex mode, the following bits must be kept cleared: - * - CLKEN bit in the USART_CR2 register, - * This function also sets the UART/USART in Half Duplex mode. - * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not - * Half-Duplex mode is supported by the USARTx instance. - * @note Call of this function is equivalent to following function call sequence : - * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function - * @note Other remaining configurations items related to Half Duplex Mode - * (as Baud Rate, Word length, Parity, ...) should be set using - * dedicated functions - * @rmtoll CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n - * CR3 HDSEL LL_USART_ConfigHalfDuplexMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) -{ - /* In Half Duplex mode, the following bits must be kept cleared: - - CLKEN bits in the USART_CR2 register */ - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); - /* set the UART/USART in Half Duplex mode */ - SET_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @brief Perform basic configuration of USART for enabling use in Multi processor Mode - * (several USARTs connected in a network, one of the USARTs can be the master, - * its TX output connected to the RX inputs of the other slaves USARTs). - * @note In MultiProcessor mode, the following bits must be kept cleared: - * - CLKEN bit in the USART_CR2 register, - * - HDSEL bit in the USART_CR3 register. - * @note Call of this function is equivalent to following function call sequence : - * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function - * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function - * @note Other remaining configurations items related to Multi processor Mode - * (as Baud Rate, Wake Up Method, Node address, ...) should be set using - * dedicated functions - * @rmtoll CR2 CLKEN LL_USART_ConfigMultiProcessMode\n - * CR3 HDSEL LL_USART_ConfigMultiProcessMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) -{ - /* In Multi Processor mode, the following bits must be kept cleared: - - CLKEN bits in the USART_CR2 register, - - HDSEL bits in the USART_CR3 register.*/ - CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); - CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management - * @{ - */ - -/** - * @brief Check if the USART Parity Error Flag is set or not - * @rmtoll SR PE LL_USART_IsActiveFlag_PE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE)); -} - -/** - * @brief Check if the USART Framing Error Flag is set or not - * @rmtoll SR FE LL_USART_IsActiveFlag_FE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE)); -} - -/** - * @brief Check if the USART Noise error detected Flag is set or not - * @rmtoll SR NF LL_USART_IsActiveFlag_NE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE)); -} - -/** - * @brief Check if the USART OverRun Error Flag is set or not - * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE)); -} - -/** - * @brief Check if the USART IDLE line detected Flag is set or not - * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE)); -} - -/** - * @brief Check if the USART Read Data Register Not Empty Flag is set or not - * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE)); -} - -/** - * @brief Check if the USART Transmission Complete Flag is set or not - * @rmtoll SR TC LL_USART_IsActiveFlag_TC - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC)); -} - -/** - * @brief Check if the USART Transmit Data Register Empty Flag is set or not - * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE)); -} - -/** - * @brief Check if the USART CTS Flag is set or not - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS)); -} - -/** - * @brief Check if the USART ABRF Flag is set or not - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRF(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_ABRF) == (USART_SR_ABRF)); -} - -/** - * @brief Check if the USART ABRE Flag is set or not - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->SR, USART_SR_ABRE) == (USART_SR_ABRE)); -} - -/** - * @brief Check if the USART Send Break Flag is set or not - * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK)); -} - -/** - * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not - * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU)); -} - -/** - * @brief Clear Parity Error Flag - * @note Clearing this flag is done by a read access to the USARTx_SR - * register followed by a read access to the USARTx_DR register. - * @note Please also consider that when clearing this flag, other flags as - * NE, FE, ORE, IDLE would also be cleared. - * @rmtoll SR PE LL_USART_ClearFlag_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) -{ - __IO uint32_t tmpreg; - tmpreg = USARTx->SR; - (void) tmpreg; - tmpreg = USARTx->DR; - (void) tmpreg; -} - -/** - * @brief Clear Framing Error Flag - * @note Clearing this flag is done by a read access to the USARTx_SR - * register followed by a read access to the USARTx_DR register. - * @note Please also consider that when clearing this flag, other flags as - * PE, NE, ORE, IDLE would also be cleared. - * @rmtoll SR FE LL_USART_ClearFlag_FE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) -{ - __IO uint32_t tmpreg; - tmpreg = USARTx->SR; - (void) tmpreg; - tmpreg = USARTx->DR; - (void) tmpreg; -} - -/** - * @brief Clear Noise detected Flag - * @note Clearing this flag is done by a read access to the USARTx_SR - * register followed by a read access to the USARTx_DR register. - * @note Please also consider that when clearing this flag, other flags as - * PE, FE, ORE, IDLE would also be cleared. - * @rmtoll SR NF LL_USART_ClearFlag_NE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) -{ - __IO uint32_t tmpreg; - tmpreg = USARTx->SR; - (void) tmpreg; - tmpreg = USARTx->DR; - (void) tmpreg; -} - -/** - * @brief Clear OverRun Error Flag - * @note Clearing this flag is done by a read access to the USARTx_SR - * register followed by a read access to the USARTx_DR register. - * @note Please also consider that when clearing this flag, other flags as - * PE, NE, FE, IDLE would also be cleared. - * @rmtoll SR ORE LL_USART_ClearFlag_ORE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) -{ - __IO uint32_t tmpreg; - tmpreg = USARTx->SR; - (void) tmpreg; - tmpreg = USARTx->DR; - (void) tmpreg; -} - -/** - * @brief Clear IDLE line detected Flag - * @note Clearing this flag is done by a read access to the USARTx_SR - * register followed by a read access to the USARTx_DR register. - * @note Please also consider that when clearing this flag, other flags as - * PE, NE, FE, ORE would also be cleared. - * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) -{ - __IO uint32_t tmpreg; - tmpreg = USARTx->SR; - (void) tmpreg; - tmpreg = USARTx->DR; - (void) tmpreg; -} - -/** - * @brief Clear Transmission Complete Flag - * @rmtoll SR TC LL_USART_ClearFlag_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->SR, ~(USART_SR_TC)); -} - -/** - * @brief Clear RX Not Empty Flag - * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->SR, ~(USART_SR_RXNE)); -} - -/** - * @brief Clear CTS Interrupt Flag - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll SR CTS LL_USART_ClearFlag_nCTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) -{ - WRITE_REG(USARTx->SR, ~(USART_SR_CTS)); -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_IT_Management IT_Management - * @{ - */ - -/** - * @brief Enable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); -} - -/** - * @brief Enable RX Not Empty Interrupt - * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); -} - -/** - * @brief Enable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_USART_EnableIT_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_TCIE); -} - -/** - * @brief Enable TX Empty Interrupt - * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_TXEIE); -} - -/** - * @brief Enable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_USART_EnableIT_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Enable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). - * 0: Interrupt is inhibited - * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. - * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Enable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_CTSIE); -} - -/** - * @brief Disable IDLE Interrupt - * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); -} - -/** - * @brief Disable RX Not Empty Interrupt - * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); -} - -/** - * @brief Disable Transmission Complete Interrupt - * @rmtoll CR1 TCIE LL_USART_DisableIT_TC - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); -} - -/** - * @brief Disable TX Empty Interrupt - * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); -} - -/** - * @brief Disable Parity Error Interrupt - * @rmtoll CR1 PEIE LL_USART_DisableIT_PE - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); -} - -/** - * @brief Disable Error Interrupt - * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing - * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). - * 0: Interrupt is inhibited - * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. - * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); -} - -/** - * @brief Disable CTS Interrupt - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); -} - -/** - * @brief Check if the USART IDLE Interrupt source is enabled or disabled. - * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); -} - -/** - * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. - * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); -} - -/** - * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. - * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); -} - -/** - * @brief Check if the USART TX Empty Interrupt is enabled or disabled. - * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); -} - -/** - * @brief Check if the USART Parity Error Interrupt is enabled or disabled. - * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); -} - - -/** - * @brief Check if the USART Error Interrupt is enabled or disabled. - * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); -} - -/** - * @brief Check if the USART CTS Interrupt is enabled or disabled. - * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not - * Hardware Flow control feature is supported by the USARTx instance. - * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); -} - -/** - * @} - */ - -#if (defined(DMA1) || defined(DMA)) -/** @defgroup USART_LL_EF_DMA_Management DMA_Management - * @{ - */ - -/** - * @brief Enable DMA Mode for reception - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Disable DMA Mode for reception - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); -} - -/** - * @brief Check if DMA Mode is enabled for reception - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); -} - -/** - * @brief Enable DMA Mode for transmission - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Disable DMA Mode for transmission - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); -} - -/** - * @brief Check if DMA Mode is enabled for transmission - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); -} - -/** - * @brief Get the data register address used for DMA transfer - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @rmtoll DR DR LL_USART_DMA_GetRegAddr - * @note Address of Data Register is valid for both Transmit and Receive transfers. - * @param USARTx USART Instance - * @retval Address of data register - */ -__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) -{ - /* return address of DR register */ - return ((uint32_t) & (USARTx->DR)); -} -#endif /* DMA1 or DMA */ - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Data_Management Data_Management - * @{ - */ - -/** - * @brief Read Receiver Data register (Receive Data value, 8 bits) - * @rmtoll DR DR LL_USART_ReceiveData8 - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0xFF - */ -__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) -{ - return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR)); -} - -/** - * @brief Read Receiver Data register (Receive Data value, 9 bits) - * @rmtoll DR DR LL_USART_ReceiveData9 - * @param USARTx USART Instance - * @retval Value between Min_Data=0x00 and Max_Data=0x1FF - */ -__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) -{ - return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR)); -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) - * @rmtoll DR DR LL_USART_TransmitData8 - * @param USARTx USART Instance - * @param Value between Min_Data=0x00 and Max_Data=0xFF - * @retval None - */ -__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) -{ - USARTx->DR = Value; -} - -/** - * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) - * @rmtoll DR DR LL_USART_TransmitData9 - * @param USARTx USART Instance - * @param Value between Min_Data=0x00 and Max_Data=0x1FF - * @retval None - */ -__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) -{ - USARTx->DR = Value & 0x1FFU; -} - -/** - * @} - */ - -/** @defgroup USART_LL_EF_Execution Execution - * @{ - */ - -/** - * @brief Request Break sending - * @rmtoll CR1 SBK LL_USART_RequestBreakSending - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_SBK); -} - -/** - * @brief Put USART in Mute mode - * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR1, USART_CR1_RWU); -} - -/** - * @brief Put USART in Active mode - * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR1, USART_CR1_RWU); -} - -/** - * @} - */ - -/** - * @brief Enable automatic baud rate detection - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->CR3, USART_CR3_ABREN); -} - -/** - * @brief Disable automatic baud rate detection - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) -{ - CLEAR_BIT(USARTx->CR3, USART_CR3_ABREN); -} - -/** - * @brief Indicate if enable automatic baud rate detection - * @param USARTx USART Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaudRate(USART_TypeDef *USARTx) -{ - return (READ_BIT(USARTx->CR3, USART_CR3_ABREN) == (USART_CR3_ABREN)); -} - -/** - * @brief Set auto baud rate detection mode - * @param USARTx USART Instance - * @param mode This parameter can be one of the following values: - * @arg @ref LL_USART_AUTOBAUDRATE_ONSTARTBIT - * @arg @ref LL_USART_AUTOBAUDRATE_ONFALLINGEDGE - * @retval None - */ -__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t mode) -{ - MODIFY_REG(USARTx->CR3, USART_CR3_ABRMODE, mode); -} - -/** - * @brief Get auto baud rate detection mode - * @param USARTx USART Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_USART_AUTOBAUDRATE_ONSTARTBIT - * @arg @ref LL_USART_AUTOBAUDRATE_ONFALLINGEDGE - */ -__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) -{ - return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_ABRMODE)); -} - -/** - * @brief Request automatic baud rate detection - * @param USARTx USART Instance - * @retval None - */ -__STATIC_INLINE void LL_USART_SendAutoBaudRateReq(USART_TypeDef *USARTx) -{ - SET_BIT(USARTx->SR, USART_SR_ABRRQ); -} - -#if defined(USE_FULL_LL_DRIVER) -/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions - * @{ - */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); -void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); -void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); -/** - * @} - */ -#endif /* USE_FULL_LL_DRIVER */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* USART1 || USART2 */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* __PY32F0XX_LL_USART_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_usart.h + * @author MCU Application Team + * @brief Header file of USART LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __PY32F0xx_LL_USART_H +#define __PY32F0xx_LL_USART_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0XX_LL_Driver + * @{ + */ + +#if defined (USART1) || defined (USART2) + +/** @defgroup USART_LL USART + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup USART_LL_Private_Constants USART Private Constants + * @{ + */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_Private_Macros USART Private Macros + * @{ + */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/* Exported types ------------------------------------------------------------*/ +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_ES_INIT USART Exported Init structures + * @{ + */ + +/** + * @brief LL USART Init Structure definition + */ +typedef struct +{ + uint32_t BaudRate; /*!< This field defines expected Usart communication baud rate. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetBaudRate().*/ + + uint32_t DataWidth; /*!< Specifies the number of data bits transmitted or received in a frame. + This parameter can be a value of @ref USART_LL_EC_DATAWIDTH. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetDataWidth().*/ + + uint32_t StopBits; /*!< Specifies the number of stop bits transmitted. + This parameter can be a value of @ref USART_LL_EC_STOPBITS. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetStopBitsLength().*/ + + uint32_t Parity; /*!< Specifies the parity mode. + This parameter can be a value of @ref USART_LL_EC_PARITY. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetParity().*/ + + uint32_t TransferDirection; /*!< Specifies whether the Receive and/or Transmit mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_DIRECTION. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetTransferDirection().*/ + + uint32_t HardwareFlowControl; /*!< Specifies whether the hardware flow control mode is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_HWCONTROL. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetHWFlowCtrl().*/ + + uint32_t OverSampling; /*!< Specifies whether USART oversampling mode is 16 or 8. + This parameter can be a value of @ref USART_LL_EC_OVERSAMPLING. + + This feature can be modified afterwards using unitary function @ref LL_USART_SetOverSampling().*/ + +} LL_USART_InitTypeDef; + +/** + * @brief LL USART Clock Init Structure definition + */ +typedef struct +{ + uint32_t ClockOutput; /*!< Specifies whether the USART clock is enabled or disabled. + This parameter can be a value of @ref USART_LL_EC_CLOCK. + + USART HW configuration can be modified afterwards using unitary functions + @ref LL_USART_EnableSCLKOutput() or @ref LL_USART_DisableSCLKOutput(). + For more details, refer to description of this function. */ + + uint32_t ClockPolarity; /*!< Specifies the steady state of the serial clock. + This parameter can be a value of @ref USART_LL_EC_POLARITY. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPolarity(). + For more details, refer to description of this function. */ + + uint32_t ClockPhase; /*!< Specifies the clock transition on which the bit capture is made. + This parameter can be a value of @ref USART_LL_EC_PHASE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetClockPhase(). + For more details, refer to description of this function. */ + + uint32_t LastBitClockPulse; /*!< Specifies whether the clock pulse corresponding to the last transmitted + data bit (MSB) has to be output on the SCLK pin in synchronous mode. + This parameter can be a value of @ref USART_LL_EC_LASTCLKPULSE. + + USART HW configuration can be modified afterwards using unitary functions @ref LL_USART_SetLastClkPulseOutput(). + For more details, refer to description of this function. */ + +} LL_USART_ClockInitTypeDef; + +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/* Exported constants --------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Constants USART Exported Constants + * @{ + */ + +/** @defgroup USART_LL_EC_GET_FLAG Get Flags Defines + * @brief Flags defines which can be used with LL_USART_ReadReg function + * @{ + */ +#define LL_USART_SR_PE USART_SR_PE /*!< Parity error flag */ +#define LL_USART_SR_FE USART_SR_FE /*!< Framing error flag */ +#define LL_USART_SR_NE USART_SR_NE /*!< Noise detected flag */ +#define LL_USART_SR_ORE USART_SR_ORE /*!< Overrun error flag */ +#define LL_USART_SR_IDLE USART_SR_IDLE /*!< Idle line detected flag */ +#define LL_USART_SR_RXNE USART_SR_RXNE /*!< Read data register not empty flag */ +#define LL_USART_SR_TC USART_SR_TC /*!< Transmission complete flag */ +#define LL_USART_SR_TXE USART_SR_TXE /*!< Transmit data register empty flag */ +#define LL_USART_SR_CTS USART_SR_CTS /*!< CTS flag */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_USART_ReadReg and LL_USART_WriteReg functions + * @{ + */ +#define LL_USART_CR1_IDLEIE USART_CR1_IDLEIE /*!< IDLE interrupt enable */ +#define LL_USART_CR1_RXNEIE USART_CR1_RXNEIE /*!< Read data register not empty interrupt enable */ +#define LL_USART_CR1_TCIE USART_CR1_TCIE /*!< Transmission complete interrupt enable */ +#define LL_USART_CR1_TXEIE USART_CR1_TXEIE /*!< Transmit data register empty interrupt enable */ +#define LL_USART_CR1_PEIE USART_CR1_PEIE /*!< Parity error */ +#define LL_USART_CR3_EIE USART_CR3_EIE /*!< Error interrupt enable */ +#define LL_USART_CR3_CTSIE USART_CR3_CTSIE /*!< CTS interrupt enable */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DIRECTION Communication Direction + * @{ + */ +#define LL_USART_DIRECTION_NONE 0x00000000U /*!< Transmitter and Receiver are disabled */ +#define LL_USART_DIRECTION_RX USART_CR1_RE /*!< Transmitter is disabled and Receiver is enabled */ +#define LL_USART_DIRECTION_TX USART_CR1_TE /*!< Transmitter is enabled and Receiver is disabled */ +#define LL_USART_DIRECTION_TX_RX (USART_CR1_TE |USART_CR1_RE) /*!< Transmitter and Receiver are enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PARITY Parity Control + * @{ + */ +#define LL_USART_PARITY_NONE 0x00000000U /*!< Parity control disabled */ +#define LL_USART_PARITY_EVEN USART_CR1_PCE /*!< Parity control enabled and Even Parity is selected */ +#define LL_USART_PARITY_ODD (USART_CR1_PCE | USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_WAKEUP Wakeup + * @{ + */ +#define LL_USART_WAKEUP_IDLELINE 0x00000000U /*!< USART wake up from Mute mode on Idle Line */ +#define LL_USART_WAKEUP_ADDRESSMARK USART_CR1_WAKE /*!< USART wake up from Mute mode on Address Mark */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_DATAWIDTH Datawidth + * @{ + */ +#define LL_USART_DATAWIDTH_8B 0x00000000U /*!< 8 bits word length : Start bit, 8 data bits, n stop bits */ +#define LL_USART_DATAWIDTH_9B USART_CR1_M /*!< 9 bits word length : Start bit, 9 data bits, n stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_OVERSAMPLING Oversampling + * @{ + */ +#define LL_USART_OVERSAMPLING_16 0x00000000U /*!< Oversampling by 16 */ +#if defined(USART_CR3_OVER8) +#define LL_USART_OVERSAMPLING_8 USART_CR3_OVER8 /*!< Oversampling by 8 */ +#endif /* USART_OverSampling_Feature */ +/** + * @} + */ + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EC_CLOCK Clock Signal + * @{ + */ + +#define LL_USART_CLOCK_DISABLE 0x00000000U /*!< Clock signal not provided */ +#define LL_USART_CLOCK_ENABLE USART_CR2_CLKEN /*!< Clock signal provided */ +/** + * @} + */ +#endif /*USE_FULL_LL_DRIVER*/ + +/** @defgroup USART_LL_EC_LASTCLKPULSE Last Clock Pulse + * @{ + */ +#define LL_USART_LASTCLKPULSE_NO_OUTPUT 0x00000000U /*!< The clock pulse of the last data bit is not output to the SCLK pin */ +#define LL_USART_LASTCLKPULSE_OUTPUT USART_CR2_LBCL /*!< The clock pulse of the last data bit is output to the SCLK pin */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_PHASE Clock Phase + * @{ + */ +#define LL_USART_PHASE_1EDGE 0x00000000U /*!< The first clock transition is the first data capture edge */ +#define LL_USART_PHASE_2EDGE USART_CR2_CPHA /*!< The second clock transition is the first data capture edge */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_POLARITY Clock Polarity + * @{ + */ +#define LL_USART_POLARITY_LOW 0x00000000U /*!< Steady low value on SCLK pin outside transmission window*/ +#define LL_USART_POLARITY_HIGH USART_CR2_CPOL /*!< Steady high value on SCLK pin outside transmission window */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_STOPBITS Stop Bits + * @{ + */ +#define LL_USART_STOPBITS_1 0x00000000U /*!< 1 stop bit */ +#define LL_USART_STOPBITS_2 USART_CR2_STOP /*!< 2 stop bits */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_HWCONTROL Hardware Control + * @{ + */ +#define LL_USART_HWCONTROL_NONE 0x00000000U /*!< CTS and RTS hardware flow control disabled */ +#define LL_USART_HWCONTROL_RTS USART_CR3_RTSE /*!< RTS output enabled, data is only requested when there is space in the receive buffer */ +#define LL_USART_HWCONTROL_CTS USART_CR3_CTSE /*!< CTS mode enabled, data is only transmitted when the nCTS input is asserted (tied to 0) */ +#define LL_USART_HWCONTROL_RTS_CTS (USART_CR3_RTSE | USART_CR3_CTSE) /*!< CTS and RTS hardware flow control enabled */ +/** + * @} + */ + +/** @defgroup USART_LL_EC_AUTOBAUNDMODE Auto baud rate detection mode + * @{ + */ +#define LL_USART_AUTOBAUDRATE_ONSTARTBIT 0x00000000U /*!< Auto Baud rate detection on start bit */ +#define LL_USART_AUTOBAUDRATE_ONFALLINGEDGE USART_CR3_ABRMODE_0 /*!< Auto Baud rate detection on falling edge */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup USART_LL_Exported_Macros USART Exported Macros + * @{ + */ + +/** @defgroup USART_LL_EM_WRITE_READ Common Write and read registers Macros + * @{ + */ + +/** + * @brief Write a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_USART_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in USART register + * @param __INSTANCE__ USART Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_USART_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** @defgroup USART_LL_EM_Exported_Macros_Helper Exported_Macros_Helper + * @{ + */ + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 8 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_8 case + */ +#define __LL_USART_DIV_SAMPLING8_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(2*(__BAUDRATE__))) +#define __LL_USART_DIVMANT_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__))/100) +#define __LL_USART_DIVFRAQ_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING8_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 8 + 50) / 100) +/* UART BRR = mantissa + overflow + fraction + = (UART DIVMANT << 4) + ((UART DIVFRAQ & 0xF8) << 1) + (UART DIVFRAQ & 0x07) */ +#define __LL_USART_DIV_SAMPLING8(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ + ((__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0xF8) << 1)) + \ + (__LL_USART_DIVFRAQ_SAMPLING8((__PERIPHCLK__), (__BAUDRATE__)) & 0x07)) + +/** + * @brief Compute USARTDIV value according to Peripheral Clock and + * expected Baud Rate in 16 bits sampling mode (32 bits value of USARTDIV is returned) + * @param __PERIPHCLK__ Peripheral Clock frequency used for USART instance + * @param __BAUDRATE__ Baud rate value to achieve + * @retval USARTDIV value to be used for BRR register filling in OverSampling_16 case + */ +#define __LL_USART_DIV_SAMPLING16_100(__PERIPHCLK__, __BAUDRATE__) (((__PERIPHCLK__)*25)/(4*(__BAUDRATE__))) +#define __LL_USART_DIVMANT_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__))/100) +#define __LL_USART_DIVFRAQ_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIV_SAMPLING16_100((__PERIPHCLK__), (__BAUDRATE__)) - (__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) * 100)) * 16 + 50) / 100) +/* USART BRR = mantissa + overflow + fraction + = (USART DIVMANT << 4) + (USART DIVFRAQ & 0xF0) + (USART DIVFRAQ & 0x0F) */ +#define __LL_USART_DIV_SAMPLING16(__PERIPHCLK__, __BAUDRATE__) (((__LL_USART_DIVMANT_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) << 4) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0xF0)) + \ + (__LL_USART_DIVFRAQ_SAMPLING16((__PERIPHCLK__), (__BAUDRATE__)) & 0x0F)) + +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ + +/** @defgroup USART_LL_Exported_Functions USART Exported Functions + * @{ + */ + +/** @defgroup USART_LL_EF_Configuration Configuration functions + * @{ + */ + +/** + * @brief USART Enable + * @rmtoll CR1 UE LL_USART_Enable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Enable(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief USART Disable (all USART prescalers and outputs are disabled) + * @note When USART is disabled, USART prescalers and outputs are stopped immediately, + * and current operations are discarded. The configuration of the USART is kept, but all the status + * flags, in the USARTx_SR are set to their default values. + * @rmtoll CR1 UE LL_USART_Disable + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_Disable(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_UE); +} + +/** + * @brief Indicate if USART is enabled + * @rmtoll CR1 UE LL_USART_IsEnabled + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabled(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_UE) == (USART_CR1_UE)); +} + +/** + * @brief Receiver Enable (Receiver is enabled and begins searching for a start bit) + * @rmtoll CR1 RE LL_USART_EnableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionRx(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Receiver Disable + * @rmtoll CR1 RE LL_USART_DisableDirectionRx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionRx(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RE); +} + +/** + * @brief Transmitter Enable + * @rmtoll CR1 TE LL_USART_EnableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDirectionTx(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Transmitter Disable + * @rmtoll CR1 TE LL_USART_DisableDirectionTx + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDirectionTx(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TE); +} + +/** + * @brief Configure simultaneously enabled/disabled states + * of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_SetTransferDirection\n + * CR1 TE LL_USART_SetTransferDirection + * @param USARTx USART Instance + * @param TransferDirection This parameter can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + * @retval None + */ +__STATIC_INLINE void LL_USART_SetTransferDirection(USART_TypeDef *USARTx, uint32_t TransferDirection) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_RE | USART_CR1_TE, TransferDirection); +} + +/** + * @brief Return enabled/disabled states of Transmitter and Receiver + * @rmtoll CR1 RE LL_USART_GetTransferDirection\n + * CR1 TE LL_USART_GetTransferDirection + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DIRECTION_NONE + * @arg @ref LL_USART_DIRECTION_RX + * @arg @ref LL_USART_DIRECTION_TX + * @arg @ref LL_USART_DIRECTION_TX_RX + */ +__STATIC_INLINE uint32_t LL_USART_GetTransferDirection(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_RE | USART_CR1_TE)); +} + +/** + * @brief Configure Parity (enabled/disabled and parity mode if enabled). + * @note This function selects if hardware parity control (generation and detection) is enabled or disabled. + * When the parity control is enabled (Odd or Even), computed parity bit is inserted at the MSB position + * (9th or 8th bit depending on data width) and parity is checked on the received data. + * @rmtoll CR1 PS LL_USART_SetParity\n + * CR1 PCE LL_USART_SetParity + * @param USARTx USART Instance + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @retval None + */ +__STATIC_INLINE void LL_USART_SetParity(USART_TypeDef *USARTx, uint32_t Parity) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE, Parity); +} + +/** + * @brief Return Parity configuration (enabled/disabled and parity mode if enabled) + * @rmtoll CR1 PS LL_USART_GetParity\n + * CR1 PCE LL_USART_GetParity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + */ +__STATIC_INLINE uint32_t LL_USART_GetParity(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set Receiver Wake Up method from Mute mode. + * @rmtoll CR1 WAKE LL_USART_SetWakeUpMethod + * @param USARTx USART Instance + * @param Method This parameter can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + * @retval None + */ +__STATIC_INLINE void LL_USART_SetWakeUpMethod(USART_TypeDef *USARTx, uint32_t Method) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_WAKE, Method); +} + +/** + * @brief Return Receiver Wake Up method from Mute mode + * @rmtoll CR1 WAKE LL_USART_GetWakeUpMethod + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_WAKEUP_IDLELINE + * @arg @ref LL_USART_WAKEUP_ADDRESSMARK + */ +__STATIC_INLINE uint32_t LL_USART_GetWakeUpMethod(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_WAKE)); +} + +/** + * @brief Set Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_USART_SetDataWidth + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @retval None + */ +__STATIC_INLINE void LL_USART_SetDataWidth(USART_TypeDef *USARTx, uint32_t DataWidth) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_M, DataWidth); +} + +/** + * @brief Return Word length (i.e. nb of data bits, excluding start and stop bits) + * @rmtoll CR1 M LL_USART_GetDataWidth + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + */ +__STATIC_INLINE uint32_t LL_USART_GetDataWidth(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR1, USART_CR1_M)); +} + +#if defined(USART_CR3_OVER8) +/** + * @brief Set Oversampling to 8-bit or 16-bit mode + * @rmtoll CR1 OVER8 LL_USART_SetOverSampling + * @param USARTx USART Instance + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetOverSampling(USART_TypeDef *USARTx, uint32_t OverSampling) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_OVER8, OverSampling); +} + +/** + * @brief Return Oversampling mode + * @rmtoll CR1 OVER8 LL_USART_GetOverSampling + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + */ +__STATIC_INLINE uint32_t LL_USART_GetOverSampling(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_OVER8)); +} +#endif /* USART_OverSampling_Feature */ + +/** + * @brief Configure if Clock pulse of the last data bit is output to the SCLK pin or not + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_SetLastClkPulseOutput + * @param USARTx USART Instance + * @param LastBitClockPulse This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_SetLastClkPulseOutput(USART_TypeDef *USARTx, uint32_t LastBitClockPulse) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_LBCL, LastBitClockPulse); +} + +/** + * @brief Retrieve Clock pulse of the last data bit output configuration + * (Last bit Clock pulse output to the SCLK pin or not) + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 LBCL LL_USART_GetLastClkPulseOutput + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + */ +__STATIC_INLINE uint32_t LL_USART_GetLastClkPulseOutput(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_LBCL)); +} + +/** + * @brief Select the phase of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_SetClockPhase + * @param USARTx USART Instance + * @param ClockPhase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPhase(USART_TypeDef *USARTx, uint32_t ClockPhase) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA, ClockPhase); +} + +/** + * @brief Return phase of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPHA LL_USART_GetClockPhase + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPhase(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPHA)); +} + +/** + * @brief Select the polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_SetClockPolarity + * @param USARTx USART Instance + * @param ClockPolarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @retval None + */ +__STATIC_INLINE void LL_USART_SetClockPolarity(USART_TypeDef *USARTx, uint32_t ClockPolarity) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPOL, ClockPolarity); +} + +/** + * @brief Return polarity of the clock output on the SCLK pin in synchronous mode + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CPOL LL_USART_GetClockPolarity + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + */ +__STATIC_INLINE uint32_t LL_USART_GetClockPolarity(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_CPOL)); +} + +/** + * @brief Configure Clock signal format (Phase Polarity and choice about output of last bit clock pulse) + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clock Phase configuration using @ref LL_USART_SetClockPhase() function + * - Clock Polarity configuration using @ref LL_USART_SetClockPolarity() function + * - Output of Last bit Clock pulse configuration using @ref LL_USART_SetLastClkPulseOutput() function + * @rmtoll CR2 CPHA LL_USART_ConfigClock\n + * CR2 CPOL LL_USART_ConfigClock\n + * CR2 LBCL LL_USART_ConfigClock + * @param USARTx USART Instance + * @param Phase This parameter can be one of the following values: + * @arg @ref LL_USART_PHASE_1EDGE + * @arg @ref LL_USART_PHASE_2EDGE + * @param Polarity This parameter can be one of the following values: + * @arg @ref LL_USART_POLARITY_LOW + * @arg @ref LL_USART_POLARITY_HIGH + * @param LBCPOutput This parameter can be one of the following values: + * @arg @ref LL_USART_LASTCLKPULSE_NO_OUTPUT + * @arg @ref LL_USART_LASTCLKPULSE_OUTPUT + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigClock(USART_TypeDef *USARTx, uint32_t Phase, uint32_t Polarity, uint32_t LBCPOutput) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, Phase | Polarity | LBCPOutput); +} + +/** + * @brief Enable Clock output on SCLK pin + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_EnableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableSCLKOutput(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Disable Clock output on SCLK pin + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_DisableSCLKOutput + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableSCLKOutput(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Indicate if Clock output on SCLK pin is enabled + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @rmtoll CR2 CLKEN LL_USART_IsEnabledSCLKOutput + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledSCLKOutput(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR2, USART_CR2_CLKEN) == (USART_CR2_CLKEN)); +} + +/** + * @brief Set the length of the stop bits + * @rmtoll CR2 STOP LL_USART_SetStopBitsLength + * @param USARTx USART Instance + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_SetStopBitsLength(USART_TypeDef *USARTx, uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Retrieve the length of the stop bits + * @rmtoll CR2 STOP LL_USART_GetStopBitsLength + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_2 + */ +__STATIC_INLINE uint32_t LL_USART_GetStopBitsLength(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_STOP)); +} + +/** + * @brief Configure Character frame format (Datawidth, Parity control, Stop Bits) + * @note Call of this function is equivalent to following function call sequence : + * - Data Width configuration using @ref LL_USART_SetDataWidth() function + * - Parity Control and mode configuration using @ref LL_USART_SetParity() function + * - Stop bits configuration using @ref LL_USART_SetStopBitsLength() function + * @rmtoll CR1 PS LL_USART_ConfigCharacter\n + * CR1 PCE LL_USART_ConfigCharacter\n + * CR1 M LL_USART_ConfigCharacter\n + * CR2 STOP LL_USART_ConfigCharacter + * @param USARTx USART Instance + * @param DataWidth This parameter can be one of the following values: + * @arg @ref LL_USART_DATAWIDTH_8B + * @arg @ref LL_USART_DATAWIDTH_9B + * @param Parity This parameter can be one of the following values: + * @arg @ref LL_USART_PARITY_NONE + * @arg @ref LL_USART_PARITY_EVEN + * @arg @ref LL_USART_PARITY_ODD + * @param StopBits This parameter can be one of the following values: + * @arg @ref LL_USART_STOPBITS_1 + * @arg @ref LL_USART_STOPBITS_2 + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigCharacter(USART_TypeDef *USARTx, uint32_t DataWidth, uint32_t Parity, + uint32_t StopBits) +{ + MODIFY_REG(USARTx->CR1, USART_CR1_PS | USART_CR1_PCE | USART_CR1_M, Parity | DataWidth); + MODIFY_REG(USARTx->CR2, USART_CR2_STOP, StopBits); +} + +/** + * @brief Set Address of the USART node. + * @note This is used in multiprocessor communication during Mute mode or Stop mode, + * for wake up with address mark detection. + * @rmtoll CR2 ADD LL_USART_SetNodeAddress + * @param USARTx USART Instance + * @param NodeAddress 4 bit Address of the USART node. + * @retval None + */ +__STATIC_INLINE void LL_USART_SetNodeAddress(USART_TypeDef *USARTx, uint32_t NodeAddress) +{ + MODIFY_REG(USARTx->CR2, USART_CR2_ADD, (NodeAddress & USART_CR2_ADD)); +} + +/** + * @brief Return 4 bit Address of the USART node as set in ADD field of CR2. + * @note only 4bits (b3-b0) of returned value are relevant (b31-b4 are not relevant) + * @rmtoll CR2 ADD LL_USART_GetNodeAddress + * @param USARTx USART Instance + * @retval Address of the USART node (Value between Min_Data=0 and Max_Data=255) + */ +__STATIC_INLINE uint32_t LL_USART_GetNodeAddress(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR2, USART_CR2_ADD)); +} + +/** + * @brief Enable RTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_EnableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Disable RTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_DisableRTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableRTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_RTSE); +} + +/** + * @brief Enable CTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_EnableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Disable CTS HW Flow Control + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSE LL_USART_DisableCTSHWFlowCtrl + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableCTSHWFlowCtrl(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSE); +} + +/** + * @brief Configure HW Flow Control mode (both CTS and RTS) + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_SetHWFlowCtrl\n + * CR3 CTSE LL_USART_SetHWFlowCtrl + * @param USARTx USART Instance + * @param HardwareFlowControl This parameter can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + * @retval None + */ +__STATIC_INLINE void LL_USART_SetHWFlowCtrl(USART_TypeDef *USARTx, uint32_t HardwareFlowControl) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE, HardwareFlowControl); +} + +/** + * @brief Return HW Flow Control configuration (both CTS and RTS) + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 RTSE LL_USART_GetHWFlowCtrl\n + * CR3 CTSE LL_USART_GetHWFlowCtrl + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_HWCONTROL_NONE + * @arg @ref LL_USART_HWCONTROL_RTS + * @arg @ref LL_USART_HWCONTROL_CTS + * @arg @ref LL_USART_HWCONTROL_RTS_CTS + */ +__STATIC_INLINE uint32_t LL_USART_GetHWFlowCtrl(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_RTSE | USART_CR3_CTSE)); +} + + +#if defined(USART_CR3_OVER8) +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling, + uint32_t BaudRate) +{ + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING8(PeriphClk, BaudRate)); + } + else + { + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); + } +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param OverSampling This parameter can be one of the following values: + * @arg @ref LL_USART_OVERSAMPLING_16 + * @arg @ref LL_USART_OVERSAMPLING_8 + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t OverSampling) +{ + register uint32_t usartdiv = 0x0U; + register uint32_t brrresult = 0x0U; + + usartdiv = USARTx->BRR; + + if (OverSampling == LL_USART_OVERSAMPLING_8) + { + if ((usartdiv & 0xFFF7U) != 0U) + { + usartdiv = (uint16_t)((usartdiv & 0xFFF0U) | ((usartdiv & 0x0007U) << 1U)) ; + brrresult = (PeriphClk * 2U) / usartdiv; + } + } + else + { + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = PeriphClk / usartdiv; + } + } + return (brrresult); +} +#else +/** + * @brief Configure USART BRR register for achieving expected Baud Rate value. + * @note Compute and set USARTDIV value in BRR Register (full BRR content) + * according to used Peripheral Clock, Oversampling mode, and expected Baud Rate values + * @note Peripheral clock and Baud rate values provided as function parameters should be valid + * (Baud rate value != 0) + * @rmtoll BRR BRR LL_USART_SetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @param BaudRate Baud Rate + * @retval None + */ +__STATIC_INLINE void LL_USART_SetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk, uint32_t BaudRate) +{ + USARTx->BRR = (uint16_t)(__LL_USART_DIV_SAMPLING16(PeriphClk, BaudRate)); +} + +/** + * @brief Return current Baud Rate value, according to USARTDIV present in BRR register + * (full BRR content), and to used Peripheral Clock and Oversampling mode values + * @note In case of non-initialized or invalid value stored in BRR register, value 0 will be returned. + * @rmtoll BRR BRR LL_USART_GetBaudRate + * @param USARTx USART Instance + * @param PeriphClk Peripheral Clock + * @retval Baud Rate + */ +__STATIC_INLINE uint32_t LL_USART_GetBaudRate(USART_TypeDef *USARTx, uint32_t PeriphClk) +{ + register uint32_t usartdiv = 0x0U; + register uint32_t brrresult = 0x0U; + + usartdiv = USARTx->BRR; + + if ((usartdiv & 0xFFFFU) != 0U) + { + brrresult = PeriphClk / usartdiv; + } + return (brrresult); +} +#endif /* USART_OverSampling_Feature */ + +/** + * @} + */ + + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Configuration_HalfDuplex Configuration functions related to Half Duplex feature + * @{ + */ + +/** + * @brief Enable Single Wire Half-Duplex mode + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_EnableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableHalfDuplex(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Disable Single Wire Half-Duplex mode + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_DisableHalfDuplex + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableHalfDuplex(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Indicate if Single Wire Half-Duplex mode is enabled + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @rmtoll CR3 HDSEL LL_USART_IsEnabledHalfDuplex + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledHalfDuplex(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_HDSEL) == (USART_CR3_HDSEL)); +} + +/** + * @} + */ + + +/** + * @} + */ + +/** @defgroup USART_LL_EF_AdvancedConfiguration Advanced Configurations services + * @{ + */ + +/** + * @brief Perform basic configuration of USART for enabling use in Asynchronous Mode (UART) + * @note In UART mode, the following bits must be kept cleared: + * - CLKEN bit in the USART_CR2 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Asynchronous Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigAsyncMode\n + * CR3 HDSEL LL_USART_ConfigAsyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigAsyncMode(USART_TypeDef *USARTx) +{ + /* In Asynchronous mode, the following bits must be kept cleared: + - CLKEN bits in the USART_CR2 register, + - HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Synchronous Mode + * @note In Synchronous mode, the following bits must be kept cleared: + * - HDSEL bit in the USART_CR3 register. + * This function also sets the USART in Synchronous mode. + * @note Macro @ref IS_USART_INSTANCE(USARTx) can be used to check whether or not + * Synchronous mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * - Set CLKEN in CR2 using @ref LL_USART_EnableSCLKOutput() function + * @note Other remaining configurations items related to Synchronous Mode + * (as Baud Rate, Word length, Parity, Clock Polarity, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigSyncMode\n + * CR3 HDSEL LL_USART_ConfigSyncMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigSyncMode(USART_TypeDef *USARTx) +{ + /* In Synchronous mode, the following bits must be kept cleared: + - HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); + /* set the UART/USART in Synchronous mode */ + SET_BIT(USARTx->CR2, USART_CR2_CLKEN); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Half Duplex Mode + * @note In Half Duplex mode, the following bits must be kept cleared: + * - CLKEN bit in the USART_CR2 register, + * This function also sets the UART/USART in Half Duplex mode. + * @note Macro @ref IS_UART_HALFDUPLEX_INSTANCE(USARTx) can be used to check whether or not + * Half-Duplex mode is supported by the USARTx instance. + * @note Call of this function is equivalent to following function call sequence : + * - Set HDSEL in CR3 using @ref LL_USART_EnableHalfDuplex() function + * @note Other remaining configurations items related to Half Duplex Mode + * (as Baud Rate, Word length, Parity, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigHalfDuplexMode\n + * CR3 HDSEL LL_USART_ConfigHalfDuplexMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigHalfDuplexMode(USART_TypeDef *USARTx) +{ + /* In Half Duplex mode, the following bits must be kept cleared: + - CLKEN bits in the USART_CR2 register */ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); + /* set the UART/USART in Half Duplex mode */ + SET_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Perform basic configuration of USART for enabling use in Multi processor Mode + * (several USARTs connected in a network, one of the USARTs can be the master, + * its TX output connected to the RX inputs of the other slaves USARTs). + * @note In MultiProcessor mode, the following bits must be kept cleared: + * - CLKEN bit in the USART_CR2 register, + * - HDSEL bit in the USART_CR3 register. + * @note Call of this function is equivalent to following function call sequence : + * - Clear CLKEN in CR2 using @ref LL_USART_DisableSCLKOutput() function + * - Clear HDSEL in CR3 using @ref LL_USART_DisableHalfDuplex() function + * @note Other remaining configurations items related to Multi processor Mode + * (as Baud Rate, Wake Up Method, Node address, ...) should be set using + * dedicated functions + * @rmtoll CR2 CLKEN LL_USART_ConfigMultiProcessMode\n + * CR3 HDSEL LL_USART_ConfigMultiProcessMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ConfigMultiProcessMode(USART_TypeDef *USARTx) +{ + /* In Multi Processor mode, the following bits must be kept cleared: + - CLKEN bits in the USART_CR2 register, + - HDSEL bits in the USART_CR3 register.*/ + CLEAR_BIT(USARTx->CR2, USART_CR2_CLKEN); + CLEAR_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_FLAG_Management FLAG_Management + * @{ + */ + +/** + * @brief Check if the USART Parity Error Flag is set or not + * @rmtoll SR PE LL_USART_IsActiveFlag_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_PE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_PE) == (USART_SR_PE)); +} + +/** + * @brief Check if the USART Framing Error Flag is set or not + * @rmtoll SR FE LL_USART_IsActiveFlag_FE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_FE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_FE) == (USART_SR_FE)); +} + +/** + * @brief Check if the USART Noise error detected Flag is set or not + * @rmtoll SR NF LL_USART_IsActiveFlag_NE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_NE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_NE) == (USART_SR_NE)); +} + +/** + * @brief Check if the USART OverRun Error Flag is set or not + * @rmtoll SR ORE LL_USART_IsActiveFlag_ORE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ORE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_ORE) == (USART_SR_ORE)); +} + +/** + * @brief Check if the USART IDLE line detected Flag is set or not + * @rmtoll SR IDLE LL_USART_IsActiveFlag_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_IDLE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_IDLE) == (USART_SR_IDLE)); +} + +/** + * @brief Check if the USART Read Data Register Not Empty Flag is set or not + * @rmtoll SR RXNE LL_USART_IsActiveFlag_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RXNE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_RXNE) == (USART_SR_RXNE)); +} + +/** + * @brief Check if the USART Transmission Complete Flag is set or not + * @rmtoll SR TC LL_USART_IsActiveFlag_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TC(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_TC) == (USART_SR_TC)); +} + +/** + * @brief Check if the USART Transmit Data Register Empty Flag is set or not + * @rmtoll SR TXE LL_USART_IsActiveFlag_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_TXE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_TXE) == (USART_SR_TXE)); +} + +/** + * @brief Check if the USART CTS Flag is set or not + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll SR CTS LL_USART_IsActiveFlag_nCTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_nCTS(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_CTS) == (USART_SR_CTS)); +} + +/** + * @brief Check if the USART ABRF Flag is set or not + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRF(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_ABRF) == (USART_SR_ABRF)); +} + +/** + * @brief Check if the USART ABRE Flag is set or not + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_ABRE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->SR, USART_SR_ABRE) == (USART_SR_ABRE)); +} + +/** + * @brief Check if the USART Send Break Flag is set or not + * @rmtoll CR1 SBK LL_USART_IsActiveFlag_SBK + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_SBK(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_SBK) == (USART_CR1_SBK)); +} + +/** + * @brief Check if the USART Receive Wake Up from mute mode Flag is set or not + * @rmtoll CR1 RWU LL_USART_IsActiveFlag_RWU + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsActiveFlag_RWU(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RWU) == (USART_CR1_RWU)); +} + +/** + * @brief Clear Parity Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * NE, FE, ORE, IDLE would also be cleared. + * @rmtoll SR PE LL_USART_ClearFlag_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_PE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Framing Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, ORE, IDLE would also be cleared. + * @rmtoll SR FE LL_USART_ClearFlag_FE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_FE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Noise detected Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, FE, ORE, IDLE would also be cleared. + * @rmtoll SR NF LL_USART_ClearFlag_NE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_NE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear OverRun Error Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, FE, IDLE would also be cleared. + * @rmtoll SR ORE LL_USART_ClearFlag_ORE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_ORE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear IDLE line detected Flag + * @note Clearing this flag is done by a read access to the USARTx_SR + * register followed by a read access to the USARTx_DR register. + * @note Please also consider that when clearing this flag, other flags as + * PE, NE, FE, ORE would also be cleared. + * @rmtoll SR IDLE LL_USART_ClearFlag_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_IDLE(USART_TypeDef *USARTx) +{ + __IO uint32_t tmpreg; + tmpreg = USARTx->SR; + (void) tmpreg; + tmpreg = USARTx->DR; + (void) tmpreg; +} + +/** + * @brief Clear Transmission Complete Flag + * @rmtoll SR TC LL_USART_ClearFlag_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_TC(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_TC)); +} + +/** + * @brief Clear RX Not Empty Flag + * @rmtoll SR RXNE LL_USART_ClearFlag_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_RXNE(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_RXNE)); +} + +/** + * @brief Clear CTS Interrupt Flag + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll SR CTS LL_USART_ClearFlag_nCTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_ClearFlag_nCTS(USART_TypeDef *USARTx) +{ + WRITE_REG(USARTx->SR, ~(USART_SR_CTS)); +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_IT_Management IT_Management + * @{ + */ + +/** + * @brief Enable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_EnableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_IDLE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Enable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_EnableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_RXNE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Enable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_EnableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TC(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Enable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_EnableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_TXE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Enable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_EnableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_PE(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Enable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. + * @rmtoll CR3 EIE LL_USART_EnableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_ERROR(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Enable CTS Interrupt + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_EnableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableIT_CTS(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Disable IDLE Interrupt + * @rmtoll CR1 IDLEIE LL_USART_DisableIT_IDLE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_IDLE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_IDLEIE); +} + +/** + * @brief Disable RX Not Empty Interrupt + * @rmtoll CR1 RXNEIE LL_USART_DisableIT_RXNE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_RXNE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RXNEIE); +} + +/** + * @brief Disable Transmission Complete Interrupt + * @rmtoll CR1 TCIE LL_USART_DisableIT_TC + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TC(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TCIE); +} + +/** + * @brief Disable TX Empty Interrupt + * @rmtoll CR1 TXEIE LL_USART_DisableIT_TXE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_TXE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_TXEIE); +} + +/** + * @brief Disable Parity Error Interrupt + * @rmtoll CR1 PEIE LL_USART_DisableIT_PE + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_PE(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_PEIE); +} + +/** + * @brief Disable Error Interrupt + * @note When set, Error Interrupt Enable Bit is enabling interrupt generation in case of a framing + * error, overrun error or noise flag (FE=1 or ORE=1 or NF=1 in the USARTx_SR register). + * 0: Interrupt is inhibited + * 1: An interrupt is generated when FE=1 or ORE=1 or NF=1 in the USARTx_SR register. + * @rmtoll CR3 EIE LL_USART_DisableIT_ERROR + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_ERROR(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_EIE); +} + +/** + * @brief Disable CTS Interrupt + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_DisableIT_CTS + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableIT_CTS(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_CTSIE); +} + +/** + * @brief Check if the USART IDLE Interrupt source is enabled or disabled. + * @rmtoll CR1 IDLEIE LL_USART_IsEnabledIT_IDLE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_IDLE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_IDLEIE) == (USART_CR1_IDLEIE)); +} + +/** + * @brief Check if the USART RX Not Empty Interrupt is enabled or disabled. + * @rmtoll CR1 RXNEIE LL_USART_IsEnabledIT_RXNE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_RXNE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_RXNEIE) == (USART_CR1_RXNEIE)); +} + +/** + * @brief Check if the USART Transmission Complete Interrupt is enabled or disabled. + * @rmtoll CR1 TCIE LL_USART_IsEnabledIT_TC + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TC(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TCIE) == (USART_CR1_TCIE)); +} + +/** + * @brief Check if the USART TX Empty Interrupt is enabled or disabled. + * @rmtoll CR1 TXEIE LL_USART_IsEnabledIT_TXE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_TXE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_TXEIE) == (USART_CR1_TXEIE)); +} + +/** + * @brief Check if the USART Parity Error Interrupt is enabled or disabled. + * @rmtoll CR1 PEIE LL_USART_IsEnabledIT_PE + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_PE(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR1, USART_CR1_PEIE) == (USART_CR1_PEIE)); +} + + +/** + * @brief Check if the USART Error Interrupt is enabled or disabled. + * @rmtoll CR3 EIE LL_USART_IsEnabledIT_ERROR + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_ERROR(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_EIE) == (USART_CR3_EIE)); +} + +/** + * @brief Check if the USART CTS Interrupt is enabled or disabled. + * @note Macro @ref IS_UART_HWFLOW_INSTANCE(USARTx) can be used to check whether or not + * Hardware Flow control feature is supported by the USARTx instance. + * @rmtoll CR3 CTSIE LL_USART_IsEnabledIT_CTS + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledIT_CTS(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_CTSIE) == (USART_CR3_CTSIE)); +} + +/** + * @} + */ + +#if (defined(DMA1) || defined(DMA)) +/** @defgroup USART_LL_EF_DMA_Management DMA_Management + * @{ + */ + +/** + * @brief Enable DMA Mode for reception + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR3 DMAR LL_USART_EnableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_RX(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Disable DMA Mode for reception + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR3 DMAR LL_USART_DisableDMAReq_RX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_RX(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DMAR); +} + +/** + * @brief Check if DMA Mode is enabled for reception + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR3 DMAR LL_USART_IsEnabledDMAReq_RX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_RX(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAR) == (USART_CR3_DMAR)); +} + +/** + * @brief Enable DMA Mode for transmission + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR3 DMAT LL_USART_EnableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableDMAReq_TX(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Disable DMA Mode for transmission + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR3 DMAT LL_USART_DisableDMAReq_TX + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableDMAReq_TX(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_DMAT); +} + +/** + * @brief Check if DMA Mode is enabled for transmission + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll CR3 DMAT LL_USART_IsEnabledDMAReq_TX + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledDMAReq_TX(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_DMAT) == (USART_CR3_DMAT)); +} + +/** + * @brief Get the data register address used for DMA transfer + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @rmtoll DR DR LL_USART_DMA_GetRegAddr + * @note Address of Data Register is valid for both Transmit and Receive transfers. + * @param USARTx USART Instance + * @retval Address of data register + */ +__STATIC_INLINE uint32_t LL_USART_DMA_GetRegAddr(USART_TypeDef *USARTx) +{ + /* return address of DR register */ + return ((uint32_t) & (USARTx->DR)); +} +#endif /* DMA1 or DMA */ + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Data_Management Data_Management + * @{ + */ + +/** + * @brief Read Receiver Data register (Receive Data value, 8 bits) + * @rmtoll DR DR LL_USART_ReceiveData8 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0xFF + */ +__STATIC_INLINE uint8_t LL_USART_ReceiveData8(USART_TypeDef *USARTx) +{ + return (uint8_t)(READ_BIT(USARTx->DR, USART_DR_DR)); +} + +/** + * @brief Read Receiver Data register (Receive Data value, 9 bits) + * @rmtoll DR DR LL_USART_ReceiveData9 + * @param USARTx USART Instance + * @retval Value between Min_Data=0x00 and Max_Data=0x1FF + */ +__STATIC_INLINE uint16_t LL_USART_ReceiveData9(USART_TypeDef *USARTx) +{ + return (uint16_t)(READ_BIT(USARTx->DR, USART_DR_DR)); +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 8 bits) + * @rmtoll DR DR LL_USART_TransmitData8 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0xFF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData8(USART_TypeDef *USARTx, uint8_t Value) +{ + USARTx->DR = Value; +} + +/** + * @brief Write in Transmitter Data Register (Transmit Data value, 9 bits) + * @rmtoll DR DR LL_USART_TransmitData9 + * @param USARTx USART Instance + * @param Value between Min_Data=0x00 and Max_Data=0x1FF + * @retval None + */ +__STATIC_INLINE void LL_USART_TransmitData9(USART_TypeDef *USARTx, uint16_t Value) +{ + USARTx->DR = Value & 0x1FFU; +} + +/** + * @} + */ + +/** @defgroup USART_LL_EF_Execution Execution + * @{ + */ + +/** + * @brief Request Break sending + * @rmtoll CR1 SBK LL_USART_RequestBreakSending + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestBreakSending(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_SBK); +} + +/** + * @brief Put USART in Mute mode + * @rmtoll CR1 RWU LL_USART_RequestEnterMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestEnterMuteMode(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR1, USART_CR1_RWU); +} + +/** + * @brief Put USART in Active mode + * @rmtoll CR1 RWU LL_USART_RequestExitMuteMode + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_RequestExitMuteMode(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR1, USART_CR1_RWU); +} + +/** + * @} + */ + +/** + * @brief Enable automatic baud rate detection + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_EnableAutoBaudRate(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->CR3, USART_CR3_ABREN); +} + +/** + * @brief Disable automatic baud rate detection + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_DisableAutoBaudRate(USART_TypeDef *USARTx) +{ + CLEAR_BIT(USARTx->CR3, USART_CR3_ABREN); +} + +/** + * @brief Indicate if enable automatic baud rate detection + * @param USARTx USART Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_USART_IsEnabledAutoBaudRate(USART_TypeDef *USARTx) +{ + return (READ_BIT(USARTx->CR3, USART_CR3_ABREN) == (USART_CR3_ABREN)); +} + +/** + * @brief Set auto baud rate detection mode + * @param USARTx USART Instance + * @param mode This parameter can be one of the following values: + * @arg @ref LL_USART_AUTOBAUDRATE_ONSTARTBIT + * @arg @ref LL_USART_AUTOBAUDRATE_ONFALLINGEDGE + * @retval None + */ +__STATIC_INLINE void LL_USART_SetAutoBaudRateMode(USART_TypeDef *USARTx, uint32_t mode) +{ + MODIFY_REG(USARTx->CR3, USART_CR3_ABRMODE, mode); +} + +/** + * @brief Get auto baud rate detection mode + * @param USARTx USART Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_USART_AUTOBAUDRATE_ONSTARTBIT + * @arg @ref LL_USART_AUTOBAUDRATE_ONFALLINGEDGE + */ +__STATIC_INLINE uint32_t LL_USART_GetAutoBaudRateMode(USART_TypeDef *USARTx) +{ + return (uint32_t)(READ_BIT(USARTx->CR3, USART_CR3_ABRMODE)); +} + +/** + * @brief Request automatic baud rate detection + * @param USARTx USART Instance + * @retval None + */ +__STATIC_INLINE void LL_USART_SendAutoBaudRateReq(USART_TypeDef *USARTx) +{ + SET_BIT(USARTx->SR, USART_SR_ABRRQ); +} + +#if defined(USE_FULL_LL_DRIVER) +/** @defgroup USART_LL_EF_Init Initialization and de-initialization functions + * @{ + */ +ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx); +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct); +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct); +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct); +/** + * @} + */ +#endif /* USE_FULL_LL_DRIVER */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __PY32F0XX_LL_USART_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_utils.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_utils.h similarity index 99% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_utils.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_utils.h index e8e758e..e10fb54 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_utils.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_utils.h @@ -16,18 +16,18 @@ @endverbatim ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_wwdg.h b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_wwdg.h similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_wwdg.h rename to Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_wwdg.h index 8b4738f..ba02e5b 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_ll_wwdg.h +++ b/Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_wwdg.h @@ -1,321 +1,321 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_wwdg.h - * @author MCU Application Team - * @brief Header file of WWDG LL module. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -/* Define to prevent recursive inclusion -------------------------------------*/ -#ifndef PY32F0XX_LL_WWDG_H -#define PY32F0XX_LL_WWDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx.h" - -/** @addtogroup PY32F0XX_LL_Driver - * @{ - */ - -#if defined (WWDG) -/** @defgroup WWDG_LL WWDG - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Exported types ------------------------------------------------------------*/ -/* Exported constants --------------------------------------------------------*/ -/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants - * @{ - */ - -/** @defgroup WWDG_LL_EC_IT IT Defines - * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions - * @{ - */ -#define LL_WWDG_CFR_EWI WWDG_CFR_EWI -/** - * @} - */ - -/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER -* @{ -*/ -#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ -#define LL_WWDG_PRESCALER_2 ( WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/2 */ -#define LL_WWDG_PRESCALER_4 (WWDG_CFR_WDGTB_1 ) /*!< WWDG counter clock = (PCLK1/4096)/4 */ -#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ -/** - * @} - */ - -/** - * @} - */ - -/* Exported macro ------------------------------------------------------------*/ -/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros - * @{ - */ -/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros - * @{ - */ -/** - * @brief Write a value in WWDG register - * @param __INSTANCE__ WWDG Instance - * @param __REG__ Register to be written - * @param __VALUE__ Value to be written in the register - * @retval None - */ -#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) - -/** - * @brief Read a value in WWDG register - * @param __INSTANCE__ WWDG Instance - * @param __REG__ Register to be read - * @retval Register value - */ -#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) -/** - * @} - */ - -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions - * @{ - */ - -/** @defgroup WWDG_LL_EF_Configuration Configuration - * @{ - */ -/** - * @brief Enable Window Watchdog. The watchdog is always disabled after a reset. - * @note It is enabled by setting the WDGA bit in the WWDG_CR register, - * then it cannot be disabled again except by a reset. - * This bit is set by software and only cleared by hardware after a reset. - * When WDGA = 1, the watchdog can generate a reset. - * @rmtoll CR WDGA LL_WWDG_Enable - * @param WWDGx WWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) -{ - SET_BIT(WWDGx->CR, WWDG_CR_WDGA); -} - -/** - * @brief Checks if Window Watchdog is enabled - * @rmtoll CR WDGA LL_WWDG_IsEnabled - * @param WWDGx WWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) -{ - return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)); -} - -/** - * @brief Set the Watchdog counter value to provided value (7-bits T[6:0]) - * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset - * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles - * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) - * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled) - * @rmtoll CR T LL_WWDG_SetCounter - * @param WWDGx WWDG Instance - * @param Counter 0..0x7F (7 bit counter value) - * @retval None - */ -__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) -{ - MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter); -} - -/** - * @brief Return current Watchdog Counter Value (7 bits counter value) - * @rmtoll CR T LL_WWDG_GetCounter - * @param WWDGx WWDG Instance - * @retval 7 bit Watchdog Counter value - */ -__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) -{ - return (READ_BIT(WWDGx->CR, WWDG_CR_T)); -} - -/** - * @brief Set the time base of the prescaler (WDGTB). - * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter - * is decremented every (4096 x 2expWDGTB) PCLK cycles - * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler - * @param WWDGx WWDG Instance - * @param Prescaler This parameter can be one of the following values: - * @arg @ref LL_WWDG_PRESCALER_1 - * @arg @ref LL_WWDG_PRESCALER_2 - * @arg @ref LL_WWDG_PRESCALER_4 - * @arg @ref LL_WWDG_PRESCALER_8 - * @retval None - */ -__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler) -{ - MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler); -} - -/** - * @brief Return current Watchdog Prescaler Value - * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler - * @param WWDGx WWDG Instance - * @retval Returned value can be one of the following values: - * @arg @ref LL_WWDG_PRESCALER_1 - * @arg @ref LL_WWDG_PRESCALER_2 - * @arg @ref LL_WWDG_PRESCALER_4 - * @arg @ref LL_WWDG_PRESCALER_8 - */ -__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) -{ - return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); -} - -/** - * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]). - * @note This window value defines when write in the WWDG_CR register - * to program Watchdog counter is allowed. - * Watchdog counter value update must occur only when the counter value - * is lower than the Watchdog window register value. - * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value - * (in the control register) is refreshed before the downcounter has reached - * the watchdog window register value. - * Physically is possible to set the Window lower then 0x40 but it is not recommended. - * To generate an immediate reset, it is possible to set the Counter lower than 0x40. - * @rmtoll CFR W LL_WWDG_SetWindow - * @param WWDGx WWDG Instance - * @param Window 0x00..0x7F (7 bit Window value) - * @retval None - */ -__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) -{ - MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window); -} - -/** - * @brief Return current Watchdog Window Value (7 bits value) - * @rmtoll CFR W LL_WWDG_GetWindow - * @param WWDGx WWDG Instance - * @retval 7 bit Watchdog Window value - */ -__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) -{ - return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); -} - -/** - * @} - */ - -/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management - * @{ - */ -/** - * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not. - * @note This bit is set by hardware when the counter has reached the value 0x40. - * It must be cleared by software by writing 0. - * A write of 1 has no effect. This bit is also set if the interrupt is not enabled. - * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP - * @param WWDGx WWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) -{ - return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)); -} - -/** - * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF) - * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP - * @param WWDGx WWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx) -{ - WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF); -} - -/** - * @} - */ - -/** @defgroup WWDG_LL_EF_IT_Management IT_Management - * @{ - */ -/** - * @brief Enable the Early Wakeup Interrupt. - * @note When set, an interrupt occurs whenever the counter reaches value 0x40. - * This interrupt is only cleared by hardware after a reset - * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP - * @param WWDGx WWDG Instance - * @retval None - */ -__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) -{ - SET_BIT(WWDGx->CFR, WWDG_CFR_EWI); -} - -/** - * @brief Check if Early Wakeup Interrupt is enabled - * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP - * @param WWDGx WWDG Instance - * @retval State of bit (1 or 0). - */ -__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) -{ - return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* WWDG */ - -/** - * @} - */ - -#ifdef __cplusplus -} -#endif - -#endif /* PY32F0XX_LL_WWDG_H */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_wwdg.h + * @author MCU Application Team + * @brief Header file of WWDG LL module. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef PY32F0XX_LL_WWDG_H +#define PY32F0XX_LL_WWDG_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx.h" + +/** @addtogroup PY32F0XX_LL_Driver + * @{ + */ + +#if defined (WWDG) +/** @defgroup WWDG_LL WWDG + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Constants WWDG Exported Constants + * @{ + */ + +/** @defgroup WWDG_LL_EC_IT IT Defines + * @brief IT defines which can be used with LL_WWDG_ReadReg and LL_WWDG_WriteReg functions + * @{ + */ +#define LL_WWDG_CFR_EWI WWDG_CFR_EWI +/** + * @} + */ + +/** @defgroup WWDG_LL_EC_PRESCALER PRESCALER +* @{ +*/ +#define LL_WWDG_PRESCALER_1 0x00000000U /*!< WWDG counter clock = (PCLK1/4096)/1 */ +#define LL_WWDG_PRESCALER_2 ( WWDG_CFR_WDGTB_0) /*!< WWDG counter clock = (PCLK1/4096)/2 */ +#define LL_WWDG_PRESCALER_4 (WWDG_CFR_WDGTB_1 ) /*!< WWDG counter clock = (PCLK1/4096)/4 */ +#define LL_WWDG_PRESCALER_8 (WWDG_CFR_WDGTB_0 | WWDG_CFR_WDGTB_1) /*!< WWDG counter clock = (PCLK1/4096)/8 */ +/** + * @} + */ + +/** + * @} + */ + +/* Exported macro ------------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Macros WWDG Exported Macros + * @{ + */ +/** @defgroup WWDG_LL_EM_WRITE_READ Common Write and read registers macros + * @{ + */ +/** + * @brief Write a value in WWDG register + * @param __INSTANCE__ WWDG Instance + * @param __REG__ Register to be written + * @param __VALUE__ Value to be written in the register + * @retval None + */ +#define LL_WWDG_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__)) + +/** + * @brief Read a value in WWDG register + * @param __INSTANCE__ WWDG Instance + * @param __REG__ Register to be read + * @retval Register value + */ +#define LL_WWDG_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__) +/** + * @} + */ + +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @defgroup WWDG_LL_Exported_Functions WWDG Exported Functions + * @{ + */ + +/** @defgroup WWDG_LL_EF_Configuration Configuration + * @{ + */ +/** + * @brief Enable Window Watchdog. The watchdog is always disabled after a reset. + * @note It is enabled by setting the WDGA bit in the WWDG_CR register, + * then it cannot be disabled again except by a reset. + * This bit is set by software and only cleared by hardware after a reset. + * When WDGA = 1, the watchdog can generate a reset. + * @rmtoll CR WDGA LL_WWDG_Enable + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_Enable(WWDG_TypeDef *WWDGx) +{ + SET_BIT(WWDGx->CR, WWDG_CR_WDGA); +} + +/** + * @brief Checks if Window Watchdog is enabled + * @rmtoll CR WDGA LL_WWDG_IsEnabled + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabled(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CR, WWDG_CR_WDGA) == (WWDG_CR_WDGA)); +} + +/** + * @brief Set the Watchdog counter value to provided value (7-bits T[6:0]) + * @note When writing to the WWDG_CR register, always write 1 in the MSB b6 to avoid generating an immediate reset + * This counter is decremented every (4096 x 2expWDGTB) PCLK cycles + * A reset is produced when it rolls over from 0x40 to 0x3F (bit T6 becomes cleared) + * Setting the counter lower then 0x40 causes an immediate reset (if WWDG enabled) + * @rmtoll CR T LL_WWDG_SetCounter + * @param WWDGx WWDG Instance + * @param Counter 0..0x7F (7 bit counter value) + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetCounter(WWDG_TypeDef *WWDGx, uint32_t Counter) +{ + MODIFY_REG(WWDGx->CR, WWDG_CR_T, Counter); +} + +/** + * @brief Return current Watchdog Counter Value (7 bits counter value) + * @rmtoll CR T LL_WWDG_GetCounter + * @param WWDGx WWDG Instance + * @retval 7 bit Watchdog Counter value + */ +__STATIC_INLINE uint32_t LL_WWDG_GetCounter(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CR, WWDG_CR_T)); +} + +/** + * @brief Set the time base of the prescaler (WDGTB). + * @note Prescaler is used to apply ratio on PCLK clock, so that Watchdog counter + * is decremented every (4096 x 2expWDGTB) PCLK cycles + * @rmtoll CFR WDGTB LL_WWDG_SetPrescaler + * @param WWDGx WWDG Instance + * @param Prescaler This parameter can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetPrescaler(WWDG_TypeDef *WWDGx, uint32_t Prescaler) +{ + MODIFY_REG(WWDGx->CFR, WWDG_CFR_WDGTB, Prescaler); +} + +/** + * @brief Return current Watchdog Prescaler Value + * @rmtoll CFR WDGTB LL_WWDG_GetPrescaler + * @param WWDGx WWDG Instance + * @retval Returned value can be one of the following values: + * @arg @ref LL_WWDG_PRESCALER_1 + * @arg @ref LL_WWDG_PRESCALER_2 + * @arg @ref LL_WWDG_PRESCALER_4 + * @arg @ref LL_WWDG_PRESCALER_8 + */ +__STATIC_INLINE uint32_t LL_WWDG_GetPrescaler(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CFR, WWDG_CFR_WDGTB)); +} + +/** + * @brief Set the Watchdog Window value to be compared to the downcounter (7-bits W[6:0]). + * @note This window value defines when write in the WWDG_CR register + * to program Watchdog counter is allowed. + * Watchdog counter value update must occur only when the counter value + * is lower than the Watchdog window register value. + * Otherwise, a MCU reset is generated if the 7-bit Watchdog counter value + * (in the control register) is refreshed before the downcounter has reached + * the watchdog window register value. + * Physically is possible to set the Window lower then 0x40 but it is not recommended. + * To generate an immediate reset, it is possible to set the Counter lower than 0x40. + * @rmtoll CFR W LL_WWDG_SetWindow + * @param WWDGx WWDG Instance + * @param Window 0x00..0x7F (7 bit Window value) + * @retval None + */ +__STATIC_INLINE void LL_WWDG_SetWindow(WWDG_TypeDef *WWDGx, uint32_t Window) +{ + MODIFY_REG(WWDGx->CFR, WWDG_CFR_W, Window); +} + +/** + * @brief Return current Watchdog Window Value (7 bits value) + * @rmtoll CFR W LL_WWDG_GetWindow + * @param WWDGx WWDG Instance + * @retval 7 bit Watchdog Window value + */ +__STATIC_INLINE uint32_t LL_WWDG_GetWindow(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CFR, WWDG_CFR_W)); +} + +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_FLAG_Management FLAG_Management + * @{ + */ +/** + * @brief Indicates if the WWDG Early Wakeup Interrupt Flag is set or not. + * @note This bit is set by hardware when the counter has reached the value 0x40. + * It must be cleared by software by writing 0. + * A write of 1 has no effect. This bit is also set if the interrupt is not enabled. + * @rmtoll SR EWIF LL_WWDG_IsActiveFlag_EWKUP + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsActiveFlag_EWKUP(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->SR, WWDG_SR_EWIF) == (WWDG_SR_EWIF)); +} + +/** + * @brief Clear WWDG Early Wakeup Interrupt Flag (EWIF) + * @rmtoll SR EWIF LL_WWDG_ClearFlag_EWKUP + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_ClearFlag_EWKUP(WWDG_TypeDef *WWDGx) +{ + WRITE_REG(WWDGx->SR, ~WWDG_SR_EWIF); +} + +/** + * @} + */ + +/** @defgroup WWDG_LL_EF_IT_Management IT_Management + * @{ + */ +/** + * @brief Enable the Early Wakeup Interrupt. + * @note When set, an interrupt occurs whenever the counter reaches value 0x40. + * This interrupt is only cleared by hardware after a reset + * @rmtoll CFR EWI LL_WWDG_EnableIT_EWKUP + * @param WWDGx WWDG Instance + * @retval None + */ +__STATIC_INLINE void LL_WWDG_EnableIT_EWKUP(WWDG_TypeDef *WWDGx) +{ + SET_BIT(WWDGx->CFR, WWDG_CFR_EWI); +} + +/** + * @brief Check if Early Wakeup Interrupt is enabled + * @rmtoll CFR EWI LL_WWDG_IsEnabledIT_EWKUP + * @param WWDGx WWDG Instance + * @retval State of bit (1 or 0). + */ +__STATIC_INLINE uint32_t LL_WWDG_IsEnabledIT_EWKUP(WWDG_TypeDef *WWDGx) +{ + return (READ_BIT(WWDGx->CFR, WWDG_CFR_EWI) == (WWDG_CFR_EWI)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* WWDG */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* PY32F0XX_LL_WWDG_H */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_adc.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_adc.c similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_adc.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_adc.c index 808d8eb..cc636ff 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_adc.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_adc.c @@ -1,582 +1,582 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_adc.c - * @author MCU Application Team - * @brief ADC LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_adc.h" -#include "py32f0xx_ll_bus.h" - - -#ifdef USE_FULL_ASSERT -#include "PY32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (ADC1) - -/** @addtogroup ADC_LL ADC - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup ADC_LL_Private_Constants - * @{ - */ - -/* Definitions of ADC hardware constraints delays */ -/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ -/* not timeout values: */ -/* Timeout values for ADC operations are dependent to device clock */ -/* configuration (system clock versus ADC clock), */ -/* and therefore must be defined in user application. */ -/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ -/* values definition. */ -/* Unit: CPU cycles. */ -#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U) -#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) -#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ - -/** @addtogroup ADC_LL_Private_Macros - * @{ - */ - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* common to several ADC instances. */ -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* ADC instance. */ -#define IS_LL_ADC_CLOCK(__CLOCK__) \ - ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV64) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV32) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV16) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ - || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV64) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV32) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV16) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV8) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV4) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV2) \ - || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV1) \ - ) - -#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ - ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ - || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ - || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ - || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ - ) - -#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ - ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ - || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ - ) - -#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ - ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ - || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ - ) - -/* Check of parameters for configuration of ADC hierarchical scope: */ -/* ADC group regular */ -#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ - ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \ - || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ - ) - -#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ - ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ - || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ - ) - -#if (defined(DMA) || defined(DMA1)) -#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ - ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ - || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ - || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ - ) -#endif - -#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ - ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ - || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ - ) - -#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ - ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ - || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ - ) - -/** - * @} - */ - - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup ADC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup ADC_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize registers of all ADC instances belonging to - * the same ADC common instance to their default reset values. - * @note This function is performing a hard reset, using high level - * clock source RCC ADC reset. - * @param ADCxy_COMMON ADC common instance - * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC common registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) -{ - /* Check the parameters */ - assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); - - /* Force reset of ADC clock (core clock) */ - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1); - - /* Release reset of ADC clock (core clock) */ - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1); - - return SUCCESS; -} - -/** - * @brief De-initialize registers of the selected ADC instance - * to their default reset values. - * @note To reset all ADC instances quickly (perform a hard reset), - * use function @ref LL_ADC_CommonDeInit(). - * @note If this functions returns error status, it means that ADC instance - * is in an unknown state. - * In this case, perform a hard reset using high level - * clock source RCC ADC reset. - * Refer to function @ref LL_ADC_CommonDeInit(). - * @param ADCx ADC instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are de-initialized - * - ERROR: ADC registers are not de-initialized - */ -ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) -{ - ErrorStatus status = SUCCESS; - - __IO uint32_t timeout_cpu_cycles = 0U; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - - /* Disable ADC instance if not already disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 1U) - { - /* Set ADC group regular trigger source to SW start to ensure to not */ - /* have an external trigger event occurring during the conversion stop */ - /* ADC disable process. */ - LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); - - /* Stop potential ADC conversion on going on ADC group regular. */ - if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U) - { - if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U) - { - LL_ADC_REG_StopConversion(ADCx); - } - } - else - { - (ADCx->CFGR1)|=(0x7<<6); - (ADCx->CFGR1)|=(0x3<<10); - __disable_irq(); - LL_ADC_REG_StartConversion(ADCx); - LL_ADC_REG_StopConversion(ADCx); - __enable_irq(); - } - - /* Wait for ADC conversions are effectively stopped */ - timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; - while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U) - { - if(timeout_cpu_cycles-- == 0U) - { - /* Time-out error */ - status = ERROR; - } - } - - /* Wait for ADC instance is effectively disabled */ - timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; - while (LL_ADC_IsEnabled(ADCx) == 1U) - { - if(timeout_cpu_cycles-- == 0U) - { - /* Time-out error */ - status = ERROR; - } - } - } - - /* Check whether ADC state is compliant with expected state */ - if(READ_BIT(ADCx->CR,(ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADEN ))== 0U) - { - /* ========== Reset ADC registers ========== */ - /* Reset register IER */ - CLEAR_BIT(ADCx->IER, - ( LL_ADC_IT_EOC - | LL_ADC_IT_EOS - | LL_ADC_IT_OVR - | LL_ADC_IT_EOSMP - | LL_ADC_IT_AWD ) - ); - - /* Reset register ISR */ - SET_BIT(ADCx->ISR, - ( LL_ADC_FLAG_EOC - | LL_ADC_FLAG_EOS - | LL_ADC_FLAG_OVR - | LL_ADC_FLAG_EOSMP - | LL_ADC_FLAG_AWD ) - ); - - /* Reset register CR */ - /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ - /* "read-set": no direct reset applicable. */ - /* No action on register CR */ - - /* Reset register CFGR1 */ -#if (defined(DMA) || defined(DMA1)) - CLEAR_BIT(ADCx->CFGR1, - ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN - | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD - | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RESSEL - | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ) - ); -#else - CLEAR_BIT(ADCx->CFGR1, - ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN - | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD - | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RESSEL - | ADC_CFGR1_SCANDIR ) - ); -#endif - - /* Reset register CFGR2 */ - /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ - /* already done above. */ - CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE); - - /* Reset register SMPR */ - CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP); - - /* Reset register TR */ - MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT); - - /* Reset register CHSELR */ - - CLEAR_BIT(ADCx->CHSELR, - ( ADC_CHSELR_CHSEL12 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 - | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 - | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ) - ); - - /* Reset register CCR */ - CLEAR_BIT(__LL_ADC_COMMON_INSTANCE(ADC1)->CCR,ADC_CCR_TSEN | ADC_CCR_VREFEN); - - /* Reset register DR */ - /* bits in access mode read only, no direct reset applicable */ - - } - else - { - /* ADC instance is in an unknown state */ - /* Need to performing a hard reset of ADC instance, using high level */ - /* clock source RCC ADC reset. */ - /* Caution: On this PY32 serie, if several ADC instances are available */ - /* on the selected device, RCC ADC reset will reset */ - /* all ADC instances belonging to the common ADC instance. */ - status = ERROR; - } - - return status; -} - - -/** - * @brief Initialize some features of ADC instance. - * @note These parameters have an impact on ADC scope: ADC instance. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Instance . - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all PY32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - * @note After using this function, some other features must be configured - * using LL unitary functions. - * The minimum configuration remaining to be done is: - * - Set ADC group regular sequencer: - * map channel on rank corresponding to channel number. - * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); - * - Set ADC channel sampling time - * Refer to function LL_ADC_SetChannelSamplingTime(); - * @param ADCx ADC instance - * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are initialized - * - ERROR: ADC registers are not initialized - */ -ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - - assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock)); - assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); - assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); - assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); - - /* Note: Hardware constraint (refer to description of this function): */ - /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) - { - /* Configuration of ADC hierarchical scope: */ - /* - ADC instance */ - /* - Set ADC data resolution */ - /* - Set ADC conversion data alignment */ - /* - Set ADC low power mode */ - MODIFY_REG(ADCx->CFGR1, - ADC_CFGR1_RESSEL - | ADC_CFGR1_ALIGN - | ADC_CFGR1_WAIT - , - ADC_InitStruct->Resolution - | ADC_InitStruct->DataAlignment - | ADC_InitStruct->LowPowerMode - ); - - MODIFY_REG(ADCx->CFGR2, - ADC_CFGR2_CKMODE - , - ADC_InitStruct->Clock - ); - } - else - { - /* Initialization error: ADC instance is not disabled. */ - status = ERROR; - } - return status; -} - -/** - * @brief Set each @ref LL_ADC_InitTypeDef field to default value. - * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) -{ - /* Set ADC_InitStruct fields to default values */ - /* Set fields of ADC instance */ - ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; - ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; - ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; - ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; -} - - -/** - * @brief Initialize some features of ADC group regular. - * @note These parameters have an impact on ADC scope: ADC group regular. - * Refer to corresponding unitary functions into - * @ref ADC_LL_EF_Configuration_ADC_Group_Regular - * (functions with prefix "REG"). - * @note The setting of these parameters by function @ref LL_ADC_Init() - * is conditioned to ADC state: - * ADC instance must be disabled. - * This condition is applied to all ADC features, for efficiency - * and compatibility over all PY32 families. However, the different - * features can be set under different ADC state conditions - * (setting possible with ADC enabled without conversion on going, - * ADC enabled with conversion on going, ...) - * Each feature can be updated afterwards with a unitary function - * and potentially with ADC in a different state than disabled, - * refer to description of each function for setting - * conditioned to ADC state. - * @note After using this function, other features must be configured - * using LL unitary functions. - * The minimum configuration remaining to be done is: - * - Set ADC group regular sequencer: - * map channel on rank corresponding to channel number. - * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); - * - Set ADC channel sampling time - * Refer to function LL_ADC_SetChannelSamplingTime(); - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @param ADCx ADC instance - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ADC registers are initialized - * - ERROR: ADC registers are not initialized - */ -ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_ADC_ALL_INSTANCE(ADCx)); - assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); - assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); - assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); -#if (defined(DMA) || defined(DMA1)) - assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); -#endif - assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); - - /* Note: Hardware constraint (refer to description of this function): */ - /* ADC instance must be disabled. */ - if(LL_ADC_IsEnabled(ADCx) == 0U) - { - /* Configuration of ADC hierarchical scope: */ - /* - ADC group regular */ - /* - Set ADC group regular trigger source */ - /* - Set ADC group regular sequencer discontinuous mode */ - /* - Set ADC group regular continuous mode */ - /* - Set ADC group regular conversion data transfer: no transfer or */ - /* transfer by DMA, and DMA requests mode */ - /* - Set ADC group regular overrun behavior */ - /* Note: On this PY32 serie, ADC trigger edge is set to value 0x0 by */ - /* setting of trigger source to SW start. */ - -#if (defined(DMA) || defined(DMA1)) - MODIFY_REG(ADCx->CFGR1, - ADC_CFGR1_EXTSEL - | ADC_CFGR1_EXTEN - | ADC_CFGR1_DISCEN - | ADC_CFGR1_CONT - | ADC_CFGR1_DMAEN - | ADC_CFGR1_DMACFG - | ADC_CFGR1_OVRMOD - , - ADC_REG_InitStruct->TriggerSource - | ADC_REG_InitStruct->SequencerDiscont - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->DMATransfer - | ADC_REG_InitStruct->Overrun - ); -#else - MODIFY_REG(ADCx->CFGR1, - ADC_CFGR1_EXTSEL - | ADC_CFGR1_EXTEN - | ADC_CFGR1_DISCEN - | ADC_CFGR1_CONT - | ADC_CFGR1_OVRMOD - , - ADC_REG_InitStruct->TriggerSource - | ADC_REG_InitStruct->SequencerDiscont - | ADC_REG_InitStruct->ContinuousMode - | ADC_REG_InitStruct->Overrun - ); -#endif - } - else - { - /* Initialization error: ADC instance is not disabled. */ - status = ERROR; - } - return status; -} - -/** - * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. - * @note Depending on devices and packages, DMA may not be available. - * Refer to device datasheet for DMA availability. - * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) -{ - /* Set ADC_REG_InitStruct fields to default values */ - /* Set fields of ADC group regular */ - /* Note: On this PY32 serie, ADC trigger edge is set to value 0x0 by */ - /* setting of trigger source to SW start. */ - ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; - ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; - ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; -#if (defined(DMA) || defined(DMA1)) - ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; -#endif - ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* ADC1 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_adc.c + * @author MCU Application Team + * @brief ADC LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_adc.h" +#include "py32f0xx_ll_bus.h" + + +#ifdef USE_FULL_ASSERT +#include "PY32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (ADC1) + +/** @addtogroup ADC_LL ADC + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup ADC_LL_Private_Constants + * @{ + */ + +/* Definitions of ADC hardware constraints delays */ +/* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */ +/* not timeout values: */ +/* Timeout values for ADC operations are dependent to device clock */ +/* configuration (system clock versus ADC clock), */ +/* and therefore must be defined in user application. */ +/* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */ +/* values definition. */ +/* Unit: CPU cycles. */ +#define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U) +#define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) +#define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U) + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup ADC_LL_Private_Macros + * @{ + */ + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* common to several ADC instances. */ +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC instance. */ +#define IS_LL_ADC_CLOCK(__CLOCK__) \ + ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV64) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV32) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV16) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV64) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV32) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV16) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV8) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV4) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV2) \ + || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_HSI_DIV1) \ + ) + +#define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \ + ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \ + || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \ + ) + +#define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \ + ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \ + || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \ + ) + +#define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \ + ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \ + || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \ + ) + +/* Check of parameters for configuration of ADC hierarchical scope: */ +/* ADC group regular */ +#define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \ + ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH4) \ + || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \ + ) + +#define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \ + ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \ + || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \ + ) + +#if (defined(DMA) || defined(DMA1)) +#define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \ + ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \ + || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \ + ) +#endif + +#define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \ + ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \ + || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \ + ) + +#define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \ + ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \ + || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \ + ) + +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup ADC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup ADC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize registers of all ADC instances belonging to + * the same ADC common instance to their default reset values. + * @note This function is performing a hard reset, using high level + * clock source RCC ADC reset. + * @param ADCxy_COMMON ADC common instance + * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() ) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC common registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON) +{ + /* Check the parameters */ + assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON)); + + /* Force reset of ADC clock (core clock) */ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_ADC1); + + /* Release reset of ADC clock (core clock) */ + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_ADC1); + + return SUCCESS; +} + +/** + * @brief De-initialize registers of the selected ADC instance + * to their default reset values. + * @note To reset all ADC instances quickly (perform a hard reset), + * use function @ref LL_ADC_CommonDeInit(). + * @note If this functions returns error status, it means that ADC instance + * is in an unknown state. + * In this case, perform a hard reset using high level + * clock source RCC ADC reset. + * Refer to function @ref LL_ADC_CommonDeInit(). + * @param ADCx ADC instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are de-initialized + * - ERROR: ADC registers are not de-initialized + */ +ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx) +{ + ErrorStatus status = SUCCESS; + + __IO uint32_t timeout_cpu_cycles = 0U; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + /* Disable ADC instance if not already disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 1U) + { + /* Set ADC group regular trigger source to SW start to ensure to not */ + /* have an external trigger event occurring during the conversion stop */ + /* ADC disable process. */ + LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE); + + /* Stop potential ADC conversion on going on ADC group regular. */ + if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U) + { + if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U) + { + LL_ADC_REG_StopConversion(ADCx); + } + } + else + { + (ADCx->CFGR1)|=(0x7<<6); + (ADCx->CFGR1)|=(0x3<<10); + __disable_irq(); + LL_ADC_REG_StartConversion(ADCx); + LL_ADC_REG_StopConversion(ADCx); + __enable_irq(); + } + + /* Wait for ADC conversions are effectively stopped */ + timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES; + while (LL_ADC_REG_IsStopConversionOngoing(ADCx) == 1U) + { + if(timeout_cpu_cycles-- == 0U) + { + /* Time-out error */ + status = ERROR; + } + } + + /* Wait for ADC instance is effectively disabled */ + timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES; + while (LL_ADC_IsEnabled(ADCx) == 1U) + { + if(timeout_cpu_cycles-- == 0U) + { + /* Time-out error */ + status = ERROR; + } + } + } + + /* Check whether ADC state is compliant with expected state */ + if(READ_BIT(ADCx->CR,(ADC_CR_ADSTP | ADC_CR_ADSTART | ADC_CR_ADEN ))== 0U) + { + /* ========== Reset ADC registers ========== */ + /* Reset register IER */ + CLEAR_BIT(ADCx->IER, + ( LL_ADC_IT_EOC + | LL_ADC_IT_EOS + | LL_ADC_IT_OVR + | LL_ADC_IT_EOSMP + | LL_ADC_IT_AWD ) + ); + + /* Reset register ISR */ + SET_BIT(ADCx->ISR, + ( LL_ADC_FLAG_EOC + | LL_ADC_FLAG_EOS + | LL_ADC_FLAG_OVR + | LL_ADC_FLAG_EOSMP + | LL_ADC_FLAG_AWD ) + ); + + /* Reset register CR */ + /* Bits ADC_CR_ADCAL, ADC_CR_ADSTP, ADC_CR_ADSTART are in access mode */ + /* "read-set": no direct reset applicable. */ + /* No action on register CR */ + + /* Reset register CFGR1 */ +#if (defined(DMA) || defined(DMA1)) + CLEAR_BIT(ADCx->CFGR1, + ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN + | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD + | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RESSEL + | ADC_CFGR1_SCANDIR | ADC_CFGR1_DMACFG | ADC_CFGR1_DMAEN ) + ); +#else + CLEAR_BIT(ADCx->CFGR1, + ( ADC_CFGR1_AWDCH | ADC_CFGR1_AWDEN | ADC_CFGR1_AWDSGL | ADC_CFGR1_DISCEN + | ADC_CFGR1_WAIT | ADC_CFGR1_CONT | ADC_CFGR1_OVRMOD + | ADC_CFGR1_EXTEN | ADC_CFGR1_EXTSEL | ADC_CFGR1_ALIGN | ADC_CFGR1_RESSEL + | ADC_CFGR1_SCANDIR ) + ); +#endif + + /* Reset register CFGR2 */ + /* Note: Update of ADC clock mode is conditioned to ADC state disabled: */ + /* already done above. */ + CLEAR_BIT(ADCx->CFGR2, ADC_CFGR2_CKMODE); + + /* Reset register SMPR */ + CLEAR_BIT(ADCx->SMPR, ADC_SMPR_SMP); + + /* Reset register TR */ + MODIFY_REG(ADCx->TR, ADC_TR_HT | ADC_TR_LT, ADC_TR_HT); + + /* Reset register CHSELR */ + + CLEAR_BIT(ADCx->CHSELR, + ( ADC_CHSELR_CHSEL12 | ADC_CHSELR_CHSEL11 | ADC_CHSELR_CHSEL9 | ADC_CHSELR_CHSEL8 + | ADC_CHSELR_CHSEL7 | ADC_CHSELR_CHSEL6 | ADC_CHSELR_CHSEL5 | ADC_CHSELR_CHSEL4 + | ADC_CHSELR_CHSEL3 | ADC_CHSELR_CHSEL2 | ADC_CHSELR_CHSEL1 | ADC_CHSELR_CHSEL0 ) + ); + + /* Reset register CCR */ + CLEAR_BIT(__LL_ADC_COMMON_INSTANCE(ADC1)->CCR,ADC_CCR_TSEN | ADC_CCR_VREFEN); + + /* Reset register DR */ + /* bits in access mode read only, no direct reset applicable */ + + } + else + { + /* ADC instance is in an unknown state */ + /* Need to performing a hard reset of ADC instance, using high level */ + /* clock source RCC ADC reset. */ + /* Caution: On this PY32 serie, if several ADC instances are available */ + /* on the selected device, RCC ADC reset will reset */ + /* all ADC instances belonging to the common ADC instance. */ + status = ERROR; + } + + return status; +} + + +/** + * @brief Initialize some features of ADC instance. + * @note These parameters have an impact on ADC scope: ADC instance. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Instance . + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all PY32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, some other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular sequencer: + * map channel on rank corresponding to channel number. + * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @param ADCx ADC instance + * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + + assert_param(IS_LL_ADC_CLOCK(ADC_InitStruct->Clock)); + assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution)); + assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment)); + assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0U) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC instance */ + /* - Set ADC data resolution */ + /* - Set ADC conversion data alignment */ + /* - Set ADC low power mode */ + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_RESSEL + | ADC_CFGR1_ALIGN + | ADC_CFGR1_WAIT + , + ADC_InitStruct->Resolution + | ADC_InitStruct->DataAlignment + | ADC_InitStruct->LowPowerMode + ); + + MODIFY_REG(ADCx->CFGR2, + ADC_CFGR2_CKMODE + , + ADC_InitStruct->Clock + ); + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_InitTypeDef field to default value. + * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct) +{ + /* Set ADC_InitStruct fields to default values */ + /* Set fields of ADC instance */ + ADC_InitStruct->Clock = LL_ADC_CLOCK_SYNC_PCLK_DIV2; + ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B; + ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT; + ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE; +} + + +/** + * @brief Initialize some features of ADC group regular. + * @note These parameters have an impact on ADC scope: ADC group regular. + * Refer to corresponding unitary functions into + * @ref ADC_LL_EF_Configuration_ADC_Group_Regular + * (functions with prefix "REG"). + * @note The setting of these parameters by function @ref LL_ADC_Init() + * is conditioned to ADC state: + * ADC instance must be disabled. + * This condition is applied to all ADC features, for efficiency + * and compatibility over all PY32 families. However, the different + * features can be set under different ADC state conditions + * (setting possible with ADC enabled without conversion on going, + * ADC enabled with conversion on going, ...) + * Each feature can be updated afterwards with a unitary function + * and potentially with ADC in a different state than disabled, + * refer to description of each function for setting + * conditioned to ADC state. + * @note After using this function, other features must be configured + * using LL unitary functions. + * The minimum configuration remaining to be done is: + * - Set ADC group regular sequencer: + * map channel on rank corresponding to channel number. + * Refer to function @ref LL_ADC_REG_SetSequencerChannels(); + * - Set ADC channel sampling time + * Refer to function LL_ADC_SetChannelSamplingTime(); + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @param ADCx ADC instance + * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ADC registers are initialized + * - ERROR: ADC registers are not initialized + */ +ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_ADC_ALL_INSTANCE(ADCx)); + assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource)); + assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont)); + assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode)); +#if (defined(DMA) || defined(DMA1)) + assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer)); +#endif + assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun)); + + /* Note: Hardware constraint (refer to description of this function): */ + /* ADC instance must be disabled. */ + if(LL_ADC_IsEnabled(ADCx) == 0U) + { + /* Configuration of ADC hierarchical scope: */ + /* - ADC group regular */ + /* - Set ADC group regular trigger source */ + /* - Set ADC group regular sequencer discontinuous mode */ + /* - Set ADC group regular continuous mode */ + /* - Set ADC group regular conversion data transfer: no transfer or */ + /* transfer by DMA, and DMA requests mode */ + /* - Set ADC group regular overrun behavior */ + /* Note: On this PY32 serie, ADC trigger edge is set to value 0x0 by */ + /* setting of trigger source to SW start. */ + +#if (defined(DMA) || defined(DMA1)) + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_EXTSEL + | ADC_CFGR1_EXTEN + | ADC_CFGR1_DISCEN + | ADC_CFGR1_CONT + | ADC_CFGR1_DMAEN + | ADC_CFGR1_DMACFG + | ADC_CFGR1_OVRMOD + , + ADC_REG_InitStruct->TriggerSource + | ADC_REG_InitStruct->SequencerDiscont + | ADC_REG_InitStruct->ContinuousMode + | ADC_REG_InitStruct->DMATransfer + | ADC_REG_InitStruct->Overrun + ); +#else + MODIFY_REG(ADCx->CFGR1, + ADC_CFGR1_EXTSEL + | ADC_CFGR1_EXTEN + | ADC_CFGR1_DISCEN + | ADC_CFGR1_CONT + | ADC_CFGR1_OVRMOD + , + ADC_REG_InitStruct->TriggerSource + | ADC_REG_InitStruct->SequencerDiscont + | ADC_REG_InitStruct->ContinuousMode + | ADC_REG_InitStruct->Overrun + ); +#endif + } + else + { + /* Initialization error: ADC instance is not disabled. */ + status = ERROR; + } + return status; +} + +/** + * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value. + * @note Depending on devices and packages, DMA may not be available. + * Refer to device datasheet for DMA availability. + * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct) +{ + /* Set ADC_REG_InitStruct fields to default values */ + /* Set fields of ADC group regular */ + /* Note: On this PY32 serie, ADC trigger edge is set to value 0x0 by */ + /* setting of trigger source to SW start. */ + ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE; + ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE; + ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE; +#if (defined(DMA) || defined(DMA1)) + ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE; +#endif + ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* ADC1 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_comp.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_comp.c similarity index 99% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_comp.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_comp.c index 171ba87..491b992 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_comp.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_comp.c @@ -3,21 +3,21 @@ * @file py32f0xx_ll_comp.c * @author MCU Application Team * @brief COMP LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_crc.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_crc.c similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_crc.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_crc.c index af5ae1c..e6fdd07 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_crc.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_crc.c @@ -1,111 +1,111 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_crc.c - * @author MCU Application Team - * @brief CRC LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_crc.h" -#include "py32f0xx_ll_bus.h" - -#ifdef USE_FULL_ASSERT - #include "py32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (CRC) - -/** @addtogroup CRC_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup CRC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup CRC_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize CRC registers (Registers restored to their default values). - * @param CRCx CRC Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: CRC registers are de-initialized - * - ERROR: CRC registers are not de-initialized - */ -ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_CRC_ALL_INSTANCE(CRCx)); - - if (CRCx == CRC) - { - - /* Reset the CRC calculation unit */ - LL_CRC_ResetCRCCalculationUnit(CRCx); - - /* Reset IDR register */ - LL_CRC_Write_IDR(CRCx, 0x00U); - } - else - { - status = ERROR; - } - - return (status); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (CRC) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ - +/** + ****************************************************************************** + * @file py32f0xx_ll_crc.c + * @author MCU Application Team + * @brief CRC LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_crc.h" +#include "py32f0xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT + #include "py32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (CRC) + +/** @addtogroup CRC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup CRC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup CRC_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize CRC registers (Registers restored to their default values). + * @param CRCx CRC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: CRC registers are de-initialized + * - ERROR: CRC registers are not de-initialized + */ +ErrorStatus LL_CRC_DeInit(CRC_TypeDef *CRCx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_CRC_ALL_INSTANCE(CRCx)); + + if (CRCx == CRC) + { + + /* Reset the CRC calculation unit */ + LL_CRC_ResetCRCCalculationUnit(CRCx); + + /* Reset IDR register */ + LL_CRC_Write_IDR(CRCx, 0x00U); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (CRC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ + diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_dma.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_dma.c similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_dma.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_dma.c index ad4af4e..164ea7a 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_dma.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_dma.c @@ -1,265 +1,265 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_dma.c - * @author MCU Application Team - * @brief DMA LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_dma.h" -#ifdef USE_FULL_ASSERT - #include "py32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (DMA1) - -/** @defgroup DMA_LL DMA - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup DMA_LL_Private_Macros - * @{ - */ -#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ - ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ - ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) - -#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ - ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) - -#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ - ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) - -#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ - ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) - -#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ - ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ - ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) - -#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ - ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ - ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) - -#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - -#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ - ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ - ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ - ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) - -#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ - (((CHANNEL) == LL_DMA_CHANNEL_1) || \ - ((CHANNEL) == LL_DMA_CHANNEL_2) || \ - ((CHANNEL) == LL_DMA_CHANNEL_3)))) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup DMA_LL_Exported_Functions - * @{ - */ - -/** @addtogroup DMA_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the DMA registers to their default reset values. - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @retval An ErrorStatus enumeration value: - * - SUCCESS: DMA registers are de-initialized - * - ERROR: DMA registers are not de-initialized - */ -uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) -{ - DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; - ErrorStatus status = SUCCESS; - - /* Check the DMA Instance DMAx and Channel parameters*/ - assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); - - tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); - - /* Disable the selected DMAx_Channely */ - CLEAR_BIT(tmp->CCR, DMA_CCR_EN); - - /* Reset DMAx_Channely control register */ - LL_DMA_WriteReg(tmp, CCR, 0U); - - /* Reset DMAx_Channely remaining bytes register */ - LL_DMA_WriteReg(tmp, CNDTR, 0U); - - /* Reset DMAx_Channely peripheral address register */ - LL_DMA_WriteReg(tmp, CPAR, 0U); - - /* Reset DMAx_Channely memory address register */ - LL_DMA_WriteReg(tmp, CMAR, 0U); - - if (Channel == LL_DMA_CHANNEL_1) - { - /* Reset interrupt pending bits for DMAx Channel1 */ - LL_DMA_ClearFlag_GI1(DMAx); - } - else if (Channel == LL_DMA_CHANNEL_2) - { - /* Reset interrupt pending bits for DMAx Channel2 */ - LL_DMA_ClearFlag_GI2(DMAx); - } - else if (Channel == LL_DMA_CHANNEL_3) - { - /* Reset interrupt pending bits for DMAx Channel3 */ - LL_DMA_ClearFlag_GI3(DMAx); - } - else - { - status = ERROR; - } - - return status; -} - -/** - * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. - * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : - * @arg @ref __LL_DMA_GET_INSTANCE - * @arg @ref __LL_DMA_GET_CHANNEL - * @param DMAx DMAx Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_DMA_CHANNEL_1 - * @arg @ref LL_DMA_CHANNEL_2 - * @arg @ref LL_DMA_CHANNEL_3 - * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: DMA registers are initialized - * - ERROR: Not applicable - */ -uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) -{ - /* Check the DMA Instance DMAx and Channel parameters*/ - assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); - - /* Check the DMA parameters from DMA_InitStruct */ - assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); - assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); - assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); - assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); - assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); - assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); - assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); - assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); - - /*---------------------------- DMAx CCR Configuration ------------------------ - * Configure DMAx_Channely: data transfer direction, data transfer mode, - * peripheral and memory increment mode, - * data size alignment and priority level with parameters : - * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits - * - Mode: DMA_CCR_CIRC bit - * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit - * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit - * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits - * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits - * - Priority: DMA_CCR_PL[1:0] bits - */ - LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ - DMA_InitStruct->Mode | \ - DMA_InitStruct->PeriphOrM2MSrcIncMode | \ - DMA_InitStruct->MemoryOrM2MDstIncMode | \ - DMA_InitStruct->PeriphOrM2MSrcDataSize | \ - DMA_InitStruct->MemoryOrM2MDstDataSize | \ - DMA_InitStruct->Priority); - - /*-------------------------- DMAx CMAR Configuration ------------------------- - * Configure the memory or destination base address with parameter : - * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits - */ - LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); - - /*-------------------------- DMAx CPAR Configuration ------------------------- - * Configure the peripheral or source base address with parameter : - * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits - */ - LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); - - /*--------------------------- DMAx CNDTR Configuration ----------------------- - * Configure the peripheral base address with parameter : - * - NbData: DMA_CNDTR_NDT[15:0] bits - */ - LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); - - return SUCCESS; -} - -/** - * @brief Set each @ref LL_DMA_InitTypeDef field to default value. - * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. - * @retval None - */ -void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) -{ - /* Set DMA_InitStruct fields to default values */ - DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; - DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; - DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; - DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; - DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; - DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; - DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; - DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; - DMA_InitStruct->NbData = 0x00000000U; - DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* DMA1 || DMA2 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_dma.c + * @author MCU Application Team + * @brief DMA LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_dma.h" +#ifdef USE_FULL_ASSERT + #include "py32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (DMA1) + +/** @defgroup DMA_LL DMA + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup DMA_LL_Private_Macros + * @{ + */ +#define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \ + ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY)) + +#define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \ + ((__VALUE__) == LL_DMA_MODE_CIRCULAR)) + +#define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \ + ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT)) + +#define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \ + ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT)) + +#define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_PDATAALIGN_WORD)) + +#define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \ + ((__VALUE__) == LL_DMA_MDATAALIGN_WORD)) + +#define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + +#define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \ + ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \ + ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \ + ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH)) + +#define IS_LL_DMA_ALL_CHANNEL_INSTANCE(INSTANCE, CHANNEL) ((((INSTANCE) == DMA1) && \ + (((CHANNEL) == LL_DMA_CHANNEL_1) || \ + ((CHANNEL) == LL_DMA_CHANNEL_2) || \ + ((CHANNEL) == LL_DMA_CHANNEL_3)))) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup DMA_LL_Exported_Functions + * @{ + */ + +/** @addtogroup DMA_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the DMA registers to their default reset values. + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are de-initialized + * - ERROR: DMA registers are not de-initialized + */ +uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel) +{ + DMA_Channel_TypeDef *tmp = (DMA_Channel_TypeDef *)DMA1_Channel1; + ErrorStatus status = SUCCESS; + + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + tmp = (DMA_Channel_TypeDef *)(__LL_DMA_GET_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Disable the selected DMAx_Channely */ + CLEAR_BIT(tmp->CCR, DMA_CCR_EN); + + /* Reset DMAx_Channely control register */ + LL_DMA_WriteReg(tmp, CCR, 0U); + + /* Reset DMAx_Channely remaining bytes register */ + LL_DMA_WriteReg(tmp, CNDTR, 0U); + + /* Reset DMAx_Channely peripheral address register */ + LL_DMA_WriteReg(tmp, CPAR, 0U); + + /* Reset DMAx_Channely memory address register */ + LL_DMA_WriteReg(tmp, CMAR, 0U); + + if (Channel == LL_DMA_CHANNEL_1) + { + /* Reset interrupt pending bits for DMAx Channel1 */ + LL_DMA_ClearFlag_GI1(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_2) + { + /* Reset interrupt pending bits for DMAx Channel2 */ + LL_DMA_ClearFlag_GI2(DMAx); + } + else if (Channel == LL_DMA_CHANNEL_3) + { + /* Reset interrupt pending bits for DMAx Channel3 */ + LL_DMA_ClearFlag_GI3(DMAx); + } + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct. + * @note To convert DMAx_Channely Instance to DMAx Instance and Channely, use helper macros : + * @arg @ref __LL_DMA_GET_INSTANCE + * @arg @ref __LL_DMA_GET_CHANNEL + * @param DMAx DMAx Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_DMA_CHANNEL_1 + * @arg @ref LL_DMA_CHANNEL_2 + * @arg @ref LL_DMA_CHANNEL_3 + * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: DMA registers are initialized + * - ERROR: Not applicable + */ +uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Check the DMA Instance DMAx and Channel parameters*/ + assert_param(IS_LL_DMA_ALL_CHANNEL_INSTANCE(DMAx, Channel)); + + /* Check the DMA parameters from DMA_InitStruct */ + assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction)); + assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode)); + assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode)); + assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode)); + assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize)); + assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize)); + assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData)); + assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority)); + + /*---------------------------- DMAx CCR Configuration ------------------------ + * Configure DMAx_Channely: data transfer direction, data transfer mode, + * peripheral and memory increment mode, + * data size alignment and priority level with parameters : + * - Direction: DMA_CCR_DIR and DMA_CCR_MEM2MEM bits + * - Mode: DMA_CCR_CIRC bit + * - PeriphOrM2MSrcIncMode: DMA_CCR_PINC bit + * - MemoryOrM2MDstIncMode: DMA_CCR_MINC bit + * - PeriphOrM2MSrcDataSize: DMA_CCR_PSIZE[1:0] bits + * - MemoryOrM2MDstDataSize: DMA_CCR_MSIZE[1:0] bits + * - Priority: DMA_CCR_PL[1:0] bits + */ + LL_DMA_ConfigTransfer(DMAx, Channel, DMA_InitStruct->Direction | \ + DMA_InitStruct->Mode | \ + DMA_InitStruct->PeriphOrM2MSrcIncMode | \ + DMA_InitStruct->MemoryOrM2MDstIncMode | \ + DMA_InitStruct->PeriphOrM2MSrcDataSize | \ + DMA_InitStruct->MemoryOrM2MDstDataSize | \ + DMA_InitStruct->Priority); + + /*-------------------------- DMAx CMAR Configuration ------------------------- + * Configure the memory or destination base address with parameter : + * - MemoryOrM2MDstAddress: DMA_CMAR_MA[31:0] bits + */ + LL_DMA_SetMemoryAddress(DMAx, Channel, DMA_InitStruct->MemoryOrM2MDstAddress); + + /*-------------------------- DMAx CPAR Configuration ------------------------- + * Configure the peripheral or source base address with parameter : + * - PeriphOrM2MSrcAddress: DMA_CPAR_PA[31:0] bits + */ + LL_DMA_SetPeriphAddress(DMAx, Channel, DMA_InitStruct->PeriphOrM2MSrcAddress); + + /*--------------------------- DMAx CNDTR Configuration ----------------------- + * Configure the peripheral base address with parameter : + * - NbData: DMA_CNDTR_NDT[15:0] bits + */ + LL_DMA_SetDataLength(DMAx, Channel, DMA_InitStruct->NbData); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_DMA_InitTypeDef field to default value. + * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure. + * @retval None + */ +void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct) +{ + /* Set DMA_InitStruct fields to default values */ + DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U; + DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U; + DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY; + DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL; + DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT; + DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT; + DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE; + DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE; + DMA_InitStruct->NbData = 0x00000000U; + DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DMA1 || DMA2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_exti.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_exti.c similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_exti.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_exti.c index aec4ab1..5eadb5e 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_exti.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_exti.c @@ -1,238 +1,238 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_exti.c - * @author MCU Application Team - * @brief EXTI LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_exti.h" -#ifdef USE_FULL_ASSERT - #include "py32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (EXTI) - -/** @defgroup EXTI_LL EXTI - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup EXTI_LL_Private_Macros - * @{ - */ - -#define IS_LL_EXTI_LINE(__VALUE__) ((__VALUE__ == LL_EXTI_LINE_0 ) || \ - (__VALUE__ == LL_EXTI_LINE_1 ) || \ - (__VALUE__ == LL_EXTI_LINE_2 ) || \ - (__VALUE__ == LL_EXTI_LINE_3 ) || \ - (__VALUE__ == LL_EXTI_LINE_4 ) || \ - (__VALUE__ == LL_EXTI_LINE_5 ) || \ - (__VALUE__ == LL_EXTI_LINE_6 ) || \ - (__VALUE__ == LL_EXTI_LINE_7 ) || \ - (__VALUE__ == LL_EXTI_LINE_8 ) || \ - (__VALUE__ == LL_EXTI_LINE_9 ) || \ - (__VALUE__ == LL_EXTI_LINE_10 ) || \ - (__VALUE__ == LL_EXTI_LINE_11 ) || \ - (__VALUE__ == LL_EXTI_LINE_12 ) || \ - (__VALUE__ == LL_EXTI_LINE_13 ) || \ - (__VALUE__ == LL_EXTI_LINE_14 ) || \ - (__VALUE__ == LL_EXTI_LINE_15 ) || \ - (__VALUE__ == LL_EXTI_LINE_16 ) || \ - (__VALUE__ == LL_EXTI_LINE_17 ) || \ - (__VALUE__ == LL_EXTI_LINE_18 ) || \ - (__VALUE__ == LL_EXTI_LINE_19 ) || \ - (__VALUE__ == LL_EXTI_LINE_29 )) - -#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ - || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ - || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) - - -#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ - || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup EXTI_LL_Exported_Functions - * @{ - */ - -/** @addtogroup EXTI_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the EXTI registers to their default reset values. - * @retval An ErrorStatus enumeration value: - * - 0x00: EXTI registers are de-initialized - */ -uint32_t LL_EXTI_DeInit(void) -{ - /* Interrupt mask register set to default reset values */ - LL_EXTI_WriteReg(IMR, 0x20080000U); - /* Event mask register set to default reset values */ - LL_EXTI_WriteReg(EMR, 0x00000000U); - /* Rising Trigger selection register set to default reset values */ - LL_EXTI_WriteReg(RTSR, 0x00000000U); - /* Falling Trigger selection register set to default reset values */ - LL_EXTI_WriteReg(FTSR, 0x00000000U); - /* Software interrupt event register set to default reset values */ - LL_EXTI_WriteReg(SWIER, 0x00000000U); - /* Pending register set to default reset values */ - LL_EXTI_WriteReg(PR, 0x00007FFFFU); - - return 0x00u; -} - -/** - * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. - * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - 0x00: EXTI registers are initialized - * - any other value : wrong configuration - */ -uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) -{ - uint32_t status = 0x00u; - - /* Check the parameters */ - assert_param(IS_LL_EXTI_LINE(EXTI_InitStruct->Line)); - assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); - assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); - - /* ENABLE LineCommand */ - if (EXTI_InitStruct->LineCommand != DISABLE) - { - assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); - - /* Configure EXTI Lines*/ - if (EXTI_InitStruct->Line != LL_EXTI_LINE_NONE) - { - switch (EXTI_InitStruct->Mode) - { - case LL_EXTI_MODE_IT: - /* First Disable Event on provided Lines */ - LL_EXTI_DisableEvent(EXTI_InitStruct->Line); - /* Then Enable IT on provided Lines */ - LL_EXTI_EnableIT(EXTI_InitStruct->Line); - break; - case LL_EXTI_MODE_EVENT: - /* First Disable IT on provided Lines */ - LL_EXTI_DisableIT(EXTI_InitStruct->Line); - /* Then Enable Event on provided Lines */ - LL_EXTI_EnableEvent(EXTI_InitStruct->Line); - break; - case LL_EXTI_MODE_IT_EVENT: - /* Directly Enable IT & Event on provided Lines */ - LL_EXTI_EnableIT(EXTI_InitStruct->Line); - LL_EXTI_EnableEvent(EXTI_InitStruct->Line); - break; - default: - status = 0x01u; - break; - } - if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) - { - switch (EXTI_InitStruct->Trigger) - { - case LL_EXTI_TRIGGER_RISING: - /* First Disable Falling Trigger on provided Lines */ - LL_EXTI_DisableFallingTrig(EXTI_InitStruct->Line); - /* Then Enable Rising Trigger on provided Lines */ - LL_EXTI_EnableRisingTrig(EXTI_InitStruct->Line); - break; - case LL_EXTI_TRIGGER_FALLING: - /* First Disable Rising Trigger on provided Lines */ - LL_EXTI_DisableRisingTrig(EXTI_InitStruct->Line); - /* Then Enable Falling Trigger on provided Lines */ - LL_EXTI_EnableFallingTrig(EXTI_InitStruct->Line); - break; - case LL_EXTI_TRIGGER_RISING_FALLING: - LL_EXTI_EnableRisingTrig(EXTI_InitStruct->Line); - LL_EXTI_EnableFallingTrig(EXTI_InitStruct->Line); - break; - default: - status |= 0x02u; - break; - } - } - } - } - /* DISABLE LineCommand */ - else - { - /* De-configure EXTI Lines*/ - LL_EXTI_DisableIT(EXTI_InitStruct->Line); - LL_EXTI_DisableEvent(EXTI_InitStruct->Line); - } - - return status; -} - -/** - * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. - * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. - * @retval None - */ -void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) -{ - EXTI_InitStruct->Line = LL_EXTI_LINE_NONE; - EXTI_InitStruct->LineCommand = DISABLE; - EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; - EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined (EXTI) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_exti.c + * @author MCU Application Team + * @brief EXTI LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_exti.h" +#ifdef USE_FULL_ASSERT + #include "py32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (EXTI) + +/** @defgroup EXTI_LL EXTI + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Private_Macros + * @{ + */ + +#define IS_LL_EXTI_LINE(__VALUE__) ((__VALUE__ == LL_EXTI_LINE_0 ) || \ + (__VALUE__ == LL_EXTI_LINE_1 ) || \ + (__VALUE__ == LL_EXTI_LINE_2 ) || \ + (__VALUE__ == LL_EXTI_LINE_3 ) || \ + (__VALUE__ == LL_EXTI_LINE_4 ) || \ + (__VALUE__ == LL_EXTI_LINE_5 ) || \ + (__VALUE__ == LL_EXTI_LINE_6 ) || \ + (__VALUE__ == LL_EXTI_LINE_7 ) || \ + (__VALUE__ == LL_EXTI_LINE_8 ) || \ + (__VALUE__ == LL_EXTI_LINE_9 ) || \ + (__VALUE__ == LL_EXTI_LINE_10 ) || \ + (__VALUE__ == LL_EXTI_LINE_11 ) || \ + (__VALUE__ == LL_EXTI_LINE_12 ) || \ + (__VALUE__ == LL_EXTI_LINE_13 ) || \ + (__VALUE__ == LL_EXTI_LINE_14 ) || \ + (__VALUE__ == LL_EXTI_LINE_15 ) || \ + (__VALUE__ == LL_EXTI_LINE_16 ) || \ + (__VALUE__ == LL_EXTI_LINE_17 ) || \ + (__VALUE__ == LL_EXTI_LINE_18 ) || \ + (__VALUE__ == LL_EXTI_LINE_19 ) || \ + (__VALUE__ == LL_EXTI_LINE_29 )) + +#define IS_LL_EXTI_MODE(__VALUE__) (((__VALUE__) == LL_EXTI_MODE_IT) \ + || ((__VALUE__) == LL_EXTI_MODE_EVENT) \ + || ((__VALUE__) == LL_EXTI_MODE_IT_EVENT)) + + +#define IS_LL_EXTI_TRIGGER(__VALUE__) (((__VALUE__) == LL_EXTI_TRIGGER_NONE) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_FALLING) \ + || ((__VALUE__) == LL_EXTI_TRIGGER_RISING_FALLING)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup EXTI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup EXTI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the EXTI registers to their default reset values. + * @retval An ErrorStatus enumeration value: + * - 0x00: EXTI registers are de-initialized + */ +uint32_t LL_EXTI_DeInit(void) +{ + /* Interrupt mask register set to default reset values */ + LL_EXTI_WriteReg(IMR, 0x20080000U); + /* Event mask register set to default reset values */ + LL_EXTI_WriteReg(EMR, 0x00000000U); + /* Rising Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(RTSR, 0x00000000U); + /* Falling Trigger selection register set to default reset values */ + LL_EXTI_WriteReg(FTSR, 0x00000000U); + /* Software interrupt event register set to default reset values */ + LL_EXTI_WriteReg(SWIER, 0x00000000U); + /* Pending register set to default reset values */ + LL_EXTI_WriteReg(PR, 0x00007FFFFU); + + return 0x00u; +} + +/** + * @brief Initialize the EXTI registers according to the specified parameters in EXTI_InitStruct. + * @param EXTI_InitStruct pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - 0x00: EXTI registers are initialized + * - any other value : wrong configuration + */ +uint32_t LL_EXTI_Init(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + uint32_t status = 0x00u; + + /* Check the parameters */ + assert_param(IS_LL_EXTI_LINE(EXTI_InitStruct->Line)); + assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->LineCommand)); + assert_param(IS_LL_EXTI_MODE(EXTI_InitStruct->Mode)); + + /* ENABLE LineCommand */ + if (EXTI_InitStruct->LineCommand != DISABLE) + { + assert_param(IS_LL_EXTI_TRIGGER(EXTI_InitStruct->Trigger)); + + /* Configure EXTI Lines*/ + if (EXTI_InitStruct->Line != LL_EXTI_LINE_NONE) + { + switch (EXTI_InitStruct->Mode) + { + case LL_EXTI_MODE_IT: + /* First Disable Event on provided Lines */ + LL_EXTI_DisableEvent(EXTI_InitStruct->Line); + /* Then Enable IT on provided Lines */ + LL_EXTI_EnableIT(EXTI_InitStruct->Line); + break; + case LL_EXTI_MODE_EVENT: + /* First Disable IT on provided Lines */ + LL_EXTI_DisableIT(EXTI_InitStruct->Line); + /* Then Enable Event on provided Lines */ + LL_EXTI_EnableEvent(EXTI_InitStruct->Line); + break; + case LL_EXTI_MODE_IT_EVENT: + /* Directly Enable IT & Event on provided Lines */ + LL_EXTI_EnableIT(EXTI_InitStruct->Line); + LL_EXTI_EnableEvent(EXTI_InitStruct->Line); + break; + default: + status = 0x01u; + break; + } + if (EXTI_InitStruct->Trigger != LL_EXTI_TRIGGER_NONE) + { + switch (EXTI_InitStruct->Trigger) + { + case LL_EXTI_TRIGGER_RISING: + /* First Disable Falling Trigger on provided Lines */ + LL_EXTI_DisableFallingTrig(EXTI_InitStruct->Line); + /* Then Enable Rising Trigger on provided Lines */ + LL_EXTI_EnableRisingTrig(EXTI_InitStruct->Line); + break; + case LL_EXTI_TRIGGER_FALLING: + /* First Disable Rising Trigger on provided Lines */ + LL_EXTI_DisableRisingTrig(EXTI_InitStruct->Line); + /* Then Enable Falling Trigger on provided Lines */ + LL_EXTI_EnableFallingTrig(EXTI_InitStruct->Line); + break; + case LL_EXTI_TRIGGER_RISING_FALLING: + LL_EXTI_EnableRisingTrig(EXTI_InitStruct->Line); + LL_EXTI_EnableFallingTrig(EXTI_InitStruct->Line); + break; + default: + status |= 0x02u; + break; + } + } + } + } + /* DISABLE LineCommand */ + else + { + /* De-configure EXTI Lines*/ + LL_EXTI_DisableIT(EXTI_InitStruct->Line); + LL_EXTI_DisableEvent(EXTI_InitStruct->Line); + } + + return status; +} + +/** + * @brief Set each @ref LL_EXTI_InitTypeDef field to default value. + * @param EXTI_InitStruct Pointer to a @ref LL_EXTI_InitTypeDef structure. + * @retval None + */ +void LL_EXTI_StructInit(LL_EXTI_InitTypeDef *EXTI_InitStruct) +{ + EXTI_InitStruct->Line = LL_EXTI_LINE_NONE; + EXTI_InitStruct->LineCommand = DISABLE; + EXTI_InitStruct->Mode = LL_EXTI_MODE_IT; + EXTI_InitStruct->Trigger = LL_EXTI_TRIGGER_FALLING; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined (EXTI) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_gpio.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_gpio.c similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_gpio.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_gpio.c index 27164cb..6a8d495 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_gpio.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_gpio.c @@ -1,261 +1,261 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_gpio.c - * @author MCU Application Team - * @brief GPIO LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_gpio.h" -#include "py32f0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT - #include "py32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (GPIOA) || defined (GPIOB) || defined (GPIOF) - -/** @addtogroup GPIO_LL - * @{ - */ -/** MISRA C:2012 deviation rule has been granted for following rules: - * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of - * range of the shift operator in following API : - * LL_GPIO_Init - * LL_GPIO_DeInit - * LL_GPIO_SetPinMode - * LL_GPIO_GetPinMode - * LL_GPIO_SetPinSpeed - * LL_GPIO_GetPinSpeed - * LL_GPIO_SetPinPull - * LL_GPIO_GetPinPull - * LL_GPIO_GetAFPin_0_7 - * LL_GPIO_SetAFPin_0_7 - * LL_GPIO_SetAFPin_8_15 - * LL_GPIO_GetAFPin_8_15 - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/** @addtogroup GPIO_LL_Private_Macros - * @{ - */ -#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) - -#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ - ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ - ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ - ((__VALUE__) == LL_GPIO_MODE_ANALOG)) - -#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ - ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) - -#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ - ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) - -#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ - ((__VALUE__) == LL_GPIO_PULL_UP) ||\ - ((__VALUE__) == LL_GPIO_PULL_DOWN)) - -#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ - ((__VALUE__) == LL_GPIO_AF_1 ) ||\ - ((__VALUE__) == LL_GPIO_AF_2 ) ||\ - ((__VALUE__) == LL_GPIO_AF_3 ) ||\ - ((__VALUE__) == LL_GPIO_AF_4 ) ||\ - ((__VALUE__) == LL_GPIO_AF_5 ) ||\ - ((__VALUE__) == LL_GPIO_AF_6 ) ||\ - ((__VALUE__) == LL_GPIO_AF_7 ) ||\ - ((__VALUE__) == LL_GPIO_AF_8 ) ||\ - ((__VALUE__) == LL_GPIO_AF_9 ) ||\ - ((__VALUE__) == LL_GPIO_AF_10 ) ||\ - ((__VALUE__) == LL_GPIO_AF_11 ) ||\ - ((__VALUE__) == LL_GPIO_AF_12 ) ||\ - ((__VALUE__) == LL_GPIO_AF_13 ) ||\ - ((__VALUE__) == LL_GPIO_AF_14 ) ||\ - ((__VALUE__) == LL_GPIO_AF_15 )) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup GPIO_LL_Exported_Functions - * @{ - */ - -/** @addtogroup GPIO_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize GPIO registers (Registers restored to their default values). - * @param GPIOx GPIO Port - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are de-initialized - * - ERROR: Wrong GPIO Port - */ -ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - - /* Force and Release reset on clock of GPIOx Port */ - if (GPIOx == GPIOA) - { - LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOA); - LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOA); - } - else if (GPIOx == GPIOB) - { - LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOB); - LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOB); - } - else if (GPIOx == GPIOF) - { - LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOF); - LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOF); - } - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. - * @param GPIOx GPIO Port - * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure - * that contains the configuration information for the specified GPIO peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content - * - ERROR: Not applicable - */ -ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) -{ - uint32_t pinpos; - uint32_t currentpin; - - /* Check the parameters */ - assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); - assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); - assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); - assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); - - /* ------------------------- Configure the port pins ---------------- */ - /* Initialize pinpos on first pin set */ - pinpos = 0; - - /* Configure the port pins */ - while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) - { - /* Get current io position */ - currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); - - if (currentpin != 0x00u) - { - /* Pin Mode configuration */ - LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Speed mode parameters */ - assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); - - /* Speed mode configuration */ - LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); - } - - /* Pull-up Pull down resistor configuration*/ - LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); - - if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) - { - /* Check Alternate parameter */ - assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); - - /* Speed mode configuration */ - if (currentpin < LL_GPIO_PIN_8) - { - LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); - } - else - { - LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); - } - } - } - pinpos++; - } - - if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) - { - /* Check Output mode parameters */ - assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); - - /* Output mode configuration*/ - LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); - - } - return (SUCCESS); -} - -/** - * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ - -void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) -{ - /* Reset GPIO init structure parameters values */ - GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; - GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; - GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; - GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; - GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; - GPIO_InitStruct->Alternate = LL_GPIO_AF_0; -} - - - - - - -#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOF) */ - - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya Semiconductor *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_gpio.c + * @author MCU Application Team + * @brief GPIO LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_gpio.h" +#include "py32f0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT + #include "py32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (GPIOA) || defined (GPIOB) || defined (GPIOF) + +/** @addtogroup GPIO_LL + * @{ + */ +/** MISRA C:2012 deviation rule has been granted for following rules: + * Rule-12.2 - Medium: RHS argument is in interval [0,INF] which is out of + * range of the shift operator in following API : + * LL_GPIO_Init + * LL_GPIO_DeInit + * LL_GPIO_SetPinMode + * LL_GPIO_GetPinMode + * LL_GPIO_SetPinSpeed + * LL_GPIO_GetPinSpeed + * LL_GPIO_SetPinPull + * LL_GPIO_GetPinPull + * LL_GPIO_GetAFPin_0_7 + * LL_GPIO_SetAFPin_0_7 + * LL_GPIO_SetAFPin_8_15 + * LL_GPIO_GetAFPin_8_15 + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup GPIO_LL_Private_Macros + * @{ + */ +#define IS_LL_GPIO_PIN(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (LL_GPIO_PIN_ALL))) + +#define IS_LL_GPIO_MODE(__VALUE__) (((__VALUE__) == LL_GPIO_MODE_INPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_OUTPUT) ||\ + ((__VALUE__) == LL_GPIO_MODE_ALTERNATE) ||\ + ((__VALUE__) == LL_GPIO_MODE_ANALOG)) + +#define IS_LL_GPIO_OUTPUT_TYPE(__VALUE__) (((__VALUE__) == LL_GPIO_OUTPUT_PUSHPULL) ||\ + ((__VALUE__) == LL_GPIO_OUTPUT_OPENDRAIN)) + +#define IS_LL_GPIO_SPEED(__VALUE__) (((__VALUE__) == LL_GPIO_SPEED_FREQ_LOW) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_MEDIUM) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_HIGH) ||\ + ((__VALUE__) == LL_GPIO_SPEED_FREQ_VERY_HIGH)) + +#define IS_LL_GPIO_PULL(__VALUE__) (((__VALUE__) == LL_GPIO_PULL_NO) ||\ + ((__VALUE__) == LL_GPIO_PULL_UP) ||\ + ((__VALUE__) == LL_GPIO_PULL_DOWN)) + +#define IS_LL_GPIO_ALTERNATE(__VALUE__) (((__VALUE__) == LL_GPIO_AF_0 ) ||\ + ((__VALUE__) == LL_GPIO_AF_1 ) ||\ + ((__VALUE__) == LL_GPIO_AF_2 ) ||\ + ((__VALUE__) == LL_GPIO_AF_3 ) ||\ + ((__VALUE__) == LL_GPIO_AF_4 ) ||\ + ((__VALUE__) == LL_GPIO_AF_5 ) ||\ + ((__VALUE__) == LL_GPIO_AF_6 ) ||\ + ((__VALUE__) == LL_GPIO_AF_7 ) ||\ + ((__VALUE__) == LL_GPIO_AF_8 ) ||\ + ((__VALUE__) == LL_GPIO_AF_9 ) ||\ + ((__VALUE__) == LL_GPIO_AF_10 ) ||\ + ((__VALUE__) == LL_GPIO_AF_11 ) ||\ + ((__VALUE__) == LL_GPIO_AF_12 ) ||\ + ((__VALUE__) == LL_GPIO_AF_13 ) ||\ + ((__VALUE__) == LL_GPIO_AF_14 ) ||\ + ((__VALUE__) == LL_GPIO_AF_15 )) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup GPIO_LL_Exported_Functions + * @{ + */ + +/** @addtogroup GPIO_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize GPIO registers (Registers restored to their default values). + * @param GPIOx GPIO Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are de-initialized + * - ERROR: Wrong GPIO Port + */ +ErrorStatus LL_GPIO_DeInit(GPIO_TypeDef *GPIOx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + + /* Force and Release reset on clock of GPIOx Port */ + if (GPIOx == GPIOA) + { + LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOA); + LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOA); + } + else if (GPIOx == GPIOB) + { + LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOB); + LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOB); + } + else if (GPIOx == GPIOF) + { + LL_IOP_GRP1_ForceReset(LL_IOP_GRP1_PERIPH_GPIOF); + LL_IOP_GRP1_ReleaseReset(LL_IOP_GRP1_PERIPH_GPIOF); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. + * @param GPIOx GPIO Port + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * that contains the configuration information for the specified GPIO peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_GPIO_Init(GPIO_TypeDef *GPIOx, LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + uint32_t pinpos; + uint32_t currentpin; + + /* Check the parameters */ + assert_param(IS_GPIO_ALL_INSTANCE(GPIOx)); + assert_param(IS_LL_GPIO_PIN(GPIO_InitStruct->Pin)); + assert_param(IS_LL_GPIO_MODE(GPIO_InitStruct->Mode)); + assert_param(IS_LL_GPIO_PULL(GPIO_InitStruct->Pull)); + + /* ------------------------- Configure the port pins ---------------- */ + /* Initialize pinpos on first pin set */ + pinpos = 0; + + /* Configure the port pins */ + while (((GPIO_InitStruct->Pin) >> pinpos) != 0x00u) + { + /* Get current io position */ + currentpin = (GPIO_InitStruct->Pin) & (0x00000001uL << pinpos); + + if (currentpin != 0x00u) + { + /* Pin Mode configuration */ + LL_GPIO_SetPinMode(GPIOx, currentpin, GPIO_InitStruct->Mode); + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Speed mode parameters */ + assert_param(IS_LL_GPIO_SPEED(GPIO_InitStruct->Speed)); + + /* Speed mode configuration */ + LL_GPIO_SetPinSpeed(GPIOx, currentpin, GPIO_InitStruct->Speed); + } + + /* Pull-up Pull down resistor configuration*/ + LL_GPIO_SetPinPull(GPIOx, currentpin, GPIO_InitStruct->Pull); + + if (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE) + { + /* Check Alternate parameter */ + assert_param(IS_LL_GPIO_ALTERNATE(GPIO_InitStruct->Alternate)); + + /* Speed mode configuration */ + if (currentpin < LL_GPIO_PIN_8) + { + LL_GPIO_SetAFPin_0_7(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + else + { + LL_GPIO_SetAFPin_8_15(GPIOx, currentpin, GPIO_InitStruct->Alternate); + } + } + } + pinpos++; + } + + if ((GPIO_InitStruct->Mode == LL_GPIO_MODE_OUTPUT) || (GPIO_InitStruct->Mode == LL_GPIO_MODE_ALTERNATE)) + { + /* Check Output mode parameters */ + assert_param(IS_LL_GPIO_OUTPUT_TYPE(GPIO_InitStruct->OutputType)); + + /* Output mode configuration*/ + LL_GPIO_SetPinOutputType(GPIOx, GPIO_InitStruct->Pin, GPIO_InitStruct->OutputType); + + } + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_GPIO_StructInit(LL_GPIO_InitTypeDef *GPIO_InitStruct) +{ + /* Reset GPIO init structure parameters values */ + GPIO_InitStruct->Pin = LL_GPIO_PIN_ALL; + GPIO_InitStruct->Mode = LL_GPIO_MODE_ANALOG; + GPIO_InitStruct->Speed = LL_GPIO_SPEED_FREQ_LOW; + GPIO_InitStruct->OutputType = LL_GPIO_OUTPUT_PUSHPULL; + GPIO_InitStruct->Pull = LL_GPIO_PULL_NO; + GPIO_InitStruct->Alternate = LL_GPIO_AF_0; +} + + + + + + +#endif /* defined (GPIOA) || defined (GPIOB) || defined (GPIOF) */ + + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya Semiconductor *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_i2c.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_i2c.c similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_i2c.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_i2c.c index 1448988..77a3332 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_i2c.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_i2c.c @@ -1,194 +1,194 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_i2c.c - * @author MCU Application Team - * @brief I2C LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_i2c.h" -#include "py32f0xx_ll_bus.h" -#include "py32f0xx_ll_rcc.h" -#ifdef USE_FULL_ASSERT - #include "py32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (I2C1) || defined (I2C2) - -/** @defgroup I2C_LL I2C - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup I2C_LL_Private_Macros - * @{ - */ -#define IS_LL_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST)) - -#define IS_LL_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \ - ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9)) - -#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) - -#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ - ((__VALUE__) == LL_I2C_NACK)) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2C_LL_Exported_Functions - * @{ - */ - -/** @addtogroup I2C_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the I2C registers to their default reset values. - * @param I2Cx I2C Instance. - * @retval An ErrorStatus enumeration value: - * - SUCCESS I2C registers are de-initialized - * - ERROR I2C registers are not de-initialized - */ -uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx) -{ - ErrorStatus status = SUCCESS; - - /* Check the I2C Instance I2Cx */ - assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); - - if (I2Cx == I2C1) - { - /* Force reset of I2C clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); - - /* Release reset of I2C clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); - } - else - { - status = ERROR; - } - - return status; -} - -/** - * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. - * @param I2Cx I2C Instance. - * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure. - * @retval An ErrorStatus enumeration value: - * - SUCCESS I2C registers are initialized - * - ERROR Not applicable - */ -uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) -{ - LL_RCC_ClocksTypeDef rcc_clocks; - - /* Check the I2C Instance I2Cx */ - assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); - - /* Check the I2C parameters from I2C_InitStruct */ - assert_param(IS_LL_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed)); - assert_param(IS_LL_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle)); - assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1)); - assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge)); - - /* Disable the selected I2Cx Peripheral */ - LL_I2C_Disable(I2Cx); - - /* Retrieve Clock frequencies */ - LL_RCC_GetSystemClocksFreq(&rcc_clocks); - - /*---------------------------- I2Cx SCL Clock Speed Configuration ------------ - * Configure the SCL speed : - * - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS, - * and I2C_CCR_CCR[11:0] bits - * - DutyCycle: I2C_CCR_DUTY[7:0] bits - */ - LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle); - - /*---------------------------- I2Cx OAR1 Configuration ----------------------- - * Disable, Configure and Enable I2Cx device own address 1 with parameters : - * - OwnAddress1: I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits - * - OwnAddrSize: I2C_OAR1_ADDMODE bit - */ - LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, 0); - - /* Enable the selected I2Cx Peripheral */ - LL_I2C_Enable(I2Cx); - - /*---------------------------- I2Cx CR2 Configuration ------------------------ - * Configure the ACKnowledge or Non ACKnowledge condition - * after the address receive match code or next received byte with parameter : - * - TypeAcknowledge: I2C_CR2_NACK bit - */ - LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge); - - return SUCCESS; -} - -/** - * @brief Set each @ref LL_I2C_InitTypeDef field to default value. - * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure. - * @retval None - */ -void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) -{ - /* Set I2C_InitStruct fields to default values */ - I2C_InitStruct->ClockSpeed = 5000U; - I2C_InitStruct->DutyCycle = LL_I2C_DUTYCYCLE_2; - I2C_InitStruct->OwnAddress1 = 0U; - I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* I2C1 || I2C2 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_i2c.c + * @author MCU Application Team + * @brief I2C LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_i2c.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT + #include "py32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (I2C1) || defined (I2C2) + +/** @defgroup I2C_LL I2C + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup I2C_LL_Private_Macros + * @{ + */ +#define IS_LL_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST)) + +#define IS_LL_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \ + ((__VALUE__) == LL_I2C_DUTYCYCLE_16_9)) + +#define IS_LL_I2C_OWN_ADDRESS1(__VALUE__) ((__VALUE__) <= 0x000003FFU) + +#define IS_LL_I2C_TYPE_ACKNOWLEDGE(__VALUE__) (((__VALUE__) == LL_I2C_ACK) || \ + ((__VALUE__) == LL_I2C_NACK)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2C_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2C_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the I2C registers to their default reset values. + * @param I2Cx I2C Instance. + * @retval An ErrorStatus enumeration value: + * - SUCCESS I2C registers are de-initialized + * - ERROR I2C registers are not de-initialized + */ +uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx) +{ + ErrorStatus status = SUCCESS; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + if (I2Cx == I2C1) + { + /* Force reset of I2C clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_I2C1); + + /* Release reset of I2C clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_I2C1); + } + else + { + status = ERROR; + } + + return status; +} + +/** + * @brief Initialize the I2C registers according to the specified parameters in I2C_InitStruct. + * @param I2Cx I2C Instance. + * @param I2C_InitStruct pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval An ErrorStatus enumeration value: + * - SUCCESS I2C registers are initialized + * - ERROR Not applicable + */ +uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct) +{ + LL_RCC_ClocksTypeDef rcc_clocks; + + /* Check the I2C Instance I2Cx */ + assert_param(IS_I2C_ALL_INSTANCE(I2Cx)); + + /* Check the I2C parameters from I2C_InitStruct */ + assert_param(IS_LL_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed)); + assert_param(IS_LL_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle)); + assert_param(IS_LL_I2C_OWN_ADDRESS1(I2C_InitStruct->OwnAddress1)); + assert_param(IS_LL_I2C_TYPE_ACKNOWLEDGE(I2C_InitStruct->TypeAcknowledge)); + + /* Disable the selected I2Cx Peripheral */ + LL_I2C_Disable(I2Cx); + + /* Retrieve Clock frequencies */ + LL_RCC_GetSystemClocksFreq(&rcc_clocks); + + /*---------------------------- I2Cx SCL Clock Speed Configuration ------------ + * Configure the SCL speed : + * - ClockSpeed: I2C_CR2_FREQ[5:0], I2C_TRISE_TRISE[5:0], I2C_CCR_FS, + * and I2C_CCR_CCR[11:0] bits + * - DutyCycle: I2C_CCR_DUTY[7:0] bits + */ + LL_I2C_ConfigSpeed(I2Cx, rcc_clocks.PCLK1_Frequency, I2C_InitStruct->ClockSpeed, I2C_InitStruct->DutyCycle); + + /*---------------------------- I2Cx OAR1 Configuration ----------------------- + * Disable, Configure and Enable I2Cx device own address 1 with parameters : + * - OwnAddress1: I2C_OAR1_ADD[9:8], I2C_OAR1_ADD[7:1] and I2C_OAR1_ADD0 bits + * - OwnAddrSize: I2C_OAR1_ADDMODE bit + */ + LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, 0); + + /* Enable the selected I2Cx Peripheral */ + LL_I2C_Enable(I2Cx); + + /*---------------------------- I2Cx CR2 Configuration ------------------------ + * Configure the ACKnowledge or Non ACKnowledge condition + * after the address receive match code or next received byte with parameter : + * - TypeAcknowledge: I2C_CR2_NACK bit + */ + LL_I2C_AcknowledgeNextData(I2Cx, I2C_InitStruct->TypeAcknowledge); + + return SUCCESS; +} + +/** + * @brief Set each @ref LL_I2C_InitTypeDef field to default value. + * @param I2C_InitStruct Pointer to a @ref LL_I2C_InitTypeDef structure. + * @retval None + */ +void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct) +{ + /* Set I2C_InitStruct fields to default values */ + I2C_InitStruct->ClockSpeed = 5000U; + I2C_InitStruct->DutyCycle = LL_I2C_DUTYCYCLE_2; + I2C_InitStruct->OwnAddress1 = 0U; + I2C_InitStruct->TypeAcknowledge = LL_I2C_NACK; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* I2C1 || I2C2 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_led.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_led.c similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_led.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_led.c index 586217f..39ced46 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_led.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_led.c @@ -1,158 +1,158 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_led.c - * @author MCU Application Team - * @brief LED LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_led.h" -#include "py32f0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT - #include "py32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (LED) - -/** @addtogroup LED_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ - -/** @addtogroup LED_LL_Private_Macros - * @{ - */ -#define IS_LL_LED_COM_DRIVE(__VALUE__) (((__VALUE__) == LL_LED_COMDRIVE_LOW) ||\ - ((__VALUE__) == LL_LED_COMDRIVE_HIGH)) - -#define IS_LL_LED_PRESCALER(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (0xFFu))) - -#define IS_LL_LED_COM_SELECT(__VALUE__) (((__VALUE__) == LL_LED_COMSELECT_1COM) ||\ - ((__VALUE__) == LL_LED_COMSELECT_2COM) ||\ - ((__VALUE__) == LL_LED_COMSELECT_3COM) ||\ - ((__VALUE__) == LL_LED_COMSELECT_4COM)) - -#define IS_LL_LED_LIGHT_TIME(__VALUE__) (((0x01u) < (__VALUE__)) && ((__VALUE__) <= (0xFFu))) - -#define IS_LL_LED_DEAD_TIME(__VALUE__) (((0x01u) < (__VALUE__)) && ((__VALUE__) <= (0xFFu))) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup LED_LL_Exported_Functions - * @{ - */ - -/** @addtogroup LED_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize LED registers. - * @param LEDx LED Port - * @retval An ErrorStatus enumeration value: - * - SUCCESS: LED registers are de-initialized - * - ERROR: Wrong LED - */ -ErrorStatus LL_LED_DeInit(LED_TypeDef *LEDx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_LED_ALL_INSTANCE(LEDx)); - - /* Force and Release reset on clock of LEDx */ - if (LEDx == LED) - { - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LED); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LED); - } - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initializes the LED registers according to the specified parameters in the LED_InitStruct. - * @param LEDx LEDx Instance - * @param LED_InitStruct pointer to a @ref LL_LED_InitTypeDef structure - * that contains the configuration information for the specified LED peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: LED registers are initialized according to LED_InitStruct content - * - ERROR: Not applicable - */ -ErrorStatus LL_LED_Init(LED_TypeDef *LEDx, LL_LED_InitTypeDef *LED_InitStruct) -{ - /* Check the parameters */ - assert_param(IS_LED_ALL_INSTANCE(LEDx)); - assert_param(IS_LL_LED_COM_DRIVE(LED_InitStruct->ComDrive)); - assert_param(IS_LL_LED_PRESCALER(LED_InitStruct->Prescaler)); - assert_param(IS_LL_LED_COM_SELECT(LED_InitStruct->ComSelect)); - assert_param(IS_LL_LED_LIGHT_TIME(LED_InitStruct->LightTime)); - assert_param(IS_LL_LED_DEAD_TIME(LED_InitStruct->DeadTime)); - - /* LED Register config */ - MODIFY_REG(LEDx->CR, (uint32_t)(LED_CR_LED_COM_SEL | LED_CR_EHS), - (LED_InitStruct->ComSelect | LED_InitStruct->ComDrive)); - LL_LED_SetPrescaler(LEDx, LED_InitStruct->Prescaler); - LL_LED_SetLightAndDeadTime(LEDx, LED_InitStruct->LightTime, LED_InitStruct->DeadTime); - LL_LED_Enable(LEDx); - - return (SUCCESS); -} - -/** - * @brief Set each @ref LL_LED_InitTypeDef field to default value. - * @param LED_InitStruct pointer to a @ref LL_LED_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ - -void LL_LED_StructInit(LL_LED_InitTypeDef *LED_InitStruct) -{ - /* Reset LED init structure parameters values */ - LED_InitStruct->ComDrive = LL_LED_COMDRIVE_LOW; - LED_InitStruct->Prescaler = 0x0u; - LED_InitStruct->ComSelect = LL_LED_COMSELECT_1COM; - LED_InitStruct->LightTime = 0x0u; - LED_InitStruct->DeadTime = 0x0u; -} - -#endif /* defined (LED) */ - - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya Semiconductor *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_led.c + * @author MCU Application Team + * @brief LED LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_led.h" +#include "py32f0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT + #include "py32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (LED) + +/** @addtogroup LED_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ + +/** @addtogroup LED_LL_Private_Macros + * @{ + */ +#define IS_LL_LED_COM_DRIVE(__VALUE__) (((__VALUE__) == LL_LED_COMDRIVE_LOW) ||\ + ((__VALUE__) == LL_LED_COMDRIVE_HIGH)) + +#define IS_LL_LED_PRESCALER(__VALUE__) (((0x00u) < (__VALUE__)) && ((__VALUE__) <= (0xFFu))) + +#define IS_LL_LED_COM_SELECT(__VALUE__) (((__VALUE__) == LL_LED_COMSELECT_1COM) ||\ + ((__VALUE__) == LL_LED_COMSELECT_2COM) ||\ + ((__VALUE__) == LL_LED_COMSELECT_3COM) ||\ + ((__VALUE__) == LL_LED_COMSELECT_4COM)) + +#define IS_LL_LED_LIGHT_TIME(__VALUE__) (((0x01u) < (__VALUE__)) && ((__VALUE__) <= (0xFFu))) + +#define IS_LL_LED_DEAD_TIME(__VALUE__) (((0x01u) < (__VALUE__)) && ((__VALUE__) <= (0xFFu))) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup LED_LL_Exported_Functions + * @{ + */ + +/** @addtogroup LED_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize LED registers. + * @param LEDx LED Port + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LED registers are de-initialized + * - ERROR: Wrong LED + */ +ErrorStatus LL_LED_DeInit(LED_TypeDef *LEDx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_LED_ALL_INSTANCE(LEDx)); + + /* Force and Release reset on clock of LEDx */ + if (LEDx == LED) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_LED); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_LED); + } + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initializes the LED registers according to the specified parameters in the LED_InitStruct. + * @param LEDx LEDx Instance + * @param LED_InitStruct pointer to a @ref LL_LED_InitTypeDef structure + * that contains the configuration information for the specified LED peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: LED registers are initialized according to LED_InitStruct content + * - ERROR: Not applicable + */ +ErrorStatus LL_LED_Init(LED_TypeDef *LEDx, LL_LED_InitTypeDef *LED_InitStruct) +{ + /* Check the parameters */ + assert_param(IS_LED_ALL_INSTANCE(LEDx)); + assert_param(IS_LL_LED_COM_DRIVE(LED_InitStruct->ComDrive)); + assert_param(IS_LL_LED_PRESCALER(LED_InitStruct->Prescaler)); + assert_param(IS_LL_LED_COM_SELECT(LED_InitStruct->ComSelect)); + assert_param(IS_LL_LED_LIGHT_TIME(LED_InitStruct->LightTime)); + assert_param(IS_LL_LED_DEAD_TIME(LED_InitStruct->DeadTime)); + + /* LED Register config */ + MODIFY_REG(LEDx->CR, (uint32_t)(LED_CR_LED_COM_SEL | LED_CR_EHS), + (LED_InitStruct->ComSelect | LED_InitStruct->ComDrive)); + LL_LED_SetPrescaler(LEDx, LED_InitStruct->Prescaler); + LL_LED_SetLightAndDeadTime(LEDx, LED_InitStruct->LightTime, LED_InitStruct->DeadTime); + LL_LED_Enable(LEDx); + + return (SUCCESS); +} + +/** + * @brief Set each @ref LL_LED_InitTypeDef field to default value. + * @param LED_InitStruct pointer to a @ref LL_LED_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_LED_StructInit(LL_LED_InitTypeDef *LED_InitStruct) +{ + /* Reset LED init structure parameters values */ + LED_InitStruct->ComDrive = LL_LED_COMDRIVE_LOW; + LED_InitStruct->Prescaler = 0x0u; + LED_InitStruct->ComSelect = LL_LED_COMSELECT_1COM; + LED_InitStruct->LightTime = 0x0u; + LED_InitStruct->DeadTime = 0x0u; +} + +#endif /* defined (LED) */ + + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya Semiconductor *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_lptim.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_lptim.c similarity index 99% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_lptim.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_lptim.c index 7b12d57..7ce76c6 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_lptim.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_lptim.c @@ -3,21 +3,21 @@ * @file py32f0xx_ll_lptim.c * @author MCU Application Team * @brief LPTIM LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_pwr.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_pwr.c similarity index 99% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_pwr.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_pwr.c index 64d2c42..af52904 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_pwr.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_pwr.c @@ -3,21 +3,21 @@ * @file py32f0xx_ll_pwr.c * @author MCU Application Team * @brief PWR LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** */ #if defined(USE_FULL_LL_DRIVER) diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_rcc.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_rcc.c similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_rcc.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_rcc.c index 31988e2..afe17f8 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_rcc.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_rcc.c @@ -1,558 +1,558 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_rcc.c - * @author MCU Application Team - * @brief RCC LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_rcc.h" -#ifdef USE_FULL_ASSERT - #include "py32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined(RCC) - -/** @addtogroup RCC_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RCC_LL_Private_Macros - * @{ - */ -#define IS_LL_RCC_MCO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_MCO1_CLKSOURCE)) - -#if (defined(RCC_CCIPR_COMP1SEL) && defined(RCC_CCIPR_COMP2SEL)) -#define IS_LL_RCC_COMP_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_COMP1_CLKSOURCE) \ - || ((__VALUE__) == LL_RCC_COMP2_CLKSOURCE)) -#endif - -#if defined(RCC_CCIPR_LPTIMSEL) - #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)) -#endif /* LPTIM1 */ - - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup RCC_LL_Private_Functions RCC Private functions - * @{ - */ -uint32_t RCC_GetSystemClockFreq(void); -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); -#if defined(RCC_PLL_SUPPORT) - uint32_t RCC_PLL_GetFreqDomain_SYS(void); -#endif -/** - * @} - */ - - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RCC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup RCC_LL_EF_Init - * @{ - */ - -/** - * @brief Reset the RCC clock configuration to the default reset state. - * @note The default reset state of the clock configuration is given below: - * - HSI ON and used as system clock source - * - HSE and PLL OFF - * - AHB and APB1 prescaler set to 1. - * - CSS, MCO OFF - * - All interrupts disabled - * @note This function does not modify the configuration of the - * - Peripheral clocks - * - LSI, LSE and RTC clocks - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RCC registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_RCC_DeInit(void) -{ - /* Set HSION bit and wait for HSI READY bit */ - LL_RCC_HSI_Enable(); - while (LL_RCC_HSI_IsReady() != 1U) - {} - - /* Set HSI_FS, HSITRIM bits to default value*/ - LL_RCC_HSI_SetCalibFreq(LL_RCC_HSICALIBRATION_8MHz); - - /* Reset CFGR register */ - LL_RCC_WriteReg(CFGR, 0x00000000U); - - /* Wait till SYSCLK is HSISYS */ - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS) - {} - - /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */ - LL_RCC_WriteReg(CR, RCC_CR_HSION); - while (LL_RCC_HSE_IsReady() != 0U) - {} - LL_RCC_WriteReg(CR, RCC_CR_HSION); -#if defined(RCC_PLL_SUPPORT) - /* Wait for PLL READY bit to be reset */ - while (LL_RCC_PLL_IsReady() != 0U) - {} - - /* Reset PLLCFGR register */ - LL_RCC_WriteReg(PLLCFGR, 0x00000000U); -#endif - /* Disable all interrupts */ - LL_RCC_WriteReg(CIER, 0x00000000U); - - /* Clear all interrupts flags */ - LL_RCC_WriteReg(CICR, 0xFFFFFFFFU); - - return SUCCESS; -} - -/** - * @} - */ - -/** @addtogroup RCC_LL_EF_Get_Freq - * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks - * and different peripheral clocks available on the device. - * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE divided by HSI division factor(**) - * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) - * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) - * or HSI_VALUE(**) multiplied/divided by the PLL factors. - * @note (**) HSI_VALUE is a constant defined in this file (default value - * 8 MHz) but the real value may vary depending on the variations - * in voltage and temperature. - * @note (***) HSE_VALUE is a constant defined in this file (default value - * 8 MHz), user has to ensure that HSE_VALUE is same as the real - * frequency of the crystal used. Otherwise, this function may - * have wrong result. - * @note The result of this function could be incorrect when using fractional - * value for HSE crystal. - * @note This function can be used by the user application to compute the - * baud-rate for the communication peripherals or configure other parameters. - * @{ - */ - -/** - * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks - * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function - * must be called to update structure fields. Otherwise, any - * configuration based on this function will be incorrect. - * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies - * @retval None - */ -void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) -{ - /* Get SYSCLK frequency */ - RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); - - /* HCLK clock frequency */ - RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); - - /* PCLK1 clock frequency */ - RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); -} - -/** - * @brief Return MCO clock frequency - * @param MCOx This parameter can be one of the following values: - * @arg @ref LL_RCC_MCO1_CLKSOURCE - * @retval MCO clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSE, LSI or LSE) is not ready - * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected - */ -uint32_t LL_RCC_GetMCOClockFreq(uint32_t MCOx) -{ - uint32_t mco_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_MCO_CLKSOURCE(MCOx)); - - switch (LL_RCC_GetMCOClockSource(MCOx)) - { - case LL_RCC_MCO1SOURCE_SYSCLK: /* MCO Clock is SYSCLK */ - mco_frequency = SystemCoreClock; - break; - case LL_RCC_MCO1SOURCE_HSI: /* MCO Clock is HSI */ - mco_frequency = LL_RCC_HSI_GetFreq(); - break; - case LL_RCC_MCO1SOURCE_HSE: /* MCO Clock is HSE */ - if (LL_RCC_HSE_IsReady() == 1U) - { - mco_frequency = HSE_VALUE; - } - break; -#if defined(RCC_PLL_SUPPORT) - case LL_RCC_MCO1SOURCE_PLLCLK: /* MCO Clock is PLLCLK */ - mco_frequency = RCC_PLL_GetFreqDomain_SYS(); - break; -#endif - case LL_RCC_MCO1SOURCE_LSI: /* MCO Clock is LSI */ - if (LL_RCC_LSI_IsReady() == 1U) - { - mco_frequency = LSI_VALUE; - } - break; -#if defined(RCC_LSE_SUPPORT) - case LL_RCC_MCO1SOURCE_LSE: /* MCO Clock is LSE */ - if (LL_RCC_LSE_IsReady() == 1U) - { - mco_frequency = LSE_VALUE; - } - break; -#endif - case LL_RCC_MCO1SOURCE_NOCLOCK: /* No clock used as MCO clock source */ - default: - mco_frequency = LL_RCC_PERIPH_FREQUENCY_NA; - return mco_frequency; - } - - mco_frequency = mco_frequency / (1U << (LL_RCC_GetMCODiv(MCOx) >> RCC_CFGR_MCOPRE_Pos)); - - return mco_frequency; -} - -#if defined(RCC_BDCR_LSCOEN) -/** - * @brief Return LSC clock frequency - * @retval LSC clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (LSI or LSE) is not ready - */ -uint32_t LL_RCC_GetLSCClockFreq(void) -{ -#if defined(RCC_LSE_SUPPORT) - uint32_t lsc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - switch (LL_RCC_LSCO_GetSource()) - { - case LL_RCC_LSCO_CLKSOURCE_LSE: /* LSC Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady() == 1U) - { - lsc_frequency = LSE_VALUE; - } - break; - - case LL_RCC_LSCO_CLKSOURCE_LSI: /* LSC Clock is LSI Osc. */ - default: - if (LL_RCC_LSI_IsReady() == 1U) - { - lsc_frequency = LSI_VALUE; - } - break; - } - return lsc_frequency; -#else - return LSI_VALUE; -#endif -} -#endif - -#if defined(RCC_CCIPR_PVDSEL) -/** - * @brief Return PVD clock frequency - * @retval PVD clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (PCLK1, LSI or LSE) is not ready - */ -uint32_t LL_RCC_GetPVDClockFreq(void) -{ - uint32_t pvd_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* PVDCLK clock frequency */ - switch (LL_RCC_GetPVDClockSource()) - { - case LL_RCC_PVD_CLKSOURCE_LSC: /* PVD Clock is LSC */ - pvd_frequency = LL_RCC_GetLSCClockFreq(); - break; - - case LL_RCC_PVD_CLKSOURCE_PCLK1: /* PVD Clock is PCLK1 */ - default: - pvd_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - return pvd_frequency; - -} -#endif - -#if defined(COMP1) -/** - * @brief Return COMP clock frequency - * @param COMPx This parameter can be one of the following values: - * @arg @ref LL_RCC_COMP1_CLKSOURCE - * @retval COMP clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (PCLK1, LSI or LSE) is not ready - */ -uint32_t LL_RCC_GetCOMPClockFreq(uint32_t COMPx) -{ - uint32_t comp_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_COMP_CLKSOURCE(COMPx)); - - if (COMPx == LL_RCC_COMP1_CLKSOURCE) - { - /* COMP1CLK clock frequency */ - switch (LL_RCC_GetCOMPClockSource(COMPx)) - { - case LL_RCC_COMP1_CLKSOURCE_LSC: /* COMP1 Clock is LSC */ - comp_frequency = LL_RCC_GetLSCClockFreq(); - break; - - case LL_RCC_COMP1_CLKSOURCE_PCLK1: /* COMP1 Clock is PCLK1 */ - default: - comp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } -#if defined(COMP2) - else - { - /* COMP2CLK clock frequency */ - switch (LL_RCC_GetCOMPClockSource(COMPx)) - { - case LL_RCC_COMP2_CLKSOURCE_LSC: /* COMP2 Clock is LSC */ - comp_frequency = LL_RCC_GetLSCClockFreq(); - break; - - case LL_RCC_COMP2_CLKSOURCE_PCLK1: /* COMP2 Clock is PCLK1 */ - default: - comp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } -#endif - return comp_frequency; -} -#endif - -/** - * @brief Return LPTIMx clock frequency - * @param LPTIMx This parameter can be one of the following values: - * @arg @ref LL_RCC_LPTIM1_CLKSOURCE - * @retval LPTIM clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (PCLK1, LSI or LSE) is not ready - * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected - */ -uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMx) -{ - uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* Check parameter */ - assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMx)); - - if (LPTIMx == LL_RCC_LPTIM1_CLKSOURCE) - { - /* LPTIM1CLK clock frequency */ - switch (LL_RCC_GetLPTIMClockSource(LPTIMx)) - { - case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ - if (LL_RCC_LSI_IsReady() == 1U) - { - lptim_frequency = LSI_VALUE; - } - break; - - case LL_RCC_LPTIM1_CLKSOURCE_NONE: /* No clock used as LPTIM1 clock source */ - lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NA; - break; -#if defined(RCC_LSE_SUPPORT) - case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ - if (LL_RCC_LSE_IsReady() == 1U) - { - lptim_frequency = LSE_VALUE; - } - break; -#endif - case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ - default: - lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); - break; - } - } - return lptim_frequency; -} - -#if defined(RCC_BDCR_RTCSEL) -/** - * @brief Return RTC clock frequency - * @retval RTC clock frequency (in Hz) - * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready - * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected - */ -uint32_t LL_RCC_GetRTCClockFreq(void) -{ - uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; - - /* RTCCLK clock frequency */ - switch (LL_RCC_GetRTCClockSource()) - { -#if defined(RCC_LSE_SUPPORT) - case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */ - if (LL_RCC_LSE_IsReady() == 1U) - { - rtc_frequency = LSE_VALUE; - } - break; -#endif - case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */ - if (LL_RCC_LSI_IsReady() == 1U) - { - rtc_frequency = LSI_VALUE; - } - break; - - case LL_RCC_RTC_CLKSOURCE_HSE_DIV128: /* HSE/128 clock used as RTC clock source */ - if (LL_RCC_HSE_IsReady() == 1U) - { - rtc_frequency = HSE_VALUE / 128U; - } - - break; - - case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */ - default: - rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; - break; - } - return rtc_frequency; -} -#endif - -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup RCC_LL_Private_Functions - * @{ - */ - -/** - * @brief Return SYSTEM clock frequency - * @retval SYSTEM clock frequency (in Hz) - */ -uint32_t RCC_GetSystemClockFreq(void) -{ - uint32_t frequency; - - /* Get SYSCLK source -------------------------------------------------------*/ - switch (LL_RCC_GetSysClkSource()) - { - case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ - frequency = HSE_VALUE; - break; -#if defined(RCC_PLL_SUPPORT) - case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ - frequency = RCC_PLL_GetFreqDomain_SYS(); - break; -#endif - case LL_RCC_SYS_CLKSOURCE_STATUS_LSI: - frequency = LSI_VALUE; -#if defined(RCC_LSE_SUPPORT) - case LL_RCC_SYS_CLKSOURCE_STATUS_LSE: - frequency = LSE_VALUE; -#endif - case LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS: /* HSISYS used as system clock source */ - default: - frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_GetHSIDiv()); - break; - } - - return frequency; -} - -/** - * @brief Return HCLK clock frequency - * @param SYSCLK_Frequency SYSCLK clock frequency - * @retval HCLK clock frequency (in Hz) - */ -uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) -{ - /* HCLK clock frequency */ - return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); -} - -/** - * @brief Return PCLK1 clock frequency - * @param HCLK_Frequency HCLK clock frequency - * @retval PCLK1 clock frequency (in Hz) - */ -uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) -{ - /* PCLK1 clock frequency */ - return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); -} -#if defined(RCC_PLL_SUPPORT) -/** - * @brief Return PLL clock frequency used for system domain - * @retval PLL clock frequency (in Hz) - */ -uint32_t RCC_PLL_GetFreqDomain_SYS(void) -{ - uint32_t pllinputfreq; - uint32_t pllsource; - - pllsource = LL_RCC_PLL_GetMainSource(); - - switch (pllsource) - { - case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ - pllinputfreq = HSE_VALUE; - break; - - case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ - default: - pllinputfreq = LL_RCC_HSI_GetFreq(); - break; - } - return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq); -} -#endif -/** - * @} - */ - - -#endif /* defined(RCC) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya*****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_rcc.c + * @author MCU Application Team + * @brief RCC LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_rcc.h" +#ifdef USE_FULL_ASSERT + #include "py32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined(RCC) + +/** @addtogroup RCC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RCC_LL_Private_Macros + * @{ + */ +#define IS_LL_RCC_MCO_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_MCO1_CLKSOURCE)) + +#if (defined(RCC_CCIPR_COMP1SEL) && defined(RCC_CCIPR_COMP2SEL)) +#define IS_LL_RCC_COMP_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_COMP1_CLKSOURCE) \ + || ((__VALUE__) == LL_RCC_COMP2_CLKSOURCE)) +#endif + +#if defined(RCC_CCIPR_LPTIMSEL) + #define IS_LL_RCC_LPTIM_CLKSOURCE(__VALUE__) (((__VALUE__) == LL_RCC_LPTIM1_CLKSOURCE)) +#endif /* LPTIM1 */ + + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup RCC_LL_Private_Functions RCC Private functions + * @{ + */ +uint32_t RCC_GetSystemClockFreq(void); +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency); +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency); +#if defined(RCC_PLL_SUPPORT) + uint32_t RCC_PLL_GetFreqDomain_SYS(void); +#endif +/** + * @} + */ + + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RCC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RCC_LL_EF_Init + * @{ + */ + +/** + * @brief Reset the RCC clock configuration to the default reset state. + * @note The default reset state of the clock configuration is given below: + * - HSI ON and used as system clock source + * - HSE and PLL OFF + * - AHB and APB1 prescaler set to 1. + * - CSS, MCO OFF + * - All interrupts disabled + * @note This function does not modify the configuration of the + * - Peripheral clocks + * - LSI, LSE and RTC clocks + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RCC registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_RCC_DeInit(void) +{ + /* Set HSION bit and wait for HSI READY bit */ + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + {} + + /* Set HSI_FS, HSITRIM bits to default value*/ + LL_RCC_HSI_SetCalibFreq(LL_RCC_HSICALIBRATION_8MHz); + + /* Reset CFGR register */ + LL_RCC_WriteReg(CFGR, 0x00000000U); + + /* Wait till SYSCLK is HSISYS */ + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS) + {} + + /* Reset whole CR register but HSI in 2 steps in case HSEBYP is set */ + LL_RCC_WriteReg(CR, RCC_CR_HSION); + while (LL_RCC_HSE_IsReady() != 0U) + {} + LL_RCC_WriteReg(CR, RCC_CR_HSION); +#if defined(RCC_PLL_SUPPORT) + /* Wait for PLL READY bit to be reset */ + while (LL_RCC_PLL_IsReady() != 0U) + {} + + /* Reset PLLCFGR register */ + LL_RCC_WriteReg(PLLCFGR, 0x00000000U); +#endif + /* Disable all interrupts */ + LL_RCC_WriteReg(CIER, 0x00000000U); + + /* Clear all interrupts flags */ + LL_RCC_WriteReg(CICR, 0xFFFFFFFFU); + + return SUCCESS; +} + +/** + * @} + */ + +/** @addtogroup RCC_LL_EF_Get_Freq + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * and different peripheral clocks available on the device. + * @note If SYSCLK source is HSI, function returns values based on HSI_VALUE divided by HSI division factor(**) + * @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(***) + * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(***) + * or HSI_VALUE(**) multiplied/divided by the PLL factors. + * @note (**) HSI_VALUE is a constant defined in this file (default value + * 8 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * @note (***) HSE_VALUE is a constant defined in this file (default value + * 8 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * @note The result of this function could be incorrect when using fractional + * value for HSE crystal. + * @note This function can be used by the user application to compute the + * baud-rate for the communication peripherals or configure other parameters. + * @{ + */ + +/** + * @brief Return the frequencies of different on chip clocks; System, AHB and APB1 buses clocks + * @note Each time SYSCLK, HCLK and/or PCLK1 clock changes, this function + * must be called to update structure fields. Otherwise, any + * configuration based on this function will be incorrect. + * @param RCC_Clocks pointer to a @ref LL_RCC_ClocksTypeDef structure which will hold the clocks frequencies + * @retval None + */ +void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks) +{ + /* Get SYSCLK frequency */ + RCC_Clocks->SYSCLK_Frequency = RCC_GetSystemClockFreq(); + + /* HCLK clock frequency */ + RCC_Clocks->HCLK_Frequency = RCC_GetHCLKClockFreq(RCC_Clocks->SYSCLK_Frequency); + + /* PCLK1 clock frequency */ + RCC_Clocks->PCLK1_Frequency = RCC_GetPCLK1ClockFreq(RCC_Clocks->HCLK_Frequency); +} + +/** + * @brief Return MCO clock frequency + * @param MCOx This parameter can be one of the following values: + * @arg @ref LL_RCC_MCO1_CLKSOURCE + * @retval MCO clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (HSE, LSI or LSE) is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetMCOClockFreq(uint32_t MCOx) +{ + uint32_t mco_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_MCO_CLKSOURCE(MCOx)); + + switch (LL_RCC_GetMCOClockSource(MCOx)) + { + case LL_RCC_MCO1SOURCE_SYSCLK: /* MCO Clock is SYSCLK */ + mco_frequency = SystemCoreClock; + break; + case LL_RCC_MCO1SOURCE_HSI: /* MCO Clock is HSI */ + mco_frequency = LL_RCC_HSI_GetFreq(); + break; + case LL_RCC_MCO1SOURCE_HSE: /* MCO Clock is HSE */ + if (LL_RCC_HSE_IsReady() == 1U) + { + mco_frequency = HSE_VALUE; + } + break; +#if defined(RCC_PLL_SUPPORT) + case LL_RCC_MCO1SOURCE_PLLCLK: /* MCO Clock is PLLCLK */ + mco_frequency = RCC_PLL_GetFreqDomain_SYS(); + break; +#endif + case LL_RCC_MCO1SOURCE_LSI: /* MCO Clock is LSI */ + if (LL_RCC_LSI_IsReady() == 1U) + { + mco_frequency = LSI_VALUE; + } + break; +#if defined(RCC_LSE_SUPPORT) + case LL_RCC_MCO1SOURCE_LSE: /* MCO Clock is LSE */ + if (LL_RCC_LSE_IsReady() == 1U) + { + mco_frequency = LSE_VALUE; + } + break; +#endif + case LL_RCC_MCO1SOURCE_NOCLOCK: /* No clock used as MCO clock source */ + default: + mco_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + return mco_frequency; + } + + mco_frequency = mco_frequency / (1U << (LL_RCC_GetMCODiv(MCOx) >> RCC_CFGR_MCOPRE_Pos)); + + return mco_frequency; +} + +#if defined(RCC_BDCR_LSCOEN) +/** + * @brief Return LSC clock frequency + * @retval LSC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (LSI or LSE) is not ready + */ +uint32_t LL_RCC_GetLSCClockFreq(void) +{ +#if defined(RCC_LSE_SUPPORT) + uint32_t lsc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + switch (LL_RCC_LSCO_GetSource()) + { + case LL_RCC_LSCO_CLKSOURCE_LSE: /* LSC Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + lsc_frequency = LSE_VALUE; + } + break; + + case LL_RCC_LSCO_CLKSOURCE_LSI: /* LSC Clock is LSI Osc. */ + default: + if (LL_RCC_LSI_IsReady() == 1U) + { + lsc_frequency = LSI_VALUE; + } + break; + } + return lsc_frequency; +#else + return LSI_VALUE; +#endif +} +#endif + +#if defined(RCC_CCIPR_PVDSEL) +/** + * @brief Return PVD clock frequency + * @retval PVD clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (PCLK1, LSI or LSE) is not ready + */ +uint32_t LL_RCC_GetPVDClockFreq(void) +{ + uint32_t pvd_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* PVDCLK clock frequency */ + switch (LL_RCC_GetPVDClockSource()) + { + case LL_RCC_PVD_CLKSOURCE_LSC: /* PVD Clock is LSC */ + pvd_frequency = LL_RCC_GetLSCClockFreq(); + break; + + case LL_RCC_PVD_CLKSOURCE_PCLK1: /* PVD Clock is PCLK1 */ + default: + pvd_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + return pvd_frequency; + +} +#endif + +#if defined(COMP1) +/** + * @brief Return COMP clock frequency + * @param COMPx This parameter can be one of the following values: + * @arg @ref LL_RCC_COMP1_CLKSOURCE + * @retval COMP clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (PCLK1, LSI or LSE) is not ready + */ +uint32_t LL_RCC_GetCOMPClockFreq(uint32_t COMPx) +{ + uint32_t comp_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_COMP_CLKSOURCE(COMPx)); + + if (COMPx == LL_RCC_COMP1_CLKSOURCE) + { + /* COMP1CLK clock frequency */ + switch (LL_RCC_GetCOMPClockSource(COMPx)) + { + case LL_RCC_COMP1_CLKSOURCE_LSC: /* COMP1 Clock is LSC */ + comp_frequency = LL_RCC_GetLSCClockFreq(); + break; + + case LL_RCC_COMP1_CLKSOURCE_PCLK1: /* COMP1 Clock is PCLK1 */ + default: + comp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#if defined(COMP2) + else + { + /* COMP2CLK clock frequency */ + switch (LL_RCC_GetCOMPClockSource(COMPx)) + { + case LL_RCC_COMP2_CLKSOURCE_LSC: /* COMP2 Clock is LSC */ + comp_frequency = LL_RCC_GetLSCClockFreq(); + break; + + case LL_RCC_COMP2_CLKSOURCE_PCLK1: /* COMP2 Clock is PCLK1 */ + default: + comp_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } +#endif + return comp_frequency; +} +#endif + +/** + * @brief Return LPTIMx clock frequency + * @param LPTIMx This parameter can be one of the following values: + * @arg @ref LL_RCC_LPTIM1_CLKSOURCE + * @retval LPTIM clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillator (PCLK1, LSI or LSE) is not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMx) +{ + uint32_t lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* Check parameter */ + assert_param(IS_LL_RCC_LPTIM_CLKSOURCE(LPTIMx)); + + if (LPTIMx == LL_RCC_LPTIM1_CLKSOURCE) + { + /* LPTIM1CLK clock frequency */ + switch (LL_RCC_GetLPTIMClockSource(LPTIMx)) + { + case LL_RCC_LPTIM1_CLKSOURCE_LSI: /* LPTIM1 Clock is LSI Osc. */ + if (LL_RCC_LSI_IsReady() == 1U) + { + lptim_frequency = LSI_VALUE; + } + break; + + case LL_RCC_LPTIM1_CLKSOURCE_NONE: /* No clock used as LPTIM1 clock source */ + lptim_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; +#if defined(RCC_LSE_SUPPORT) + case LL_RCC_LPTIM1_CLKSOURCE_LSE: /* LPTIM1 Clock is LSE Osc. */ + if (LL_RCC_LSE_IsReady() == 1U) + { + lptim_frequency = LSE_VALUE; + } + break; +#endif + case LL_RCC_LPTIM1_CLKSOURCE_PCLK1: /* LPTIM1 Clock is PCLK1 */ + default: + lptim_frequency = RCC_GetPCLK1ClockFreq(RCC_GetHCLKClockFreq(RCC_GetSystemClockFreq())); + break; + } + } + return lptim_frequency; +} + +#if defined(RCC_BDCR_RTCSEL) +/** + * @brief Return RTC clock frequency + * @retval RTC clock frequency (in Hz) + * - @ref LL_RCC_PERIPH_FREQUENCY_NO indicates that oscillators (LSI, LSE or HSE) are not ready + * - @ref LL_RCC_PERIPH_FREQUENCY_NA indicates that no clock source selected + */ +uint32_t LL_RCC_GetRTCClockFreq(void) +{ + uint32_t rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NO; + + /* RTCCLK clock frequency */ + switch (LL_RCC_GetRTCClockSource()) + { +#if defined(RCC_LSE_SUPPORT) + case LL_RCC_RTC_CLKSOURCE_LSE: /* LSE clock used as RTC clock source */ + if (LL_RCC_LSE_IsReady() == 1U) + { + rtc_frequency = LSE_VALUE; + } + break; +#endif + case LL_RCC_RTC_CLKSOURCE_LSI: /* LSI clock used as RTC clock source */ + if (LL_RCC_LSI_IsReady() == 1U) + { + rtc_frequency = LSI_VALUE; + } + break; + + case LL_RCC_RTC_CLKSOURCE_HSE_DIV128: /* HSE/128 clock used as RTC clock source */ + if (LL_RCC_HSE_IsReady() == 1U) + { + rtc_frequency = HSE_VALUE / 128U; + } + + break; + + case LL_RCC_RTC_CLKSOURCE_NONE: /* No clock used as RTC clock source */ + default: + rtc_frequency = LL_RCC_PERIPH_FREQUENCY_NA; + break; + } + return rtc_frequency; +} +#endif + +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup RCC_LL_Private_Functions + * @{ + */ + +/** + * @brief Return SYSTEM clock frequency + * @retval SYSTEM clock frequency (in Hz) + */ +uint32_t RCC_GetSystemClockFreq(void) +{ + uint32_t frequency; + + /* Get SYSCLK source -------------------------------------------------------*/ + switch (LL_RCC_GetSysClkSource()) + { + case LL_RCC_SYS_CLKSOURCE_STATUS_HSE: /* HSE used as system clock source */ + frequency = HSE_VALUE; + break; +#if defined(RCC_PLL_SUPPORT) + case LL_RCC_SYS_CLKSOURCE_STATUS_PLL: /* PLL used as system clock source */ + frequency = RCC_PLL_GetFreqDomain_SYS(); + break; +#endif + case LL_RCC_SYS_CLKSOURCE_STATUS_LSI: + frequency = LSI_VALUE; +#if defined(RCC_LSE_SUPPORT) + case LL_RCC_SYS_CLKSOURCE_STATUS_LSE: + frequency = LSE_VALUE; +#endif + case LL_RCC_SYS_CLKSOURCE_STATUS_HSISYS: /* HSISYS used as system clock source */ + default: + frequency = __LL_RCC_CALC_HSI_FREQ(LL_RCC_GetHSIDiv()); + break; + } + + return frequency; +} + +/** + * @brief Return HCLK clock frequency + * @param SYSCLK_Frequency SYSCLK clock frequency + * @retval HCLK clock frequency (in Hz) + */ +uint32_t RCC_GetHCLKClockFreq(uint32_t SYSCLK_Frequency) +{ + /* HCLK clock frequency */ + return __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, LL_RCC_GetAHBPrescaler()); +} + +/** + * @brief Return PCLK1 clock frequency + * @param HCLK_Frequency HCLK clock frequency + * @retval PCLK1 clock frequency (in Hz) + */ +uint32_t RCC_GetPCLK1ClockFreq(uint32_t HCLK_Frequency) +{ + /* PCLK1 clock frequency */ + return __LL_RCC_CALC_PCLK1_FREQ(HCLK_Frequency, LL_RCC_GetAPB1Prescaler()); +} +#if defined(RCC_PLL_SUPPORT) +/** + * @brief Return PLL clock frequency used for system domain + * @retval PLL clock frequency (in Hz) + */ +uint32_t RCC_PLL_GetFreqDomain_SYS(void) +{ + uint32_t pllinputfreq; + uint32_t pllsource; + + pllsource = LL_RCC_PLL_GetMainSource(); + + switch (pllsource) + { + case LL_RCC_PLLSOURCE_HSE: /* HSE used as PLL clock source */ + pllinputfreq = HSE_VALUE; + break; + + case LL_RCC_PLLSOURCE_HSI: /* HSI used as PLL clock source */ + default: + pllinputfreq = LL_RCC_HSI_GetFreq(); + break; + } + return __LL_RCC_CALC_PLLCLK_FREQ(pllinputfreq); +} +#endif +/** + * @} + */ + + +#endif /* defined(RCC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya*****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_rtc.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_rtc.c similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_rtc.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_rtc.c index 88c07e3..2828c7f 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_rtc.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_rtc.c @@ -1,550 +1,550 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_rtc.c - * @author MCU Application Team - * @brief RTC LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ - -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_rtc.h" -#include "py32f0xx_ll_cortex.h" -#ifdef USE_FULL_ASSERT -#include "py32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined(RTC) - -/** @addtogroup RTC_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup RTC_LL_Private_Constants - * @{ - */ -/* Default values used for prescaler */ -#define RTC_ASYNCH_PRESC_DEFAULT 0x00007FFFU - -/* Values used for timeout */ -#define RTC_INITMODE_TIMEOUT 2000U /* 2s when tick set to 1ms */ -#define RTC_SYNCHRO_TIMEOUT 2000U /* 2s when tick set to 1ms */ -#define RTC_WAIT_RTOFF_ZERO 4U /* 1ms when tick set to 1ms */ -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup RTC_LL_Private_Macros - * @{ - */ - -#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0xFFFFFU) - -#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ - || ((__VALUE__) == LL_RTC_FORMAT_BCD)) - -#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) -#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) -#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) -#define IS_LL_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_NONE) || \ - ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_RTCCLOCK) || \ - ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_ALARM) || \ - ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_SECOND)) -/** - * @} - */ -/* Private function prototypes -----------------------------------------------*/ -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup RTC_LL_Exported_Functions - * @{ - */ - -/** @addtogroup RTC_LL_EF_Init - * @{ - */ - -/** - * @brief De-Initializes the RTC registers to their default reset values. - * @note This function doesn't reset the RTC Clock source and RTC Backup Data - * registers. - * @param RTCx RTC Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are de-initialized - * - ERROR: RTC registers are not de-initialized - */ -ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) -{ - ErrorStatus status = ERROR; - - /* Check the parameter */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - - /* Disable the write protection for RTC registers */ - LL_RTC_DisableWriteProtection(RTCx); - - /* Set Initialization mode */ - if (LL_RTC_EnterInitMode(RTCx) != ERROR) - { - LL_RTC_WriteReg(RTCx, CNTL, 0x0000); - LL_RTC_WriteReg(RTCx, CNTH, 0x0000); - LL_RTC_WriteReg(RTCx, PRLH, 0x0000); - LL_RTC_WriteReg(RTCx, PRLL, 0x8000); - LL_RTC_WriteReg(RTCx, CRH, 0x0000); - LL_RTC_WriteReg(RTCx, CRL, 0x0020); - - /* Reset Tamper and alternate functions configuration register */ - LL_RTC_WriteReg(RTCx, BKP_RTCCR, 0x0000); - - /* Exit Initialization Mode */ - if (LL_RTC_ExitInitMode(RTCx) != ERROR) - { - /* Wait till the RTC RSF flag is set */ - status = LL_RTC_WaitForSynchro(RTCx); - - /* Clear RSF Flag */ - LL_RTC_ClearFlag_RS(RTCx); - - /* Enable the write protection for RTC registers */ - LL_RTC_EnableWriteProtection(RTCx); - } - } - else - { - /* Enable the write protection for RTC registers */ - LL_RTC_EnableWriteProtection(RTCx); - } - - return status; -} - -/** - * @brief Initializes the RTC registers according to the specified parameters - * in RTC_InitStruct. - * @param RTCx RTC Instance - * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains - * the configuration information for the RTC peripheral. - * @note The RTC Prescaler register is write protected and can be written in - * initialization mode only. - * @note the user should call LL_RTC_StructInit() or the structure of Prescaler - * need to be initialized before RTC init() - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are initialized - * - ERROR: RTC registers are not initialized - */ -ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler)); - assert_param(IS_LL_RTC_CALIB_OUTPUT(RTC_InitStruct->OutPutSource)); - /* Waiting for synchro */ - if (LL_RTC_WaitForSynchro(RTCx) != ERROR) - { - /* Set Initialization mode */ - if (LL_RTC_EnterInitMode(RTCx) != ERROR) - { - /* Clear Flag Bits */ - LL_RTC_ClearFlag_ALR(RTCx); - LL_RTC_ClearFlag_OW(RTCx); - LL_RTC_ClearFlag_SEC(RTCx); - - /* Set the signal which will be routed to RTC Tamper Pin */ - LL_RTC_SetOutputSource(RTCx, RTC_InitStruct->OutPutSource); - - /* Configure Synchronous and Asynchronous prescaler factor */ - LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler); - - /* Exit Initialization Mode */ - LL_RTC_ExitInitMode(RTCx); - - status = SUCCESS; - } - } - return status; -} - -/** - * @brief Set each @ref LL_RTC_InitTypeDef field to default value. - * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized. - * @retval None - */ -void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct) -{ - /* Set RTC_InitStruct fields to default values */ - RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT; - RTC_InitStruct->OutPutSource = LL_RTC_CALIB_OUTPUT_NONE; -} - -/** - * @brief Set the RTC current time. - * @param RTCx RTC Instance - * @param RTC_Format This parameter can be one of the following values: - * @arg @ref LL_RTC_FORMAT_BIN - * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains - * the time configuration information for the RTC. - * @note The user should call LL_RTC_TIME_StructInit() or the structure - * of time need to be initialized before time init() - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Time register is configured - * - ERROR: RTC Time register is not configured - */ -ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct) -{ - ErrorStatus status = ERROR; - uint32_t counter_time = 0U; - - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - assert_param(IS_LL_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == LL_RTC_FORMAT_BIN) - { - assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); - assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes)); - assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds)); - } - else - { - assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); - assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); - assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))); - } - - /* Enter Initialization mode */ - if (LL_RTC_EnterInitMode(RTCx) != ERROR) - { - /* Check the input parameters format */ - if (RTC_Format == LL_RTC_FORMAT_BIN) - { - counter_time = (uint32_t)(((uint32_t)RTC_TimeStruct->Hours * 3600U) + \ - ((uint32_t)RTC_TimeStruct->Minutes * 60U) + \ - ((uint32_t)RTC_TimeStruct->Seconds)); - LL_RTC_TIME_Set(RTCx, counter_time); - } - else - { - counter_time = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)) * 3600U) + \ - ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)) * 60U) + \ - ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)))); - LL_RTC_TIME_Set(RTCx, counter_time); - } - status = SUCCESS; - } - /* Exit Initialization mode */ - LL_RTC_ExitInitMode(RTCx); - - return status; -} - -/** - * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec). - * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized. - * @retval None - */ -void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) -{ - /* Time = 00h:00min:00sec */ - RTC_TimeStruct->Hours = 0U; - RTC_TimeStruct->Minutes = 0U; - RTC_TimeStruct->Seconds = 0U; -} - -/** - * @brief Set the RTC Alarm. - * @param RTCx RTC Instance - * @param RTC_Format This parameter can be one of the following values: - * @arg @ref LL_RTC_FORMAT_BIN - * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that - * contains the alarm configuration parameters. - * @note the user should call LL_RTC_ALARM_StructInit() or the structure - * of Alarm need to be initialized before Alarm init() - * @retval An ErrorStatus enumeration value: - * - SUCCESS: ALARM registers are configured - * - ERROR: ALARM registers are not configured - */ -ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) -{ - ErrorStatus status = ERROR; - uint32_t counter_alarm = 0U; - /* Check the parameters */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - assert_param(IS_LL_RTC_FORMAT(RTC_Format)); - - if (RTC_Format == LL_RTC_FORMAT_BIN) - { - assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); - assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); - assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); - } - else - { - assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); - assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); - assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); - } - - /* Enter Initialization mode */ - if (LL_RTC_EnterInitMode(RTCx) != ERROR) - { - /* Check the input parameters format */ - if (RTC_Format == LL_RTC_FORMAT_BIN) - { - counter_alarm = (uint32_t)(((uint32_t)RTC_AlarmStruct->AlarmTime.Hours * 3600U) + \ - ((uint32_t)RTC_AlarmStruct->AlarmTime.Minutes * 60U) + \ - ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds)); - LL_RTC_ALARM_Set(RTCx, counter_alarm); - } - else - { - counter_alarm = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)) * 3600U) + \ - ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)) * 60U) + \ - ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)))); - LL_RTC_ALARM_Set(RTCx, counter_alarm); - } - status = SUCCESS; - } - /* Exit Initialization mode */ - LL_RTC_ExitInitMode(RTCx); - - return status; -} - -/** - * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARM field to default value (Time = 00h:00mn:00sec / - * Day = 1st day of the month/Mask = all fields are masked). - * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. - * @retval None - */ -void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) -{ - /* Alarm Time Settings : Time = 00h:00mn:00sec */ - RTC_AlarmStruct->AlarmTime.Hours = 0U; - RTC_AlarmStruct->AlarmTime.Minutes = 0U; - RTC_AlarmStruct->AlarmTime.Seconds = 0U; -} - -/** - * @brief Enters the RTC Initialization mode. - * @param RTCx RTC Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC is in Init mode - * - ERROR: RTC is not in Init mode - */ -ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) -{ - __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; - ErrorStatus status = SUCCESS; - uint32_t tmp = 0U; - - /* Check the parameter */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); - while ((timeout != 0U) && (tmp == 0U)) - { - if (LL_SYSTICK_IsActiveCounterFlag() == 1U) - { - timeout --; - } - tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); - if (timeout == 0U) - { - status = ERROR; - } - } - - /* Disable the write protection for RTC registers */ - LL_RTC_DisableWriteProtection(RTCx); - - return status; -} - -/** - * @brief Exit the RTC Initialization mode. - * @note When the initialization sequence is complete, the calendar restarts - * counting after 4 RTCCLK cycles. - * @param RTCx RTC Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC exited from in Init mode - * - ERROR: Not applicable - */ -ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) -{ - __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; - __IO uint32_t timeout_waitRtoffZer0 = RTC_WAIT_RTOFF_ZERO; - ErrorStatus status = SUCCESS; - uint32_t tmp = 0U; - - /* Check the parameter */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - - /* Disable initialization mode */ - LL_RTC_EnableWriteProtection(RTCx); - - /* Wait till RTC is in INIT state and if Time out is reached exit */ - tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); - while ((timeout_waitRtoffZer0 != 0U) && (tmp !=0U)) - { - if (LL_SYSTICK_IsActiveCounterFlag() == 1U) - { - timeout_waitRtoffZer0 --; - } - tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); - } - while ((timeout != 0U) && (tmp ==0U)) - { - if (LL_SYSTICK_IsActiveCounterFlag() == 1U) - { - timeout --; - } - tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); - if (timeout == 0U) - { - status = ERROR; - } - } - return status; -} - -/** - * @brief Set the Time Counter - * @param RTCx RTC Instance - * @param TimeCounter this value can be from 0 to 0xFFFFFFFF - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC Counter register configured - * - ERROR: Not applicable - */ -ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter) -{ - ErrorStatus status = ERROR; - /* Check the parameter */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - - /* Enter Initialization mode */ - if (LL_RTC_EnterInitMode(RTCx) != ERROR) - { - LL_RTC_TIME_Set(RTCx, TimeCounter); - status = SUCCESS; - } - /* Exit Initialization mode */ - LL_RTC_ExitInitMode(RTCx); - - return status; -} - -/** - * @brief Set Alarm Counter. - * @param RTCx RTC Instance - * @param AlarmCounter this value can be from 0 to 0xFFFFFFFF - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC exited from in Init mode - * - ERROR: Not applicable - */ -ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter) -{ - ErrorStatus status = ERROR; - /* Check the parameter */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - - /* Enter Initialization mode */ - if (LL_RTC_EnterInitMode(RTCx) != ERROR) - { - LL_RTC_ALARM_Set(RTCx, AlarmCounter); - status = SUCCESS; - } - /* Exit Initialization mode */ - LL_RTC_ExitInitMode(RTCx); - - return status; -} - -/** - * @brief Waits until the RTC registers are synchronized with RTC APB clock. - * @note The RTC Resynchronization mode is write protected, use the - * @ref LL_RTC_DisableWriteProtection before calling this function. - * @param RTCx RTC Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: RTC registers are synchronised - * - ERROR: RTC registers are not synchronised - */ -ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) -{ - __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; - ErrorStatus status = SUCCESS; - uint32_t tmp = 0U; - - /* Check the parameter */ - assert_param(IS_RTC_ALL_INSTANCE(RTCx)); - - /* Clear RSF flag */ - LL_RTC_ClearFlag_RS(RTCx); - - /* Wait the registers to be synchronised */ - tmp = LL_RTC_IsActiveFlag_RS(RTCx); - while ((timeout != 0U) && (tmp == 0U)) - { - if (LL_SYSTICK_IsActiveCounterFlag() == 1U) - { - timeout--; - } - tmp = LL_RTC_IsActiveFlag_RS(RTCx); - if (timeout == 0U) - { - status = ERROR; - } - } - - return (status); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* defined(RTC) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_rtc.c + * @author MCU Application Team + * @brief RTC LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_rtc.h" +#include "py32f0xx_ll_cortex.h" +#ifdef USE_FULL_ASSERT +#include "py32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined(RTC) + +/** @addtogroup RTC_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Constants + * @{ + */ +/* Default values used for prescaler */ +#define RTC_ASYNCH_PRESC_DEFAULT 0x00007FFFU + +/* Values used for timeout */ +#define RTC_INITMODE_TIMEOUT 2000U /* 2s when tick set to 1ms */ +#define RTC_SYNCHRO_TIMEOUT 2000U /* 2s when tick set to 1ms */ +#define RTC_WAIT_RTOFF_ZERO 4U /* 1ms when tick set to 1ms */ +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup RTC_LL_Private_Macros + * @{ + */ + +#define IS_LL_RTC_ASYNCH_PREDIV(__VALUE__) ((__VALUE__) <= 0xFFFFFU) + +#define IS_LL_RTC_FORMAT(__VALUE__) (((__VALUE__) == LL_RTC_FORMAT_BIN) \ + || ((__VALUE__) == LL_RTC_FORMAT_BCD)) + +#define IS_LL_RTC_HOUR24(__HOUR__) ((__HOUR__) <= 23U) +#define IS_LL_RTC_MINUTES(__MINUTES__) ((__MINUTES__) <= 59U) +#define IS_LL_RTC_SECONDS(__SECONDS__) ((__SECONDS__) <= 59U) +#define IS_LL_RTC_CALIB_OUTPUT(__OUTPUT__) (((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_NONE) || \ + ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_RTCCLOCK) || \ + ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_ALARM) || \ + ((__OUTPUT__) == LL_RTC_CALIB_OUTPUT_SECOND)) +/** + * @} + */ +/* Private function prototypes -----------------------------------------------*/ +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup RTC_LL_Exported_Functions + * @{ + */ + +/** @addtogroup RTC_LL_EF_Init + * @{ + */ + +/** + * @brief De-Initializes the RTC registers to their default reset values. + * @note This function doesn't reset the RTC Clock source and RTC Backup Data + * registers. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are de-initialized + * - ERROR: RTC registers are not de-initialized + */ +ErrorStatus LL_RTC_DeInit(RTC_TypeDef *RTCx) +{ + ErrorStatus status = ERROR; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + LL_RTC_WriteReg(RTCx, CNTL, 0x0000); + LL_RTC_WriteReg(RTCx, CNTH, 0x0000); + LL_RTC_WriteReg(RTCx, PRLH, 0x0000); + LL_RTC_WriteReg(RTCx, PRLL, 0x8000); + LL_RTC_WriteReg(RTCx, CRH, 0x0000); + LL_RTC_WriteReg(RTCx, CRL, 0x0020); + + /* Reset Tamper and alternate functions configuration register */ + LL_RTC_WriteReg(RTCx, BKP_RTCCR, 0x0000); + + /* Exit Initialization Mode */ + if (LL_RTC_ExitInitMode(RTCx) != ERROR) + { + /* Wait till the RTC RSF flag is set */ + status = LL_RTC_WaitForSynchro(RTCx); + + /* Clear RSF Flag */ + LL_RTC_ClearFlag_RS(RTCx); + + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + } + } + else + { + /* Enable the write protection for RTC registers */ + LL_RTC_EnableWriteProtection(RTCx); + } + + return status; +} + +/** + * @brief Initializes the RTC registers according to the specified parameters + * in RTC_InitStruct. + * @param RTCx RTC Instance + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure that contains + * the configuration information for the RTC peripheral. + * @note The RTC Prescaler register is write protected and can be written in + * initialization mode only. + * @note the user should call LL_RTC_StructInit() or the structure of Prescaler + * need to be initialized before RTC init() + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are initialized + * - ERROR: RTC registers are not initialized + */ +ErrorStatus LL_RTC_Init(RTC_TypeDef *RTCx, LL_RTC_InitTypeDef *RTC_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_ASYNCH_PREDIV(RTC_InitStruct->AsynchPrescaler)); + assert_param(IS_LL_RTC_CALIB_OUTPUT(RTC_InitStruct->OutPutSource)); + /* Waiting for synchro */ + if (LL_RTC_WaitForSynchro(RTCx) != ERROR) + { + /* Set Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Clear Flag Bits */ + LL_RTC_ClearFlag_ALR(RTCx); + LL_RTC_ClearFlag_OW(RTCx); + LL_RTC_ClearFlag_SEC(RTCx); + + /* Set the signal which will be routed to RTC Tamper Pin */ + LL_RTC_SetOutputSource(RTCx, RTC_InitStruct->OutPutSource); + + /* Configure Synchronous and Asynchronous prescaler factor */ + LL_RTC_SetAsynchPrescaler(RTCx, RTC_InitStruct->AsynchPrescaler); + + /* Exit Initialization Mode */ + LL_RTC_ExitInitMode(RTCx); + + status = SUCCESS; + } + } + return status; +} + +/** + * @brief Set each @ref LL_RTC_InitTypeDef field to default value. + * @param RTC_InitStruct pointer to a @ref LL_RTC_InitTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_StructInit(LL_RTC_InitTypeDef *RTC_InitStruct) +{ + /* Set RTC_InitStruct fields to default values */ + RTC_InitStruct->AsynchPrescaler = RTC_ASYNCH_PRESC_DEFAULT; + RTC_InitStruct->OutPutSource = LL_RTC_CALIB_OUTPUT_NONE; +} + +/** + * @brief Set the RTC current time. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_TimeStruct pointer to a RTC_TimeTypeDef structure that contains + * the time configuration information for the RTC. + * @note The user should call LL_RTC_TIME_StructInit() or the structure + * of time need to be initialized before time init() + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Time register is configured + * - ERROR: RTC Time register is not configured + */ +ErrorStatus LL_RTC_TIME_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + ErrorStatus status = ERROR; + uint32_t counter_time = 0U; + + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + assert_param(IS_LL_RTC_HOUR24(RTC_TimeStruct->Hours)); + assert_param(IS_LL_RTC_MINUTES(RTC_TimeStruct->Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_TimeStruct->Seconds)); + } + else + { + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours))); + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds))); + } + + /* Enter Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + counter_time = (uint32_t)(((uint32_t)RTC_TimeStruct->Hours * 3600U) + \ + ((uint32_t)RTC_TimeStruct->Minutes * 60U) + \ + ((uint32_t)RTC_TimeStruct->Seconds)); + LL_RTC_TIME_Set(RTCx, counter_time); + } + else + { + counter_time = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Hours)) * 3600U) + \ + ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Minutes)) * 60U) + \ + ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_TimeStruct->Seconds)))); + LL_RTC_TIME_Set(RTCx, counter_time); + } + status = SUCCESS; + } + /* Exit Initialization mode */ + LL_RTC_ExitInitMode(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_TimeTypeDef field to default value (Time = 00h:00min:00sec). + * @param RTC_TimeStruct pointer to a @ref LL_RTC_TimeTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_TIME_StructInit(LL_RTC_TimeTypeDef *RTC_TimeStruct) +{ + /* Time = 00h:00min:00sec */ + RTC_TimeStruct->Hours = 0U; + RTC_TimeStruct->Minutes = 0U; + RTC_TimeStruct->Seconds = 0U; +} + +/** + * @brief Set the RTC Alarm. + * @param RTCx RTC Instance + * @param RTC_Format This parameter can be one of the following values: + * @arg @ref LL_RTC_FORMAT_BIN + * @arg @ref LL_RTC_FORMAT_BCD + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure that + * contains the alarm configuration parameters. + * @note the user should call LL_RTC_ALARM_StructInit() or the structure + * of Alarm need to be initialized before Alarm init() + * @retval An ErrorStatus enumeration value: + * - SUCCESS: ALARM registers are configured + * - ERROR: ALARM registers are not configured + */ +ErrorStatus LL_RTC_ALARM_Init(RTC_TypeDef *RTCx, uint32_t RTC_Format, LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + ErrorStatus status = ERROR; + uint32_t counter_alarm = 0U; + /* Check the parameters */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + assert_param(IS_LL_RTC_FORMAT(RTC_Format)); + + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + assert_param(IS_LL_RTC_HOUR24(RTC_AlarmStruct->AlarmTime.Hours)); + assert_param(IS_LL_RTC_MINUTES(RTC_AlarmStruct->AlarmTime.Minutes)); + assert_param(IS_LL_RTC_SECONDS(RTC_AlarmStruct->AlarmTime.Seconds)); + } + else + { + assert_param(IS_LL_RTC_HOUR24(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours))); + assert_param(IS_LL_RTC_MINUTES(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes))); + assert_param(IS_LL_RTC_SECONDS(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds))); + } + + /* Enter Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + /* Check the input parameters format */ + if (RTC_Format == LL_RTC_FORMAT_BIN) + { + counter_alarm = (uint32_t)(((uint32_t)RTC_AlarmStruct->AlarmTime.Hours * 3600U) + \ + ((uint32_t)RTC_AlarmStruct->AlarmTime.Minutes * 60U) + \ + ((uint32_t)RTC_AlarmStruct->AlarmTime.Seconds)); + LL_RTC_ALARM_Set(RTCx, counter_alarm); + } + else + { + counter_alarm = (((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Hours)) * 3600U) + \ + ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Minutes)) * 60U) + \ + ((uint32_t)(__LL_RTC_CONVERT_BCD2BIN(RTC_AlarmStruct->AlarmTime.Seconds)))); + LL_RTC_ALARM_Set(RTCx, counter_alarm); + } + status = SUCCESS; + } + /* Exit Initialization mode */ + LL_RTC_ExitInitMode(RTCx); + + return status; +} + +/** + * @brief Set each @ref LL_RTC_AlarmTypeDef of ALARM field to default value (Time = 00h:00mn:00sec / + * Day = 1st day of the month/Mask = all fields are masked). + * @param RTC_AlarmStruct pointer to a @ref LL_RTC_AlarmTypeDef structure which will be initialized. + * @retval None + */ +void LL_RTC_ALARM_StructInit(LL_RTC_AlarmTypeDef *RTC_AlarmStruct) +{ + /* Alarm Time Settings : Time = 00h:00mn:00sec */ + RTC_AlarmStruct->AlarmTime.Hours = 0U; + RTC_AlarmStruct->AlarmTime.Minutes = 0U; + RTC_AlarmStruct->AlarmTime.Seconds = 0U; +} + +/** + * @brief Enters the RTC Initialization mode. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC is in Init mode + * - ERROR: RTC is not in Init mode + */ +ErrorStatus LL_RTC_EnterInitMode(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp = 0U; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); + while ((timeout != 0U) && (tmp == 0U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout --; + } + tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + + /* Disable the write protection for RTC registers */ + LL_RTC_DisableWriteProtection(RTCx); + + return status; +} + +/** + * @brief Exit the RTC Initialization mode. + * @note When the initialization sequence is complete, the calendar restarts + * counting after 4 RTCCLK cycles. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC exited from in Init mode + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_ExitInitMode(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_INITMODE_TIMEOUT; + __IO uint32_t timeout_waitRtoffZer0 = RTC_WAIT_RTOFF_ZERO; + ErrorStatus status = SUCCESS; + uint32_t tmp = 0U; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Disable initialization mode */ + LL_RTC_EnableWriteProtection(RTCx); + + /* Wait till RTC is in INIT state and if Time out is reached exit */ + tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); + while ((timeout_waitRtoffZer0 != 0U) && (tmp !=0U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout_waitRtoffZer0 --; + } + tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); + } + while ((timeout != 0U) && (tmp ==0U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout --; + } + tmp = LL_RTC_IsActiveFlag_RTOF(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + return status; +} + +/** + * @brief Set the Time Counter + * @param RTCx RTC Instance + * @param TimeCounter this value can be from 0 to 0xFFFFFFFF + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC Counter register configured + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_TIME_SetCounter(RTC_TypeDef *RTCx, uint32_t TimeCounter) +{ + ErrorStatus status = ERROR; + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Enter Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + LL_RTC_TIME_Set(RTCx, TimeCounter); + status = SUCCESS; + } + /* Exit Initialization mode */ + LL_RTC_ExitInitMode(RTCx); + + return status; +} + +/** + * @brief Set Alarm Counter. + * @param RTCx RTC Instance + * @param AlarmCounter this value can be from 0 to 0xFFFFFFFF + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC exited from in Init mode + * - ERROR: Not applicable + */ +ErrorStatus LL_RTC_ALARM_SetCounter(RTC_TypeDef *RTCx, uint32_t AlarmCounter) +{ + ErrorStatus status = ERROR; + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Enter Initialization mode */ + if (LL_RTC_EnterInitMode(RTCx) != ERROR) + { + LL_RTC_ALARM_Set(RTCx, AlarmCounter); + status = SUCCESS; + } + /* Exit Initialization mode */ + LL_RTC_ExitInitMode(RTCx); + + return status; +} + +/** + * @brief Waits until the RTC registers are synchronized with RTC APB clock. + * @note The RTC Resynchronization mode is write protected, use the + * @ref LL_RTC_DisableWriteProtection before calling this function. + * @param RTCx RTC Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: RTC registers are synchronised + * - ERROR: RTC registers are not synchronised + */ +ErrorStatus LL_RTC_WaitForSynchro(RTC_TypeDef *RTCx) +{ + __IO uint32_t timeout = RTC_SYNCHRO_TIMEOUT; + ErrorStatus status = SUCCESS; + uint32_t tmp = 0U; + + /* Check the parameter */ + assert_param(IS_RTC_ALL_INSTANCE(RTCx)); + + /* Clear RSF flag */ + LL_RTC_ClearFlag_RS(RTCx); + + /* Wait the registers to be synchronised */ + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + while ((timeout != 0U) && (tmp == 0U)) + { + if (LL_SYSTICK_IsActiveCounterFlag() == 1U) + { + timeout--; + } + tmp = LL_RTC_IsActiveFlag_RS(RTCx); + if (timeout == 0U) + { + status = ERROR; + } + } + + return (status); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* defined(RTC) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_spi.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_spi.c similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_spi.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_spi.c index c366344..2196066 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_spi.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_spi.c @@ -1,512 +1,512 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_spi.c - * @author MCU Application Team - * @brief SPI LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_spi.h" -#include "py32f0xx_ll_bus.h" -#include "py32f0xx_ll_rcc.h" - -#ifdef USE_FULL_ASSERT - #include "py32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (SPI1) || defined (SPI2) - -/** @addtogroup SPI_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ - -/* Private constants ---------------------------------------------------------*/ -/** @defgroup SPI_LL_Private_Constants SPI Private Constants - * @{ - */ -/* SPI registers Masks */ -#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ - SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ - SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | \ - SPI_CR1_BIDIMODE) -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @defgroup SPI_LL_Private_Macros SPI Private Macros - * @{ - */ -#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ - || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ - || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ - || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) - -#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ - || ((__VALUE__) == LL_SPI_MODE_SLAVE)) - -#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ - || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) - -#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ - || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) - -#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ - || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) - -#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ - || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ - || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) - -#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ - || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) - -#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ - || ((__VALUE__) == LL_SPI_MSB_FIRST)) - -#define IS_LL_SPI_SLAVE_SPEED_MODE(__VALUE__) (((__VALUE__) == LL_SPI_SLAVE_SPEED_NORMAL) \ - || ((__VALUE__) == LL_SPI_SLAVE_SPEED_FAST)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup SPI_LL_Exported_Functions - * @{ - */ - -/** @addtogroup SPI_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the SPI registers to their default reset values. - * @param SPIx SPI Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: SPI registers are de-initialized - * - ERROR: SPI registers are not de-initialized - */ -ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) -{ - ErrorStatus status = ERROR; - - /* Check the parameters */ - assert_param(IS_SPI_ALL_INSTANCE(SPIx)); - - if (SPIx == SPI1) - { - /* Force reset of SPI clock */ - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SPI1); - - /* Release reset of SPI clock */ - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SPI1); - - status = SUCCESS; - } -#if defined(SPI2) - if (SPIx == SPI2) - { - /* Force reset of SPI clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); - - /* Release reset of SPI clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); - - status = SUCCESS; - } -#endif - return status; -} - -/** - * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @param SPIx SPI Instance - * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure - * @retval An ErrorStatus enumeration value. (Return always SUCCESS) - */ -ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) -{ - ErrorStatus status = ERROR; - - /* Check the SPI Instance SPIx*/ - assert_param(IS_SPI_ALL_INSTANCE(SPIx)); - - /* Check the SPI parameters from SPI_InitStruct*/ - assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); - assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); - assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); - assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); - assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); - assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); - assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); - assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); - assert_param(IS_LL_SPI_SLAVE_SPEED_MODE(SPI_InitStruct->SlaveSpeedMode)); - - if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) - { - /*---------------------------- SPIx CR1 Configuration ------------------------ - * Configure SPIx CR1 with parameters: - * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits - * - Master/Slave Mode: SPI_CR1_MSTR bit - * - ClockPolarity: SPI_CR1_CPOL bit - * - ClockPhase: SPI_CR1_CPHA bit - * - NSS management: SPI_CR1_SSM bit - * - BaudRate prescaler: SPI_CR1_BR[2:0] bits - * - BitOrder: SPI_CR1_LSBFIRST bit - * - CRCCalculation: SPI_CR1_CRCEN bit - */ - MODIFY_REG(SPIx->CR1, - SPI_CR1_CLEAR_MASK, - SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | - SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | - (SPI_InitStruct->NSS & SPI_CR1_SSM) | SPI_InitStruct->BaudRate | - SPI_InitStruct->BitOrder); - - /*---------------------------- SPIx CR2 Configuration ------------------------ - * Configure SPIx CR2 with parameters: - * - DataWidth: DS[3:0] bits - * - NSS management: SSOE bit - */ - MODIFY_REG(SPIx->CR2, - (SPI_CR2_DS | SPI_CR2_SSOE | SPI_CR2_SLVFM), - (SPI_InitStruct->DataWidth | ((SPI_InitStruct->NSS >> 16U) & SPI_CR2_SSOE) | SPI_InitStruct->SlaveSpeedMode)); - - /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */ - if (SPI_InitStruct->DataWidth == LL_SPI_DATAWIDTH_8BIT) - { - LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER); - } - else - { - LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_HALF); - } - - status = SUCCESS; - } - return status; -} - -/** - * @brief Set each @ref LL_SPI_InitTypeDef field to default value. - * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) -{ - /* Set SPI_InitStruct fields to default values */ - SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; - SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; - SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; - SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; - SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; - SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; - SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; - SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; - SPI_InitStruct->SlaveSpeedMode = LL_SPI_SLAVE_SPEED_NORMAL; -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#if defined(SPI_I2S_SUPPORT) -/** @addtogroup I2S_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @defgroup I2S_LL_Private_Constants I2S Private Constants - * @{ - */ -/* I2S registers Masks */ -#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ - SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ - SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) - -#define I2S_I2SPR_CLEAR_MASK 0x0002U -/** - * @} - */ -/* Private macros ------------------------------------------------------------*/ -/** @defgroup I2S_LL_Private_Macros I2S Private Macros - * @{ - */ - -#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ - || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) - -#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ - || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) - -#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ - || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ - || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ - || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ - || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) - -#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ - || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ - || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) - -#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ - || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) - -#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ - && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ - || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) - -#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) - -#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ - || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup I2S_LL_Exported_Functions - * @{ - */ - -/** @addtogroup I2S_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize the SPI/I2S registers to their default reset values. - * @param SPIx SPI Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: SPI registers are de-initialized - * - ERROR: SPI registers are not de-initialized - */ -ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) -{ - return LL_SPI_DeInit(SPIx); -} - -/** - * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. - * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), - * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @param SPIx SPI Instance - * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: SPI registers are Initialized - * - ERROR: SPI registers are not Initialized - */ -ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) -{ - uint32_t i2sdiv = 2U; - uint32_t i2sodd = 0U; - uint32_t packetlength = 1U; - uint32_t tmp; - LL_RCC_ClocksTypeDef rcc_clocks; - uint32_t sourceclock; - ErrorStatus status = ERROR; - - /* Check the I2S parameters */ - assert_param(IS_I2S_ALL_INSTANCE(SPIx)); - assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); - assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); - assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); - assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); - assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); - assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); - - if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) - { - /*---------------------------- SPIx I2SCFGR Configuration -------------------- - * Configure SPIx I2SCFGR with parameters: - * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit - * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits - * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits - * - ClockPolarity: SPI_I2SCFGR_CKPOL bit - */ - - /* Write to SPIx I2SCFGR */ - MODIFY_REG(SPIx->I2SCFGR, - I2S_I2SCFGR_CLEAR_MASK, - I2S_InitStruct->Mode | I2S_InitStruct->Standard | - I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | - SPI_I2SCFGR_I2SMOD); - - /*---------------------------- SPIx I2SPR Configuration ---------------------- - * Configure SPIx I2SPR with parameters: - * - MCLKOutput: SPI_I2SPR_MCKOE bit - * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits - */ - - /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) - * else, default values are used: i2sodd = 0U, i2sdiv = 2U. - */ - if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) - { - /* Check the frame length (For the Prescaler computing) - * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). - */ - if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) - { - /* Packet length is 32 bits */ - packetlength = 2U; - } - - /* I2S Clock source is System clock: Get System Clock frequency */ - LL_RCC_GetSystemClocksFreq(&rcc_clocks); - - /* Get the source clock value: based on System Clock value */ - sourceclock = rcc_clocks.SYSCLK_Frequency; - - /* Compute the Real divider depending on the MCLK output state with a floating point */ - if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) - { - /* MCLK output is enabled */ - tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); - } - else - { - /* MCLK output is disabled */ - tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); - } - - /* Remove the floating point */ - tmp = tmp / 10U; - - /* Check the parity of the divider */ - i2sodd = (tmp & (uint16_t)0x0001U); - - /* Compute the i2sdiv prescaler */ - i2sdiv = ((tmp - i2sodd) / 2U); - - /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ - i2sodd = (i2sodd << 8U); - } - - /* Test if the divider is 1 or 0 or greater than 0xFF */ - if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) - { - /* Set the default values */ - i2sdiv = 2U; - i2sodd = 0U; - } - - /* Write to SPIx I2SPR register the computed value */ - WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); - - status = SUCCESS; - } - return status; -} - -/** - * @brief Set each @ref LL_I2S_InitTypeDef field to default value. - * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) -{ - /*--------------- Reset I2S init structure parameters values -----------------*/ - I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; - I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; - I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; - I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; - I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; - I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; -} - -/** - * @brief Set linear and parity prescaler. - * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n - * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). - * @param SPIx SPI Instance - * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. - * @param PrescalerParity This parameter can be one of the following values: - * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN - * @arg @ref LL_I2S_PRESCALER_PARITY_ODD - * @retval None - */ -void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) -{ - /* Check the I2S parameters */ - assert_param(IS_I2S_ALL_INSTANCE(SPIx)); - assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); - assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); - - /* Write to SPIx I2SPR */ - MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ -#endif /* SPI_I2S_SUPPORT */ - -#endif /* defined (SPI1) || defined (SPI2) */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_spi.c + * @author MCU Application Team + * @brief SPI LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_spi.h" +#include "py32f0xx_ll_bus.h" +#include "py32f0xx_ll_rcc.h" + +#ifdef USE_FULL_ASSERT + #include "py32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (SPI1) || defined (SPI2) + +/** @addtogroup SPI_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ + +/* Private constants ---------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Constants SPI Private Constants + * @{ + */ +/* SPI registers Masks */ +#define SPI_CR1_CLEAR_MASK (SPI_CR1_CPHA | SPI_CR1_CPOL | SPI_CR1_MSTR | \ + SPI_CR1_BR | SPI_CR1_LSBFIRST | SPI_CR1_SSI | \ + SPI_CR1_SSM | SPI_CR1_RXONLY | SPI_CR1_BIDIOE | \ + SPI_CR1_BIDIMODE) +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @defgroup SPI_LL_Private_Macros SPI Private Macros + * @{ + */ +#define IS_LL_SPI_TRANSFER_DIRECTION(__VALUE__) (((__VALUE__) == LL_SPI_FULL_DUPLEX) \ + || ((__VALUE__) == LL_SPI_SIMPLEX_RX) \ + || ((__VALUE__) == LL_SPI_HALF_DUPLEX_RX) \ + || ((__VALUE__) == LL_SPI_HALF_DUPLEX_TX)) + +#define IS_LL_SPI_MODE(__VALUE__) (((__VALUE__) == LL_SPI_MODE_MASTER) \ + || ((__VALUE__) == LL_SPI_MODE_SLAVE)) + +#define IS_LL_SPI_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_SPI_DATAWIDTH_8BIT) \ + || ((__VALUE__) == LL_SPI_DATAWIDTH_16BIT)) + +#define IS_LL_SPI_POLARITY(__VALUE__) (((__VALUE__) == LL_SPI_POLARITY_LOW) \ + || ((__VALUE__) == LL_SPI_POLARITY_HIGH)) + +#define IS_LL_SPI_PHASE(__VALUE__) (((__VALUE__) == LL_SPI_PHASE_1EDGE) \ + || ((__VALUE__) == LL_SPI_PHASE_2EDGE)) + +#define IS_LL_SPI_NSS(__VALUE__) (((__VALUE__) == LL_SPI_NSS_SOFT) \ + || ((__VALUE__) == LL_SPI_NSS_HARD_INPUT) \ + || ((__VALUE__) == LL_SPI_NSS_HARD_OUTPUT)) + +#define IS_LL_SPI_BAUDRATE(__VALUE__) (((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV2) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV4) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV8) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV16) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV32) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV64) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV128) \ + || ((__VALUE__) == LL_SPI_BAUDRATEPRESCALER_DIV256)) + +#define IS_LL_SPI_BITORDER(__VALUE__) (((__VALUE__) == LL_SPI_LSB_FIRST) \ + || ((__VALUE__) == LL_SPI_MSB_FIRST)) + +#define IS_LL_SPI_SLAVE_SPEED_MODE(__VALUE__) (((__VALUE__) == LL_SPI_SLAVE_SPEED_NORMAL) \ + || ((__VALUE__) == LL_SPI_SLAVE_SPEED_FAST)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup SPI_LL_Exported_Functions + * @{ + */ + +/** @addtogroup SPI_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_SPI_DeInit(SPI_TypeDef *SPIx) +{ + ErrorStatus status = ERROR; + + /* Check the parameters */ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + + if (SPIx == SPI1) + { + /* Force reset of SPI clock */ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_SPI1); + + /* Release reset of SPI clock */ + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_SPI1); + + status = SUCCESS; + } +#if defined(SPI2) + if (SPIx == SPI2) + { + /* Force reset of SPI clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_SPI2); + + /* Release reset of SPI clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_SPI2); + + status = SUCCESS; + } +#endif + return status; +} + +/** + * @brief Initialize the SPI registers according to the specified parameters in SPI_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), + * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * @retval An ErrorStatus enumeration value. (Return always SUCCESS) + */ +ErrorStatus LL_SPI_Init(SPI_TypeDef *SPIx, LL_SPI_InitTypeDef *SPI_InitStruct) +{ + ErrorStatus status = ERROR; + + /* Check the SPI Instance SPIx*/ + assert_param(IS_SPI_ALL_INSTANCE(SPIx)); + + /* Check the SPI parameters from SPI_InitStruct*/ + assert_param(IS_LL_SPI_TRANSFER_DIRECTION(SPI_InitStruct->TransferDirection)); + assert_param(IS_LL_SPI_MODE(SPI_InitStruct->Mode)); + assert_param(IS_LL_SPI_DATAWIDTH(SPI_InitStruct->DataWidth)); + assert_param(IS_LL_SPI_POLARITY(SPI_InitStruct->ClockPolarity)); + assert_param(IS_LL_SPI_PHASE(SPI_InitStruct->ClockPhase)); + assert_param(IS_LL_SPI_NSS(SPI_InitStruct->NSS)); + assert_param(IS_LL_SPI_BAUDRATE(SPI_InitStruct->BaudRate)); + assert_param(IS_LL_SPI_BITORDER(SPI_InitStruct->BitOrder)); + assert_param(IS_LL_SPI_SLAVE_SPEED_MODE(SPI_InitStruct->SlaveSpeedMode)); + + if (LL_SPI_IsEnabled(SPIx) == 0x00000000U) + { + /*---------------------------- SPIx CR1 Configuration ------------------------ + * Configure SPIx CR1 with parameters: + * - TransferDirection: SPI_CR1_BIDIMODE, SPI_CR1_BIDIOE and SPI_CR1_RXONLY bits + * - Master/Slave Mode: SPI_CR1_MSTR bit + * - ClockPolarity: SPI_CR1_CPOL bit + * - ClockPhase: SPI_CR1_CPHA bit + * - NSS management: SPI_CR1_SSM bit + * - BaudRate prescaler: SPI_CR1_BR[2:0] bits + * - BitOrder: SPI_CR1_LSBFIRST bit + * - CRCCalculation: SPI_CR1_CRCEN bit + */ + MODIFY_REG(SPIx->CR1, + SPI_CR1_CLEAR_MASK, + SPI_InitStruct->TransferDirection | SPI_InitStruct->Mode | + SPI_InitStruct->ClockPolarity | SPI_InitStruct->ClockPhase | + (SPI_InitStruct->NSS & SPI_CR1_SSM) | SPI_InitStruct->BaudRate | + SPI_InitStruct->BitOrder); + + /*---------------------------- SPIx CR2 Configuration ------------------------ + * Configure SPIx CR2 with parameters: + * - DataWidth: DS[3:0] bits + * - NSS management: SSOE bit + */ + MODIFY_REG(SPIx->CR2, + (SPI_CR2_DS | SPI_CR2_SSOE | SPI_CR2_SLVFM), + (SPI_InitStruct->DataWidth | ((SPI_InitStruct->NSS >> 16U) & SPI_CR2_SSOE) | SPI_InitStruct->SlaveSpeedMode)); + + /* Set Rx FIFO to Quarter (1 Byte) in case of 8 Bits mode. No DataPacking by default */ + if (SPI_InitStruct->DataWidth == LL_SPI_DATAWIDTH_8BIT) + { + LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_QUARTER); + } + else + { + LL_SPI_SetRxFIFOThreshold(SPIx, LL_SPI_RX_FIFO_TH_HALF); + } + + status = SUCCESS; + } + return status; +} + +/** + * @brief Set each @ref LL_SPI_InitTypeDef field to default value. + * @param SPI_InitStruct pointer to a @ref LL_SPI_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_SPI_StructInit(LL_SPI_InitTypeDef *SPI_InitStruct) +{ + /* Set SPI_InitStruct fields to default values */ + SPI_InitStruct->TransferDirection = LL_SPI_FULL_DUPLEX; + SPI_InitStruct->Mode = LL_SPI_MODE_SLAVE; + SPI_InitStruct->DataWidth = LL_SPI_DATAWIDTH_8BIT; + SPI_InitStruct->ClockPolarity = LL_SPI_POLARITY_LOW; + SPI_InitStruct->ClockPhase = LL_SPI_PHASE_1EDGE; + SPI_InitStruct->NSS = LL_SPI_NSS_HARD_INPUT; + SPI_InitStruct->BaudRate = LL_SPI_BAUDRATEPRESCALER_DIV2; + SPI_InitStruct->BitOrder = LL_SPI_MSB_FIRST; + SPI_InitStruct->SlaveSpeedMode = LL_SPI_SLAVE_SPEED_NORMAL; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#if defined(SPI_I2S_SUPPORT) +/** @addtogroup I2S_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Constants I2S Private Constants + * @{ + */ +/* I2S registers Masks */ +#define I2S_I2SCFGR_CLEAR_MASK (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN | \ + SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD | \ + SPI_I2SCFGR_I2SCFG | SPI_I2SCFGR_I2SMOD ) + +#define I2S_I2SPR_CLEAR_MASK 0x0002U +/** + * @} + */ +/* Private macros ------------------------------------------------------------*/ +/** @defgroup I2S_LL_Private_Macros I2S Private Macros + * @{ + */ + +#define IS_LL_I2S_DATAFORMAT(__VALUE__) (((__VALUE__) == LL_I2S_DATAFORMAT_16B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_16B_EXTENDED) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_24B) \ + || ((__VALUE__) == LL_I2S_DATAFORMAT_32B)) + +#define IS_LL_I2S_CPOL(__VALUE__) (((__VALUE__) == LL_I2S_POLARITY_LOW) \ + || ((__VALUE__) == LL_I2S_POLARITY_HIGH)) + +#define IS_LL_I2S_STANDARD(__VALUE__) (((__VALUE__) == LL_I2S_STANDARD_PHILIPS) \ + || ((__VALUE__) == LL_I2S_STANDARD_MSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_LSB) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_SHORT) \ + || ((__VALUE__) == LL_I2S_STANDARD_PCM_LONG)) + +#define IS_LL_I2S_MODE(__VALUE__) (((__VALUE__) == LL_I2S_MODE_SLAVE_TX) \ + || ((__VALUE__) == LL_I2S_MODE_SLAVE_RX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_TX) \ + || ((__VALUE__) == LL_I2S_MODE_MASTER_RX)) + +#define IS_LL_I2S_MCLK_OUTPUT(__VALUE__) (((__VALUE__) == LL_I2S_MCLK_OUTPUT_ENABLE) \ + || ((__VALUE__) == LL_I2S_MCLK_OUTPUT_DISABLE)) + +#define IS_LL_I2S_AUDIO_FREQ(__VALUE__) ((((__VALUE__) >= LL_I2S_AUDIOFREQ_8K) \ + && ((__VALUE__) <= LL_I2S_AUDIOFREQ_192K)) \ + || ((__VALUE__) == LL_I2S_AUDIOFREQ_DEFAULT)) + +#define IS_LL_I2S_PRESCALER_LINEAR(__VALUE__) ((__VALUE__) >= 0x2U) + +#define IS_LL_I2S_PRESCALER_PARITY(__VALUE__) (((__VALUE__) == LL_I2S_PRESCALER_PARITY_EVEN) \ + || ((__VALUE__) == LL_I2S_PRESCALER_PARITY_ODD)) +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup I2S_LL_Exported_Functions + * @{ + */ + +/** @addtogroup I2S_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize the SPI/I2S registers to their default reset values. + * @param SPIx SPI Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are de-initialized + * - ERROR: SPI registers are not de-initialized + */ +ErrorStatus LL_I2S_DeInit(SPI_TypeDef *SPIx) +{ + return LL_SPI_DeInit(SPIx); +} + +/** + * @brief Initializes the SPI/I2S registers according to the specified parameters in I2S_InitStruct. + * @note As some bits in SPI configuration registers can only be written when the SPI is disabled (SPI_CR1_SPE bit =0), + * SPI peripheral should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param SPIx SPI Instance + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: SPI registers are Initialized + * - ERROR: SPI registers are not Initialized + */ +ErrorStatus LL_I2S_Init(SPI_TypeDef *SPIx, LL_I2S_InitTypeDef *I2S_InitStruct) +{ + uint32_t i2sdiv = 2U; + uint32_t i2sodd = 0U; + uint32_t packetlength = 1U; + uint32_t tmp; + LL_RCC_ClocksTypeDef rcc_clocks; + uint32_t sourceclock; + ErrorStatus status = ERROR; + + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_MODE(I2S_InitStruct->Mode)); + assert_param(IS_LL_I2S_STANDARD(I2S_InitStruct->Standard)); + assert_param(IS_LL_I2S_DATAFORMAT(I2S_InitStruct->DataFormat)); + assert_param(IS_LL_I2S_MCLK_OUTPUT(I2S_InitStruct->MCLKOutput)); + assert_param(IS_LL_I2S_AUDIO_FREQ(I2S_InitStruct->AudioFreq)); + assert_param(IS_LL_I2S_CPOL(I2S_InitStruct->ClockPolarity)); + + if (LL_I2S_IsEnabled(SPIx) == 0x00000000U) + { + /*---------------------------- SPIx I2SCFGR Configuration -------------------- + * Configure SPIx I2SCFGR with parameters: + * - Mode: SPI_I2SCFGR_I2SCFG[1:0] bit + * - Standard: SPI_I2SCFGR_I2SSTD[1:0] and SPI_I2SCFGR_PCMSYNC bits + * - DataFormat: SPI_I2SCFGR_CHLEN and SPI_I2SCFGR_DATLEN bits + * - ClockPolarity: SPI_I2SCFGR_CKPOL bit + */ + + /* Write to SPIx I2SCFGR */ + MODIFY_REG(SPIx->I2SCFGR, + I2S_I2SCFGR_CLEAR_MASK, + I2S_InitStruct->Mode | I2S_InitStruct->Standard | + I2S_InitStruct->DataFormat | I2S_InitStruct->ClockPolarity | + SPI_I2SCFGR_I2SMOD); + + /*---------------------------- SPIx I2SPR Configuration ---------------------- + * Configure SPIx I2SPR with parameters: + * - MCLKOutput: SPI_I2SPR_MCKOE bit + * - AudioFreq: SPI_I2SPR_I2SDIV[7:0] and SPI_I2SPR_ODD bits + */ + + /* If the requested audio frequency is not the default, compute the prescaler (i2sodd, i2sdiv) + * else, default values are used: i2sodd = 0U, i2sdiv = 2U. + */ + if (I2S_InitStruct->AudioFreq != LL_I2S_AUDIOFREQ_DEFAULT) + { + /* Check the frame length (For the Prescaler computing) + * Default value: LL_I2S_DATAFORMAT_16B (packetlength = 1U). + */ + if (I2S_InitStruct->DataFormat != LL_I2S_DATAFORMAT_16B) + { + /* Packet length is 32 bits */ + packetlength = 2U; + } + + /* I2S Clock source is System clock: Get System Clock frequency */ + LL_RCC_GetSystemClocksFreq(&rcc_clocks); + + /* Get the source clock value: based on System Clock value */ + sourceclock = rcc_clocks.SYSCLK_Frequency; + + /* Compute the Real divider depending on the MCLK output state with a floating point */ + if (I2S_InitStruct->MCLKOutput == LL_I2S_MCLK_OUTPUT_ENABLE) + { + /* MCLK output is enabled */ + tmp = (((((sourceclock / 256U) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + } + else + { + /* MCLK output is disabled */ + tmp = (((((sourceclock / (32U * packetlength)) * 10U) / I2S_InitStruct->AudioFreq)) + 5U); + } + + /* Remove the floating point */ + tmp = tmp / 10U; + + /* Check the parity of the divider */ + i2sodd = (tmp & (uint16_t)0x0001U); + + /* Compute the i2sdiv prescaler */ + i2sdiv = ((tmp - i2sodd) / 2U); + + /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */ + i2sodd = (i2sodd << 8U); + } + + /* Test if the divider is 1 or 0 or greater than 0xFF */ + if ((i2sdiv < 2U) || (i2sdiv > 0xFFU)) + { + /* Set the default values */ + i2sdiv = 2U; + i2sodd = 0U; + } + + /* Write to SPIx I2SPR register the computed value */ + WRITE_REG(SPIx->I2SPR, i2sdiv | i2sodd | I2S_InitStruct->MCLKOutput); + + status = SUCCESS; + } + return status; +} + +/** + * @brief Set each @ref LL_I2S_InitTypeDef field to default value. + * @param I2S_InitStruct pointer to a @ref LL_I2S_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_I2S_StructInit(LL_I2S_InitTypeDef *I2S_InitStruct) +{ + /*--------------- Reset I2S init structure parameters values -----------------*/ + I2S_InitStruct->Mode = LL_I2S_MODE_SLAVE_TX; + I2S_InitStruct->Standard = LL_I2S_STANDARD_PHILIPS; + I2S_InitStruct->DataFormat = LL_I2S_DATAFORMAT_16B; + I2S_InitStruct->MCLKOutput = LL_I2S_MCLK_OUTPUT_DISABLE; + I2S_InitStruct->AudioFreq = LL_I2S_AUDIOFREQ_DEFAULT; + I2S_InitStruct->ClockPolarity = LL_I2S_POLARITY_LOW; +} + +/** + * @brief Set linear and parity prescaler. + * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n + * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). + * @param SPIx SPI Instance + * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. + * @param PrescalerParity This parameter can be one of the following values: + * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN + * @arg @ref LL_I2S_PRESCALER_PARITY_ODD + * @retval None + */ +void LL_I2S_ConfigPrescaler(SPI_TypeDef *SPIx, uint32_t PrescalerLinear, uint32_t PrescalerParity) +{ + /* Check the I2S parameters */ + assert_param(IS_I2S_ALL_INSTANCE(SPIx)); + assert_param(IS_LL_I2S_PRESCALER_LINEAR(PrescalerLinear)); + assert_param(IS_LL_I2S_PRESCALER_PARITY(PrescalerParity)); + + /* Write to SPIx I2SPR */ + MODIFY_REG(SPIx->I2SPR, SPI_I2SPR_I2SDIV | SPI_I2SPR_ODD, PrescalerLinear | (PrescalerParity << 8U)); +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +#endif /* SPI_I2S_SUPPORT */ + +#endif /* defined (SPI1) || defined (SPI2) */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_tim.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_tim.c similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_tim.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_tim.c index 7424045..4fc09ed 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_tim.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_tim.c @@ -1,1201 +1,1201 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_tim.c - * @author MCU Application Team - * @brief TIM LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_tim.h" -#include "py32f0xx_ll_bus.h" - -#ifdef USE_FULL_ASSERT -#include "py32_assert.h" -#else -#define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup PY32F0XX_LL_Driver - * @{ - */ - -#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) - -/** @addtogroup TIM_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup TIM_LL_Private_Macros - * @{ - */ -#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ - || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) - -#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ - || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) - -#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ - || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ - || ((__VALUE__) == LL_TIM_OCMODE_PWM2)) - -#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ - || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) - -#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ - || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) - -#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ - || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) - -#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ - || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) - -#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ - || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) - -#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ - || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) - -#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) - -#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ - || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) - -#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ - || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) - -#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) - -#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ - || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) - -#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ - || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) - -#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ - || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) - -#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ - || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) - -#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ - || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) -/** - * @} - */ - - -/* Private function prototypes -----------------------------------------------*/ -/** @defgroup TIM_LL_Private_Functions TIM Private Functions - * @{ - */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); -/** - * @} - */ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup TIM_LL_Exported_Functions - * @{ - */ - -/** @addtogroup TIM_LL_EF_Init - * @{ - */ - -/** - * @brief Set TIMx registers to their reset values. - * @param TIMx Timer instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: invalid TIMx instance - */ -ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) -{ - ErrorStatus result = SUCCESS; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(TIMx)); - - if (TIMx == TIM1) - { - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM1); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM1); - } -#if defined(TIM2) - if (TIMx == TIM2) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); - } -#endif -#if defined(TIM3) - else if (TIMx == TIM3) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); - } -#endif -#if defined(TIM4) - else if (TIMx == TIM4) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); - } -#endif -#if defined(TIM5) - else if (TIMx == TIM5) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); - } -#endif -#if defined(TIM6) - else if (TIMx == TIM6) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); - } -#endif -#if defined (TIM7) - else if (TIMx == TIM7) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); - } -#endif -#if defined(TIM8) - else if (TIMx == TIM8) - { - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM8); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM8); - } -#endif -#if defined(TIM9) - else if (TIMx == TIM9) - { - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM9); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM9); - } -#endif -#if defined(TIM10) - else if (TIMx == TIM10) - { - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM10); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM10); - } -#endif -#if defined(TIM11) - else if (TIMx == TIM11) - { - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM11); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM11); - } -#endif -#if defined(TIM12) - else if (TIMx == TIM12) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); - } -#endif -#if defined(TIM13) - else if (TIMx == TIM13) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); - } -#endif -#if defined(TIM14) - else if (TIMx == TIM14) - { - LL_APB1_GRP1_ForceReset(LL_APB1_GRP2_PERIPH_TIM14); - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM14); - } -#endif -#if defined(TIM15) - else if (TIMx == TIM15) - { - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM15); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM15); - } -#endif -#if defined(TIM16) - else if (TIMx == TIM16) - { - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM16); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM16); - } -#endif -#if defined(TIM17) - else if (TIMx == TIM17) - { - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM17); - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM17); - } -#endif - else - { - result = ERROR; - } - - return result; -} - -/** - * @brief Set the fields of the time base unit configuration data structure - * to their default values. - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) - * @retval None - */ -void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) -{ - /* Set the default configuration */ - TIM_InitStruct->Prescaler = (uint16_t)0x0000; - TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; - TIM_InitStruct->Autoreload = 0xFFFFFFFFU; - TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; - TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; -} - -/** - * @brief Configure the TIMx time base unit. - * @param TIMx Timer Instance - * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) -{ - uint32_t tmpcr1; - - /* Check the parameters */ - assert_param(IS_TIM_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); - assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); - - tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); - - if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) - { - /* Select the Counter Mode */ - MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); - } - - if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) - { - /* Set the clock division */ - MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); - } - - /* Write to TIMx CR1 */ - LL_TIM_WriteReg(TIMx, CR1, tmpcr1); - - /* Set the Autoreload value */ - LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); - - /* Set the Prescaler value */ - LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); - - if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) - { - /* Set the Repetition Counter value */ - LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); - } - - /* Generate an update event to reload the Prescaler - and the repetition counter value (if applicable) immediately */ - LL_TIM_GenerateEvent_UPDATE(TIMx); - - return SUCCESS; -} - -/** - * @brief Set the fields of the TIMx output channel configuration data - * structure to their default values. - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) - * @retval None - */ -void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) -{ - /* Set the default configuration */ - TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; - TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; - TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; - TIM_OC_InitStruct->CompareValue = 0x00000000U; - TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; - TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; - TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; - TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; -} - -/** - * @brief Configure the TIMx output channel. - * @param TIMx Timer Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx output channel is initialized - * - ERROR: TIMx output channel is not initialized - */ -ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) -{ - ErrorStatus result = ERROR; - - switch (Channel) - { - case LL_TIM_CHANNEL_CH1: - result = OC1Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH2: - result = OC2Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH3: - result = OC3Config(TIMx, TIM_OC_InitStruct); - break; - case LL_TIM_CHANNEL_CH4: - result = OC4Config(TIMx, TIM_OC_InitStruct); - break; - default: - break; - } - - return result; -} - -/** - * @brief Set the fields of the TIMx input channel configuration data - * structure to their default values. - * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) - * @retval None - */ -void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Set the default configuration */ - TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; - TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; - TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; - TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; -} - -/** - * @brief Configure the TIMx input channel. - * @param TIMx Timer Instance - * @param Channel This parameter can be one of the following values: - * @arg @ref LL_TIM_CHANNEL_CH1 - * @arg @ref LL_TIM_CHANNEL_CH2 - * @arg @ref LL_TIM_CHANNEL_CH3 - * @arg @ref LL_TIM_CHANNEL_CH4 - * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx output channel is initialized - * - ERROR: TIMx output channel is not initialized - */ -ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) -{ - ErrorStatus result = ERROR; - - switch (Channel) - { - case LL_TIM_CHANNEL_CH1: - result = IC1Config(TIMx, TIM_IC_InitStruct); - break; - case LL_TIM_CHANNEL_CH2: - result = IC2Config(TIMx, TIM_IC_InitStruct); - break; - case LL_TIM_CHANNEL_CH3: - result = IC3Config(TIMx, TIM_IC_InitStruct); - break; - case LL_TIM_CHANNEL_CH4: - result = IC4Config(TIMx, TIM_IC_InitStruct); - break; - default: - break; - } - - return result; -} - -/** - * @brief Fills each TIM_EncoderInitStruct field with its default value - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) - * @retval None - */ -void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) -{ - /* Set the default configuration */ - TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; - TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; - TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; - TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; - TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; - TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; - TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; - TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; - TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; -} - -/** - * @brief Configure the encoder interface of the timer instance. - * @param TIMx Timer Instance - * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - - /* Check the parameters */ - assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); - assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); - assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); - - /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ - TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Configure TI1 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); - - /* Configure TI2 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); - tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); - - /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ - tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); - tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); - tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Set encoder mode */ - LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Set the fields of the TIMx Hall sensor interface configuration data - * structure to their default values. - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) - * @retval None - */ -void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) -{ - /* Set the default configuration */ - TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; - TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; - TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; - TIM_HallSensorInitStruct->CommutationDelay = 0U; -} - -/** - * @brief Configure the Hall sensor interface of the timer instance. - * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR - * to the TI1 input channel - * @note TIMx slave mode controller is configured in reset mode. - Selected internal trigger is TI1F_ED. - * @note Channel 1 is configured as input, IC1 is mapped on TRC. - * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed - * between 2 changes on the inputs. It gives information about motor speed. - * @note Channel 2 is configured in output PWM 2 mode. - * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. - * @note OC2REF is selected as trigger output on TRGO. - * @param TIMx Timer Instance - * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) -{ - uint32_t tmpcr2; - uint32_t tmpccmr1; - uint32_t tmpccer; - uint32_t tmpsmcr; - - /* Check the parameters */ - assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); - assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); - - /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ - TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx SMCR register value */ - tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); - - /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ - tmpcr2 |= TIM_CR2_TI1S; - - /* OC2REF signal is used as trigger output (TRGO) */ - tmpcr2 |= LL_TIM_TRGO_OC2REF; - - /* Configure the slave mode controller */ - tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); - tmpsmcr |= LL_TIM_TS_TI1F_ED; - tmpsmcr |= LL_TIM_SLAVEMODE_RESET; - - /* Configure input channel 1 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); - tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); - tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); - tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); - - /* Configure input channel 2 */ - tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); - tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); - - /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ - tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); - tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); - tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx SMCR */ - LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - /* Write to TIMx CCR2 */ - LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); - - return SUCCESS; -} - -/** - * @brief Set the fields of the Break and Dead Time configuration data structure - * to their default values. - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) - * @retval None - */ -void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) -{ - /* Set the default configuration */ - TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; - TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; - TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; - TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; - TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; - TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; - TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; -} - -/** - * @brief Configure the Break and Dead Time feature of the timer instance. - * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked - * depending on the LOCK configuration, it can be necessary to configure all of - * them during the first write access to the TIMx_BDTR register. - * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not - * a timer instance provides a break input. - * @param TIMx Timer Instance - * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Break and Dead Time is initialized - * - ERROR: not applicable - */ -ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) -{ - uint32_t tmpbdtr = 0; - - /* Check the parameters */ - assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); - assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); - assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); - assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); - assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); - assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); - - /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, - the OSSI State, the dead time value and the Automatic Output Enable Bit */ - - /* Set the BDTR bits */ - MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); - MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); - MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); - MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); - MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); - MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); - - /* Set TIMx_BDTR */ - LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); - - return SUCCESS; -} -/** - * @} - */ - -/** - * @} - */ - -/** @addtogroup TIM_LL_Private_Functions TIM Private Functions - * @brief Private functions - * @{ - */ -/** - * @brief Configure the TIMx output channel 1. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); - - /* Set the Output Compare Mode */ - MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the complementary output Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); - - /* Set the complementary output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); - - /* Set the complementary output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 2. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr1; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR1 register value */ - tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the complementary output Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); - - /* Set the complementary output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); - - /* Set the complementary output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR1 */ - LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 3. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - - /* Disable the Channel 3: Reset the CC3E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the complementary output Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); - - /* Set the complementary output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); - - /* Set the complementary output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR2 */ - LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx output channel 4. - * @param TIMx Timer Instance - * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) -{ - uint32_t tmpccmr2; - uint32_t tmpccer; - uint32_t tmpcr2; - - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); - assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); - assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); - - /* Get the TIMx CCER register value */ - tmpccer = LL_TIM_ReadReg(TIMx, CCER); - - /* Get the TIMx CR2 register value */ - tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); - - /* Get the TIMx CCMR2 register value */ - tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); - - /* Reset Capture/Compare selection Bits */ - CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); - - /* Select the Output Compare Mode */ - MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); - - /* Set the Output Compare Polarity */ - MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); - - /* Set the Output State */ - MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); - - if (IS_TIM_BREAK_INSTANCE(TIMx)) - { - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); - assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); - - /* Set the Output Idle state */ - MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); - } - - /* Write to TIMx CR2 */ - LL_TIM_WriteReg(TIMx, CR2, tmpcr2); - - /* Write to TIMx CCMR2 */ - LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); - - /* Set the Capture Compare Register value */ - LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); - - /* Write to TIMx CCER */ - LL_TIM_WriteReg(TIMx, CCER, tmpccer); - - return SUCCESS; -} - - -/** - * @brief Configure the TIMx input channel 1. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC1_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 1: Reset the CC1E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR1, - (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); - - /* Select the Polarity and set the CC1E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC1P | TIM_CCER_CC1NP), - (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 2. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC2_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 2: Reset the CC2E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR1, - (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - - /* Select the Polarity and set the CC2E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC2P | TIM_CCER_CC2NP), - ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 3. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC3_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 3: Reset the CC3E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR2, - (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); - - /* Select the Polarity and set the CC3E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC3P | TIM_CCER_CC3NP), - ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); - - return SUCCESS; -} - -/** - * @brief Configure the TIMx input channel 4. - * @param TIMx Timer Instance - * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure - * @retval An ErrorStatus enumeration value: - * - SUCCESS: TIMx registers are de-initialized - * - ERROR: not applicable - */ -static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) -{ - /* Check the parameters */ - assert_param(IS_TIM_CC4_INSTANCE(TIMx)); - assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); - assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); - assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); - assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); - - /* Disable the Channel 4: Reset the CC4E Bit */ - TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; - - /* Select the Input and set the filter and the prescaler value */ - MODIFY_REG(TIMx->CCMR2, - (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), - (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); - - /* Select the Polarity and set the CC4E Bit */ - MODIFY_REG(TIMx->CCER, - (TIM_CCER_CC4P | TIM_CCER_CC4NP), - ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); - - return SUCCESS; -} - - -/** - * @} - */ - -/** - * @} - */ - -#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_tim.c + * @author MCU Application Team + * @brief TIM LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_tim.h" +#include "py32f0xx_ll_bus.h" + +#ifdef USE_FULL_ASSERT +#include "py32_assert.h" +#else +#define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup PY32F0XX_LL_Driver + * @{ + */ + +#if defined (TIM1) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM6) || defined (TIM7) || defined (TIM8) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM15) || defined (TIM16) || defined (TIM17) + +/** @addtogroup TIM_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup TIM_LL_Private_Macros + * @{ + */ +#define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \ + || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN)) + +#define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \ + || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4)) + +#define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \ + || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \ + || ((__VALUE__) == LL_TIM_OCMODE_PWM2)) + +#define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \ + || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE)) + +#define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \ + || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW)) + +#define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \ + || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH)) + +#define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \ + || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC)) + +#define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \ + || ((__VALUE__) == LL_TIM_ICPSC_DIV8)) + +#define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \ + || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8)) + +#define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \ + || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12)) + +#define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \ + || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING)) + +#define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSR_ENABLE)) + +#define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \ + || ((__VALUE__) == LL_TIM_OSSI_ENABLE)) + +#define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_1) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_2) \ + || ((__VALUE__) == LL_TIM_LOCKLEVEL_3)) + +#define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \ + || ((__VALUE__) == LL_TIM_BREAK_ENABLE)) + +#define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \ + || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH)) + +#define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \ + || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE)) +/** + * @} + */ + + +/* Private function prototypes -----------------------------------------------*/ +/** @defgroup TIM_LL_Private_Functions TIM Private Functions + * @{ + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct); +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct); +/** + * @} + */ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup TIM_LL_Exported_Functions + * @{ + */ + +/** @addtogroup TIM_LL_EF_Init + * @{ + */ + +/** + * @brief Set TIMx registers to their reset values. + * @param TIMx Timer instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: invalid TIMx instance + */ +ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx) +{ + ErrorStatus result = SUCCESS; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + + if (TIMx == TIM1) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM1); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM1); + } +#if defined(TIM2) + if (TIMx == TIM2) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2); + } +#endif +#if defined(TIM3) + else if (TIMx == TIM3) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3); + } +#endif +#if defined(TIM4) + else if (TIMx == TIM4) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4); + } +#endif +#if defined(TIM5) + else if (TIMx == TIM5) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5); + } +#endif +#if defined(TIM6) + else if (TIMx == TIM6) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6); + } +#endif +#if defined (TIM7) + else if (TIMx == TIM7) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7); + } +#endif +#if defined(TIM8) + else if (TIMx == TIM8) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM8); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM8); + } +#endif +#if defined(TIM9) + else if (TIMx == TIM9) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM9); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM9); + } +#endif +#if defined(TIM10) + else if (TIMx == TIM10) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM10); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM10); + } +#endif +#if defined(TIM11) + else if (TIMx == TIM11) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM11); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM11); + } +#endif +#if defined(TIM12) + else if (TIMx == TIM12) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12); + } +#endif +#if defined(TIM13) + else if (TIMx == TIM13) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13); + } +#endif +#if defined(TIM14) + else if (TIMx == TIM14) + { + LL_APB1_GRP1_ForceReset(LL_APB1_GRP2_PERIPH_TIM14); + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM14); + } +#endif +#if defined(TIM15) + else if (TIMx == TIM15) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM15); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM15); + } +#endif +#if defined(TIM16) + else if (TIMx == TIM16) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM16); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM16); + } +#endif +#if defined(TIM17) + else if (TIMx == TIM17) + { + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_TIM17); + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_TIM17); + } +#endif + else + { + result = ERROR; + } + + return result; +} + +/** + * @brief Set the fields of the time base unit configuration data structure + * to their default values. + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure) + * @retval None + */ +void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct) +{ + /* Set the default configuration */ + TIM_InitStruct->Prescaler = (uint16_t)0x0000; + TIM_InitStruct->CounterMode = LL_TIM_COUNTERMODE_UP; + TIM_InitStruct->Autoreload = 0xFFFFFFFFU; + TIM_InitStruct->ClockDivision = LL_TIM_CLOCKDIVISION_DIV1; + TIM_InitStruct->RepetitionCounter = (uint8_t)0x00; +} + +/** + * @brief Configure the TIMx time base unit. + * @param TIMx Timer Instance + * @param TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct) +{ + uint32_t tmpcr1; + + /* Check the parameters */ + assert_param(IS_TIM_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode)); + assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision)); + + tmpcr1 = LL_TIM_ReadReg(TIMx, CR1); + + if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx)) + { + /* Select the Counter Mode */ + MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode); + } + + if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx)) + { + /* Set the clock division */ + MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision); + } + + /* Write to TIMx CR1 */ + LL_TIM_WriteReg(TIMx, CR1, tmpcr1); + + /* Set the Autoreload value */ + LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload); + + /* Set the Prescaler value */ + LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler); + + if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx)) + { + /* Set the Repetition Counter value */ + LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter); + } + + /* Generate an update event to reload the Prescaler + and the repetition counter value (if applicable) immediately */ + LL_TIM_GenerateEvent_UPDATE(TIMx); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx output channel configuration data + * structure to their default values. + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure) + * @retval None + */ +void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + /* Set the default configuration */ + TIM_OC_InitStruct->OCMode = LL_TIM_OCMODE_FROZEN; + TIM_OC_InitStruct->OCState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->OCNState = LL_TIM_OCSTATE_DISABLE; + TIM_OC_InitStruct->CompareValue = 0x00000000U; + TIM_OC_InitStruct->OCPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCNPolarity = LL_TIM_OCPOLARITY_HIGH; + TIM_OC_InitStruct->OCIdleState = LL_TIM_OCIDLESTATE_LOW; + TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW; +} + +/** + * @brief Configure the TIMx output channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = OC1Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = OC2Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = OC3Config(TIMx, TIM_OC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = OC4Config(TIMx, TIM_OC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Set the fields of the TIMx input channel configuration data + * structure to their default values. + * @param TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure) + * @retval None + */ +void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Set the default configuration */ + TIM_ICInitStruct->ICPolarity = LL_TIM_IC_POLARITY_RISING; + TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_ICInitStruct->ICPrescaler = LL_TIM_ICPSC_DIV1; + TIM_ICInitStruct->ICFilter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the TIMx input channel. + * @param TIMx Timer Instance + * @param Channel This parameter can be one of the following values: + * @arg @ref LL_TIM_CHANNEL_CH1 + * @arg @ref LL_TIM_CHANNEL_CH2 + * @arg @ref LL_TIM_CHANNEL_CH3 + * @arg @ref LL_TIM_CHANNEL_CH4 + * @param TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx output channel is initialized + * - ERROR: TIMx output channel is not initialized + */ +ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct) +{ + ErrorStatus result = ERROR; + + switch (Channel) + { + case LL_TIM_CHANNEL_CH1: + result = IC1Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH2: + result = IC2Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH3: + result = IC3Config(TIMx, TIM_IC_InitStruct); + break; + case LL_TIM_CHANNEL_CH4: + result = IC4Config(TIMx, TIM_IC_InitStruct); + break; + default: + break; + } + + return result; +} + +/** + * @brief Fills each TIM_EncoderInitStruct field with its default value + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure) + * @retval None + */ +void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + /* Set the default configuration */ + TIM_EncoderInitStruct->EncoderMode = LL_TIM_ENCODERMODE_X2_TI1; + TIM_EncoderInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_EncoderInitStruct->IC2Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI; + TIM_EncoderInitStruct->IC2Prescaler = LL_TIM_ICPSC_DIV1; + TIM_EncoderInitStruct->IC2Filter = LL_TIM_IC_FILTER_FDIV1; +} + +/** + * @brief Configure the encoder interface of the timer instance. + * @param TIMx Timer Instance + * @param TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + + /* Check the parameters */ + assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Configure TI1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U); + + /* Configure TI2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U); + tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U); + + /* Set TI1 and TI2 polarity and enable TI1 and TI2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Set encoder mode */ + LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Set the fields of the TIMx Hall sensor interface configuration data + * structure to their default values. + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure) + * @retval None + */ +void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + /* Set the default configuration */ + TIM_HallSensorInitStruct->IC1Polarity = LL_TIM_IC_POLARITY_RISING; + TIM_HallSensorInitStruct->IC1Prescaler = LL_TIM_ICPSC_DIV1; + TIM_HallSensorInitStruct->IC1Filter = LL_TIM_IC_FILTER_FDIV1; + TIM_HallSensorInitStruct->CommutationDelay = 0U; +} + +/** + * @brief Configure the Hall sensor interface of the timer instance. + * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR + * to the TI1 input channel + * @note TIMx slave mode controller is configured in reset mode. + Selected internal trigger is TI1F_ED. + * @note Channel 1 is configured as input, IC1 is mapped on TRC. + * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed + * between 2 changes on the inputs. It gives information about motor speed. + * @note Channel 2 is configured in output PWM 2 mode. + * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay. + * @note OC2REF is selected as trigger output on TRGO. + * @param TIMx Timer Instance + * @param TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct) +{ + uint32_t tmpcr2; + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpsmcr; + + /* Check the parameters */ + assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity)); + assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter)); + + /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */ + TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx SMCR register value */ + tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR); + + /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */ + tmpcr2 |= TIM_CR2_TI1S; + + /* OC2REF signal is used as trigger output (TRGO) */ + tmpcr2 |= LL_TIM_TRGO_OC2REF; + + /* Configure the slave mode controller */ + tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS); + tmpsmcr |= LL_TIM_TS_TI1F_ED; + tmpsmcr |= LL_TIM_SLAVEMODE_RESET; + + /* Configure input channel 1 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC); + tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U); + tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U); + + /* Configure input channel 2 */ + tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE | TIM_CCMR1_OC2PE | TIM_CCMR1_OC2CE); + tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U); + + /* Set Channel 1 polarity and enable Channel 1 and Channel2 */ + tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP); + tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity); + tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E); + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx SMCR */ + LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + /* Write to TIMx CCR2 */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay); + + return SUCCESS; +} + +/** + * @brief Set the fields of the Break and Dead Time configuration data structure + * to their default values. + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @retval None + */ +void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + /* Set the default configuration */ + TIM_BDTRInitStruct->OSSRState = LL_TIM_OSSR_DISABLE; + TIM_BDTRInitStruct->OSSIState = LL_TIM_OSSI_DISABLE; + TIM_BDTRInitStruct->LockLevel = LL_TIM_LOCKLEVEL_OFF; + TIM_BDTRInitStruct->DeadTime = (uint8_t)0x00; + TIM_BDTRInitStruct->BreakState = LL_TIM_BREAK_DISABLE; + TIM_BDTRInitStruct->BreakPolarity = LL_TIM_BREAK_POLARITY_LOW; + TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE; +} + +/** + * @brief Configure the Break and Dead Time feature of the timer instance. + * @note As the bits AOE, BKP, BKE, OSSR, OSSI and DTG[7:0] can be write-locked + * depending on the LOCK configuration, it can be necessary to configure all of + * them during the first write access to the TIMx_BDTR register. + * @note Macro IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not + * a timer instance provides a break input. + * @param TIMx Timer Instance + * @param TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure) + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Break and Dead Time is initialized + * - ERROR: not applicable + */ +ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct) +{ + uint32_t tmpbdtr = 0; + + /* Check the parameters */ + assert_param(IS_TIM_BREAK_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState)); + assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState)); + assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel)); + assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState)); + assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity)); + assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput)); + + /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State, + the OSSI State, the dead time value and the Automatic Output Enable Bit */ + + /* Set the BDTR bits */ + MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime); + MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState); + MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState); + MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity); + MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput); + MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput); + + /* Set TIMx_BDTR */ + LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr); + + return SUCCESS; +} +/** + * @} + */ + +/** + * @} + */ + +/** @addtogroup TIM_LL_Private_Functions TIM Private Functions + * @brief Private functions + * @{ + */ +/** + * @brief Configure the TIMx output channel 1. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S); + + /* Set the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 2. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr1; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR1 register value */ + tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR1 */ + LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 3. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the complementary output Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U); + + /* Set the complementary output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U); + + /* Set the complementary output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx output channel 4. + * @param TIMx Timer Instance + * @param TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct) +{ + uint32_t tmpccmr2; + uint32_t tmpccer; + uint32_t tmpcr2; + + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity)); + assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity)); + assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E); + + /* Get the TIMx CCER register value */ + tmpccer = LL_TIM_ReadReg(TIMx, CCER); + + /* Get the TIMx CR2 register value */ + tmpcr2 = LL_TIM_ReadReg(TIMx, CR2); + + /* Get the TIMx CCMR2 register value */ + tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2); + + /* Reset Capture/Compare selection Bits */ + CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S); + + /* Select the Output Compare Mode */ + MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U); + + /* Set the Output Compare Polarity */ + MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U); + + /* Set the Output State */ + MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U); + + if (IS_TIM_BREAK_INSTANCE(TIMx)) + { + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState)); + assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState)); + + /* Set the Output Idle state */ + MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U); + } + + /* Write to TIMx CR2 */ + LL_TIM_WriteReg(TIMx, CR2, tmpcr2); + + /* Write to TIMx CCMR2 */ + LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2); + + /* Set the Capture Compare Register value */ + LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue); + + /* Write to TIMx CCER */ + LL_TIM_WriteReg(TIMx, CCER, tmpccer); + + return SUCCESS; +} + + +/** + * @brief Configure the TIMx input channel 1. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC1_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 1: Reset the CC1E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC1E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC1P | TIM_CCER_CC1NP), + (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 2. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC2_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 2: Reset the CC2E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR1, + (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC2E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC2P | TIM_CCER_CC2NP), + ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 3. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC3_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 3: Reset the CC3E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U); + + /* Select the Polarity and set the CC3E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC3P | TIM_CCER_CC3NP), + ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E)); + + return SUCCESS; +} + +/** + * @brief Configure the TIMx input channel 4. + * @param TIMx Timer Instance + * @param TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure + * @retval An ErrorStatus enumeration value: + * - SUCCESS: TIMx registers are de-initialized + * - ERROR: not applicable + */ +static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct) +{ + /* Check the parameters */ + assert_param(IS_TIM_CC4_INSTANCE(TIMx)); + assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity)); + assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput)); + assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler)); + assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter)); + + /* Disable the Channel 4: Reset the CC4E Bit */ + TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E; + + /* Select the Input and set the filter and the prescaler value */ + MODIFY_REG(TIMx->CCMR2, + (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC), + (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U); + + /* Select the Polarity and set the CC4E Bit */ + MODIFY_REG(TIMx->CCER, + (TIM_CCER_CC4P | TIM_CCER_CC4NP), + ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E)); + + return SUCCESS; +} + + +/** + * @} + */ + +/** + * @} + */ + +#endif /* TIM1 || TIM2 || TIM3 || TIM4 || TIM5 || TIM6 || TIM7 || TIM8 || TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM15 || TIM16 || TIM17 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_usart.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_usart.c similarity index 97% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_usart.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_usart.c index 39c567b..ba109d6 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_usart.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_usart.c @@ -1,388 +1,388 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_usart.c - * @author MCU Application Team - * @brief USART LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -#if defined(USE_FULL_LL_DRIVER) - -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_usart.h" -#include "py32f0xx_ll_rcc.h" -#include "py32f0xx_ll_bus.h" -#ifdef USE_FULL_ASSERT - #include "py32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -#if defined (USART1) || defined (USART2) - -/** @addtogroup USART_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup USART_LL_Private_Constants - * @{ - */ - -/** - * @} - */ - - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup USART_LL_Private_Macros - * @{ - */ - -/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available - * divided by the smallest oversampling used on the USART (i.e. 8) */ -#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4500000U) - -/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ -#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) - -/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ -#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) - -#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ - || ((__VALUE__) == LL_USART_DIRECTION_RX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX) \ - || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) - -#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ - || ((__VALUE__) == LL_USART_PARITY_EVEN) \ - || ((__VALUE__) == LL_USART_PARITY_ODD)) - -#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \ - || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) - -#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ - || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) - -#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ - || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) - -#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ - || ((__VALUE__) == LL_USART_PHASE_2EDGE)) - -#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ - || ((__VALUE__) == LL_USART_POLARITY_HIGH)) - -#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ - || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) - -#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_1) \ - || ((__VALUE__) == LL_USART_STOPBITS_2)) - -#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ - || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) - -/** - * @} - */ - -/* Private function prototypes -----------------------------------------------*/ - -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup USART_LL_Exported_Functions - * @{ - */ - -/** @addtogroup USART_LL_EF_Init - * @{ - */ - -/** - * @brief De-initialize USART registers (Registers restored to their default values). - * @param USARTx USART Instance - * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers are de-initialized - * - ERROR: USART registers are not de-initialized - */ -ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) -{ - ErrorStatus status = SUCCESS; - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(USARTx)); - - if (USARTx == USART1) - { - /* Force reset of USART clock */ - LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART1); - - /* Release reset of USART clock */ - LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART1); - } -#if defined(USART2) - else if (USARTx == USART2) - { - /* Force reset of USART clock */ - LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); - - /* Release reset of USART clock */ - LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); - } -#endif /* USART2 */ - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Initialize USART registers according to the specified - * parameters in USART_InitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). - * @param USARTx USART Instance - * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure - * that contains the configuration information for the specified USART peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers are initialized according to USART_InitStruct content - * - ERROR: Problem occurred during USART Registers initialization - */ -ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) -{ - ErrorStatus status = ERROR; - uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; - LL_RCC_ClocksTypeDef rcc_clocks; - - /* Check the parameters */ - assert_param(IS_UART_INSTANCE(USARTx)); - assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); - assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); - assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); - assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); - assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); - assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); -#if defined(USART_CR3_OVER8) - assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); -#endif /* USART_OverSampling_Feature */ - - /* USART needs to be in disabled state, in order to be able to configure some bits in - CRx registers */ - if (LL_USART_IsEnabled(USARTx) == 0U) - { - /*---------------------------- USART CR1 Configuration ----------------------- - * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: - * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value - * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value - * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value - * - Oversampling: USART_CR3_OVER8 bit according to USART_InitStruct->OverSampling value. - */ -#if defined(USART_CR3_OVER8) - MODIFY_REG(USARTx->CR1, - (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | - USART_CR1_TE | USART_CR1_RE), - (USART_InitStruct->DataWidth | USART_InitStruct->Parity | - USART_InitStruct->TransferDirection)); - MODIFY_REG(USARTx->CR3, USART_CR3_OVER8, USART_InitStruct->OverSampling); -#else - MODIFY_REG(USARTx->CR1, - (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | - USART_CR1_TE | USART_CR1_RE), - (USART_InitStruct->DataWidth | USART_InitStruct->Parity | - USART_InitStruct->TransferDirection)); -#endif /* USART_OverSampling_Feature */ - /*---------------------------- USART CR2 Configuration ----------------------- - * Configure USARTx CR2 (Stop bits) with parameters: - * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. - * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). - */ - LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); - - /*---------------------------- USART CR3 Configuration ----------------------- - * Configure USARTx CR3 (Hardware Flow Control) with parameters: - * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. - */ - LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); - - /*---------------------------- USART BRR Configuration ----------------------- - * Retrieve Clock frequency used for USART Peripheral - */ - LL_RCC_GetSystemClocksFreq(&rcc_clocks); - periphclk = rcc_clocks.PCLK1_Frequency; - - /* Configure the USART Baud Rate : - - valid baud rate value (different from 0) is required - - Peripheral clock as returned by RCC service, should be valid (different from 0). - */ - if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) - && (USART_InitStruct->BaudRate != 0U)) - { - status = SUCCESS; -#if defined(USART_CR3_OVER8) - LL_USART_SetBaudRate(USARTx, - periphclk, - USART_InitStruct->OverSampling, - USART_InitStruct->BaudRate); -#else - LL_USART_SetBaudRate(USARTx, - periphclk, - USART_InitStruct->BaudRate); -#endif /* USART_OverSampling_Feature */ - /* Check BRR is greater than or equal to 16d */ - assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); - - /* Check BRR is greater than or equal to 16d */ - assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); - } - } - /* Endif (=> USART not in Disabled state => return ERROR) */ - - return (status); -} - -/** - * @brief Set each @ref LL_USART_InitTypeDef field to default value. - * @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ - -void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) -{ - /* Set USART_InitStruct fields to default values */ - USART_InitStruct->BaudRate = 9600U; - USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; - USART_InitStruct->StopBits = LL_USART_STOPBITS_1; - USART_InitStruct->Parity = LL_USART_PARITY_NONE ; - USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; - USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; -#if defined(USART_CR3_OVER8) - USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; -#endif /* USART_OverSampling_Feature */ -} - -/** - * @brief Initialize USART Clock related settings according to the - * specified parameters in the USART_ClockInitStruct. - * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), - * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. - * @param USARTx USART Instance - * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure - * that contains the Clock configuration information for the specified USART peripheral. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content - * - ERROR: Problem occurred during USART Registers initialization - */ -ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - ErrorStatus status = SUCCESS; - - /* Check USART Instance and Clock signal output parameters */ - assert_param(IS_UART_INSTANCE(USARTx)); - assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); - - /* USART needs to be in disabled state, in order to be able to configure some bits in - CRx registers */ - if (LL_USART_IsEnabled(USARTx) == 0U) - { - /*---------------------------- USART CR2 Configuration -----------------------*/ - /* If Clock signal has to be output */ - if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) - { - /* Deactivate Clock signal delivery : - * - Disable Clock Output: USART_CR2_CLKEN cleared - */ - LL_USART_DisableSCLKOutput(USARTx); - } - else - { - /* Ensure USART instance is USART capable */ - assert_param(IS_USART_INSTANCE(USARTx)); - - /* Check clock related parameters */ - assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); - assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); - assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); - - /*---------------------------- USART CR2 Configuration ----------------------- - * Configure USARTx CR2 (Clock signal related bits) with parameters: - * - Enable Clock Output: USART_CR2_CLKEN set - * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value - * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value - * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. - */ - MODIFY_REG(USARTx->CR2, - USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, - USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | - USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); - } - } - /* Else (USART not in Disabled state => return ERROR */ - else - { - status = ERROR; - } - - return (status); -} - -/** - * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. - * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure - * whose fields will be set to default values. - * @retval None - */ -void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) -{ - /* Set LL_USART_ClockInitStruct fields with default values */ - USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; - USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ - USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ -} - -/** - * @} - */ - -/** - * @} - */ - -/** - * @} - */ - -#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */ - -/** - * @} - */ - -#endif /* USE_FULL_LL_DRIVER */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ - +/** + ****************************************************************************** + * @file py32f0xx_ll_usart.c + * @author MCU Application Team + * @brief USART LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +#if defined(USE_FULL_LL_DRIVER) + +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_usart.h" +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_bus.h" +#ifdef USE_FULL_ASSERT + #include "py32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +#if defined (USART1) || defined (USART2) + +/** @addtogroup USART_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Constants + * @{ + */ + +/** + * @} + */ + + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup USART_LL_Private_Macros + * @{ + */ + +/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available + * divided by the smallest oversampling used on the USART (i.e. 8) */ +#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 4500000U) + +/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */ +#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U) + +/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */ +#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU) + +#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \ + || ((__VALUE__) == LL_USART_DIRECTION_RX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX) \ + || ((__VALUE__) == LL_USART_DIRECTION_TX_RX)) + +#define IS_LL_USART_PARITY(__VALUE__) (((__VALUE__) == LL_USART_PARITY_NONE) \ + || ((__VALUE__) == LL_USART_PARITY_EVEN) \ + || ((__VALUE__) == LL_USART_PARITY_ODD)) + +#define IS_LL_USART_DATAWIDTH(__VALUE__) (((__VALUE__) == LL_USART_DATAWIDTH_8B) \ + || ((__VALUE__) == LL_USART_DATAWIDTH_9B)) + +#define IS_LL_USART_OVERSAMPLING(__VALUE__) (((__VALUE__) == LL_USART_OVERSAMPLING_16) \ + || ((__VALUE__) == LL_USART_OVERSAMPLING_8)) + +#define IS_LL_USART_LASTBITCLKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_LASTCLKPULSE_NO_OUTPUT) \ + || ((__VALUE__) == LL_USART_LASTCLKPULSE_OUTPUT)) + +#define IS_LL_USART_CLOCKPHASE(__VALUE__) (((__VALUE__) == LL_USART_PHASE_1EDGE) \ + || ((__VALUE__) == LL_USART_PHASE_2EDGE)) + +#define IS_LL_USART_CLOCKPOLARITY(__VALUE__) (((__VALUE__) == LL_USART_POLARITY_LOW) \ + || ((__VALUE__) == LL_USART_POLARITY_HIGH)) + +#define IS_LL_USART_CLOCKOUTPUT(__VALUE__) (((__VALUE__) == LL_USART_CLOCK_DISABLE) \ + || ((__VALUE__) == LL_USART_CLOCK_ENABLE)) + +#define IS_LL_USART_STOPBITS(__VALUE__) (((__VALUE__) == LL_USART_STOPBITS_1) \ + || ((__VALUE__) == LL_USART_STOPBITS_2)) + +#define IS_LL_USART_HWCONTROL(__VALUE__) (((__VALUE__) == LL_USART_HWCONTROL_NONE) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_CTS) \ + || ((__VALUE__) == LL_USART_HWCONTROL_RTS_CTS)) + +/** + * @} + */ + +/* Private function prototypes -----------------------------------------------*/ + +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup USART_LL_Exported_Functions + * @{ + */ + +/** @addtogroup USART_LL_EF_Init + * @{ + */ + +/** + * @brief De-initialize USART registers (Registers restored to their default values). + * @param USARTx USART Instance + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are de-initialized + * - ERROR: USART registers are not de-initialized + */ +ErrorStatus LL_USART_DeInit(USART_TypeDef *USARTx) +{ + ErrorStatus status = SUCCESS; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + + if (USARTx == USART1) + { + /* Force reset of USART clock */ + LL_APB1_GRP2_ForceReset(LL_APB1_GRP2_PERIPH_USART1); + + /* Release reset of USART clock */ + LL_APB1_GRP2_ReleaseReset(LL_APB1_GRP2_PERIPH_USART1); + } +#if defined(USART2) + else if (USARTx == USART2) + { + /* Force reset of USART clock */ + LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_USART2); + + /* Release reset of USART clock */ + LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_USART2); + } +#endif /* USART2 */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Initialize USART registers according to the specified + * parameters in USART_InitStruct. + * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), + * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0). + * @param USARTx USART Instance + * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure + * that contains the configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers are initialized according to USART_InitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_Init(USART_TypeDef *USARTx, LL_USART_InitTypeDef *USART_InitStruct) +{ + ErrorStatus status = ERROR; + uint32_t periphclk = LL_RCC_PERIPH_FREQUENCY_NO; + LL_RCC_ClocksTypeDef rcc_clocks; + + /* Check the parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_BAUDRATE(USART_InitStruct->BaudRate)); + assert_param(IS_LL_USART_DATAWIDTH(USART_InitStruct->DataWidth)); + assert_param(IS_LL_USART_STOPBITS(USART_InitStruct->StopBits)); + assert_param(IS_LL_USART_PARITY(USART_InitStruct->Parity)); + assert_param(IS_LL_USART_DIRECTION(USART_InitStruct->TransferDirection)); + assert_param(IS_LL_USART_HWCONTROL(USART_InitStruct->HardwareFlowControl)); +#if defined(USART_CR3_OVER8) + assert_param(IS_LL_USART_OVERSAMPLING(USART_InitStruct->OverSampling)); +#endif /* USART_OverSampling_Feature */ + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /*---------------------------- USART CR1 Configuration ----------------------- + * Configure USARTx CR1 (USART Word Length, Parity, Mode and Oversampling bits) with parameters: + * - DataWidth: USART_CR1_M bits according to USART_InitStruct->DataWidth value + * - Parity: USART_CR1_PCE, USART_CR1_PS bits according to USART_InitStruct->Parity value + * - TransferDirection: USART_CR1_TE, USART_CR1_RE bits according to USART_InitStruct->TransferDirection value + * - Oversampling: USART_CR3_OVER8 bit according to USART_InitStruct->OverSampling value. + */ +#if defined(USART_CR3_OVER8) + MODIFY_REG(USARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | + USART_CR1_TE | USART_CR1_RE), + (USART_InitStruct->DataWidth | USART_InitStruct->Parity | + USART_InitStruct->TransferDirection)); + MODIFY_REG(USARTx->CR3, USART_CR3_OVER8, USART_InitStruct->OverSampling); +#else + MODIFY_REG(USARTx->CR1, + (USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | + USART_CR1_TE | USART_CR1_RE), + (USART_InitStruct->DataWidth | USART_InitStruct->Parity | + USART_InitStruct->TransferDirection)); +#endif /* USART_OverSampling_Feature */ + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Stop bits) with parameters: + * - Stop Bits: USART_CR2_STOP bits according to USART_InitStruct->StopBits value. + * - CLKEN, CPOL, CPHA and LBCL bits are to be configured using LL_USART_ClockInit(). + */ + LL_USART_SetStopBitsLength(USARTx, USART_InitStruct->StopBits); + + /*---------------------------- USART CR3 Configuration ----------------------- + * Configure USARTx CR3 (Hardware Flow Control) with parameters: + * - HardwareFlowControl: USART_CR3_RTSE, USART_CR3_CTSE bits according to USART_InitStruct->HardwareFlowControl value. + */ + LL_USART_SetHWFlowCtrl(USARTx, USART_InitStruct->HardwareFlowControl); + + /*---------------------------- USART BRR Configuration ----------------------- + * Retrieve Clock frequency used for USART Peripheral + */ + LL_RCC_GetSystemClocksFreq(&rcc_clocks); + periphclk = rcc_clocks.PCLK1_Frequency; + + /* Configure the USART Baud Rate : + - valid baud rate value (different from 0) is required + - Peripheral clock as returned by RCC service, should be valid (different from 0). + */ + if ((periphclk != LL_RCC_PERIPH_FREQUENCY_NO) + && (USART_InitStruct->BaudRate != 0U)) + { + status = SUCCESS; +#if defined(USART_CR3_OVER8) + LL_USART_SetBaudRate(USARTx, + periphclk, + USART_InitStruct->OverSampling, + USART_InitStruct->BaudRate); +#else + LL_USART_SetBaudRate(USARTx, + periphclk, + USART_InitStruct->BaudRate); +#endif /* USART_OverSampling_Feature */ + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR)); + + /* Check BRR is greater than or equal to 16d */ + assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR)); + } + } + /* Endif (=> USART not in Disabled state => return ERROR) */ + + return (status); +} + +/** + * @brief Set each @ref LL_USART_InitTypeDef field to default value. + * @param USART_InitStruct Pointer to a @ref LL_USART_InitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ + +void LL_USART_StructInit(LL_USART_InitTypeDef *USART_InitStruct) +{ + /* Set USART_InitStruct fields to default values */ + USART_InitStruct->BaudRate = 9600U; + USART_InitStruct->DataWidth = LL_USART_DATAWIDTH_8B; + USART_InitStruct->StopBits = LL_USART_STOPBITS_1; + USART_InitStruct->Parity = LL_USART_PARITY_NONE ; + USART_InitStruct->TransferDirection = LL_USART_DIRECTION_TX_RX; + USART_InitStruct->HardwareFlowControl = LL_USART_HWCONTROL_NONE; +#if defined(USART_CR3_OVER8) + USART_InitStruct->OverSampling = LL_USART_OVERSAMPLING_16; +#endif /* USART_OverSampling_Feature */ +} + +/** + * @brief Initialize USART Clock related settings according to the + * specified parameters in the USART_ClockInitStruct. + * @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0), + * USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned. + * @param USARTx USART Instance + * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure + * that contains the Clock configuration information for the specified USART peripheral. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content + * - ERROR: Problem occurred during USART Registers initialization + */ +ErrorStatus LL_USART_ClockInit(USART_TypeDef *USARTx, LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + ErrorStatus status = SUCCESS; + + /* Check USART Instance and Clock signal output parameters */ + assert_param(IS_UART_INSTANCE(USARTx)); + assert_param(IS_LL_USART_CLOCKOUTPUT(USART_ClockInitStruct->ClockOutput)); + + /* USART needs to be in disabled state, in order to be able to configure some bits in + CRx registers */ + if (LL_USART_IsEnabled(USARTx) == 0U) + { + /*---------------------------- USART CR2 Configuration -----------------------*/ + /* If Clock signal has to be output */ + if (USART_ClockInitStruct->ClockOutput == LL_USART_CLOCK_DISABLE) + { + /* Deactivate Clock signal delivery : + * - Disable Clock Output: USART_CR2_CLKEN cleared + */ + LL_USART_DisableSCLKOutput(USARTx); + } + else + { + /* Ensure USART instance is USART capable */ + assert_param(IS_USART_INSTANCE(USARTx)); + + /* Check clock related parameters */ + assert_param(IS_LL_USART_CLOCKPOLARITY(USART_ClockInitStruct->ClockPolarity)); + assert_param(IS_LL_USART_CLOCKPHASE(USART_ClockInitStruct->ClockPhase)); + assert_param(IS_LL_USART_LASTBITCLKOUTPUT(USART_ClockInitStruct->LastBitClockPulse)); + + /*---------------------------- USART CR2 Configuration ----------------------- + * Configure USARTx CR2 (Clock signal related bits) with parameters: + * - Enable Clock Output: USART_CR2_CLKEN set + * - Clock Polarity: USART_CR2_CPOL bit according to USART_ClockInitStruct->ClockPolarity value + * - Clock Phase: USART_CR2_CPHA bit according to USART_ClockInitStruct->ClockPhase value + * - Last Bit Clock Pulse Output: USART_CR2_LBCL bit according to USART_ClockInitStruct->LastBitClockPulse value. + */ + MODIFY_REG(USARTx->CR2, + USART_CR2_CLKEN | USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_LBCL, + USART_CR2_CLKEN | USART_ClockInitStruct->ClockPolarity | + USART_ClockInitStruct->ClockPhase | USART_ClockInitStruct->LastBitClockPulse); + } + } + /* Else (USART not in Disabled state => return ERROR */ + else + { + status = ERROR; + } + + return (status); +} + +/** + * @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value. + * @param USART_ClockInitStruct Pointer to a @ref LL_USART_ClockInitTypeDef structure + * whose fields will be set to default values. + * @retval None + */ +void LL_USART_ClockStructInit(LL_USART_ClockInitTypeDef *USART_ClockInitStruct) +{ + /* Set LL_USART_ClockInitStruct fields with default values */ + USART_ClockInitStruct->ClockOutput = LL_USART_CLOCK_DISABLE; + USART_ClockInitStruct->ClockPolarity = LL_USART_POLARITY_LOW; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->ClockPhase = LL_USART_PHASE_1EDGE; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ + USART_ClockInitStruct->LastBitClockPulse = LL_USART_LASTCLKPULSE_NO_OUTPUT; /* Not relevant when ClockOutput = LL_USART_CLOCK_DISABLE */ +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#endif /* USART1 || USART2 || USART3 || UART4 || UART5 */ + +/** + * @} + */ + +#endif /* USE_FULL_LL_DRIVER */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ + diff --git a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_utils.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_utils.c similarity index 96% rename from Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_utils.c rename to Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_utils.c index 4ab30a0..c996097 100755 --- a/Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_ll_utils.c +++ b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_utils.c @@ -1,506 +1,506 @@ -/** - ****************************************************************************** - * @file py32f0xx_ll_utils.c - * @author MCU Application Team - * @brief UTILS LL module driver. - ****************************************************************************** - * @attention - * - *

© Copyright (c) Puya Semiconductor Co. - * All rights reserved.

- * - *

© Copyright (c) 2016 STMicroelectronics. - * All rights reserved.

- * - * This software component is licensed by ST under BSD 3-Clause license, - * the "License"; You may not use this file except in compliance with the - * License. You may obtain a copy of the License at: - * opensource.org/licenses/BSD-3-Clause - * - ****************************************************************************** - */ -/* Includes ------------------------------------------------------------------*/ -#include "py32f0xx_ll_utils.h" -#include "py32f0xx_ll_rcc.h" -#include "py32f0xx_ll_system.h" -#ifdef USE_FULL_ASSERT - #include "py32_assert.h" -#else - #define assert_param(expr) ((void)0U) -#endif /* USE_FULL_ASSERT */ - -/** @addtogroup PY32F0xx_LL_Driver - * @{ - */ - -/** @addtogroup UTILS_LL - * @{ - */ - -/* Private types -------------------------------------------------------------*/ -/* Private variables ---------------------------------------------------------*/ -/* Private constants ---------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Private_Constants - * @{ - */ -#if defined(RCC_PLL_SUPPORT) -/* Defines used for HSE range */ -#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ -#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */ - -/* Defines used for PLL input range */ -#define LL_RCC_PLLINPUT_FREQ_MIN 16000000U /*!< Frequency min for PLL input frequency, in Hz */ -#define LL_RCC_PLLINPUT_FREQ_MAX 24000000U /*!< Frequency max for PLL input frequency, in Hz */ -#endif - -/* Defines used for FLASH latency according to HCLK Frequency */ -#define UTILS_SCALE1_LATENCY1_FREQ 24000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ -#define UTILS_SCALE1_LATENCY2_FREQ 48000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ - -/** - * @} - */ - -/* Private macros ------------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Private_Macros - * @{ - */ -#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ - || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) - -#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ - || ((__VALUE__) == LL_RCC_APB1_DIV_16)) - - -#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ - || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) - -#if defined(RCC_PLL_SUPPORT) -#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) - -#define IS_LL_UTILS_PLL_INPUT_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= LL_RCC_PLLINPUT_FREQ_MIN) && ((__FREQUENCY__) <= LL_RCC_PLLINPUT_FREQ_MAX)) -#endif - -/** - * @} - */ -#if defined(RCC_PLL_SUPPORT) - /* Private function prototypes -----------------------------------------------*/ - /** @defgroup UTILS_LL_Private_Functions UTILS Private functions - * @{ - */ - static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); - static ErrorStatus UTILS_PLL_IsBusy(void); - /** - * @} - */ -#endif -/* Exported functions --------------------------------------------------------*/ -/** @addtogroup UTILS_LL_Exported_Functions - * @{ - */ - -/** @addtogroup UTILS_LL_EF_DELAY - * @{ - */ - -/** - * @brief This function configures the Cortex-M SysTick source to have 1ms time base. - * @note When a RTOS is used, it is recommended to avoid changing the Systick - * configuration by calling this function, for a delay use rather osDelay RTOS service. - * @param HCLKFrequency HCLK frequency in Hz - * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq - * @retval None - */ -void LL_Init1msTick(uint32_t HCLKFrequency) -{ - /* Use frequency provided in argument */ - LL_InitTick(HCLKFrequency, 1000U); -} - -/** - * @brief This function provides accurate delay (in milliseconds) based - * on SysTick counter flag - * @note When a RTOS is used, it is recommended to avoid using blocking delay - * and use rather osDelay service. - * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which - * will configure Systick to 1ms - * @param Delay specifies the delay time length, in milliseconds. - * @retval None - */ -void LL_mDelay(uint32_t Delay) -{ - __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ - uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */ - /* Add this code to indicate that local variable is not used */ - ((void)tmp); - tmpDelay = Delay; - /* Add a period to guaranty minimum wait */ - if (tmpDelay < LL_MAX_DELAY) - { - tmpDelay ++; - } - - while (tmpDelay != 0U) - { - if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) - { - tmpDelay --; - } - } -} - -/** - * @} - */ - -/** @addtogroup UTILS_EF_SYSTEM - * @brief System Configuration functions - * - @verbatim - =============================================================================== - ##### System Configuration functions ##### - =============================================================================== - [..] - System, AHB and APB1 buses clocks configuration - - (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 is 48000000 Hz. - @endverbatim - @internal - Depending on the device voltage range, the maximum frequency should be - adapted accordingly: - - (++) Table 1. HCLK clock frequency. - (++) +-------------------------------------------------------+ - (++) | Latency | HCLK clock frequency (MHz) | - (++) | |-------------------------------------| - (++) | | voltage range 1 | voltage range 2 | - (++) | | 1.08V - 1.32V | 0.9 V - 1.10V | - (++) |-----------------|------------------|------------------| - (++) |0WS(1 CPU cycles)| HCLK <= 24 | HCLK <= 8 | - (++) |-----------------|------------------|------------------| - (++) |1WS(2 CPU cycles)| HCLK <= 48 | HCLK <= 16 | - (++) |-----------------|------------------|------------------| - - @endinternal - * @{ - */ - -/** - * @brief This function sets directly SystemCoreClock CMSIS variable. - * @note Variable can be calculated also through SystemCoreClockUpdate function. - * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) - * @retval None - */ -void LL_SetSystemCoreClock(uint32_t HCLKFrequency) -{ - /* HCLK clock frequency */ - SystemCoreClock = HCLKFrequency; -} -#if defined(RCC_PLL_SUPPORT) -/** - * @brief This function configures system clock with HSI as clock source of the PLL - * @note The application need to ensure that PLL is disabled. - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: configuration done - * - ERROR: frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status; - uint32_t pllfreq; - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { - /* Check if the new PLL input frequency is correct */ - if (!IS_LL_UTILS_PLL_INPUT_FREQUENCY(LL_RCC_HSI_GetFreq())) - { - /* the new PLL input frequency is error */ - return ERROR; - } - - /* Calculate the new PLL output frequency */ - pllfreq = 2 * LL_RCC_HSI_GetFreq(); - - /* Enable HSI if not enabled */ - if (LL_RCC_HSI_IsReady() != 1U) - { - LL_RCC_HSI_Enable(); - while (LL_RCC_HSI_IsReady() != 1U) - { - /* Wait for HSI ready */ - } - } - - /* Configure PLL */ - LL_RCC_PLL_SetMainSource(LL_RCC_PLLSOURCE_HSI); - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @brief This function configures system clock with HSE as clock source of the PLL - * @note The application need to ensure that PLL is disabled. - * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000 - * @param HSEBypass This parameter can be one of the following values: - * @arg @ref LL_UTILS_HSEBYPASS_ON - * @arg @ref LL_UTILS_HSEBYPASS_OFF - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Max frequency configuration done - * - ERROR: Max frequency configuration not done - */ -ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status; - uint32_t pllfreq; - - /* Check the parameters */ - assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); - assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); - - /* Check if one of the PLL is enabled */ - if (UTILS_PLL_IsBusy() == SUCCESS) - { - /* Check if the new PLL input frequency is correct */ - if (!IS_LL_UTILS_PLL_INPUT_FREQUENCY(HSEFrequency)) - { - /* the new PLL input frequency is error */ - return ERROR; - } - - /* Calculate the new PLL output frequency */ - pllfreq = HSEFrequency * 2; - - /* Enable HSE if not enabled */ - if (LL_RCC_HSE_IsReady() != 1U) - { - /* Set frequency range of the HSE */ - LL_RCC_HSE_SetFreqRegion(LL_RCC_HSE_16_32MHz); - - /* Check if need to enable HSE bypass feature or not */ - if (HSEBypass == LL_UTILS_HSEBYPASS_ON) - { - LL_RCC_HSE_EnableBypass(); - } - else - { - LL_RCC_HSE_DisableBypass(); - } - - /* Enable HSE */ - LL_RCC_HSE_Enable(); - while (LL_RCC_HSE_IsReady() != 1U) - { - /* Wait for HSE ready */ - } - } - - /* Configure PLL */ - LL_RCC_PLL_SetMainSource(LL_RCC_PLLSOURCE_HSE); - - /* Enable PLL and switch system clock to PLL */ - status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); - } - else - { - /* Current PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} -#endif - -/** - * @brief Update number of Flash wait states in line with new frequency and current - * voltage range. - * @param HCLKFrequency HCLK frequency - * @retval An ErrorStatus enumeration value: - * - SUCCESS: Latency has been modified - * - ERROR: Latency cannot be modified - */ -ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency) -{ - uint32_t timeout; - uint32_t getlatency; - uint32_t latency; - ErrorStatus status; - - /* Frequency cannot be equal to 0 or greater than max clock */ - if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)) - { - latency = 0; - status = ERROR; - } - else - { - if (HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ) - { - /* 24 < HCLK <= 48 => 1WS (2 CPU cycles) */ - latency = LL_FLASH_LATENCY_1; - } - else - { - /* else HCLKFrequency < 24MHz default LL_FLASH_LATENCY_0 0WS */ - latency = LL_FLASH_LATENCY_0; - } - } - - LL_FLASH_SetLatency(latency); - - /* Check that the new number of wait states is taken into account to access the Flash - memory by reading the FLASH_ACR register */ - timeout = 2u; - do - { - /* Wait for Flash latency to be updated */ - getlatency = LL_FLASH_GetLatency(); - timeout--; - } - while ((getlatency != latency) && (timeout > 0u)); - - if (getlatency != latency) - { - status = ERROR; - } - else - { - status = SUCCESS; - } - - return status; -} - -/** - * @} - */ - -/** - * @} - */ -#if defined(RCC_PLL_SUPPORT) -/** @addtogroup UTILS_LL_Private_Functions - * @{ - */ - -/** - * @brief Function to check that PLL can be modified - * @retval An ErrorStatus enumeration value: - * - SUCCESS: PLL modification can be done - * - ERROR: PLL is busy - */ -static ErrorStatus UTILS_PLL_IsBusy(void) -{ - ErrorStatus status = SUCCESS; - - /* Check if PLL is busy*/ - if (LL_RCC_PLL_IsReady() != 0U) - { - /* PLL configuration cannot be modified */ - status = ERROR; - } - - return status; -} - -/** - * @brief Function to enable PLL and switch system clock to PLL - * @param SYSCLK_Frequency SYSCLK frequency - * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains - * the configuration information for the BUS prescalers. - * @retval An ErrorStatus enumeration value: - * - SUCCESS: No problem to switch system to PLL - * - ERROR: Problem to switch system to PLL - */ -static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) -{ - ErrorStatus status = SUCCESS; - uint32_t hclk_frequency; - - assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); - assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); - - /* Calculate HCLK frequency */ - hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); - - /* Increasing the number of wait states because of higher CPU frequency */ - if (SystemCoreClock < hclk_frequency) - { - /* Set FLASH latency to highest latency */ - status = LL_SetFlashLatency(hclk_frequency); - } - - /* Update system clock configuration */ - if (status == SUCCESS) - { - /* Enable PLL */ - LL_RCC_PLL_Enable(); - while (LL_RCC_PLL_IsReady() != 1U) - { - /* Wait for PLL ready */ - } - - /* Sysclk activation on the main PLL */ - LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); - LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); - while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) - { - /* Wait for system clock switch to PLL */ - } - - /* Set APB1 prescaler*/ - LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); - } - - /* Decreasing the number of wait states because of lower CPU frequency */ - if (SystemCoreClock > hclk_frequency) - { - /* Set FLASH latency to lowest latency */ - status = LL_SetFlashLatency(hclk_frequency); - } - - /* Update SystemCoreClock variable */ - if (status == SUCCESS) - { - LL_SetSystemCoreClock(hclk_frequency); - } - - return status; -} -/** - * @} - */ -#endif -/** - * @} - */ - -/** - * @} - */ - -/************************ (C) COPYRIGHT Puya *****END OF FILE****/ +/** + ****************************************************************************** + * @file py32f0xx_ll_utils.c + * @author MCU Application Team + * @brief UTILS LL module driver. + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ +/* Includes ------------------------------------------------------------------*/ +#include "py32f0xx_ll_utils.h" +#include "py32f0xx_ll_rcc.h" +#include "py32f0xx_ll_system.h" +#ifdef USE_FULL_ASSERT + #include "py32_assert.h" +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + +/** @addtogroup PY32F0xx_LL_Driver + * @{ + */ + +/** @addtogroup UTILS_LL + * @{ + */ + +/* Private types -------------------------------------------------------------*/ +/* Private variables ---------------------------------------------------------*/ +/* Private constants ---------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Constants + * @{ + */ +#if defined(RCC_PLL_SUPPORT) +/* Defines used for HSE range */ +#define UTILS_HSE_FREQUENCY_MIN 4000000U /*!< Frequency min for HSE frequency, in Hz */ +#define UTILS_HSE_FREQUENCY_MAX 32000000U /*!< Frequency max for HSE frequency, in Hz */ + +/* Defines used for PLL input range */ +#define LL_RCC_PLLINPUT_FREQ_MIN 16000000U /*!< Frequency min for PLL input frequency, in Hz */ +#define LL_RCC_PLLINPUT_FREQ_MAX 24000000U /*!< Frequency max for PLL input frequency, in Hz */ +#endif + +/* Defines used for FLASH latency according to HCLK Frequency */ +#define UTILS_SCALE1_LATENCY1_FREQ 24000000U /*!< HCLK frequency to set FLASH latency 1 in power scale 1 */ +#define UTILS_SCALE1_LATENCY2_FREQ 48000000U /*!< HCLK frequency to set FLASH latency 2 in power scale 1 */ + +/** + * @} + */ + +/* Private macros ------------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Private_Macros + * @{ + */ +#define IS_LL_UTILS_SYSCLK_DIV(__VALUE__) (((__VALUE__) == LL_RCC_SYSCLK_DIV_1) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_2) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_4) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_8) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_16) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_64) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_128) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_256) \ + || ((__VALUE__) == LL_RCC_SYSCLK_DIV_512)) + +#define IS_LL_UTILS_APB1_DIV(__VALUE__) (((__VALUE__) == LL_RCC_APB1_DIV_1) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_2) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_4) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_8) \ + || ((__VALUE__) == LL_RCC_APB1_DIV_16)) + + +#define IS_LL_UTILS_HSE_BYPASS(__STATE__) (((__STATE__) == LL_UTILS_HSEBYPASS_ON) \ + || ((__STATE__) == LL_UTILS_HSEBYPASS_OFF)) + +#if defined(RCC_PLL_SUPPORT) +#define IS_LL_UTILS_HSE_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= UTILS_HSE_FREQUENCY_MIN) && ((__FREQUENCY__) <= UTILS_HSE_FREQUENCY_MAX)) + +#define IS_LL_UTILS_PLL_INPUT_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) >= LL_RCC_PLLINPUT_FREQ_MIN) && ((__FREQUENCY__) <= LL_RCC_PLLINPUT_FREQ_MAX)) +#endif + +/** + * @} + */ +#if defined(RCC_PLL_SUPPORT) + /* Private function prototypes -----------------------------------------------*/ + /** @defgroup UTILS_LL_Private_Functions UTILS Private functions + * @{ + */ + static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct); + static ErrorStatus UTILS_PLL_IsBusy(void); + /** + * @} + */ +#endif +/* Exported functions --------------------------------------------------------*/ +/** @addtogroup UTILS_LL_Exported_Functions + * @{ + */ + +/** @addtogroup UTILS_LL_EF_DELAY + * @{ + */ + +/** + * @brief This function configures the Cortex-M SysTick source to have 1ms time base. + * @note When a RTOS is used, it is recommended to avoid changing the Systick + * configuration by calling this function, for a delay use rather osDelay RTOS service. + * @param HCLKFrequency HCLK frequency in Hz + * @note HCLK frequency can be calculated thanks to RCC helper macro or function @ref LL_RCC_GetSystemClocksFreq + * @retval None + */ +void LL_Init1msTick(uint32_t HCLKFrequency) +{ + /* Use frequency provided in argument */ + LL_InitTick(HCLKFrequency, 1000U); +} + +/** + * @brief This function provides accurate delay (in milliseconds) based + * on SysTick counter flag + * @note When a RTOS is used, it is recommended to avoid using blocking delay + * and use rather osDelay service. + * @note To respect 1ms timebase, user should call @ref LL_Init1msTick function which + * will configure Systick to 1ms + * @param Delay specifies the delay time length, in milliseconds. + * @retval None + */ +void LL_mDelay(uint32_t Delay) +{ + __IO uint32_t tmp = SysTick->CTRL; /* Clear the COUNTFLAG first */ + uint32_t tmpDelay; /* MISRAC2012-Rule-17.8 */ + /* Add this code to indicate that local variable is not used */ + ((void)tmp); + tmpDelay = Delay; + /* Add a period to guaranty minimum wait */ + if (tmpDelay < LL_MAX_DELAY) + { + tmpDelay ++; + } + + while (tmpDelay != 0U) + { + if ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) != 0U) + { + tmpDelay --; + } + } +} + +/** + * @} + */ + +/** @addtogroup UTILS_EF_SYSTEM + * @brief System Configuration functions + * + @verbatim + =============================================================================== + ##### System Configuration functions ##### + =============================================================================== + [..] + System, AHB and APB1 buses clocks configuration + + (+) The maximum frequency of the SYSCLK, HCLK, PCLK1 is 48000000 Hz. + @endverbatim + @internal + Depending on the device voltage range, the maximum frequency should be + adapted accordingly: + + (++) Table 1. HCLK clock frequency. + (++) +-------------------------------------------------------+ + (++) | Latency | HCLK clock frequency (MHz) | + (++) | |-------------------------------------| + (++) | | voltage range 1 | voltage range 2 | + (++) | | 1.08V - 1.32V | 0.9 V - 1.10V | + (++) |-----------------|------------------|------------------| + (++) |0WS(1 CPU cycles)| HCLK <= 24 | HCLK <= 8 | + (++) |-----------------|------------------|------------------| + (++) |1WS(2 CPU cycles)| HCLK <= 48 | HCLK <= 16 | + (++) |-----------------|------------------|------------------| + + @endinternal + * @{ + */ + +/** + * @brief This function sets directly SystemCoreClock CMSIS variable. + * @note Variable can be calculated also through SystemCoreClockUpdate function. + * @param HCLKFrequency HCLK frequency in Hz (can be calculated thanks to RCC helper macro) + * @retval None + */ +void LL_SetSystemCoreClock(uint32_t HCLKFrequency) +{ + /* HCLK clock frequency */ + SystemCoreClock = HCLKFrequency; +} +#if defined(RCC_PLL_SUPPORT) +/** + * @brief This function configures system clock with HSI as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: configuration done + * - ERROR: frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSI(LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; + uint32_t pllfreq; + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Check if the new PLL input frequency is correct */ + if (!IS_LL_UTILS_PLL_INPUT_FREQUENCY(LL_RCC_HSI_GetFreq())) + { + /* the new PLL input frequency is error */ + return ERROR; + } + + /* Calculate the new PLL output frequency */ + pllfreq = 2 * LL_RCC_HSI_GetFreq(); + + /* Enable HSI if not enabled */ + if (LL_RCC_HSI_IsReady() != 1U) + { + LL_RCC_HSI_Enable(); + while (LL_RCC_HSI_IsReady() != 1U) + { + /* Wait for HSI ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_SetMainSource(LL_RCC_PLLSOURCE_HSI); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief This function configures system clock with HSE as clock source of the PLL + * @note The application need to ensure that PLL is disabled. + * @param HSEFrequency Value between Min_Data = 4000000 and Max_Data = 48000000 + * @param HSEBypass This parameter can be one of the following values: + * @arg @ref LL_UTILS_HSEBYPASS_ON + * @arg @ref LL_UTILS_HSEBYPASS_OFF + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Max frequency configuration done + * - ERROR: Max frequency configuration not done + */ +ErrorStatus LL_PLL_ConfigSystemClock_HSE(uint32_t HSEFrequency, uint32_t HSEBypass, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status; + uint32_t pllfreq; + + /* Check the parameters */ + assert_param(IS_LL_UTILS_HSE_FREQUENCY(HSEFrequency)); + assert_param(IS_LL_UTILS_HSE_BYPASS(HSEBypass)); + + /* Check if one of the PLL is enabled */ + if (UTILS_PLL_IsBusy() == SUCCESS) + { + /* Check if the new PLL input frequency is correct */ + if (!IS_LL_UTILS_PLL_INPUT_FREQUENCY(HSEFrequency)) + { + /* the new PLL input frequency is error */ + return ERROR; + } + + /* Calculate the new PLL output frequency */ + pllfreq = HSEFrequency * 2; + + /* Enable HSE if not enabled */ + if (LL_RCC_HSE_IsReady() != 1U) + { + /* Set frequency range of the HSE */ + LL_RCC_HSE_SetFreqRegion(LL_RCC_HSE_16_32MHz); + + /* Check if need to enable HSE bypass feature or not */ + if (HSEBypass == LL_UTILS_HSEBYPASS_ON) + { + LL_RCC_HSE_EnableBypass(); + } + else + { + LL_RCC_HSE_DisableBypass(); + } + + /* Enable HSE */ + LL_RCC_HSE_Enable(); + while (LL_RCC_HSE_IsReady() != 1U) + { + /* Wait for HSE ready */ + } + } + + /* Configure PLL */ + LL_RCC_PLL_SetMainSource(LL_RCC_PLLSOURCE_HSE); + + /* Enable PLL and switch system clock to PLL */ + status = UTILS_EnablePLLAndSwitchSystem(pllfreq, UTILS_ClkInitStruct); + } + else + { + /* Current PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} +#endif + +/** + * @brief Update number of Flash wait states in line with new frequency and current + * voltage range. + * @param HCLKFrequency HCLK frequency + * @retval An ErrorStatus enumeration value: + * - SUCCESS: Latency has been modified + * - ERROR: Latency cannot be modified + */ +ErrorStatus LL_SetFlashLatency(uint32_t HCLKFrequency) +{ + uint32_t timeout; + uint32_t getlatency; + uint32_t latency; + ErrorStatus status; + + /* Frequency cannot be equal to 0 or greater than max clock */ + if ((HCLKFrequency == 0U) || (HCLKFrequency > UTILS_SCALE1_LATENCY2_FREQ)) + { + latency = 0; + status = ERROR; + } + else + { + if (HCLKFrequency > UTILS_SCALE1_LATENCY1_FREQ) + { + /* 24 < HCLK <= 48 => 1WS (2 CPU cycles) */ + latency = LL_FLASH_LATENCY_1; + } + else + { + /* else HCLKFrequency < 24MHz default LL_FLASH_LATENCY_0 0WS */ + latency = LL_FLASH_LATENCY_0; + } + } + + LL_FLASH_SetLatency(latency); + + /* Check that the new number of wait states is taken into account to access the Flash + memory by reading the FLASH_ACR register */ + timeout = 2u; + do + { + /* Wait for Flash latency to be updated */ + getlatency = LL_FLASH_GetLatency(); + timeout--; + } + while ((getlatency != latency) && (timeout > 0u)); + + if (getlatency != latency) + { + status = ERROR; + } + else + { + status = SUCCESS; + } + + return status; +} + +/** + * @} + */ + +/** + * @} + */ +#if defined(RCC_PLL_SUPPORT) +/** @addtogroup UTILS_LL_Private_Functions + * @{ + */ + +/** + * @brief Function to check that PLL can be modified + * @retval An ErrorStatus enumeration value: + * - SUCCESS: PLL modification can be done + * - ERROR: PLL is busy + */ +static ErrorStatus UTILS_PLL_IsBusy(void) +{ + ErrorStatus status = SUCCESS; + + /* Check if PLL is busy*/ + if (LL_RCC_PLL_IsReady() != 0U) + { + /* PLL configuration cannot be modified */ + status = ERROR; + } + + return status; +} + +/** + * @brief Function to enable PLL and switch system clock to PLL + * @param SYSCLK_Frequency SYSCLK frequency + * @param UTILS_ClkInitStruct pointer to a @ref LL_UTILS_ClkInitTypeDef structure that contains + * the configuration information for the BUS prescalers. + * @retval An ErrorStatus enumeration value: + * - SUCCESS: No problem to switch system to PLL + * - ERROR: Problem to switch system to PLL + */ +static ErrorStatus UTILS_EnablePLLAndSwitchSystem(uint32_t SYSCLK_Frequency, LL_UTILS_ClkInitTypeDef *UTILS_ClkInitStruct) +{ + ErrorStatus status = SUCCESS; + uint32_t hclk_frequency; + + assert_param(IS_LL_UTILS_SYSCLK_DIV(UTILS_ClkInitStruct->AHBCLKDivider)); + assert_param(IS_LL_UTILS_APB1_DIV(UTILS_ClkInitStruct->APB1CLKDivider)); + + /* Calculate HCLK frequency */ + hclk_frequency = __LL_RCC_CALC_HCLK_FREQ(SYSCLK_Frequency, UTILS_ClkInitStruct->AHBCLKDivider); + + /* Increasing the number of wait states because of higher CPU frequency */ + if (SystemCoreClock < hclk_frequency) + { + /* Set FLASH latency to highest latency */ + status = LL_SetFlashLatency(hclk_frequency); + } + + /* Update system clock configuration */ + if (status == SUCCESS) + { + /* Enable PLL */ + LL_RCC_PLL_Enable(); + while (LL_RCC_PLL_IsReady() != 1U) + { + /* Wait for PLL ready */ + } + + /* Sysclk activation on the main PLL */ + LL_RCC_SetAHBPrescaler(UTILS_ClkInitStruct->AHBCLKDivider); + LL_RCC_SetSysClkSource(LL_RCC_SYS_CLKSOURCE_PLL); + while (LL_RCC_GetSysClkSource() != LL_RCC_SYS_CLKSOURCE_STATUS_PLL) + { + /* Wait for system clock switch to PLL */ + } + + /* Set APB1 prescaler*/ + LL_RCC_SetAPB1Prescaler(UTILS_ClkInitStruct->APB1CLKDivider); + } + + /* Decreasing the number of wait states because of lower CPU frequency */ + if (SystemCoreClock > hclk_frequency) + { + /* Set FLASH latency to lowest latency */ + status = LL_SetFlashLatency(hclk_frequency); + } + + /* Update SystemCoreClock variable */ + if (status == SUCCESS) + { + LL_SetSystemCoreClock(hclk_frequency); + } + + return status; +} +/** + * @} + */ +#endif +/** + * @} + */ + +/** + * @} + */ + +/************************ (C) COPYRIGHT Puya *****END OF FILE****/ diff --git a/Makefile b/Makefile index 4323dd2..bcdca8b 100644 --- a/Makefile +++ b/Makefile @@ -7,6 +7,8 @@ BUILD_DIR = Build ##### Options ##### +# Use LL library instead of HAL +USE_LL_LIB ?= y # Enable printf float %f support, y:yes, n:no ENABLE_PRINTF_FLOAT ?= n # Build with CMSIS DSP functions, y:yes, n:no @@ -39,9 +41,7 @@ LIB_FLAGS = PY32F003x8 # C source folders CDIRS := User \ - Libraries/CMSIS/Device/PY32F0xx/Source \ - Libraries/PY32F0xx_HAL_Driver/Src \ - Libraries/BSP/Src + Libraries/CMSIS/Device/PY32F0xx/Source # C source files (if there are any single ones) CFILES := @@ -53,10 +53,20 @@ AFILES := Libraries/CMSIS/Device/PY32F0xx/Source/gcc/startup_py32f003.s # Include paths INCLUDES := Libraries/CMSIS/Include \ Libraries/CMSIS/Device/PY32F0xx/Include \ - Libraries/PY32F0xx_HAL_Driver/Inc \ - Libraries/BSP/Inc \ User +ifeq ($(USE_LL_LIB),y) +CDIRS += Libraries/PY32F0xx_LL_Driver/Src \ + Libraries/BSP_LL/Src +INCLUDES += Libraries/PY32F0xx_LL_Driver/Inc \ + Libraries/BSP_LL/Inc +else +CDIRS += Libraries/PY32F0xx_HAL_Driver/Src \ + Libraries/BSP/Src +INCLUDES += Libraries/PY32F0xx_HAL_Driver/Inc \ + Libraries/BSP/Inc +endif + ifeq ($(USE_DSP),y) LIB_FLAGS += ARM_MATH_CM0PLUS CDIRS += Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions \