From feb38b5b41f55da04673e6dd8193f0c14cb0fb73 Mon Sep 17 00:00:00 2001 From: IOsetting Date: Wed, 11 Jan 2023 23:45:54 +0800 Subject: [PATCH] chore: bump to dfp.1.1.3 --- Docs/PY32F003 Reference manual v1.1.pdf | Bin Docs/PY32F003 datasheet 105℃ Rev.1.0_EN.pdf | Bin Docs/PY32F003 datasheet Rev.1.2_EN.pdf | Bin ...Y32F030 Reference manual v1.1_EN_Final.pdf | Bin Docs/PY32F030 datasheet 105℃ Rev.1.0_EN.pdf | Bin Docs/PY32F030 datasheet Rev.1.4_EN.pdf | Bin .../Raw/ADC/ContinuousConversion_DMA/main.c | 0 .../py32f0xx_hal_conf.h | 0 .../py32f0xx_hal_msp.c | 0 .../ContinuousConversion_DMA/py32f0xx_it.c | 0 .../ContinuousConversion_DMA/py32f0xx_it.h | 0 .../SingleConversion_TriggerTimer_IT/main.c | 0 .../py32f0xx_hal_conf.h | 0 .../py32f0xx_hal_msp.c | 0 .../py32f0xx_it.c | 0 .../py32f0xx_it.h | 0 Examples/Raw/DSP/Matrix_Calc/main.c | 0 .../Raw/DSP/Matrix_Calc/py32f0xx_hal_conf.h | 0 .../Raw/DSP/Matrix_Calc/py32f0xx_hal_msp.c | 0 Examples/Raw/DSP/Matrix_Calc/py32f0xx_it.c | 0 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Bin .../Devices/Puya/PY32F072xx_OPT.FLM | Bin Misc/{ => Flash}/Devices/Puya/PY32F0xx_16.FLM | Bin Misc/{ => Flash}/Devices/Puya/PY32F0xx_20.FLM | Bin Misc/{ => Flash}/Devices/Puya/PY32F0xx_32.FLM | Bin Misc/{ => Flash}/Devices/Puya/PY32F0xx_48.FLM | Bin Misc/{ => Flash}/Devices/Puya/PY32F0xx_64.FLM | Bin Misc/{ => Flash}/Devices/Puya/PY32F0xx_8.FLM | Bin .../{ => Flash}/Devices/Puya/PY32F0xx_OPT.FLM | Bin Misc/Flash/Sources/PY32F072xx/FlashDev.c | 175 + Misc/Flash/Sources/PY32F072xx/FlashOS.h | 84 + Misc/Flash/Sources/PY32F072xx/FlashPrg.c | 452 + .../Sources/PY32F072xx/PY32F072xx.uvoptx | 1254 + .../Sources/PY32F072xx/PY32F072xx.uvprojx | 2789 ++ Misc/Flash/Sources/PY32F072xx/Target.lin | 22 + Misc/Flash/Sources/PY32F0xx/FlashDev.c | 175 + Misc/Flash/Sources/PY32F0xx/FlashOS.h | 84 + Misc/Flash/Sources/PY32F0xx/FlashPrg.c | 542 + Misc/Flash/Sources/PY32F0xx/PY32F0xx.uvoptx | 1205 + Misc/Flash/Sources/PY32F0xx/PY32F0xx.uvprojx | 2782 ++ Misc/Flash/Sources/PY32F0xx/Target.lin | 22 + Misc/JLinkDevices.xml | 0 ....1.0.pack => Puya.PY32F0xx_DFP.1.1.3.pack} | Bin 20200643 -> 20256080 bytes Misc/{ => SVD}/py32f002axx.svd | 15685 +++--- Misc/SVD/py32f002xx.svd | 7953 +++ Misc/{ => SVD}/py32f003xx.svd | 22178 ++++----- Misc/{ => SVD}/py32f030xx.svd | 23164 ++++----- Misc/{ => SVD}/py32f072xx.svd | 40502 ++++++++-------- README.md | 28 +- 501 files changed, 80959 insertions(+), 50719 deletions(-) mode change 100755 => 100644 Docs/PY32F003 Reference manual v1.1.pdf mode change 100755 => 100644 Docs/PY32F003 datasheet 105℃ Rev.1.0_EN.pdf mode change 100755 => 100644 Docs/PY32F003 datasheet Rev.1.2_EN.pdf mode change 100755 => 100644 Docs/PY32F030 Reference manual v1.1_EN_Final.pdf mode change 100755 => 100644 Docs/PY32F030 datasheet 105℃ Rev.1.0_EN.pdf mode change 100755 => 100644 Docs/PY32F030 datasheet Rev.1.4_EN.pdf mode change 100755 => 100644 Examples/Raw/ADC/ContinuousConversion_DMA/main.c mode change 100755 => 100644 Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_hal_conf.h mode change 100755 => 100644 Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_hal_msp.c mode change 100755 => 100644 Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_it.c mode change 100755 => 100644 Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_it.h mode change 100755 => 100644 Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/main.c mode change 100755 => 100644 Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_hal_conf.h mode change 100755 => 100644 Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_hal_msp.c mode change 100755 => 100644 Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_it.c mode change 100755 => 100644 Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_it.h mode change 100755 => 100644 Examples/Raw/DSP/Matrix_Calc/main.c mode change 100755 => 100644 Examples/Raw/DSP/Matrix_Calc/py32f0xx_hal_conf.h mode change 100755 => 100644 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mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f64.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f64.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_stereo_df2T_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_opt_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_opt_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_opt_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_opt_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_opt_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_opt_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_cmplx_mult_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f64.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c mode change 100755 => 100644 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Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c mode change 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100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c mode change 100755 => 100644 Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c mode change 100755 => 100644 Libraries/CMSIS/Device/PY32F0xx/Include/py32f002ax5.h create mode 100644 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Libraries/CMSIS/Device/PY32F0xx/Include/py32f030xx.h create mode 100644 Libraries/CMSIS/Device/PY32F0xx/Include/py32f072xB.h mode change 100755 => 100644 Libraries/CMSIS/Device/PY32F0xx/Include/py32f0xx.h create mode 100644 Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f003xx.h create mode 100644 Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f030xx.h create mode 100644 Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f072xx.h mode change 100755 => 100644 Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f0xx.h mode change 100755 => 100644 Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f002ax5.s create mode 100644 Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f002x5.s mode change 100755 => 100644 Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x4.s mode change 100755 => 100644 Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x6.s mode change 100755 => 100644 Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x8.s mode change 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100644 Libraries/CMSIS/Include/arm_const_structs.h mode change 100755 => 100644 Libraries/CMSIS/Include/arm_math.h mode change 100755 => 100644 Libraries/CMSIS/Include/cmsis_armcc.h mode change 100755 => 100644 Libraries/CMSIS/Include/cmsis_armcc_V6.h mode change 100755 => 100644 Libraries/CMSIS/Include/cmsis_gcc.h mode change 100755 => 100644 Libraries/CMSIS/Include/core_cm0.h mode change 100755 => 100644 Libraries/CMSIS/Include/core_cm0plus.h mode change 100755 => 100644 Libraries/CMSIS/Include/core_cm3.h mode change 100755 => 100644 Libraries/CMSIS/Include/core_cm4.h mode change 100755 => 100644 Libraries/CMSIS/Include/core_cm7.h mode change 100755 => 100644 Libraries/CMSIS/Include/core_cmFunc.h mode change 100755 => 100644 Libraries/CMSIS/Include/core_cmInstr.h mode change 100755 => 100644 Libraries/CMSIS/Include/core_cmSimd.h mode change 100755 => 100644 Libraries/CMSIS/Include/core_sc000.h mode change 100755 => 100644 Libraries/CMSIS/Include/core_sc300.h mode change 100755 => 100644 Libraries/CMSIS/RTOS/Template/cmsis_os.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_adc.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_adc_ex.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_comp.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_cortex.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_crc.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_def.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_dma.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_dma_ex.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_exti.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_flash.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_flash_ex.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_gpio.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_gpio_ex.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_i2c.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_irda.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_iwdg.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_led.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_lptim.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_pwr.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_rcc.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_rcc_ex.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_rtc.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_rtc_ex.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_spi.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_tim.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_tim_ex.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_uart.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_usart.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_wwdg.h mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_adc.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_adc_ex.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_comp.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_cortex.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_crc.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_dma.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_exti.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_flash.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_gpio.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_i2c.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_irda.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_iwdg.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_led.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_lptim.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_pwr.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_rcc.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_rcc_ex.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_rtc.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_rtc_ex.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_spi.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_tim.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_tim_ex.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_uart.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_usart.c mode change 100755 => 100644 Libraries/PY32F0xx_HAL_Driver/Src/py32f0xx_hal_wwdg.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_adc.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_bus.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_comp.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_cortex.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_crc.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_dma.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_exti.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_gpio.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_i2c.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_iwdg.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_led.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_lptim.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_pwr.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_rcc.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_rtc.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_spi.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_system.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_tim.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_usart.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_utils.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Inc/py32f0xx_ll_wwdg.h mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_adc.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_comp.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_crc.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_dma.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_exti.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_gpio.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_i2c.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_led.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_lptim.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_pwr.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_rcc.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_rtc.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_spi.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_tim.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_usart.c mode change 100755 => 100644 Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_utils.c rename Misc/{ => Flash}/Devices/Puya/PY32F003xx_16.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F003xx_32.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F003xx_64.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F003xx_OPT.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F030xx_16.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F030xx_32.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F030xx_48.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F030xx_64.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F030xx_8.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F030xx_OPT.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F072xx_128.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F072xx_OPT.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F0xx_16.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F0xx_20.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F0xx_32.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F0xx_48.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F0xx_64.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F0xx_8.FLM (100%) rename Misc/{ => Flash}/Devices/Puya/PY32F0xx_OPT.FLM (100%) create mode 100644 Misc/Flash/Sources/PY32F072xx/FlashDev.c create mode 100644 Misc/Flash/Sources/PY32F072xx/FlashOS.h create mode 100644 Misc/Flash/Sources/PY32F072xx/FlashPrg.c create mode 100644 Misc/Flash/Sources/PY32F072xx/PY32F072xx.uvoptx create mode 100644 Misc/Flash/Sources/PY32F072xx/PY32F072xx.uvprojx create mode 100644 Misc/Flash/Sources/PY32F072xx/Target.lin create mode 100644 Misc/Flash/Sources/PY32F0xx/FlashDev.c create mode 100644 Misc/Flash/Sources/PY32F0xx/FlashOS.h create mode 100644 Misc/Flash/Sources/PY32F0xx/FlashPrg.c create mode 100644 Misc/Flash/Sources/PY32F0xx/PY32F0xx.uvoptx create mode 100644 Misc/Flash/Sources/PY32F0xx/PY32F0xx.uvprojx create mode 100644 Misc/Flash/Sources/PY32F0xx/Target.lin mode change 100755 => 100644 Misc/JLinkDevices.xml rename Misc/{Puya.PY32F0xx_DFP.1.1.0.pack => Puya.PY32F0xx_DFP.1.1.3.pack} (99%) mode change 100755 => 100644 rename Misc/{ => SVD}/py32f002axx.svd (96%) create mode 100644 Misc/SVD/py32f002xx.svd rename Misc/{ => SVD}/py32f003xx.svd (96%) rename Misc/{ => SVD}/py32f030xx.svd (96%) rename Misc/{ => SVD}/py32f072xx.svd (96%) diff --git a/Docs/PY32F003 Reference manual v1.1.pdf b/Docs/PY32F003 Reference manual v1.1.pdf old mode 100755 new mode 100644 diff --git a/Docs/PY32F003 datasheet 105℃ Rev.1.0_EN.pdf b/Docs/PY32F003 datasheet 105℃ Rev.1.0_EN.pdf old mode 100755 new mode 100644 diff --git a/Docs/PY32F003 datasheet Rev.1.2_EN.pdf b/Docs/PY32F003 datasheet Rev.1.2_EN.pdf old mode 100755 new mode 100644 diff --git a/Docs/PY32F030 Reference manual v1.1_EN_Final.pdf b/Docs/PY32F030 Reference manual v1.1_EN_Final.pdf old mode 100755 new mode 100644 diff --git a/Docs/PY32F030 datasheet 105℃ Rev.1.0_EN.pdf b/Docs/PY32F030 datasheet 105℃ Rev.1.0_EN.pdf old mode 100755 new mode 100644 diff --git a/Docs/PY32F030 datasheet Rev.1.4_EN.pdf b/Docs/PY32F030 datasheet Rev.1.4_EN.pdf old mode 100755 new mode 100644 diff --git a/Examples/Raw/ADC/ContinuousConversion_DMA/main.c b/Examples/Raw/ADC/ContinuousConversion_DMA/main.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_hal_conf.h b/Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_hal_conf.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_hal_msp.c b/Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_hal_msp.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_it.c b/Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_it.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_it.h b/Examples/Raw/ADC/ContinuousConversion_DMA/py32f0xx_it.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/main.c b/Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/main.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_hal_conf.h b/Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_hal_conf.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_hal_msp.c b/Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_hal_msp.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_it.c b/Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_it.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_it.h b/Examples/Raw/ADC/SingleConversion_TriggerTimer_IT/py32f0xx_it.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/DSP/Matrix_Calc/main.c b/Examples/Raw/DSP/Matrix_Calc/main.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/DSP/Matrix_Calc/py32f0xx_hal_conf.h b/Examples/Raw/DSP/Matrix_Calc/py32f0xx_hal_conf.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/DSP/Matrix_Calc/py32f0xx_hal_msp.c b/Examples/Raw/DSP/Matrix_Calc/py32f0xx_hal_msp.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/DSP/Matrix_Calc/py32f0xx_it.c b/Examples/Raw/DSP/Matrix_Calc/py32f0xx_it.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/DSP/Matrix_Calc/py32f0xx_it.h b/Examples/Raw/DSP/Matrix_Calc/py32f0xx_it.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/GPIO/LED_Toggle/main.c b/Examples/Raw/GPIO/LED_Toggle/main.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/GPIO/LED_Toggle/py32f0xx_hal_conf.h b/Examples/Raw/GPIO/LED_Toggle/py32f0xx_hal_conf.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/GPIO/LED_Toggle/py32f0xx_hal_msp.c b/Examples/Raw/GPIO/LED_Toggle/py32f0xx_hal_msp.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/GPIO/LED_Toggle/py32f0xx_it.c b/Examples/Raw/GPIO/LED_Toggle/py32f0xx_it.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/GPIO/LED_Toggle/py32f0xx_it.h b/Examples/Raw/GPIO/LED_Toggle/py32f0xx_it.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSE_ClockConfigurate/main.c b/Examples/Raw/RCC/HSE_ClockConfigurate/main.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSE_ClockConfigurate/py32f0xx_hal_conf.h b/Examples/Raw/RCC/HSE_ClockConfigurate/py32f0xx_hal_conf.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSE_ClockConfigurate/py32f0xx_hal_msp.c b/Examples/Raw/RCC/HSE_ClockConfigurate/py32f0xx_hal_msp.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSE_ClockConfigurate/py32f0xx_it.c b/Examples/Raw/RCC/HSE_ClockConfigurate/py32f0xx_it.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSE_ClockConfigurate/py32f0xx_it.h b/Examples/Raw/RCC/HSE_ClockConfigurate/py32f0xx_it.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSE_PLL_ClockConfigurate/main.c b/Examples/Raw/RCC/HSE_PLL_ClockConfigurate/main.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSE_PLL_ClockConfigurate/py32f0xx_hal_conf.h b/Examples/Raw/RCC/HSE_PLL_ClockConfigurate/py32f0xx_hal_conf.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSE_PLL_ClockConfigurate/py32f0xx_hal_msp.c b/Examples/Raw/RCC/HSE_PLL_ClockConfigurate/py32f0xx_hal_msp.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSE_PLL_ClockConfigurate/py32f0xx_it.c b/Examples/Raw/RCC/HSE_PLL_ClockConfigurate/py32f0xx_it.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSE_PLL_ClockConfigurate/py32f0xx_it.h b/Examples/Raw/RCC/HSE_PLL_ClockConfigurate/py32f0xx_it.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSI_ClockConfigurate/main.c b/Examples/Raw/RCC/HSI_ClockConfigurate/main.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSI_ClockConfigurate/py32f0xx_hal_conf.h b/Examples/Raw/RCC/HSI_ClockConfigurate/py32f0xx_hal_conf.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSI_ClockConfigurate/py32f0xx_hal_msp.c b/Examples/Raw/RCC/HSI_ClockConfigurate/py32f0xx_hal_msp.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSI_ClockConfigurate/py32f0xx_it.c b/Examples/Raw/RCC/HSI_ClockConfigurate/py32f0xx_it.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSI_ClockConfigurate/py32f0xx_it.h b/Examples/Raw/RCC/HSI_ClockConfigurate/py32f0xx_it.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSI_PLL_Output/main.c b/Examples/Raw/RCC/HSI_PLL_Output/main.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSI_PLL_Output/py32f0xx_hal_conf.h b/Examples/Raw/RCC/HSI_PLL_Output/py32f0xx_hal_conf.h old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSI_PLL_Output/py32f0xx_hal_msp.c b/Examples/Raw/RCC/HSI_PLL_Output/py32f0xx_hal_msp.c old mode 100755 new mode 100644 diff --git a/Examples/Raw/RCC/HSI_PLL_Output/py32f0xx_it.c b/Examples/Raw/RCC/HSI_PLL_Output/py32f0xx_it.c old mode 100755 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a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c old mode 100755 new mode 100644 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b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c b/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c b/Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c b/Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_const_structs.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c 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a/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c b/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c b/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c b/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c b/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c b/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c b/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c b/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c old mode 100755 new mode 100644 diff --git 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b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c b/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c old mode 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b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c b/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_bitreversal.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q15.c b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix2_f32.c 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b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_fast_f32.c old mode 100755 new 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a/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c b/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Device/PY32F0xx/Include/py32f002ax5.h b/Libraries/CMSIS/Device/PY32F0xx/Include/py32f002ax5.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Device/PY32F0xx/Include/py32f002x5.h b/Libraries/CMSIS/Device/PY32F0xx/Include/py32f002x5.h new file mode 100644 index 0000000..510b7b8 --- /dev/null +++ b/Libraries/CMSIS/Device/PY32F0xx/Include/py32f002x5.h @@ -0,0 +1,3860 @@ +/** + ****************************************************************************** + * @file py32f002x5.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. + * This file contains all the peripheral register's definitions, bits + * definitions and memory mapping for PY32F0xx devices. + * @version v1.0.1 + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup py32f002x5 + * @{ + */ + +#ifndef __PY32F002X5_H +#define __PY32F002X5_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< PY32F0xx do not provide MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< PY32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief PY32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ + /****** Cortex-M0+ Processor Exceptions Numbers *************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** PY32F0 specific Interrupt Numbers *******************************************************************/ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_IRQn = 4, /*!< RCC global Interrupt */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + ADC_IRQn = 12, /*!< ADC Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM6_LPTIM1_IRQn = 17, /*!< TIM6 LPTIM1 global Interrupts */ + I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ + SPI1_IRQn = 25, /*!< SPI1 Interrupt */ + USART1_IRQn = 27, /*!< USART1 Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_py32f0xx.h" /* PY32F0xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** + * @brief Analog to Digital Converter + */ +typedef struct +{ + __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ + __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ + __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ + __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ + __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ + uint32_t RESERVED1[2]; /*!< Reserved, 0x18-0x1C */ + __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ + uint32_t RESERVED2; /*!< Reserved, 0x24 */ + __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ + uint32_t RESERVED3[5]; /*!< Reserved, 0x2C */ + __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ + __IO uint32_t CCSR; /*!< ADC calibration configuration&status register Address offset: 0x44 */ +} ADC_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ +} ADC_Common_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBGMCU_TypeDef; + + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t PR; /*!< EXTI Pending Register 1 Address offset: 0x0C */ + __IO uint32_t RESERVED1[4]; /*!< Reserved 1, 0x10 -- 0x1C */ + __IO uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ + __IO uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ + __IO uint32_t EXTICR[2]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x68 */ + __IO uint32_t RESERVED4[6]; /*!< Reserved 5, 0x6C -- 0x7C */ + __IO uint32_t IMR; /*!< EXTI Interrupt Mask Register , Address offset: 0x80 */ + __IO uint32_t EMR; /*!< EXTI Event Mask Register , Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + __IO uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + __IO uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18-0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t SDKR; /*!< FLASH SDK address register, Address offset: 0x24 */ + __IO uint32_t BTCR; /*!< desc BTCR, Address offset: 0x28 */ + __IO uint32_t WRPR; /*!< FLASH WRP address register, Address offset: 0x2C */ + __IO uint32_t RESERVED3[(0x90 - 0x2C) / 4 - 1]; + __IO uint32_t STCR; /*!< FLASH sleep time config register, Address offset: 0x90 */ + __IO uint32_t RESERVED4[(0x100 - 0x90) / 4 - 1]; + __IO uint32_t TS0; /*!< FLASH TS0 register, Address offset: 0x100 */ + __IO uint32_t TS1; /*!< FLASH TS1 register, Address offset: 0x104 */ + __IO uint32_t TS2P; /*!< FLASH TS2P register, Address offset: 0x108 */ + __IO uint32_t TPS3; /*!< FLASH TPS3 register, Address offset: 0x10C */ + __IO uint32_t TS3; /*!< FLASH TS3 register, Address offset: 0x110 */ + __IO uint32_t PERTPE; /*!< FLASH PERTPE register, Address offset: 0x114 */ + __IO uint32_t SMERTPE; /*!< FLASH SMERTPE register, Address offset: 0x118 */ + __IO uint32_t PRGTPE; /*!< FLASH PRGTPE register, Address offset: 0x11C */ + __IO uint32_t PRETPE; /*!< FLASH PRETPE register, Address offset: 0x120 */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes + */ +typedef struct +{ + __IO uint8_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ + __IO uint8_t USER; /*!< FLASH option byte user options, Address offset: 0x01 */ + __IO uint8_t nRDP; /*!< Complemented FLASH option byte Read protection,Address offset: 0x02 */ + __IO uint8_t nUSER; /*!< Complemented FLASH option byte user options, Address offset: 0x03 */ + __IO uint8_t SDK_STRT; /*!< SDK area start address(stored in SDK[4:0]), Address offset: 0x04 */ + __IO uint8_t SDK_END; /*!< SDK area end address(stored in SDK[12:8]), Address offset: 0x05 */ + __IO uint8_t nSDK_STRT; /*!< Complemented SDK area start address, Address offset: 0x06 */ + __IO uint8_t nSDK_END; /*!< Complemented SDK area end address, Address offset: 0x07 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x08 */ + __IO uint16_t WRP; /*!< FLASH option byte write protection, Address offset: 0x0C */ + __IO uint16_t nWRP; /*!< Complemented FLASH option byte write protection,Address offset: 0x0E */ +} OB_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** + * @brief Inter-integrated Circuit Interface + */ +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t OAR1; + __IO uint32_t OAR2; + __IO uint32_t DR; + __IO uint32_t SR1; + __IO uint32_t SR2; + __IO uint32_t CCR; + __IO uint32_t TRISE; +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ + //__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ +} IWDG_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ +} LPTIM_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ + __IO uint32_t ECSCR; /*!< RCC External clock source control register, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + __IO uint32_t RESERVED2[4];/*!< Reserved, Address offset: 0x44-0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** + * @brief Serial Peripheral Interface + */ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI desc CR1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI desc CR2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI desc SR, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI desc DR, Address offset: 0x0C */ + // __IO uint32_t CRCPR; /*!< SPI desc CRCPR, Address offset: 0x10 */ + // __IO uint32_t RXCRCR; /*!< SPI desc RXCRCR, Address offset: 0x14 */ + // __IO uint32_t TXCRCR; /*!< SPI desc TXCRCR, Address offset: 0x18 */ + // __IO uint32_t I2SCFGR; /*!< SPI desc I2SCFGR, Address offset: 0x1C */ + // __IO uint32_t I2SPR; /*!< SPI desc I2SPR, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ + __IO uint32_t RESERVED1[5]; /*!< Reserved, Address offset: 0x04 - 0x14 */ + __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ + __IO uint32_t GPIO_ENS; /*!< GPIO Filter Enable, Address offset: 0x1C */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ +// __IO uint32_t RESERVED[2]; /*!< Reserved, Address offset: 0x48 - 0x4F */ +// __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register , Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ +} USART_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define FLASH_END (0x08004FFFUL) /*!< FLASH end address */ +#define FLASH_SIZE (FLASH_END - FLASH_BASE + 1) +#define FLASH_PAGE_SIZE 0x00000080U /*!< FLASH Page Size, 128 Bytes */ +#define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) +#define FLASH_SECTOR_SIZE 0x00001000U /*!< FLASH Sector Size, 4096 Bytes */ +#define FLASH_SECTOR_NB (FLASH_SIZE / FLASH_SECTOR_SIZE) +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define SRAM_END (0x20000BFFUL) /*!< SRAM end address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define I2C_BASE (APBPERIPH_BASE + 0x00005400UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define LPTIM_BASE (APBPERIPH_BASE + 0x00007C00UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) + + +/*!< AHB peripherals */ +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ +#define OB_BASE 0x1FFF0E80UL /*!< FLASH Option Bytes base address */ +#define FLASHSIZE_BASE 0x1FFF0FFCUL /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFF0E00UL /*!< Unique device ID register base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define I2C1 ((I2C_TypeDef *) I2C_BASE) +#define I2C ((I2C_TypeDef *) I2C_BASE) /* Kept for legacy purpose */ +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM_BASE) +#define LPTIM ((LPTIM_TypeDef *) LPTIM_BASE) /* Kept for legacy purpose */ +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) +#define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */ +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for ADC_ISR register ******************/ +#define ADC_ISR_EOSMP_Pos (1U) +#define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ +#define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ +#define ADC_ISR_EOC_Pos (2U) +#define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ +#define ADC_ISR_EOSEQ_Pos (3U) +#define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ +#define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< ADC group regular end of sequence conversions flag */ +#define ADC_ISR_OVR_Pos (4U) +#define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ +#define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ +#define ADC_ISR_AWD_Pos (7U) +#define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ +#define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< ADC analog watchdog 1 flag */ + +/******************** Bits definition for ADC_IER register ******************/ +#define ADC_IER_EOSMPIE_Pos (1U) +#define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ +#define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ +#define ADC_IER_EOCIE_Pos (2U) +#define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ +#define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ +#define ADC_IER_EOSEQIE_Pos (3U) +#define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ +#define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ +#define ADC_IER_OVRIE_Pos (4U) +#define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ +#define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ +#define ADC_IER_AWDIE_Pos (7U) +#define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ +#define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ + +/******************** Bits definition for ADC_CR register *******************/ +#define ADC_CR_ADEN_Pos (0U) +#define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ +#define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ +#define ADC_CR_ADDIS_Pos (1U) +#define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */ +#define ADC_CR_ADDIS ADC_CR_ADDIS_Msk +#define ADC_CR_ADSTART_Pos (2U) +#define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ +#define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ +#define ADC_CR_ADSTP_Pos (4U) +#define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ +#define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_VREF_BUFFERE_Pos (5U) +#define ADC_CR_VREF_BUFFERE_Msk (0x1UL << ADC_CR_VREF_BUFFERE_Pos) /*!< 0x00000020 */ +#define ADC_CR_VREF_BUFFERE ADC_CR_VREF_BUFFERE_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_VERBUFF_SEL_Pos (6U) +#define ADC_CR_VERBUFF_SEL_Msk (0x3UL << ADC_CR_VERBUFF_SEL_Pos) /*!< 0x000000C0 */ +#define ADC_CR_VERBUFF_SEL ADC_CR_VERBUFF_SEL_Msk /*!< ADC group regular conversion stop */ +#define ADC_CR_ADCAL_Pos (31U) +#define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_VREF_BUFFERE_Pos) /*!< 0x80000000 */ +#define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ + +/******************* Bits definition for ADC_CFGR1 register *****************/ +#define ADC_CFGR1_SCANDIR_Pos (2U) +#define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ +#define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ +#define ADC_CFGR1_RESSEL_Pos (3U) +#define ADC_CFGR1_RESSEL_Msk (0x3UL << ADC_CFGR1_RESSEL_Pos) /*!< 0x00000018 */ +#define ADC_CFGR1_RESSEL ADC_CFGR1_RESSEL_Msk /*!< ADC data resolution */ +#define ADC_CFGR1_RESSEL_0 (0x1UL << ADC_CFGR1_RESSEL_Pos) /*!< 0x00000008 */ +#define ADC_CFGR1_RESSEL_1 (0x2UL << ADC_CFGR1_RESSEL_Pos) /*!< 0x00000010 */ +#define ADC_CFGR1_ALIGN_Pos (5U) +#define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ +#define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ +#define ADC_CFGR1_EXTSEL_Pos (6U) +#define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ +#define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ +#define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ +#define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ +#define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ +#define ADC_CFGR1_EXTEN_Pos (10U) +#define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ +#define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ +#define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ +#define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ +#define ADC_CFGR1_OVRMOD_Pos (12U) +#define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ +#define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ +#define ADC_CFGR1_CONT_Pos (13U) +#define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ +#define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ +#define ADC_CFGR1_WAIT_Pos (14U) +#define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ +#define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ +#define ADC_CFGR1_DISCEN_Pos (16U) +#define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ +#define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ +#define ADC_CFGR1_AWDSGL_Pos (22U) +#define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ +#define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ +#define ADC_CFGR1_AWDEN_Pos (23U) +#define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ +#define ADC_CFGR1_AWDCH_Pos (26U) +#define ADC_CFGR1_AWDCH_Msk (0xFUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x2C000000 */ +#define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ +#define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ +#define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ +#define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ +#define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ + +/******************* Bits definition for ADC_CFGR2 register *****************/ +#define ADC_CFGR2_CKMODE_Pos (28U) +#define ADC_CFGR2_CKMODE_Msk (0xFUL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ +#define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ +#define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x10000000 */ +#define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x20000000 */ +#define ADC_CFGR2_CKMODE_2 (0x4UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ +#define ADC_CFGR2_CKMODE_3 (0x8UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ + +/****************** Bit definition for ADC_SMPR register ********************/ +#define ADC_SMPR_SMP_Pos (0U) +#define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ +#define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ +#define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ +#define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ +#define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ + +/******************* Bit definition for ADC_TR register ********************/ +#define ADC_TR_LT_Pos (0U) +#define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_TR_LT ADC_TR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ +#define ADC_TR_LT_0 (0x001UL << ADC_TR_LT_Pos) /*!< 0x00000001 */ +#define ADC_TR_LT_1 (0x002UL << ADC_TR_LT_Pos) /*!< 0x00000002 */ +#define ADC_TR_LT_2 (0x004UL << ADC_TR_LT_Pos) /*!< 0x00000004 */ +#define ADC_TR_LT_3 (0x008UL << ADC_TR_LT_Pos) /*!< 0x00000008 */ +#define ADC_TR_LT_4 (0x010UL << ADC_TR_LT_Pos) /*!< 0x00000010 */ +#define ADC_TR_LT_5 (0x020UL << ADC_TR_LT_Pos) /*!< 0x00000020 */ +#define ADC_TR_LT_6 (0x040UL << ADC_TR_LT_Pos) /*!< 0x00000040 */ +#define ADC_TR_LT_7 (0x080UL << ADC_TR_LT_Pos) /*!< 0x00000080 */ +#define ADC_TR_LT_8 (0x100UL << ADC_TR_LT_Pos) /*!< 0x00000100 */ +#define ADC_TR_LT_9 (0x200UL << ADC_TR_LT_Pos) /*!< 0x00000200 */ +#define ADC_TR_LT_10 (0x400UL << ADC_TR_LT_Pos) /*!< 0x00000400 */ +#define ADC_TR_LT_11 (0x800UL << ADC_TR_LT_Pos) /*!< 0x00000800 */ +#define ADC_TR_HT_Pos (16U) +#define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ +#define ADC_TR_HT ADC_TR_HT_Msk /*!< ADC Analog watchdog 1 threshold high */ +#define ADC_TR_HT_0 (0x001UL << ADC_TR_HT_Pos) /*!< 0x00010000 */ +#define ADC_TR_HT_1 (0x002UL << ADC_TR_HT_Pos) /*!< 0x00020000 */ +#define ADC_TR_HT_2 (0x004UL << ADC_TR_HT_Pos) /*!< 0x00040000 */ +#define ADC_TR_HT_3 (0x008UL << ADC_TR_HT_Pos) /*!< 0x00080000 */ +#define ADC_TR_HT_4 (0x010UL << ADC_TR_HT_Pos) /*!< 0x00100000 */ +#define ADC_TR_HT_5 (0x020UL << ADC_TR_HT_Pos) /*!< 0x00200000 */ +#define ADC_TR_HT_6 (0x040UL << ADC_TR_HT_Pos) /*!< 0x00400000 */ +#define ADC_TR_HT_7 (0x080UL << ADC_TR_HT_Pos) /*!< 0x00800000 */ +#define ADC_TR_HT_8 (0x100UL << ADC_TR_HT_Pos) /*!< 0x01000000 */ +#define ADC_TR_HT_9 (0x200UL << ADC_TR_HT_Pos) /*!< 0x02000000 */ +#define ADC_TR_HT_10 (0x400UL << ADC_TR_HT_Pos) /*!< 0x04000000 */ +#define ADC_TR_HT_11 (0x800UL << ADC_TR_HT_Pos) /*!< 0x08000000 */ + +/****************** Bit definition for ADC_CHSELR register ******************/ +#define ADC_CHSELR_CHSEL_Pos (0U) +#define ADC_CHSELR_CHSEL_Msk (0x1BFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x00001BFF */ +#define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL12_Pos (12U) +#define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ +#define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL11_Pos (11U) +#define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ +#define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL9_Pos (9U) +#define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ +#define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL8_Pos (8U) +#define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ +#define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL7_Pos (7U) +#define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ +#define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL6_Pos (6U) +#define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ +#define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL5_Pos (5U) +#define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ +#define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL4_Pos (4U) +#define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ +#define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL3_Pos (3U) +#define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ +#define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL2_Pos (2U) +#define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ +#define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL1_Pos (1U) +#define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ +#define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ +#define ADC_CHSELR_CHSEL0_Pos (0U) +#define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ +#define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ + +/******************** Bit definition for ADC_DR register ********************/ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ +#define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ +#define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ +#define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ +#define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ +#define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ +#define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ +#define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ +#define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ +#define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ +#define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ +#define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ +#define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ +#define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ +#define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ +#define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ +#define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ + +/******************** Bit definition for ADC_CCSR register ********************/ +#define ADC_CCSR_CALSEL_Pos (11U) +#define ADC_CCSR_CALSEL_Msk (0x1UL << ADC_CCSR_CALSEL_Pos) /*!< 0x00000800 */ +#define ADC_CCSR_CALSEL ADC_CCSR_CALSEL_Msk /*!< ADC calibration context selection */ +#define ADC_CCSR_CALSMP_Pos (12U) +#define ADC_CCSR_CALSMP_Msk (0x3UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00003000 */ +#define ADC_CCSR_CALSMP ADC_CCSR_CALSMP_Msk /*!< ADC calibration sample time selection */ +#define ADC_CCSR_CALSMP_0 (0x1UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00001000 */ +#define ADC_CCSR_CALSMP_1 (0x2UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00002000 */ +#define ADC_CCSR_CALBYP_Pos (14U) +#define ADC_CCSR_CALBYP_Msk (0x1UL << ADC_CCSR_CALBYP_Pos) /*!< 0x00004000 */ +#define ADC_CCSR_CALBYP ADC_CCSR_CALBYP_Msk +#define ADC_CCSR_CALSET_Pos (15U) +#define ADC_CCSR_CALSET_Msk (0x1UL << ADC_CCSR_CALSET_Pos) /*!< 0x00008000 */ +#define ADC_CCSR_CALSET ADC_CCSR_CALSET_Msk +#define ADC_CCSR_OFFSUC_Pos (29U) +#define ADC_CCSR_OFFSUC_Msk (0x1UL << ADC_CCSR_OFFSUC_Pos) /*!< 0x20000000 */ +#define ADC_CCSR_OFFSUC ADC_CCSR_OFFSUC_Msk +#define ADC_CCSR_CALFAIL_Pos (30U) +#define ADC_CCSR_CALFAIL_Msk (0x1UL << ADC_CCSR_CALFAIL_Pos) /*!< 0x40000000 */ +#define ADC_CCSR_CALFAIL ADC_CCSR_CALFAIL_Msk /*!< ADC calibration fail flag */ +#define ADC_CCSR_CALON_Pos (31U) +#define ADC_CCSR_CALON_Msk (0x1UL << ADC_CCSR_CALON_Pos) /*!< 0x80000000 */ +#define ADC_CCSR_CALON ADC_CCSR_CALON_Msk /*!< ADC calibration flag */ + +/************************* ADC Common registers *****************************/ +/******************* Bit definition for ADC_CCR register ********************/ +#define ADC_CCR_VREFEN_Pos (22U) +#define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ +#define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ +#define ADC_CCR_TSEN_Pos (23U) +#define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ +#define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ + + +/******************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/******************************************************************************/ +/******************* Bit definition for CRC_DR register *********************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ********************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ********************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ + +/******************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/******************************************************************************/ +/******************** Bit definition for DBG_IDCODE register *************/ +// #define DBGMCU_IDCODE_DEV_ID_Pos (0U) +// #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +// #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk +#define DBGMCU_IDCODE_REV_ID_Pos (0U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk + +/******************** Bit definition for DBGMCU_CR register *****************/ +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk + +/******************** Bit definition for DBGMCU_APB_FZ1 register ***********/ +#define DBGMCU_APB_FZ1_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB_FZ1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB_FZ1_DBG_TIM6_STOP DBGMCU_APB_FZ1_DBG_TIM6_STOP_Msk +#define DBGMCU_APB_FZ1_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB_FZ1_DBG_IWDG_STOP DBGMCU_APB_FZ1_DBG_IWDG_STOP_Msk +#define DBGMCU_APB_FZ1_DBG_I2C1_TIMEOUT_Pos (21U) +#define DBGMCU_APB_FZ1_DBG_I2C1_TIMEOUT_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_I2C1_TIMEOUT_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB_FZ1_DBG_I2C1_TIMEOUT DBGMCU_APB_FZ1_DBG_I2C1_TIMEOUT_Msk +#define DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Pos (31U) +#define DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Pos) /*!< 0x80000000 */ +#define DBGMCU_APB_FZ1_DBG_LPTIM_STOP DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Msk + +/******************** Bit definition for DBGMCU_APB_FZ2 register ************/ +#define DBGMCU_APB_FZ2_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB_FZ2_DBG_TIM1_STOP DBGMCU_APB_FZ2_DBG_TIM1_STOP_Msk + +/******************************************************************************/ +/* */ +/* External Interrupt/Event Controller (EXTI) */ +/* */ +/******************************************************************************/ +/****************** Bit definition for EXTI_RTSR register ******************/ +#define EXTI_RTSR_RT0_Pos (0U) +#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR_RT1_Pos (1U) +#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR_RT2_Pos (2U) +#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR_RT3_Pos (3U) +#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR_RT4_Pos (4U) +#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR_RT5_Pos (5U) +#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR_RT6_Pos (6U) +#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR_RT7_Pos (7U) +#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger configuration for input line 7 */ + +/****************** Bit definition for EXTI_FTSR register ******************/ +#define EXTI_FTSR_FT0_Pos (0U) +#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR_FT1_Pos (1U) +#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR_FT2_Pos (2U) +#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR_FT3_Pos (3U) +#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR_FT4_Pos (4U) +#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR_FT5_Pos (5U) +#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR_FT6_Pos (6U) +#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR_FT7_Pos (7U) +#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger configuration for input line 7 */ + +/****************** Bit definition for EXTI_SWIER register *****************/ +#define EXTI_SWIER_SWI0_Pos (0U) +#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWI1_Pos (1U) +#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWI2_Pos (2U) +#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWI3_Pos (3U) +#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWI4_Pos (4U) +#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWI5_Pos (5U) +#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWI6_Pos (6U) +#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWI7_Pos (7U) +#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ + +/******************* Bit definition for EXTI_PR register ******************/ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_PR_PR_Pos (4U) +#define EXTI_PR_PR_Msk (0x1UL <
© Copyright (c) Puya Semiconductor Co. + * All rights reserved.
+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS_Device + * @{ + */ + +/** @addtogroup py32f072xb + * @{ + */ + +#ifndef __PY32F072XB_H +#define __PY32F072XB_H + +#ifdef __cplusplus +extern "C" { +#endif /* __cplusplus */ + +/** @addtogroup Configuration_section_for_CMSIS + * @{ + */ + +/** + * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals + */ +#define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ +#define __MPU_PRESENT 0 /*!< PY32F0xx do not provide MPU */ +#define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ +#define __NVIC_PRIO_BITS 2 /*!< PY32F0xx uses 2 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ + +/** + * @} + */ + +/** @addtogroup Peripheral_interrupt_number_definition + * @{ + */ + +/** + * @brief PY32F0xx Interrupt Number Definition, according to the selected device + * in @ref Library_configuration_section + */ + +/*!< Interrupt Number Definition */ +typedef enum +{ + /****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ + NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ + HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ + SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ + PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ + SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ + /****** PY32F0 specific Interrupt Numbers *********************************************************************/ + WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ + PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt(EXTI line 16) */ + RTC_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 */ + FLASH_IRQn = 3, /*!< FLASH global Interrupt */ + RCC_CTC_IRQn = 4, /*!< RCC and CTC global Interrupts */ + EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ + EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ + EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ + LCD_IRQn = 8, /*!< LCD global Interrupt */ + DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ + DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ + DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, 5, 6, 7 Interrupts */ + ADC_COMP_IRQn = 12, /*!< ADC&COMP Interrupts */ + TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ + TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ + TIM2_IRQn = 15, /*!< TIM2 global Interrupt */ + TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ + TIM6_LPTIM1_DAC_IRQn = 17, /*!< TIM6, LPTIM1, DAC global Interrupts */ + TIM7_IRQn = 18, /*!< TIM7 global Interrupt */ + TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ + TIM15_IRQn = 20, /*!< TIM15 global Interrupt */ + TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ + TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ + I2C1_IRQn = 23, /*!< I2C1 global Interrupt */ + I2C2_IRQn = 24, /*!< I2C2 global Interrupt */ + SPI1_IRQn = 25, /*!< SPI1 global Interrupt */ + SPI2_IRQn = 26, /*!< SPI2 global Interrupt */ + USART1_IRQn = 27, /*!< USART1 global Interrupt */ + USART2_IRQn = 28, /*!< USART2 global Interrupt */ + USART3_4_IRQn = 29, /*!< USART3, 4 global Interrupts */ + CAN_IRQn = 30, /*!< CAN global Interrupt */ + USB_IRQn = 31, /*!< USB global Interrupt */ +} IRQn_Type; + +/** + * @} + */ + +#include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ +#include "system_py32f0xx.h" /* PY32F0xx System Header */ +#include + +/** @addtogroup Peripheral_registers_structures + * @{ + */ + +/** +* @brief ADC Registers +*/ +typedef struct +{ + __IO uint32_t SR; /*!< ADC desc SR, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< ADC desc CR1, Address offset: 0x04 */ + __IO uint32_t CR2; /*!< ADC desc CR2, Address offset: 0x08 */ + __IO uint32_t SMPR1; /*!< ADC desc SMPR1, Address offset: 0x0C */ + __IO uint32_t SMPR2; /*!< ADC desc SMPR2, Address offset: 0x10 */ + __IO uint32_t SMPR3; /*!< ADC desc SMPR3, Address offset: 0x14 */ + __IO uint32_t JOFR1; /*!< ADC desc JOFR1, Address offset: 0x18 */ + __IO uint32_t JOFR2; /*!< ADC desc JOFR2, Address offset: 0x1C */ + __IO uint32_t JOFR3; /*!< ADC desc JOFR3, Address offset: 0x20 */ + __IO uint32_t JOFR4; /*!< ADC desc JOFR4, Address offset: 0x24 */ + __IO uint32_t HTR; /*!< ADC desc HTR, Address offset: 0x28 */ + __IO uint32_t LTR; /*!< ADC desc LTR, Address offset: 0x2C */ + __IO uint32_t SQR1; /*!< ADC desc SQR1, Address offset: 0x30 */ + __IO uint32_t SQR2; /*!< ADC desc SQR2, Address offset: 0x34 */ + __IO uint32_t SQR3; /*!< ADC desc SQR3, Address offset: 0x38 */ + __IO uint32_t JSQR; /*!< ADC desc JSQR, Address offset: 0x3C */ + __IO uint32_t JDR1; /*!< ADC desc JDR1, Address offset: 0x40 */ + __IO uint32_t JDR2; /*!< ADC desc JDR2, Address offset: 0x44 */ + __IO uint32_t JDR3; /*!< ADC desc JDR3, Address offset: 0x48 */ + __IO uint32_t JDR4; /*!< ADC desc JDR4, Address offset: 0x4C */ + __IO uint32_t DR; /*!< ADC desc DR, Address offset: 0x50 */ + __IO uint32_t CCSR; /*!< ADC desc CCSR, Address offset: 0x54 */ + __IO uint32_t CALRR1; /*!< ADC desc CALRR1, Address offset: 0x58 */ + __IO uint32_t CALRR2; /*!< ADC desc CALRR2, Address offset: 0x5C */ + __IO uint32_t CALFIR1; /*!< ADC desc CALFIR1, Address offset: 0x60 */ + __IO uint32_t CALFIR2; /*!< ADC desc CALFIR2, Address offset: 0x64 */ +} ADC_TypeDef; + +/** +* @brief CAN LLC Acceptance filters Registers +*/ +typedef struct +{ + __IO uint32_t ID; + __IO uint32_t FORMAT; + __IO uint32_t TYPE; + __IO uint32_t AF; +} CAN_LLC_AC_TypeDef; + +/** +* @brief CAN LLC Acceptance filters Registers +*/ +typedef struct +{ + __IO uint32_t ID; + __IO uint32_t FORMAT; + __IO uint32_t TYPE; + __IO uint32_t AF; + __IO uint32_t RTSL; + __IO uint32_t RTSH; + __IO uint32_t TTCAN; + __IO uint32_t DATA[2]; +} CAN_LLC_TypeDef; + +/** +* @brief CAN Registers +*/ +typedef struct +{ + __IO uint32_t TSNCR; /*!< CAN desc TSNCR, Address offset: 0x00 */ + __IO uint32_t ACBTR; /*!< CAN desc ACBTR, Address offset: 0x04 */ + __IO uint32_t FDBTR; /*!< CAN desc FDBTR, Address offset: 0x08 */ + __IO uint32_t XLBTR; /*!< CAN desc XLBTR, Address offset: 0x0C */ + __IO uint32_t RLSSP; /*!< CAN desc RLSSP, Address offset: 0x10 */ + __IO uint32_t IFR; /*!< CAN desc IFR, Address offset: 0x14 */ + __IO uint32_t IER; /*!< CAN desc IER, Address offset: 0x18 */ + __IO uint32_t TSR; /*!< CAN desc TSR, Address offset: 0x1C */ + __IO uint32_t TTSL; /*!< CAN desc TTSL, Address offset: 0x20 */ + __IO uint32_t TTSH; /*!< CAN desc TTSH, Address offset: 0x24 */ + __IO uint32_t MCR; /*!< CAN desc MCR, Address offset: 0x28 */ + __IO uint32_t WECR; /*!< CAN desc WECR, Address offset: 0x2C */ + __IO uint32_t REFMSG; /*!< CAN desc REFMSG, Address offset: 0x30 */ + __IO uint32_t TTCR; /*!< CAN desc TTCR, Address offset: 0x34 */ + __IO uint32_t TTTR; /*!< CAN desc TTTR, Address offset: 0x38 */ + __IO uint32_t SCMS; /*!< CAN desc SCMS, Address offset: 0x3C */ + __IO uint32_t MESR; /*!< CAN desc MESR, Address offset: 0x40 */ + __IO uint32_t ACFCR; /*!< CAN desc ACFCR, Address offset: 0x44 */ + CAN_LLC_AC_TypeDef ACFC; /*!< CAN desc ACFC, Address offset: 0x48 - 0x57 */ + CAN_LLC_AC_TypeDef ACFM; /*!< CAN desc ACFM, Address offset: 0x58 - 0x67 */ + uint8_t RESERVED18[8]; /*!< Reserved, Address offset: 0x68 - 0x6F */ + CAN_LLC_TypeDef RBUF; /*!< CAN desc RBUF, Address offset: 0x70 - 0x93 */ + CAN_LLC_TypeDef TBUF; /*!< CAN desc TBUF, Address offset: 0x94 - 0xB7 */ + __IO uint32_t PWMCR; /*!< CAN desc PWMCR, Address offset: 0xB8 */ +} CAN_TypeDef; + +/** + * @brief CRC calculation unit + */ +typedef struct +{ + __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ + __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ + __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ +} CRC_TypeDef; + +/** + * @brief Comparator + */ +typedef struct +{ + __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ + __IO uint32_t FR; /*!< COMP filter register, Address offset: 0x04 */ +} COMP_TypeDef; + +typedef struct +{ + __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ + __IO uint32_t FR_ODD; + __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ + __IO uint32_t FR_EVEN; +} COMP_Common_TypeDef; + +/** +* @brief CTC Registers +*/ +typedef struct +{ + __IO uint32_t CTL0; /*!< CTC desc CTL0, Address offset: 0x00 */ + __IO uint32_t CTL1; /*!< CTC desc CTL1, Address offset: 0x04 */ + __IO uint32_t SR; /*!< CTC desc SR, Address offset: 0x08 */ + __IO uint32_t INTC; /*!< CTC desc INTC, Address offset: 0x0C */ +} CTC_TypeDef; + +/** +* @brief DAC Registers +*/ +typedef struct +{ + __IO uint32_t CR; /*!< DAC desc CR, Address offset: 0x00 */ + __IO uint32_t SWTRIGR; /*!< DAC desc SWTRIGR, Address offset: 0x04 */ + __IO uint32_t DHR12R1; /*!< DAC desc DHR12R1, Address offset: 0x08 */ + __IO uint32_t DHR12L1; /*!< DAC desc DHR12L1, Address offset: 0x0C */ + __IO uint32_t DHR8R1; /*!< DAC desc DHR8R1, Address offset: 0x10 */ + __IO uint32_t DHR12R2; /*!< DAC desc DHR12R2, Address offset: 0x14 */ + __IO uint32_t DHR12L2; /*!< DAC desc DHR12L2, Address offset: 0x18 */ + __IO uint32_t DHR8R2; /*!< DAC desc DHR8R2, Address offset: 0x1C */ + __IO uint32_t DHR12RD; /*!< DAC desc DHR12RD, Address offset: 0x20 */ + __IO uint32_t DHR12LD; /*!< DAC desc DHR12LD, Address offset: 0x24 */ + __IO uint32_t DHR8RD; /*!< DAC desc DHR8RD, Address offset: 0x28 */ + __IO uint32_t DOR1; /*!< DAC desc DOR1, Address offset: 0x2C */ + __IO uint32_t DOR2; /*!< DAC desc DOR2, Address offset: 0x30 */ + __IO uint32_t SR; /*!< DAC desc SR, Address offset: 0x34 */ +} DAC_TypeDef; + +/** + * @brief Debug MCU + */ +typedef struct +{ + __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ + __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ + __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ + __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ +} DBGMCU_TypeDef; + +/** +* @brief HDIV Registers +*/ +typedef struct +{ + __IO uint32_t DEND; /*!< HDIV desc DEND, Address offset: 0x00 */ + __IO uint32_t SOR; /*!< HDIV desc SOR, Address offset: 0x04 */ + __IO uint32_t QUOT; /*!< HDIV desc REMA, Address offset: 0x08 */ + __IO uint32_t REMA; /*!< HDIV desc QUOT, Address offset: 0x0C */ + __IO uint32_t SIGN; /*!< HDIV desc SIGN, Address offset: 0x10 */ + __IO uint32_t STAT; /*!< HDIV desc STAT, Address offset: 0x1C */ +} DIV_TypeDef; + +/** + * @brief DMA Controller + */ +typedef struct +{ + __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ + __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ +} DMA_TypeDef; + +typedef struct +{ + __IO uint32_t CCR; /*!< DMA channel x configuration register */ + __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ + __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ + __IO uint32_t CMAR; /*!< DMA channel x memory address register */ +} DMA_Channel_TypeDef; + +/** + * @brief Asynch Interrupt/Event Controller (EXTI) + */ +typedef struct +{ + __IO uint32_t RTSR; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ + __IO uint32_t FTSR; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ + __IO uint32_t SWIER; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ + __IO uint32_t PR; /*!< EXTI Pending Register 1 Address offset: 0x0C */ + uint32_t RESERVED1[20]; /*!< Reserved 1, Address offset: 0x10 -- 0x5C */ + __IO uint32_t EXTICR[4]; /*!< EXTI External Interrupt Configuration Register, Address offset: 0x60 -- 0x6C */ + uint32_t RESERVED2[4]; /*!< Reserved 2, Address offset: 0x70 -- 0x7C */ + __IO uint32_t IMR; /*!< EXTI Interrupt Mask Register, Address offset: 0x80 */ + __IO uint32_t EMR; /*!< EXTI Event Mask Register, Address offset: 0x84 */ +} EXTI_TypeDef; + +/** + * @brief FLASH Registers + */ +typedef struct +{ + __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ + __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ + uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18-0x1C */ + __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + __IO uint32_t SDKR; /*!< FLASH SDK address register, Address offset: 0x24 */ + __IO uint32_t PCK_EN; /*!< FLASH PCK_EN address register, Address offset: 0x28 */ + __IO uint32_t WRPR; /*!< FLASH WRP address register, Address offset: 0x2C */ + uint32_t RESERVED3[(0x90 - 0x2C) / 4 - 1]; /*!< RESERVED3, Address offset: 0x30-0x8C */ + __IO uint32_t STCR; /*!< FLASH sleep time config register, Address offset: 0x90 */ + uint32_t RESERVED4[(0x100 - 0x90) / 4 - 1]; /*!< RESERVED4, Address offset: 0x94-0xFC */ + __IO uint32_t TS0; /*!< FLASH TS0 register, Address offset: 0x100 */ + __IO uint32_t TS1; /*!< FLASH TS1 register, Address offset: 0x104 */ + __IO uint32_t TS2P; /*!< FLASH TS2P register, Address offset: 0x108 */ + __IO uint32_t TPS3; /*!< FLASH TPS3 register, Address offset: 0x10C */ + __IO uint32_t TS3; /*!< FLASH TS3 register, Address offset: 0x110 */ + __IO uint32_t PERTPE; /*!< FLASH PERTPE register, Address offset: 0x114 */ + __IO uint32_t SMERTPE; /*!< FLASH SMERTPE register, Address offset: 0x118 */ + __IO uint32_t PRGTPE; /*!< FLASH PRGTPE register, Address offset: 0x11C */ + __IO uint32_t PRETPE; /*!< FLASH PRETPE register, Address offset: 0x120 */ + uint32_t RESERVED5[(0x290 - 0x120) / 4 - 1]; /*!< RESERVED4, Address offset: 0x124-0x28C */ + __IO uint32_t TRMLSR; /*!< FLASH TRMLSR register, Address offset: 0x290 */ + __IO uint32_t TRMDR[9]; /*!< FLASH TRMDR register, Address offset: 0x294 - 0x2B7 */ +} FLASH_TypeDef; + +/** + * @brief Option Bytes + */ +typedef struct +{ + __IO uint8_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ + __IO uint8_t USER; /*!< FLASH option byte user options, Address offset: 0x01 */ + __IO uint8_t nRDP; /*!< Complemented FLASH option byte Read protection, Address offset: 0x02 */ + __IO uint8_t nUSER; /*!< Complemented FLASH option byte user options, Address offset: 0x03 */ + __IO uint8_t SDK_STRT; /*!< SDK area start address(stored in SDK[4:0]), Address offset: 0x04 */ + __IO uint8_t SDK_END; /*!< SDK area end address(stored in SDK[12:8]), Address offset: 0x05 */ + __IO uint8_t nSDK_STRT; /*!< Complemented SDK area start address, Address offset: 0x06 */ + __IO uint8_t nSDK_END; /*!< Complemented SDK area end address, Address offset: 0x07 */ + uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x08 */ + __IO uint16_t WRP; /*!< FLASH option byte write protection, Address offset: 0x0C */ + __IO uint16_t nWRP; /*!< Complemented FLASH option byte write protection, Address offset: 0x0E */ +} OB_TypeDef; + +/** + * @brief General Purpose I/O + */ +typedef struct +{ + __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ + __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ + __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ + __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ + __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ + __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ + __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ + __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ + __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ + __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ +} GPIO_TypeDef; + +/** +* @brief I2C Registers +*/ +typedef struct +{ + __IO uint32_t CR1; /*!< I2C desc CR1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< I2C desc CR2, Address offset: 0x04 */ + __IO uint32_t OAR1; /*!< I2C desc OAR1, Address offset: 0x08 */ + __IO uint32_t OAR2; /*!< I2C desc OAR2, Address offset: 0x0C */ + __IO uint32_t DR; /*!< I2C desc DR, Address offset: 0x10 */ + __IO uint32_t SR1; /*!< I2C desc SR1, Address offset: 0x14 */ + __IO uint32_t SR2; /*!< I2C desc SR2, Address offset: 0x18 */ + __IO uint32_t CCR; /*!< I2C desc CCR, Address offset: 0x1C */ + __IO uint32_t TRISE; /*!< I2C desc TRISE, Address offset: 0x20 */ +} I2C_TypeDef; + +/** + * @brief Independent WATCHDOG + */ +typedef struct +{ + __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ + __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +/** + * @brief LCD + */ +typedef struct +{ + __IO uint32_t CR0; /*!< LCD desc CR0, Address offset: 0x00 */ + __IO uint32_t CR1; /*!< LCD desc CR1, Address offset: 0x04 */ + __IO uint32_t INTCLR; /*!< LCD desc INTCLR, Address offset: 0x08 */ + __IO uint32_t POEN0; /*!< LCD desc POEN0, Address offset: 0x0C */ + __IO uint32_t POEN1; /*!< LCD desc POEN1, Address offset: 0x10 */ + __IO uint32_t RAM[16]; /*!< LCD desc RAM0~F, Address offset: 0x14-0x53 */ +} LCD_TypeDef; + +/** + * @brief LPTIMER + */ +typedef struct +{ + __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ + __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ + __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ + __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ + __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x14 */ + __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ + __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ +} LPTIM_TypeDef; + +/** + * @brief OPA Registers + */ +typedef struct +{ + __IO uint32_t RESERVED1[0x30 / 4]; /*!< RESERVED1, Address offset: 0x0-0x2C */ + __IO uint32_t CR0; /*!< OPA desc CR0, Address offset: 0x30 */ + __IO uint32_t CR1; /*!< OPA desc CR1, Address offset: 0x34 */ + __IO uint32_t CR2; /*!< OPA desc CR2, Address offset: 0x38 */ + __IO uint32_t CR; /*!< OPA desc CR, Address offset: 0x3C */ +} OPA_TypeDef; + +/** + * @brief Power Control + */ +typedef struct +{ + __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ + uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x08-0x10 */ + __IO uint32_t SR; /*!< PWR Power Status Register, Address offset: 0x14 */ +} PWR_TypeDef; + +/** + * @brief Reset and Clock Control + */ +typedef struct +{ + __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ + __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ + __IO uint32_t PLLCFGR; /*!< RCC System PLL configuration Register, Address offset: 0x0C */ + __IO uint32_t ECSCR; /*!< RCC External clock source control register, Address offset: 0x10 */ + __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ + __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ + __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ + __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ + __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ + __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ + __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ + __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ + __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ + __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ + __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ + __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ + uint32_t RESERVED2[4]; /*!< Reserved, Address offset: 0x44-0x50 */ + __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ + __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ + __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ + __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ +} RCC_TypeDef; + +/** +* @brief RTC Registers +*/ +typedef struct +{ + __IO uint32_t CRH; /*!< RTC desc CRH, Address offset: 0x00 */ + __IO uint32_t CRL; /*!< RTC desc CRL, Address offset: 0x04 */ + __IO uint32_t PRLH; /*!< RTC desc PRLH, Address offset: 0x08 */ + __IO uint32_t PRLL; /*!< RTC desc PRLL, Address offset: 0x0C */ + __IO uint32_t DIVH; /*!< RTC desc DIVH, Address offset: 0x10 */ + __IO uint32_t DIVL; /*!< RTC desc DIVL, Address offset: 0x14 */ + __IO uint32_t CNTH; /*!< RTC desc CNTH, Address offset: 0x18 */ + __IO uint32_t CNTL; /*!< RTC desc CNTL, Address offset: 0x1C */ + __IO uint32_t ALRH; /*!< RTC desc ALRH, Address offset: 0x20 */ + __IO uint32_t ALRL; /*!< RTC desc ALRL, Address offset: 0x24 */ + uint32_t RESERVED1; + __IO uint32_t BKP_RTCCR; /*!< RTC desc BKP_RTCCR, Address offset: 0x2C */ +} RTC_TypeDef; + +/** +* @brief SPI Registers +*/ +typedef struct +{ + __IO uint32_t CR1; /*!< SPI desc CR1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< SPI desc CR2, Address offset: 0x04 */ + __IO uint32_t SR; /*!< SPI desc SR, Address offset: 0x08 */ + __IO uint32_t DR; /*!< SPI desc DR, Address offset: 0x0C */ + __IO uint32_t CRCPR; /*!< SPI desc CRCPR, Address offset: 0x10 */ + __IO uint32_t RXCRCR; /*!< SPI desc RXCRCR, Address offset: 0x14 */ + __IO uint32_t TXCRCR; /*!< SPI desc TXCRCR, Address offset: 0x18 */ + __IO uint32_t I2SCFGR; /*!< SPI desc I2SCFGR, Address offset: 0x1C */ + __IO uint32_t I2SPR; /*!< SPI desc I2SPR, Address offset: 0x20 */ +} SPI_TypeDef; + +/** + * @brief System configuration controller + */ +typedef struct +{ + //__IO uint32_t CFGR[4]; /*!< SYSCFG configuration registers, Address offset: 0x00 - 0x0F */ + __IO uint32_t CFGR1; /*!< SYSCFG desc CFGR1, Address offset: 0x00 */ + __IO uint32_t CFGR2; /*!< SYSCFG desc CFGR2, Address offset: 0x04 */ + __IO uint32_t CFGR3; /*!< SYSCFG desc CFGR3, Address offset: 0x08 */ + __IO uint32_t CFGR4; /*!< SYSCFG desc CFGR4, Address offset: 0x0C */ + __IO uint32_t PAENS; /*!< SYSCFG desc PAENS, Address offset: 0x10 */ + __IO uint32_t PBENS; /*!< SYSCFG desc PBENS, Address offset: 0x14 */ + __IO uint32_t PCENS; /*!< SYSCFG desc PCENS, Address offset: 0x18 */ + __IO uint32_t PFENS; /*!< SYSCFG desc PFENS, Address offset: 0x1C */ + __IO uint32_t EIIC; /*!< SYSCFG desc PEENS, Address offset: 0x20 */ +} SYSCFG_TypeDef; + +/** + * @brief TIM + */ +typedef struct +{ + __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ + __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ + __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ + __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ + __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ + __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ + __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ + __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ + __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ + __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ + __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ + __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ + __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ + __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ + __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ + __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ + __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ + __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ + __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ + __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ + __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ +} TIM_TypeDef; + +/** + * @brief Universal Synchronous Asynchronous Receiver Transmitter + */ +typedef struct +{ + __IO uint32_t SR; /*!< USART Status register , Address offset: 0x00 */ + __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ + __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ + __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ + __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ + __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ + __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ +} USART_TypeDef; + +/** +* @brief USB Registers +*/ +typedef struct +{ + __IO uint32_t CR; /*!< USB desc CR, Address offset: 0x00 */ + __IO uint32_t INTR; /*!< USB desc INTR, Address offset: 0x04 */ + __IO uint32_t INTRE; /*!< USB desc INTRE, Address offset: 0x08 */ + __IO uint32_t FRAME; /*!< USB desc FRAME, Address offset: 0x0C */ + __IO uint32_t EP0CSR; /*!< USB desc EP0CSR, Address offset: 0x10 */ + __IO uint32_t INEPxCSR; /*!< USB desc INEPxCSR, Address offset: 0x14 */ + __IO uint32_t OUTEPxCSR; /*!< USB desc OUTEPxCSR, Address offset: 0x18 */ + __IO uint32_t OUTCOUNT; /*!< USB desc OUTCOUNT, Address offset: 0x1C */ + __IO uint32_t FIFODATA[16]; /*!< USB desc FIFODATA, Address offset: 0x20 - 0x3F */ +} USB_TypeDef; + +/** + * @brief Window WATCHDOG + */ +typedef struct +{ + __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ + __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ + __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ +} WWDG_TypeDef; + +/** @addtogroup Peripheral_memory_map + * @{ + */ +#define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ +#define FLASH_END (0x0801FFFFUL) /*!< FLASH end address */ +#define FLASH_SIZE (FLASH_END - FLASH_BASE + 1) +#define FLASH_PAGE_SIZE 0x00000100U /*!< FLASH Page Size, 256 Bytes */ +#define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) +#define FLASH_SECTOR_SIZE 0x00002000U /*!< FLASH Sector Size, 8192 Bytes */ +#define FLASH_SECTOR_NB (FLASH_SIZE / FLASH_SECTOR_SIZE) +#define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ +#define SRAM_END (0x20003FFFUL) /*!< SRAM end address */ +#define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ +#define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ + +/*!< Peripheral memory map */ +#define APBPERIPH_BASE (PERIPH_BASE) +#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) + +/*!< APB peripherals */ +#define TIM2_BASE (APBPERIPH_BASE + 0x00000000UL) +#define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) +#define TIM6_BASE (APBPERIPH_BASE + 0x00001000UL) +#define TIM7_BASE (APBPERIPH_BASE + 0x00001400UL) +#define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) +#define LCD_BASE (APBPERIPH_BASE + 0x00002400UL) +#define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) +#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) +#define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) +#define SPI2_BASE (APBPERIPH_BASE + 0x00003800UL) +#define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) +#define USART3_BASE (APBPERIPH_BASE + 0x00004800UL) +#define USART4_BASE (APBPERIPH_BASE + 0x00004C00UL) +#define I2C1_BASE (APBPERIPH_BASE + 0x00005400UL) +#define I2C2_BASE (APBPERIPH_BASE + 0x00005800UL) +#define USB_BASE (APBPERIPH_BASE + 0x00005C00UL) +#define USB_SRAM_BASE (APBPERIPH_BASE + 0x00006000UL) +#define CAN1_BASE (APBPERIPH_BASE + 0x00006400UL) +#define CTC_BASE (APBPERIPH_BASE + 0x00006C00UL) +#define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) +#define DAC1_BASE (APBPERIPH_BASE + 0x00007400UL) +#define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00UL) +#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) +#define COMP1_BASE (APBPERIPH_BASE + 0x00010200UL) +#define COMP2_BASE (APBPERIPH_BASE + 0x00010210UL) +#define COMP3_BASE (APBPERIPH_BASE + 0x00010220UL) +#define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) +#define OPA_BASE (APBPERIPH_BASE + 0x00010300UL) +#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) +#define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) +#define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) +#define TIM15_BASE (APBPERIPH_BASE + 0x00014000UL) +#define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) +#define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) +#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) + +/*!< AHB peripherals */ +#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) +#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) +#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) +#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) +#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044UL) +#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058UL) +#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006CUL) +#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080UL) +#define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) +#define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) +#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ +#define OB_BASE 0x1FFF3100UL /*!< FLASH Option Bytes base address */ +#define FLASHSIZE_BASE 0x1FFF31FCUL /*!< FLASH Size register base address */ +#define UID_BASE 0x1FFF3000UL /*!< Unique device ID register base address */ +#define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) +#define DIV_BASE (AHBPERIPH_BASE + 0x00003800UL) + +/*!< IOPORT */ +#define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) +#define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) +#define GPIOC_BASE (IOPORT_BASE + 0x00000800UL) +#define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) + +/** + * @} + */ + +/** @addtogroup Peripheral_declaration + * @{ + */ +#define TIM2 ((TIM_TypeDef *) TIM2_BASE) +#define TIM3 ((TIM_TypeDef *) TIM3_BASE) +#define TIM6 ((TIM_TypeDef *) TIM6_BASE) +#define TIM7 ((TIM_TypeDef *) TIM7_BASE) +#define TIM14 ((TIM_TypeDef *) TIM14_BASE) +#define LCD ((LCD_TypeDef *) LCD_BASE) +#define RTC ((RTC_TypeDef *) RTC_BASE) +#define WWDG ((WWDG_TypeDef *) WWDG_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define SPI2 ((SPI_TypeDef *) SPI2_BASE) +#define USART2 ((USART_TypeDef *) USART2_BASE) +#define USART3 ((USART_TypeDef *) USART3_BASE) +#define USART4 ((USART_TypeDef *) USART4_BASE) +#define I2C1 ((I2C_TypeDef *) I2C1_BASE) +#define I2C2 ((I2C_TypeDef *) I2C2_BASE) +#define USB ((USB_TypeDef *) USB_BASE) +#define USB_SRAM ((USB_SRAM_TypeDef *) USB_SRAM_BASE) +#define CAN1 ((CAN_TypeDef *) CAN1_BASE) +#define CTC ((CTC_TypeDef *) CTC_BASE) +#define PWR ((PWR_TypeDef *) PWR_BASE) +#define DAC1 ((DAC_TypeDef *) DAC1_BASE) +#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE) +#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) +#define COMP1 ((COMP_TypeDef *) COMP1_BASE) +#define COMP2 ((COMP_TypeDef *) COMP2_BASE) +#define COMP3 ((COMP_TypeDef *) COMP3_BASE) +#define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) +#define OPA ((OPA_TypeDef *) OPA_BASE) +#define ADC1 ((ADC_TypeDef *) ADC1_BASE) +#define TIM1 ((TIM_TypeDef *) TIM1_BASE) +#define SPI1 ((SPI_TypeDef *) SPI1_BASE) +#define USART1 ((USART_TypeDef *) USART1_BASE) +#define TIM15 ((TIM_TypeDef *) TIM15_BASE) +#define TIM16 ((TIM_TypeDef *) TIM16_BASE) +#define TIM17 ((TIM_TypeDef *) TIM17_BASE) +#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) +#define DMA1 ((DMA_TypeDef *) DMA1_BASE) +#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) +#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) +#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) +#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE) +#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE) +#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE) +#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE) +#define RCC ((RCC_TypeDef *) RCC_BASE) +#define EXTI ((EXTI_TypeDef *) EXTI_BASE) +#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) +#define OB ((OB_TypeDef *) OB_BASE) +#define CRC ((CRC_TypeDef *) CRC_BASE) +#define DIV ((DIV_TypeDef *) DIV_BASE) +#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) +#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) +#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE) +#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) + +/** + * @} + */ + +/** @addtogroup Exported_constants + * @{ + */ + +/** @addtogroup Peripheral_Registers_Bits_Definition +* @{ +*/ + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************/ +/* */ +/* Analog to Digital Converter (ADC) */ +/* */ +/******************************************************************************/ +/******************** Bits definition for ADC_SR register *******************/ +#define ADC_SR_AWD_Pos (0U) +#define ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos) /*!< 0x00000080 */ +#define ADC_SR_AWD ADC_SR_AWD_Msk +#define ADC_SR_EOC_Pos (1U) +#define ADC_SR_EOC_Msk (0x1UL << ADC_SR_EOC_Pos) /*!< 0x00000004 */ +#define ADC_SR_EOC ADC_SR_EOC_Msk +#define ADC_SR_JEOC_Pos (2U) +#define ADC_SR_JEOC_Msk (0x1UL << ADC_SR_JEOC_Pos) /*!< 0x00000004 */ +#define ADC_SR_JEOC ADC_SR_JEOC_Msk +#define ADC_SR_JSTRT_Pos (3U) +#define ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos) /*!< 0x00000004 */ +#define ADC_SR_JSTRT ADC_SR_JSTRT_Msk +#define ADC_SR_STRT_Pos (4U) +#define ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos) /*!< 0x00000004 */ +#define ADC_SR_STRT ADC_SR_STRT_Msk +#define ADC_SR_OVER_Pos (5U) +#define ADC_SR_OVER_Msk (0x1UL << ADC_SR_OVER_Pos) /*!< 0x00000004 */ +#define ADC_SR_OVER ADC_SR_OVER_Msk + +/*!< ADC_CR1 */ +#define ADC_CR1_AWDCH_Pos (0U) +#define ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos) /*!< 0x0000001F */ +#define ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk /*!< AWDCH[4:0] bits (desc AWDCH) */ +#define ADC_CR1_AWDCH_0 (0x1UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000001 */ +#define ADC_CR1_AWDCH_1 (0x2UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000002 */ +#define ADC_CR1_AWDCH_2 (0x4UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000004 */ +#define ADC_CR1_AWDCH_3 (0x8UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000008 */ +#define ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos) /*!< 0x00000010 */ +#define ADC_CR1_EOCIE_Pos (5U) +#define ADC_CR1_EOCIE_Msk (0x1UL << ADC_CR1_EOCIE_Pos) /*!< 0x00000020 */ +#define ADC_CR1_EOCIE ADC_CR1_EOCIE_Msk +#define ADC_CR1_AWDIE_Pos (6U) +#define ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos) /*!< 0x00000040 */ +#define ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk /*!< desc AWDIE */ +#define ADC_CR1_JEOCIE_Pos (7U) +#define ADC_CR1_JEOCIE_Msk (0x1UL << ADC_CR1_JEOCIE_Pos) /*!< 0x00000080 */ +#define ADC_CR1_JEOCIE ADC_CR1_JEOCIE_Msk /*!< desc JEOCIE */ +#define ADC_CR1_SCAN_Pos (8U) +#define ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos) /*!< 0x00000100 */ +#define ADC_CR1_SCAN ADC_CR1_SCAN_Msk /*!< desc SCAN */ +#define ADC_CR1_AWDSGL_Pos (9U) +#define ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos) /*!< 0x00000200 */ +#define ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk /*!< desc AWDSGL */ +#define ADC_CR1_JAUTO_Pos (10U) +#define ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos) /*!< 0x00000400 */ +#define ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk /*!< desc JAUTO */ +#define ADC_CR1_DISCEN_Pos (11U) +#define ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos) /*!< 0x00000800 */ +#define ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk /*!< desc DISCEN */ +#define ADC_CR1_JDISCEN_Pos (12U) +#define ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos) /*!< 0x00001000 */ +#define ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk /*!< desc JDISCEN */ +#define ADC_CR1_DISCNUM_Pos (13U) +#define ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos) /*!< 0x0000E000 */ +#define ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk /*!< DISCNUM[15:13] bits (desc DISCNUM) */ +#define ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00002000 */ +#define ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00004000 */ +#define ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos) /*!< 0x00008000 */ +#define ADC_CR1_JAWDEN_Pos (22U) +#define ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos) /*!< 0x00400000 */ +#define ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk +#define ADC_CR1_AWDEN_Pos (23U) +#define ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos) /*!< 0x00800000 */ +#define ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk +#define ADC_CR1_RESSEL_Pos (24U) +#define ADC_CR1_RESSEL_Msk (0x3UL << ADC_CR1_RESSEL_Pos) /*!< 0x03000000 */ +#define ADC_CR1_RESSEL ADC_CR1_RESSEL_Msk +#define ADC_CR1_RESSEL_0 (0x1UL << ADC_CR1_RESSEL_Pos) /*!< 0x01000000 */ +#define ADC_CR1_RESSEL_1 (0x2UL << ADC_CR1_RESSEL_Pos) +#define ADC_CR1_ADSTP_Pos (27U) +#define ADC_CR1_ADSTP_Msk (0x1UL << ADC_CR1_ADSTP_Pos) /*!< 0x08000000 */ +#define ADC_CR1_ADSTP ADC_CR1_ADSTP_Msk +#define ADC_CR1_MSBSEL_Pos (28U) +#define ADC_CR1_MSBSEL_Msk (0x1UL << ADC_CR1_MSBSEL_Pos) /*!< 0x10000000 */ +#define ADC_CR1_MSBSEL ADC_CR1_MSBSEL_Msk +#define ADC_CR1_OVETIE_Pos (29U) +#define ADC_CR1_OVETIE_Msk (0x1UL << ADC_CR1_OVETIE_Pos) /*!< 0x10000000 */ +#define ADC_CR1_OVETIE ADC_CR1_OVETIE_Msk + +/*!< ADC_CR2 */ +#define ADC_CR2_ADON_Pos (0U) +#define ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos) /*!< 0x00000001 */ +#define ADC_CR2_ADON ADC_CR2_ADON_Msk /*!< desc ADON */ +#define ADC_CR2_CONT_Pos (1U) +#define ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos) /*!< 0x00000002 */ +#define ADC_CR2_CONT ADC_CR2_CONT_Msk /*!< desc CONT */ +#define ADC_CR2_CAL_Pos (2U) +#define ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos) /*!< 0x00000004 */ +#define ADC_CR2_CAL ADC_CR2_CAL_Msk /*!< desc CAL */ +#define ADC_CR2_RSTCAL_Pos (3U) +#define ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos) /*!< 0x00000008 */ +#define ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk +#define ADC_CR2_DMA_Pos (8U) +#define ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos) /*!< 0x00000100 */ +#define ADC_CR2_DMA ADC_CR2_DMA_Msk +#define ADC_CR2_ALIGN_Pos (11U) +#define ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos) /*!< 0x00000800 */ +#define ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk /*!< desc ALIGN */ +#define ADC_CR2_JEXTSEL_Pos (12U) +#define ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00007000 */ +#define ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk /*!< JEXTSEL[14:12] bits (desc JEXTSEL) */ +#define ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00001000 */ +#define ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00002000 */ +#define ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos) /*!< 0x00004000 */ +#define ADC_CR2_JEXTTRIG_Pos (15U) +#define ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos) /*!< 0x00008000 */ +#define ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk /*!< desc JEXTTRIG */ +#define ADC_CR2_EXTSEL_Pos (17U) +#define ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos) /*!< 0x000E0000 */ +#define ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk /*!< EXTSEL[19:17] bits (desc EXTSEL) */ +#define ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00020000 */ +#define ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00040000 */ +#define ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos) /*!< 0x00080000 */ +#define ADC_CR2_EXTTRIG_Pos (20U) +#define ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos) /*!< 0x00100000 */ +#define ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk /*!< desc EXTTRIG */ +#define ADC_CR2_JSWSTART_Pos (21U) +#define ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos) /*!< 0x00200000 */ +#define ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk /*!< desc JSWSTART */ +#define ADC_CR2_SWSTART_Pos (22U) +#define ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos) /*!< 0x00400000 */ +#define ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk /*!< desc SWSTART */ +#define ADC_CR2_TSVREFE_Pos (23U) +#define ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos) /*!< 0x00800000 */ +#define ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk +#define ADC_CR2_VERFBUFFEREN_Pos (25U) +#define ADC_CR2_VERFBUFFEREN_Msk (0x1UL << ADC_CR2_VERFBUFFEREN_Pos) /*!< 0x00800000 */ +#define ADC_CR2_VERFBUFFEREN ADC_CR2_VERFBUFFEREN_Msk +#define ADC_CR2_VERFBUFFERSEL_Pos (26U) +#define ADC_CR2_VERFBUFFERSEL_Msk (0x3UL << ADC_CR2_VERFBUFFERSEL_Pos) /*!< 0x00800000 */ +#define ADC_CR2_VERFBUFFERSELE ADC_CR2_VERFBUFFERSEL_Msk +#define ADC_CR2_VERFBUFFERSELE_0 (0x1UL << ADC_CR2_VERFBUFFERSEL_Pos) /*!< 0x00001000 */ +#define ADC_CR2_VERFBUFFERSELE_1 (0x2UL << ADC_CR2_VERFBUFFERSEL_Pos) + +/*!< ADC_SMPR1 */ +#define ADC_SMPR1_SMP20_Pos (0U) +#define ADC_SMPR1_SMP20_Msk (0x7UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000007 */ +#define ADC_SMPR1_SMP20 ADC_SMPR1_SMP20_Msk /*!< SMP10[2:0] bits (desc SMP10) */ +#define ADC_SMPR1_SMP20_0 (0x1UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000001 */ +#define ADC_SMPR1_SMP20_1 (0x2UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000002 */ +#define ADC_SMPR1_SMP20_2 (0x4UL << ADC_SMPR1_SMP20_Pos) /*!< 0x00000004 */ +#define ADC_SMPR1_SMP21_Pos (3U) +#define ADC_SMPR1_SMP21_Msk (0x7UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000038 */ +#define ADC_SMPR1_SMP21 ADC_SMPR1_SMP21_Msk /*!< SMP11[5:3] bits (desc SMP11) */ +#define ADC_SMPR1_SMP21_0 (0x1UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000008 */ +#define ADC_SMPR1_SMP21_1 (0x2UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000010 */ +#define ADC_SMPR1_SMP21_2 (0x4UL << ADC_SMPR1_SMP21_Pos) /*!< 0x00000020 */ +#define ADC_SMPR1_SMP22_Pos (6U) +#define ADC_SMPR1_SMP22_Msk (0x7UL << ADC_SMPR1_SMP22_Pos) /*!< 0x000001C0 */ +#define ADC_SMPR1_SMP22 ADC_SMPR1_SMP22_Msk /*!< SMP12[8:6] bits (desc SMP12) */ +#define ADC_SMPR1_SMP22_0 (0x1UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000040 */ +#define ADC_SMPR1_SMP22_1 (0x2UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000080 */ +#define ADC_SMPR1_SMP22_2 (0x4UL << ADC_SMPR1_SMP22_Pos) /*!< 0x00000100 */ +#define ADC_SMPR1_SMP23_Pos (9U) +#define ADC_SMPR1_SMP23_Msk (0x7UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000E00 */ +#define ADC_SMPR1_SMP23 ADC_SMPR1_SMP23_Msk /*!< SMP13[11:9] bits (desc SMP13) */ +#define ADC_SMPR1_SMP23_0 (0x1UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000200 */ +#define ADC_SMPR1_SMP23_1 (0x2UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000400 */ +#define ADC_SMPR1_SMP23_2 (0x4UL << ADC_SMPR1_SMP23_Pos) /*!< 0x00000800 */ + +/*!< ADC_SMPR2 */ +#define ADC_SMPR2_SMP10_Pos (0U) +#define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< SMP0[2:0] bits (desc SMP0) */ +#define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) +#define ADC_SMPR2_SMP11_Pos (3U) +#define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< SMP0[2:0] bits (desc SMP0) */ +#define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) +#define ADC_SMPR2_SMP12_Pos (6U) +#define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< SMP0[2:0] bits (desc SMP0) */ +#define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) +#define ADC_SMPR2_SMP13_Pos (9U) +#define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< SMP0[2:0] bits (desc SMP0) */ +#define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) +#define ADC_SMPR2_SMP14_Pos (12U) +#define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00000007 */ +#define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< SMP0[2:0] bits (desc SMP0) */ +#define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00000001 */ +#define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00000002 */ +#define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) +#define ADC_SMPR2_SMP15_Pos (15U) +#define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */ +#define ADC_SMPR2_SMP16_Pos (18U) +#define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) +#define ADC_SMPR2_SMP17_Pos (21U) +#define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) +#define ADC_SMPR2_SMP18_Pos (24U) +#define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) +#define ADC_SMPR2_SMP19_Pos (27U) +#define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x00038000 */ +#define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x00008000 */ +#define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x00010000 */ +#define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) +#define ADC_SMPR3_SMP0_Pos (0U) +#define ADC_SMPR3_SMP0_Msk (0x7UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP0 ADC_SMPR3_SMP0_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR3_SMP0_0 (0x1UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP0_1 (0x2UL << ADC_SMPR3_SMP0_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP0_2 (0x4UL << ADC_SMPR3_SMP0_Pos) +#define ADC_SMPR3_SMP1_Pos (3U) +#define ADC_SMPR3_SMP1_Msk (0x7UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP1 ADC_SMPR3_SMP1_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR3_SMP1_0 (0x1UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP1_1 (0x2UL << ADC_SMPR3_SMP1_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP1_2 (0x4UL << ADC_SMPR3_SMP1_Pos) +#define ADC_SMPR3_SMP2_Pos (6U) +#define ADC_SMPR3_SMP2_Msk (0x7UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP2 ADC_SMPR3_SMP2_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR3_SMP2_0 (0x1UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP2_1 (0x2UL << ADC_SMPR3_SMP2_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP2_2 (0x4UL << ADC_SMPR3_SMP2_Pos) +#define ADC_SMPR3_SMP3_Pos (9U) +#define ADC_SMPR3_SMP3_Msk (0x7UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP3 ADC_SMPR3_SMP3_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR3_SMP3_0 (0x1UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP3_1 (0x2UL << ADC_SMPR3_SMP3_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP3_2 (0x4UL << ADC_SMPR3_SMP3_Pos) +#define ADC_SMPR3_SMP4_Pos (12U) +#define ADC_SMPR3_SMP4_Msk (0x7UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP4 ADC_SMPR3_SMP4_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR3_SMP4_0 (0x1UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP4_1 (0x2UL << ADC_SMPR3_SMP4_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP4_2 (0x4UL << ADC_SMPR3_SMP4_Pos) +#define ADC_SMPR3_SMP5_Pos (15U) +#define ADC_SMPR3_SMP5_Msk (0x7UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP5 ADC_SMPR3_SMP5_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR3_SMP5_0 (0x1UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP5_1 (0x2UL << ADC_SMPR3_SMP5_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP5_2 (0x4UL << ADC_SMPR3_SMP5_Pos) +#define ADC_SMPR3_SMP6_Pos (18U) +#define ADC_SMPR3_SMP6_Msk (0x7UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP6 ADC_SMPR3_SMP6_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR3_SMP6_0 (0x1UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP6_1 (0x2UL << ADC_SMPR3_SMP6_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP6_2 (0x4UL << ADC_SMPR3_SMP6_Pos) +#define ADC_SMPR3_SMP7_Pos (21U) +#define ADC_SMPR3_SMP7_Msk (0x7UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP7 ADC_SMPR3_SMP7_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR3_SMP7_0 (0x1UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP7_1 (0x2UL << ADC_SMPR3_SMP7_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP7_2 (0x4UL << ADC_SMPR3_SMP7_Pos) +#define ADC_SMPR3_SMP8_Pos (24U) +#define ADC_SMPR3_SMP8_Msk (0x7UL << ADC_SMPR3_SMP8_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP8 ADC_SMPR3_SMP8_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR3_SMP8_0 (0x1UL << ADC_SMPR3_SMP8_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP8_1 (0x2UL << ADC_SMPR3_SMP8_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP8_2 (0x4UL << ADC_SMPR3_SMP8_Pos) +#define ADC_SMPR3_SMP9_Pos (27U) +#define ADC_SMPR3_SMP9_Msk (0x7UL << ADC_SMPR3_SMP9_Pos) /*!< 0x00038000 */ +#define ADC_SMPR3_SMP9 ADC_SMPR3_SMP9_Msk /*!< SMP15[17:15] bits (desc SMP15) */ +#define ADC_SMPR3_SMP9_0 (0x1UL << ADC_SMPR3_SMP9_Pos) /*!< 0x00008000 */ +#define ADC_SMPR3_SMP9_1 (0x2UL << ADC_SMPR3_SMP9_Pos) /*!< 0x00010000 */ +#define ADC_SMPR3_SMP9_2 (0x4UL << ADC_SMPR3_SMP9_Pos) + +/*!< ADC_JOFR1 */ +#define ADC_JOFR1_JOFFSET1_Pos (0U) +#define ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk /*!< JOFFSET1[11:0] bits (desc JOFFSET1) */ + +/*!< ADC_JOFR2 */ +#define ADC_JOFR2_JOFFSET2_Pos (0U) +#define ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk /*!< JOFFSET2[11:0] bits (desc JOFFSET2) */ + +/*!< ADC_JOFR3 */ +#define ADC_JOFR3_JOFFSET3_Pos (0U) +#define ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk /*!< JOFFSET3[11:0] bits (desc JOFFSET3) */ + +/*!< ADC_JOFR4 */ +#define ADC_JOFR4_JOFFSET4_Pos (0U) +#define ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos) /*!< 0x00000FFF */ +#define ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk /*!< JOFFSET4[11:0] bits (desc JOFFSET4) */ + +/*!< ADC_HTR */ +#define ADC_HTR_HT_Pos (0U) +#define ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos) /*!< 0x00000FFF */ +#define ADC_HTR_HT ADC_HTR_HT_Msk /*!< HT[11:0] bits (desc HT) */ + +/*!< ADC_LTR */ +#define ADC_LTR_LT_Pos (0U) +#define ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos) /*!< 0x00000FFF */ +#define ADC_LTR_LT ADC_LTR_LT_Msk + +/*!< ADC_SQR1 */ +#define ADC_SQR1_SQ13_Pos (0U) +#define ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos) /*!< 0x0000001F */ +#define ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk /*!< SQ13[4:0] bits (desc SQ13) */ +#define ADC_SQR1_SQ13_0 (0x1UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000001 */ +#define ADC_SQR1_SQ13_1 (0x2UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000002 */ +#define ADC_SQR1_SQ13_2 (0x4UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000004 */ +#define ADC_SQR1_SQ13_3 (0x8UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000008 */ +#define ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos) /*!< 0x00000010 */ +#define ADC_SQR1_SQ14_Pos (5U) +#define ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos) /*!< 0x000003E0 */ +#define ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk /*!< SQ14[9:5] bits (desc SQ14) */ +#define ADC_SQR1_SQ14_0 (0x1UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000020 */ +#define ADC_SQR1_SQ14_1 (0x2UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000040 */ +#define ADC_SQR1_SQ14_2 (0x4UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000080 */ +#define ADC_SQR1_SQ14_3 (0x8UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000100 */ +#define ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos) /*!< 0x00000200 */ +#define ADC_SQR1_SQ15_Pos (10U) +#define ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos) /*!< 0x00007C00 */ +#define ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk /*!< SQ15[14:10] bits (desc SQ15) */ +#define ADC_SQR1_SQ15_0 (0x1UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000400 */ +#define ADC_SQR1_SQ15_1 (0x2UL << ADC_SQR1_SQ15_Pos) /*!< 0x00000800 */ +#define ADC_SQR1_SQ15_2 (0x4UL << ADC_SQR1_SQ15_Pos) /*!< 0x00001000 */ +#define ADC_SQR1_SQ15_3 (0x8UL << ADC_SQR1_SQ15_Pos) /*!< 0x00002000 */ +#define ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos) /*!< 0x00004000 */ +#define ADC_SQR1_SQ16_Pos (15U) +#define ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos) /*!< 0x000F8000 */ +#define ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk /*!< SQ16[19:15] bits (desc SQ16) */ +#define ADC_SQR1_SQ16_0 (0x1UL << ADC_SQR1_SQ16_Pos) /*!< 0x00008000 */ +#define ADC_SQR1_SQ16_1 (0x2UL << ADC_SQR1_SQ16_Pos) /*!< 0x00010000 */ +#define ADC_SQR1_SQ16_2 (0x4UL << ADC_SQR1_SQ16_Pos) /*!< 0x00020000 */ +#define ADC_SQR1_SQ16_3 (0x8UL << ADC_SQR1_SQ16_Pos) /*!< 0x00040000 */ +#define ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos) /*!< 0x00080000 */ +#define ADC_SQR1_L_Pos (20U) +#define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x00F00000 */ +#define ADC_SQR1_L ADC_SQR1_L_Msk /*!< L[23:20] bits (desc L) */ +#define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00100000 */ +#define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00200000 */ +#define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00400000 */ +#define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) + +/*!< ADC_SQR2 */ +#define ADC_SQR2_SQ7_Pos (0U) +#define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0000001F */ +#define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< SQ7[4:0] bits (desc SQ7) */ +#define ADC_SQR2_SQ7_0 (0x1UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000001 */ +#define ADC_SQR2_SQ7_1 (0x2UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000002 */ +#define ADC_SQR2_SQ7_2 (0x4UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000004 */ +#define ADC_SQR2_SQ7_3 (0x8UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000008 */ +#define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00000010 */ +#define ADC_SQR2_SQ8_Pos (5U) +#define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x000003E0 */ +#define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< SQ8[9:5] bits (desc SQ8) */ +#define ADC_SQR2_SQ8_0 (0x1UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000020 */ +#define ADC_SQR2_SQ8_1 (0x2UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000040 */ +#define ADC_SQR2_SQ8_2 (0x4UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000080 */ +#define ADC_SQR2_SQ8_3 (0x8UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000100 */ +#define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00000200 */ +#define ADC_SQR2_SQ9_Pos (10U) +#define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x00007C00 */ +#define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< SQ9[14:10] bits (desc SQ9) */ +#define ADC_SQR2_SQ9_0 (0x1UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000400 */ +#define ADC_SQR2_SQ9_1 (0x2UL << ADC_SQR2_SQ9_Pos) /*!< 0x00000800 */ +#define ADC_SQR2_SQ9_2 (0x4UL << ADC_SQR2_SQ9_Pos) /*!< 0x00001000 */ +#define ADC_SQR2_SQ9_3 (0x8UL << ADC_SQR2_SQ9_Pos) /*!< 0x00002000 */ +#define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x00004000 */ +#define ADC_SQR2_SQ10_Pos (15U) +#define ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos) /*!< 0x000F8000 */ +#define ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk /*!< SQ10[19:15] bits (desc SQ10) */ +#define ADC_SQR2_SQ10_0 (0x1UL << ADC_SQR2_SQ10_Pos) /*!< 0x00008000 */ +#define ADC_SQR2_SQ10_1 (0x2UL << ADC_SQR2_SQ10_Pos) /*!< 0x00010000 */ +#define ADC_SQR2_SQ10_2 (0x4UL << ADC_SQR2_SQ10_Pos) /*!< 0x00020000 */ +#define ADC_SQR2_SQ10_3 (0x8UL << ADC_SQR2_SQ10_Pos) /*!< 0x00040000 */ +#define ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos) /*!< 0x00080000 */ +#define ADC_SQR2_SQ11_Pos (20U) +#define ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos) /*!< 0x01F00000 */ +#define ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk /*!< SQ11[24:20] bits (desc SQ11) */ +#define ADC_SQR2_SQ11_0 (0x1UL << ADC_SQR2_SQ11_Pos) /*!< 0x00100000 */ +#define ADC_SQR2_SQ11_1 (0x2UL << ADC_SQR2_SQ11_Pos) /*!< 0x00200000 */ +#define ADC_SQR2_SQ11_2 (0x4UL << ADC_SQR2_SQ11_Pos) /*!< 0x00400000 */ +#define ADC_SQR2_SQ11_3 (0x8UL << ADC_SQR2_SQ11_Pos) /*!< 0x00800000 */ +#define ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos) /*!< 0x01000000 */ +#define ADC_SQR2_SQ12_Pos (25U) +#define ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos) /*!< 0x3E000000 */ +#define ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk /*!< SQ12[29:25] bits (desc SQ12) */ +#define ADC_SQR2_SQ12_0 (0x1UL << ADC_SQR2_SQ12_Pos) /*!< 0x02000000 */ +#define ADC_SQR2_SQ12_1 (0x2UL << ADC_SQR2_SQ12_Pos) /*!< 0x04000000 */ +#define ADC_SQR2_SQ12_2 (0x4UL << ADC_SQR2_SQ12_Pos) /*!< 0x08000000 */ +#define ADC_SQR2_SQ12_3 (0x8UL << ADC_SQR2_SQ12_Pos) /*!< 0x10000000 */ +#define ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos) /*!< 0x20000000 */ + +/*!< ADC_SQR3 */ +#define ADC_SQR3_SQ1_Pos (0U) +#define ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos) /*!< 0x0000001F */ +#define ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk /*!< SQ1[4:0] bits (desc SQ1) */ +#define ADC_SQR3_SQ1_0 (0x1UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000001 */ +#define ADC_SQR3_SQ1_1 (0x2UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000002 */ +#define ADC_SQR3_SQ1_2 (0x4UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000004 */ +#define ADC_SQR3_SQ1_3 (0x8UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000008 */ +#define ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos) /*!< 0x00000010 */ +#define ADC_SQR3_SQ2_Pos (5U) +#define ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos) /*!< 0x000003E0 */ +#define ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk /*!< SQ2[9:5] bits (desc SQ2) */ +#define ADC_SQR3_SQ2_0 (0x1UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000020 */ +#define ADC_SQR3_SQ2_1 (0x2UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000040 */ +#define ADC_SQR3_SQ2_2 (0x4UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000080 */ +#define ADC_SQR3_SQ2_3 (0x8UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000100 */ +#define ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos) /*!< 0x00000200 */ +#define ADC_SQR3_SQ3_Pos (10U) +#define ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos) /*!< 0x00007C00 */ +#define ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk /*!< SQ3[14:10] bits (desc SQ3) */ +#define ADC_SQR3_SQ3_0 (0x1UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000400 */ +#define ADC_SQR3_SQ3_1 (0x2UL << ADC_SQR3_SQ3_Pos) /*!< 0x00000800 */ +#define ADC_SQR3_SQ3_2 (0x4UL << ADC_SQR3_SQ3_Pos) /*!< 0x00001000 */ +#define ADC_SQR3_SQ3_3 (0x8UL << ADC_SQR3_SQ3_Pos) /*!< 0x00002000 */ +#define ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos) /*!< 0x00004000 */ +#define ADC_SQR3_SQ4_Pos (15U) +#define ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos) /*!< 0x000F8000 */ +#define ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk /*!< SQ4[19:15] bits (desc SQ4) */ +#define ADC_SQR3_SQ4_0 (0x1UL << ADC_SQR3_SQ4_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ4_1 (0x2UL << ADC_SQR3_SQ4_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ4_2 (0x4UL << ADC_SQR3_SQ4_Pos) /*!< 0x00020000 */ +#define ADC_SQR3_SQ4_3 (0x8UL << ADC_SQR3_SQ4_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos) +#define ADC_SQR3_SQ5_Pos (20U) +#define ADC_SQR3_SQ5_Msk (0x1UL << ADC_SQR3_SQ5_Pos) /*!< 0x01000000 */ +#define ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk +#define ADC_SQR3_SQ5_0 (0x1UL << ADC_SQR3_SQ5_Pos) /*!< 0x00008000 */ +#define ADC_SQR3_SQ5_1 (0x2UL << ADC_SQR3_SQ5_Pos) /*!< 0x00010000 */ +#define ADC_SQR3_SQ5_2 (0x4UL << ADC_SQR3_SQ5_Pos) /*!< 0x00020000 */ +#define ADC_SQR3_SQ5_3 (0x8UL << ADC_SQR3_SQ5_Pos) /*!< 0x00040000 */ +#define ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos) +#define ADC_SQR3_SQ6_Pos (25U) +#define ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos) /*!< 0x3E000000 */ +#define ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk /*!< SQ6[29:25] bits (desc SQ6) */ +#define ADC_SQR3_SQ6_0 (0x1UL << ADC_SQR3_SQ6_Pos) /*!< 0x02000000 */ +#define ADC_SQR3_SQ6_1 (0x2UL << ADC_SQR3_SQ6_Pos) /*!< 0x04000000 */ +#define ADC_SQR3_SQ6_2 (0x4UL << ADC_SQR3_SQ6_Pos) /*!< 0x08000000 */ +#define ADC_SQR3_SQ6_3 (0x8UL << ADC_SQR3_SQ6_Pos) /*!< 0x10000000 */ +#define ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos) + +/*!< ADC_JSQR */ +#define ADC_JSQR_JSQ1_Pos (0U) +#define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x0000001F */ +#define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< JSQ1[4:0] bits (desc JSQ1) */ +#define ADC_JSQR_JSQ1_0 (0x1UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000001 */ +#define ADC_JSQR_JSQ1_1 (0x2UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000002 */ +#define ADC_JSQR_JSQ1_2 (0x4UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000004 */ +#define ADC_JSQR_JSQ1_3 (0x8UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000008 */ +#define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000010 */ +#define ADC_JSQR_JSQ2_Pos (5U) +#define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000003E0 */ +#define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< JSQ2[9:5] bits (desc JSQ2) */ +#define ADC_JSQR_JSQ2_0 (0x1UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000020 */ +#define ADC_JSQR_JSQ2_1 (0x2UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000040 */ +#define ADC_JSQR_JSQ2_2 (0x4UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000080 */ +#define ADC_JSQR_JSQ2_3 (0x8UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000100 */ +#define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00000200 */ +#define ADC_JSQR_JSQ3_Pos (10U) +#define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x00007C00 */ +#define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< JSQ3[14:10] bits (desc JSQ3) */ +#define ADC_JSQR_JSQ3_0 (0x1UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000400 */ +#define ADC_JSQR_JSQ3_1 (0x2UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00000800 */ +#define ADC_JSQR_JSQ3_2 (0x4UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00001000 */ +#define ADC_JSQR_JSQ3_3 (0x8UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00002000 */ +#define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00004000 */ +#define ADC_JSQR_JSQ4_Pos (15U) +#define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0x000F8000 */ +#define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< JSQ4[19:15] bits (desc JSQ4) */ +#define ADC_JSQR_JSQ4_0 (0x1UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00008000 */ +#define ADC_JSQR_JSQ4_1 (0x2UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00010000 */ +#define ADC_JSQR_JSQ4_2 (0x4UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00020000 */ +#define ADC_JSQR_JSQ4_3 (0x8UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00040000 */ +#define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x00080000 */ +#define ADC_JSQR_JL_Pos (20U) +#define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00300000 */ +#define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< JL[21:20] bits (desc JL) */ +#define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00100000 */ +#define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00200000 */ + +/*!< ADC_JDR1 */ +#define ADC_JDR1_JDR1_Pos (0U) +#define ADC_JDR1_JDR1_Msk (0xFFFFUL << ADC_JDR1_JDR1_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR1_JDR1 ADC_JDR1_JDR1_Msk /*!< JDR1[15:0] bits (desc JDR1) */ + +/*!< ADC_JDR2 */ +#define ADC_JDR2_JDR2_Pos (0U) +#define ADC_JDR2_JDR2_Msk (0xFFFFUL << ADC_JDR2_JDR2_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR2_JDR2 ADC_JDR2_JDR2_Msk /*!< JDR2[15:0] bits (desc JDR2) */ + +/*!< ADC_JDR3 */ +#define ADC_JDR3_JDR3_Pos (0U) +#define ADC_JDR3_JDR3_Msk (0xFFFFUL << ADC_JDR3_JDR3_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR3_JDR3 ADC_JDR3_JDR3_Msk /*!< JDR3[15:0] bits (desc JDR3) */ + +/*!< ADC_JDR4 */ +#define ADC_JDR4_JDR4_Pos (0U) +#define ADC_JDR4_JDR4_Msk (0xFFFFUL << ADC_JDR4_JDR4_Pos) /*!< 0x0000FFFF */ +#define ADC_JDR4_JDR4 ADC_JDR4_JDR4_Msk + +/*!< ADC_DR */ +#define ADC_DR_DATA_Pos (0U) +#define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ +#define ADC_DR_DATA ADC_DR_DATA_Msk + +/*!< ADC_CCSR */ +#define ADC_CCSR_CALSEL_Pos (11U) +#define ADC_CCSR_CALSEL_Msk (0x1UL << ADC_CCSR_CALSEL_Pos) /*!< 0x00000800 */ +#define ADC_CCSR_CALSEL ADC_CCSR_CALSEL_Msk /*!< desc CALSEL */ +#define ADC_CCSR_CALSMP_Pos (12U) +#define ADC_CCSR_CALSMP_Msk (0x3UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00003000 */ +#define ADC_CCSR_CALSMP ADC_CCSR_CALSMP_Msk /*!< CALSMP[13:12] bits (desc CALSMP) */ +#define ADC_CCSR_CALSMP_0 (0x1UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00001000 */ +#define ADC_CCSR_CALSMP_1 (0x2UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00002000 */ +#define ADC_CCSR_CALBYP_Pos (14U) +#define ADC_CCSR_CALBYP_Msk (0x1UL << ADC_CCSR_CALBYP_Pos) /*!< 0x00004000 */ +#define ADC_CCSR_CALBYP ADC_CCSR_CALBYP_Msk /*!< desc CALBYP */ +#define ADC_CCSR_CALSET_Pos (15U) +#define ADC_CCSR_CALSET_Msk (0x1UL << ADC_CCSR_CALSET_Pos) /*!< 0x00008000 */ +#define ADC_CCSR_CALSET ADC_CCSR_CALSET_Msk /*!< desc CALSET */ +#define ADC_CCSR_CALFAIL_Pos (30U) +#define ADC_CCSR_CALFAIL_Msk (0x1UL << ADC_CCSR_CALFAIL_Pos) /*!< 0x40000000 */ +#define ADC_CCSR_CALFAIL ADC_CCSR_CALFAIL_Msk /*!< desc CALFAIL */ +#define ADC_CCSR_CALON_Pos (31U) +#define ADC_CCSR_CALON_Msk (0x1UL << ADC_CCSR_CALON_Pos) /*!< 0x80000000 */ +#define ADC_CCSR_CALON ADC_CCSR_CALON_Msk + +/*!< ADC_CALRR1 */ +#define ADC_CALRR1_CALC10OUT_Pos (0U) +#define ADC_CALRR1_CALC10OUT_Msk (0xFFUL << ADC_CALRR1_CALC10OUT_Pos) /*!< 0x000000FF */ +#define ADC_CALRR1_CALC10OUT ADC_CALRR1_CALC10OUT_Msk /*!< CALC10OUT[7:0] bits (desc CALC10OUT) */ +#define ADC_CALRR1_CALC11OUT_Pos (8U) +#define ADC_CALRR1_CALC11OUT_Msk (0xFFUL << ADC_CALRR1_CALC11OUT_Pos) /*!< 0x0000FF00 */ +#define ADC_CALRR1_CALC11OUT ADC_CALRR1_CALC11OUT_Msk /*!< CALC11OUT[15:8] bits (desc CALC11OUT) */ +#define ADC_CALRR1_CALBOUT_Pos (16U) +#define ADC_CALRR1_CALBOUT_Msk (0x1FFUL << ADC_CALRR1_CALBOUT_Pos) /*!< 0x00FF0000 */ +#define ADC_CALRR1_CALBOUT ADC_CALRR1_CALBOUT_Msk + +/*!< ADC_CALRR2 */ +#define ADC_CALRR2_CALC6OUT_Pos (0U) +#define ADC_CALRR2_CALC6OUT_Msk (0xFFUL << ADC_CALRR2_CALC6OUT_Pos) /*!< 0x000000FF */ +#define ADC_CALRR2_CALC6OUT ADC_CALRR2_CALC6OUT_Msk /*!< CALC6OUT[7:0] bits (desc CALC6OUT) */ +#define ADC_CALRR2_CALC7OUT_Pos (8U) +#define ADC_CALRR2_CALC7OUT_Msk (0xFFUL << ADC_CALRR2_CALC7OUT_Pos) /*!< 0x0000FF00 */ +#define ADC_CALRR2_CALC7OUT ADC_CALRR2_CALC7OUT_Msk /*!< CALC7OUT[15:8] bits (desc CALC7OUT) */ +#define ADC_CALRR2_CALC8OUT_Pos (16U) +#define ADC_CALRR2_CALC8OUT_Msk (0xFFUL << ADC_CALRR2_CALC8OUT_Pos) /*!< 0x00FF0000 */ +#define ADC_CALRR2_CALC8OUT ADC_CALRR2_CALC8OUT_Msk /*!< CALC8OUT[23:16] bits (desc CALC8OUT) */ +#define ADC_CALRR2_CALC9OUT_Pos (24U) +#define ADC_CALRR2_CALC9OUT_Msk (0xFFUL << ADC_CALRR2_CALC9OUT_Pos) /*!< 0xFF000000 */ +#define ADC_CALRR2_CALC9OUT ADC_CALRR2_CALC9OUT_Msk /*!< CALC9OUT[31:24] bits (desc CALC9OUT) */ + +/*!< ADC_CALFIR1 */ +#define ADC_CALFIR1_CALC10IO_Pos (0U) +#define ADC_CALFIR1_CALC10IO_Msk (0xFFUL << ADC_CALFIR1_CALC10IO_Pos) /*!< 0x000000FF */ +#define ADC_CALFIR1_CALC10IO ADC_CALFIR1_CALC10IO_Msk /*!< CALC10IO[7:0] bits (desc CALC10IO) */ +#define ADC_CALFIR1_CALC11IO_Pos (8U) +#define ADC_CALFIR1_CALC11IO_Msk (0xFFUL << ADC_CALFIR1_CALC11IO_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFIR1_CALC11IO ADC_CALFIR1_CALC11IO_Msk /*!< CALC11IO[15:8] bits (desc CALC11IO) */ +#define ADC_CALFIR1_CALBIO_Pos (16U) +#define ADC_CALFIR1_CALBIO_Msk (0x1FFUL << ADC_CALFIR1_CALBIO_Pos) /*!< 0x00FF0000 */ +#define ADC_CALFIR1_CALBIO ADC_CALFIR1_CALBIO_Msk + +/*!< ADC_CALFIR2 */ +#define ADC_CALFIR2_CALC6IO_Pos (0U) +#define ADC_CALFIR2_CALC6IO_Msk (0xFFUL << ADC_CALFIR2_CALC6IO_Pos) /*!< 0x000000FF */ +#define ADC_CALFIR2_CALC6IO ADC_CALFIR2_CALC6IO_Msk /*!< CALC6IO[7:0] bits (desc CALC6IO) */ +#define ADC_CALFIR2_CALC7IO_Pos (8U) +#define ADC_CALFIR2_CALC7IO_Msk (0xFFUL << ADC_CALFIR2_CALC7IO_Pos) /*!< 0x0000FF00 */ +#define ADC_CALFIR2_CALC7IO ADC_CALFIR2_CALC7IO_Msk /*!< CALC7IO[15:8] bits (desc CALC7IO) */ +#define ADC_CALFIR2_CALC8IO_Pos (16U) +#define ADC_CALFIR2_CALC8IO_Msk (0xFFUL << ADC_CALFIR2_CALC8IO_Pos) /*!< 0x00FF0000 */ +#define ADC_CALFIR2_CALC8IO ADC_CALFIR2_CALC8IO_Msk /*!< CALC8IO[23:16] bits (desc CALC8IO) */ +#define ADC_CALFIR2_CALC9IO_Pos (24U) +#define ADC_CALFIR2_CALC9IO_Msk (0xFFUL << ADC_CALFIR2_CALC9IO_Pos) /*!< 0xFF000000 */ +#define ADC_CALFIR2_CALC9IO ADC_CALFIR2_CALC9IO_Msk + +/****************************************************************************/ +/* */ +/* Controller Area Network(CAN) */ +/* */ +/****************************************************************************/ +/********************* Bits Define For Peripheral CAN *********************/ +/*!< CAN_TSNCR */ +#define CAN_TSNCR_VERSION_Pos (0U) +#define CAN_TSNCR_VERSION_Msk (0xFFFFUL << CAN_TSNCR_VERSION_Pos) /*!< 0x0000FFFF */ +#define CAN_TSNCR_VERSION CAN_TSNCR_VERSION_Msk /*!< VERSION[15:0] bits (desc VERSION) */ +#define CAN_TSNCR_CES_Pos (16U) +#define CAN_TSNCR_CES_Msk (0x1UL << CAN_TSNCR_CES_Pos) /*!< 0x00010000 */ +#define CAN_TSNCR_CES CAN_TSNCR_CES_Msk /*!< desc CES */ +#define CAN_TSNCR_ROP_Pos (17U) +#define CAN_TSNCR_ROP_Msk (0x1UL << CAN_TSNCR_ROP_Pos) /*!< 0x00020000 */ +#define CAN_TSNCR_ROP CAN_TSNCR_ROP_Msk /*!< desc ROP */ +#define CAN_TSNCR_TMSE_Pos (18U) +#define CAN_TSNCR_TMSE_Msk (0x1UL << CAN_TSNCR_TMSE_Pos) /*!< 0x00040000 */ +#define CAN_TSNCR_TMSE CAN_TSNCR_TMSE_Msk /*!< desc TMSE */ +#define CAN_TSNCR_TSEN_Pos (24U) +#define CAN_TSNCR_TSEN_Msk (0x1UL << CAN_TSNCR_TSEN_Pos) /*!< 0x01000000 */ +#define CAN_TSNCR_TSEN CAN_TSNCR_TSEN_Msk /*!< desc TSEN */ +#define CAN_TSNCR_TSPOS_Pos (25U) +#define CAN_TSNCR_TSPOS_Msk (0x1UL << CAN_TSNCR_TSPOS_Pos) /*!< 0x02000000 */ +#define CAN_TSNCR_TSPOS CAN_TSNCR_TSPOS_Msk /*!< desc TSPOS */ + +/*!< CAN_ACBTR */ +#define CAN_ACBTR_AC_SEG_1_Pos (0U) +#define CAN_ACBTR_AC_SEG_1_Msk (0x1FFUL << CAN_ACBTR_AC_SEG_1_Pos) /*!< 0x000001FF */ +#define CAN_ACBTR_AC_SEG_1 CAN_ACBTR_AC_SEG_1_Msk /*!< AC_SEG_1[8:0] bits (desc AC_SEG_1) */ +#define CAN_ACBTR_AC_SEG_2_Pos (16U) +#define CAN_ACBTR_AC_SEG_2_Msk (0x7FUL << CAN_ACBTR_AC_SEG_2_Pos) /*!< 0x007F0000 */ +#define CAN_ACBTR_AC_SEG_2 CAN_ACBTR_AC_SEG_2_Msk /*!< AC_SEG_2[22:16] bits (desc AC_SEG_2) */ +#define CAN_ACBTR_AC_SEG_2_0 (0x1UL << CAN_ACBTR_AC_SEG_2_Pos) /*!< 0x00010000 */ +#define CAN_ACBTR_AC_SEG_2_1 (0x2UL << CAN_ACBTR_AC_SEG_2_Pos) /*!< 0x00020000 */ +#define CAN_ACBTR_AC_SEG_2_2 (0x4UL << CAN_ACBTR_AC_SEG_2_Pos) /*!< 0x00040000 */ +#define CAN_ACBTR_AC_SEG_2_3 (0x8UL << CAN_ACBTR_AC_SEG_2_Pos) /*!< 0x00080000 */ +#define CAN_ACBTR_AC_SEG_2_4 (0x10UL << CAN_ACBTR_AC_SEG_2_Pos) /*!< 0x00100000 */ +#define CAN_ACBTR_AC_SEG_2_5 (0x20UL << CAN_ACBTR_AC_SEG_2_Pos) /*!< 0x00200000 */ +#define CAN_ACBTR_AC_SEG_2_6 (0x40UL << CAN_ACBTR_AC_SEG_2_Pos) /*!< 0x00400000 */ +#define CAN_ACBTR_AC_SJW_Pos (24U) +#define CAN_ACBTR_AC_SJW_Msk (0x7FUL << CAN_ACBTR_AC_SJW_Pos) /*!< 0x7F000000 */ +#define CAN_ACBTR_AC_SJW CAN_ACBTR_AC_SJW_Msk /*!< AC_SJW[30:24] bits (desc AC_SJW) */ +#define CAN_ACBTR_AC_SJW_0 (0x1UL << CAN_ACBTR_AC_SJW_Pos) /*!< 0x01000000 */ +#define CAN_ACBTR_AC_SJW_1 (0x2UL << CAN_ACBTR_AC_SJW_Pos) /*!< 0x02000000 */ +#define CAN_ACBTR_AC_SJW_2 (0x4UL << CAN_ACBTR_AC_SJW_Pos) /*!< 0x04000000 */ +#define CAN_ACBTR_AC_SJW_3 (0x8UL << CAN_ACBTR_AC_SJW_Pos) /*!< 0x08000000 */ +#define CAN_ACBTR_AC_SJW_4 (0x10UL << CAN_ACBTR_AC_SJW_Pos) /*!< 0x10000000 */ +#define CAN_ACBTR_AC_SJW_5 (0x20UL << CAN_ACBTR_AC_SJW_Pos) /*!< 0x20000000 */ +#define CAN_ACBTR_AC_SJW_6 (0x40UL << CAN_ACBTR_AC_SJW_Pos) /*!< 0x40000000 */ + +/*!< CAN_FDBTR */ +#define CAN_FDBTR_FD_SEG_1_Pos (0U) +#define CAN_FDBTR_FD_SEG_1_Msk (0xFFUL << CAN_FDBTR_FD_SEG_1_Pos) /*!< 0x000000FF */ +#define CAN_FDBTR_FD_SEG_1 CAN_FDBTR_FD_SEG_1_Msk /*!< FD_SEG_1[7:0] bits (desc FD_SEG_1) */ +#define CAN_FDBTR_FD_SEG_2_Pos (16U) +#define CAN_FDBTR_FD_SEG_2_Msk (0x7FUL << CAN_FDBTR_FD_SEG_2_Pos) /*!< 0x007F0000 */ +#define CAN_FDBTR_FD_SEG_2 CAN_FDBTR_FD_SEG_2_Msk /*!< FD_SEG_2[22:16] bits (desc FD_SEG_2) */ +#define CAN_FDBTR_FD_SEG_2_0 (0x1UL << CAN_FDBTR_FD_SEG_2_Pos) /*!< 0x00010000 */ +#define CAN_FDBTR_FD_SEG_2_1 (0x2UL << CAN_FDBTR_FD_SEG_2_Pos) /*!< 0x00020000 */ +#define CAN_FDBTR_FD_SEG_2_2 (0x4UL << CAN_FDBTR_FD_SEG_2_Pos) /*!< 0x00040000 */ +#define CAN_FDBTR_FD_SEG_2_3 (0x8UL << CAN_FDBTR_FD_SEG_2_Pos) /*!< 0x00080000 */ +#define CAN_FDBTR_FD_SEG_2_4 (0x10UL << CAN_FDBTR_FD_SEG_2_Pos) /*!< 0x00100000 */ +#define CAN_FDBTR_FD_SEG_2_5 (0x20UL << CAN_FDBTR_FD_SEG_2_Pos) /*!< 0x00200000 */ +#define CAN_FDBTR_FD_SEG_2_6 (0x40UL << CAN_FDBTR_FD_SEG_2_Pos) /*!< 0x00400000 */ +#define CAN_FDBTR_FD_SJW_Pos (24U) +#define CAN_FDBTR_FD_SJW_Msk (0x7FUL << CAN_FDBTR_FD_SJW_Pos) /*!< 0x7F000000 */ +#define CAN_FDBTR_FD_SJW CAN_FDBTR_FD_SJW_Msk /*!< FD_SJW[30:24] bits (desc FD_SJW) */ +#define CAN_FDBTR_FD_SJW_0 (0x1UL << CAN_FDBTR_FD_SJW_Pos) /*!< 0x01000000 */ +#define CAN_FDBTR_FD_SJW_1 (0x2UL << CAN_FDBTR_FD_SJW_Pos) /*!< 0x02000000 */ +#define CAN_FDBTR_FD_SJW_2 (0x4UL << CAN_FDBTR_FD_SJW_Pos) /*!< 0x04000000 */ +#define CAN_FDBTR_FD_SJW_3 (0x8UL << CAN_FDBTR_FD_SJW_Pos) /*!< 0x08000000 */ +#define CAN_FDBTR_FD_SJW_4 (0x10UL << CAN_FDBTR_FD_SJW_Pos) /*!< 0x10000000 */ +#define CAN_FDBTR_FD_SJW_5 (0x20UL << CAN_FDBTR_FD_SJW_Pos) /*!< 0x20000000 */ +#define CAN_FDBTR_FD_SJW_6 (0x40UL << CAN_FDBTR_FD_SJW_Pos) /*!< 0x40000000 */ + +/*!< CAN_XLBTR */ +#define CAN_XLBTR_XL_SEG_1_Pos (0U) +#define CAN_XLBTR_XL_SEG_1_Msk (0xFFUL << CAN_XLBTR_XL_SEG_1_Pos) /*!< 0x000000FF */ +#define CAN_XLBTR_XL_SEG_1 CAN_XLBTR_XL_SEG_1_Msk /*!< XL_SEG_1[7:0] bits (desc XL_SEG_1) */ +#define CAN_XLBTR_XL_SEG_2_Pos (16U) +#define CAN_XLBTR_XL_SEG_2_Msk (0x7FUL << CAN_XLBTR_XL_SEG_2_Pos) /*!< 0x007F0000 */ +#define CAN_XLBTR_XL_SEG_2 CAN_XLBTR_XL_SEG_2_Msk /*!< XL_SEG_2[22:16] bits (desc XL_SEG_2) */ +#define CAN_XLBTR_XL_SEG_2_0 (0x1UL << CAN_XLBTR_XL_SEG_2_Pos) /*!< 0x00010000 */ +#define CAN_XLBTR_XL_SEG_2_1 (0x2UL << CAN_XLBTR_XL_SEG_2_Pos) /*!< 0x00020000 */ +#define CAN_XLBTR_XL_SEG_2_2 (0x4UL << CAN_XLBTR_XL_SEG_2_Pos) /*!< 0x00040000 */ +#define CAN_XLBTR_XL_SEG_2_3 (0x8UL << CAN_XLBTR_XL_SEG_2_Pos) /*!< 0x00080000 */ +#define CAN_XLBTR_XL_SEG_2_4 (0x10UL << CAN_XLBTR_XL_SEG_2_Pos) /*!< 0x00100000 */ +#define CAN_XLBTR_XL_SEG_2_5 (0x20UL << CAN_XLBTR_XL_SEG_2_Pos) /*!< 0x00200000 */ +#define CAN_XLBTR_XL_SEG_2_6 (0x40UL << CAN_XLBTR_XL_SEG_2_Pos) /*!< 0x00400000 */ +#define CAN_XLBTR_XL_SJW_Pos (24U) +#define CAN_XLBTR_XL_SJW_Msk (0x7FUL << CAN_XLBTR_XL_SJW_Pos) /*!< 0x7F000000 */ +#define CAN_XLBTR_XL_SJW CAN_XLBTR_XL_SJW_Msk /*!< XL_SJW[30:24] bits (desc XL_SJW) */ +#define CAN_XLBTR_XL_SJW_0 (0x1UL << CAN_XLBTR_XL_SJW_Pos) /*!< 0x01000000 */ +#define CAN_XLBTR_XL_SJW_1 (0x2UL << CAN_XLBTR_XL_SJW_Pos) /*!< 0x02000000 */ +#define CAN_XLBTR_XL_SJW_2 (0x4UL << CAN_XLBTR_XL_SJW_Pos) /*!< 0x04000000 */ +#define CAN_XLBTR_XL_SJW_3 (0x8UL << CAN_XLBTR_XL_SJW_Pos) /*!< 0x08000000 */ +#define CAN_XLBTR_XL_SJW_4 (0x10UL << CAN_XLBTR_XL_SJW_Pos) /*!< 0x10000000 */ +#define CAN_XLBTR_XL_SJW_5 (0x20UL << CAN_XLBTR_XL_SJW_Pos) /*!< 0x20000000 */ +#define CAN_XLBTR_XL_SJW_6 (0x40UL << CAN_XLBTR_XL_SJW_Pos) /*!< 0x40000000 */ + +/*!< CAN_RLSSP */ +#define CAN_RLSSP_PRESC_Pos (0U) +#define CAN_RLSSP_PRESC_Msk (0x1FUL << CAN_RLSSP_PRESC_Pos) /*!< 0x0000001F */ +#define CAN_RLSSP_PRESC CAN_RLSSP_PRESC_Msk /*!< PRESC[4:0] bits (desc PRESC) */ +#define CAN_RLSSP_PRESC_0 (0x1UL << CAN_RLSSP_PRESC_Pos) /*!< 0x00000001 */ +#define CAN_RLSSP_PRESC_1 (0x2UL << CAN_RLSSP_PRESC_Pos) /*!< 0x00000002 */ +#define CAN_RLSSP_PRESC_2 (0x4UL << CAN_RLSSP_PRESC_Pos) /*!< 0x00000004 */ +#define CAN_RLSSP_PRESC_3 (0x8UL << CAN_RLSSP_PRESC_Pos) /*!< 0x00000008 */ +#define CAN_RLSSP_PRESC_4 (0x10UL << CAN_RLSSP_PRESC_Pos) /*!< 0x00000010 */ +#define CAN_RLSSP_FD_SSPOFF_Pos (8U) +#define CAN_RLSSP_FD_SSPOFF_Msk (0xFFUL << CAN_RLSSP_FD_SSPOFF_Pos) /*!< 0x0000FF00 */ +#define CAN_RLSSP_FD_SSPOFF CAN_RLSSP_FD_SSPOFF_Msk /*!< FD_SSPOFF[15:8] bits (desc FD_SSPOFF) */ +#define CAN_RLSSP_XL_SSPOFF_Pos (16U) +#define CAN_RLSSP_XL_SSPOFF_Msk (0xFFUL << CAN_RLSSP_XL_SSPOFF_Pos) /*!< 0x00FF0000 */ +#define CAN_RLSSP_XL_SSPOFF CAN_RLSSP_XL_SSPOFF_Msk /*!< XL_SSPOFF[23:16] bits (desc XL_SSPOFF) */ +#define CAN_RLSSP_REALIM_Pos (24U) +#define CAN_RLSSP_REALIM_Msk (0x7UL << CAN_RLSSP_REALIM_Pos) /*!< 0x07000000 */ +#define CAN_RLSSP_REALIM CAN_RLSSP_REALIM_Msk /*!< REALIM[26:24] bits (desc REALIM) */ +#define CAN_RLSSP_REALIM_0 (0x1UL << CAN_RLSSP_REALIM_Pos) /*!< 0x01000000 */ +#define CAN_RLSSP_REALIM_1 (0x2UL << CAN_RLSSP_REALIM_Pos) /*!< 0x02000000 */ +#define CAN_RLSSP_REALIM_2 (0x4UL << CAN_RLSSP_REALIM_Pos) /*!< 0x04000000 */ +#define CAN_RLSSP_RETLIM_Pos (28U) +#define CAN_RLSSP_RETLIM_Msk (0x7UL << CAN_RLSSP_RETLIM_Pos) /*!< 0x70000000 */ +#define CAN_RLSSP_RETLIM CAN_RLSSP_RETLIM_Msk /*!< RETLIM[30:28] bits (desc RETLIM) */ +#define CAN_RLSSP_RETLIM_0 (0x1UL << CAN_RLSSP_RETLIM_Pos) /*!< 0x10000000 */ +#define CAN_RLSSP_RETLIM_1 (0x2UL << CAN_RLSSP_RETLIM_Pos) /*!< 0x20000000 */ +#define CAN_RLSSP_RETLIM_2 (0x4UL << CAN_RLSSP_RETLIM_Pos) /*!< 0x40000000 */ + +/*!< CAN_IFR */ +#define CAN_IFR_AIF_Pos (0U) +#define CAN_IFR_AIF_Msk (0x1UL << CAN_IFR_AIF_Pos) /*!< 0x00000001 */ +#define CAN_IFR_AIF CAN_IFR_AIF_Msk /*!< desc AIF */ +#define CAN_IFR_EIF_Pos (1U) +#define CAN_IFR_EIF_Msk (0x1UL << CAN_IFR_EIF_Pos) /*!< 0x00000002 */ +#define CAN_IFR_EIF CAN_IFR_EIF_Msk /*!< desc EIF */ +#define CAN_IFR_TSIF_Pos (2U) +#define CAN_IFR_TSIF_Msk (0x1UL << CAN_IFR_TSIF_Pos) /*!< 0x00000004 */ +#define CAN_IFR_TSIF CAN_IFR_TSIF_Msk /*!< desc TSIF */ +#define CAN_IFR_TPIF_Pos (3U) +#define CAN_IFR_TPIF_Msk (0x1UL << CAN_IFR_TPIF_Pos) /*!< 0x00000008 */ +#define CAN_IFR_TPIF CAN_IFR_TPIF_Msk /*!< desc TPIF */ +#define CAN_IFR_RAFIF_Pos (4U) +#define CAN_IFR_RAFIF_Msk (0x1UL << CAN_IFR_RAFIF_Pos) /*!< 0x00000010 */ +#define CAN_IFR_RAFIF CAN_IFR_RAFIF_Msk /*!< desc RAFIF */ +#define CAN_IFR_RFIF_Pos (5U) +#define CAN_IFR_RFIF_Msk (0x1UL << CAN_IFR_RFIF_Pos) /*!< 0x00000020 */ +#define CAN_IFR_RFIF CAN_IFR_RFIF_Msk /*!< desc RFIF */ +#define CAN_IFR_ROIF_Pos (6U) +#define CAN_IFR_ROIF_Msk (0x1UL << CAN_IFR_ROIF_Pos) /*!< 0x00000040 */ +#define CAN_IFR_ROIF CAN_IFR_ROIF_Msk /*!< desc ROIF */ +#define CAN_IFR_RIF_Pos (7U) +#define CAN_IFR_RIF_Msk (0x1UL << CAN_IFR_RIF_Pos) /*!< 0x00000080 */ +#define CAN_IFR_RIF CAN_IFR_RIF_Msk /*!< desc RIF */ +#define CAN_IFR_BEIF_Pos (8U) +#define CAN_IFR_BEIF_Msk (0x1UL << CAN_IFR_BEIF_Pos) /*!< 0x00000100 */ +#define CAN_IFR_BEIF CAN_IFR_BEIF_Msk /*!< desc BEIF */ +#define CAN_IFR_ALIF_Pos (9U) +#define CAN_IFR_ALIF_Msk (0x1UL << CAN_IFR_ALIF_Pos) /*!< 0x00000200 */ +#define CAN_IFR_ALIF CAN_IFR_ALIF_Msk /*!< desc ALIF */ +#define CAN_IFR_EPIF_Pos (10U) +#define CAN_IFR_EPIF_Msk (0x1UL << CAN_IFR_EPIF_Pos) /*!< 0x00000400 */ +#define CAN_IFR_EPIF CAN_IFR_EPIF_Msk /*!< desc EPIF */ +#define CAN_IFR_TTIF_Pos (11U) +#define CAN_IFR_TTIF_Msk (0x1UL << CAN_IFR_TTIF_Pos) /*!< 0x00000800 */ +#define CAN_IFR_TTIF CAN_IFR_TTIF_Msk /*!< desc TTIF */ +#define CAN_IFR_TEIF_Pos (12U) +#define CAN_IFR_TEIF_Msk (0x1UL << CAN_IFR_TEIF_Pos) /*!< 0x00001000 */ +#define CAN_IFR_TEIF CAN_IFR_TEIF_Msk /*!< desc TEIF */ +#define CAN_IFR_WTIF_Pos (13U) +#define CAN_IFR_WTIF_Msk (0x1UL << CAN_IFR_WTIF_Pos) /*!< 0x00002000 */ +#define CAN_IFR_WTIF CAN_IFR_WTIF_Msk /*!< desc WTIF */ +#define CAN_IFR_MDWIF_Pos (14U) +#define CAN_IFR_MDWIF_Msk (0x1UL << CAN_IFR_MDWIF_Pos) /*!< 0x00004000 */ +#define CAN_IFR_MDWIF CAN_IFR_MDWIF_Msk /*!< desc MDWIF */ +#define CAN_IFR_MDEIF_Pos (15U) +#define CAN_IFR_MDEIF_Msk (0x1UL << CAN_IFR_MDEIF_Pos) /*!< 0x00008000 */ +#define CAN_IFR_MDEIF CAN_IFR_MDEIF_Msk /*!< desc MDEIF */ +#define CAN_IFR_MAEIF_Pos (16U) +#define CAN_IFR_MAEIF_Msk (0x1UL << CAN_IFR_MAEIF_Pos) /*!< 0x00010000 */ +#define CAN_IFR_MAEIF CAN_IFR_MAEIF_Msk /*!< desc MAEIF */ +#define CAN_IFR_SEIF_Pos (17U) +#define CAN_IFR_SEIF_Msk (0x1UL << CAN_IFR_SEIF_Pos) /*!< 0x00020000 */ +#define CAN_IFR_SEIF CAN_IFR_SEIF_Msk /*!< desc SEIF */ +#define CAN_IFR_SWIF_Pos (18U) +#define CAN_IFR_SWIF_Msk (0x1UL << CAN_IFR_SWIF_Pos) /*!< 0x00040000 */ +#define CAN_IFR_SWIF CAN_IFR_SWIF_Msk /*!< desc SWIF */ +#define CAN_IFR_EPASS_Pos (30U) +#define CAN_IFR_EPASS_Msk (0x1UL << CAN_IFR_EPASS_Pos) /*!< 0x40000000 */ +#define CAN_IFR_EPASS CAN_IFR_EPASS_Msk /*!< desc EPASS */ +#define CAN_IFR_EWARN_Pos (31U) +#define CAN_IFR_EWARN_Msk (0x1UL << CAN_IFR_EWARN_Pos) /*!< 0x80000000 */ +#define CAN_IFR_EWARN CAN_IFR_EWARN_Msk /*!< desc EWARN */ + +/*!< CAN_IER */ +#define CAN_IER_EIE_Pos (1U) +#define CAN_IER_EIE_Msk (0x1UL << CAN_IER_EIE_Pos) /*!< 0x00000002 */ +#define CAN_IER_EIE CAN_IER_EIE_Msk /*!< desc EIE */ +#define CAN_IER_TSIE_Pos (2U) +#define CAN_IER_TSIE_Msk (0x1UL << CAN_IER_TSIE_Pos) /*!< 0x00000004 */ +#define CAN_IER_TSIE CAN_IER_TSIE_Msk /*!< desc TSIE */ +#define CAN_IER_TPIE_Pos (3U) +#define CAN_IER_TPIE_Msk (0x1UL << CAN_IER_TPIE_Pos) /*!< 0x00000008 */ +#define CAN_IER_TPIE CAN_IER_TPIE_Msk /*!< desc TPIE */ +#define CAN_IER_RAFIE_Pos (4U) +#define CAN_IER_RAFIE_Msk (0x1UL << CAN_IER_RAFIE_Pos) /*!< 0x00000010 */ +#define CAN_IER_RAFIE CAN_IER_RAFIE_Msk /*!< desc RAFIE */ +#define CAN_IER_RFIE_Pos (5U) +#define CAN_IER_RFIE_Msk (0x1UL << CAN_IER_RFIE_Pos) /*!< 0x00000020 */ +#define CAN_IER_RFIE CAN_IER_RFIE_Msk /*!< desc RFIE */ +#define CAN_IER_ROIE_Pos (6U) +#define CAN_IER_ROIE_Msk (0x1UL << CAN_IER_ROIE_Pos) /*!< 0x00000040 */ +#define CAN_IER_ROIE CAN_IER_ROIE_Msk /*!< desc ROIE */ +#define CAN_IER_RIE_Pos (7U) +#define CAN_IER_RIE_Msk (0x1UL << CAN_IER_RIE_Pos) /*!< 0x00000080 */ +#define CAN_IER_RIE CAN_IER_RIE_Msk /*!< desc RIE */ +#define CAN_IER_BEIE_Pos (8U) +#define CAN_IER_BEIE_Msk (0x1UL << CAN_IER_BEIE_Pos) /*!< 0x00000100 */ +#define CAN_IER_BEIE CAN_IER_BEIE_Msk /*!< desc BEIE */ +#define CAN_IER_ALIE_Pos (9U) +#define CAN_IER_ALIE_Msk (0x1UL << CAN_IER_ALIE_Pos) /*!< 0x00000200 */ +#define CAN_IER_ALIE CAN_IER_ALIE_Msk /*!< desc ALIE */ +#define CAN_IER_EPIE_Pos (10U) +#define CAN_IER_EPIE_Msk (0x1UL << CAN_IER_EPIE_Pos) /*!< 0x00000400 */ +#define CAN_IER_EPIE CAN_IER_EPIE_Msk /*!< desc EPIE */ +#define CAN_IER_TTIE_Pos (11U) +#define CAN_IER_TTIE_Msk (0x1UL << CAN_IER_TTIE_Pos) /*!< 0x00000800 */ +#define CAN_IER_TTIE CAN_IER_TTIE_Msk /*!< desc TTIE */ +#define CAN_IER_WTIE_Pos (13U) +#define CAN_IER_WTIE_Msk (0x1UL << CAN_IER_WTIE_Pos) /*!< 0x00002000 */ +#define CAN_IER_WTIE CAN_IER_WTIE_Msk /*!< desc WTIE */ +#define CAN_IER_MDWIE_Pos (14U) +#define CAN_IER_MDWIE_Msk (0x1UL << CAN_IER_MDWIE_Pos) /*!< 0x00004000 */ +#define CAN_IER_MDWIE CAN_IER_MDWIE_Msk /*!< desc MDWIE */ +#define CAN_IER_SWIE_Pos (18U) +#define CAN_IER_SWIE_Msk (0x1UL << CAN_IER_SWIE_Pos) /*!< 0x00040000 */ +#define CAN_IER_SWIE CAN_IER_SWIE_Msk /*!< desc SWIE */ + +/*!< CAN_TSR */ +#define CAN_TSR_HANDLE_L_Pos (0U) +#define CAN_TSR_HANDLE_L_Msk (0xFFUL << CAN_TSR_HANDLE_L_Pos) /*!< 0x000000FF */ +#define CAN_TSR_HANDLE_L CAN_TSR_HANDLE_L_Msk /*!< HANDLE_L[7:0] bits (desc HANDLE_L) */ +#define CAN_TSR_TSTAT_L_Pos (8U) +#define CAN_TSR_TSTAT_L_Msk (0x7UL << CAN_TSR_TSTAT_L_Pos) /*!< 0x00000700 */ +#define CAN_TSR_TSTAT_L CAN_TSR_TSTAT_L_Msk /*!< TSTAT_L[10:8] bits (desc TSTAT_L) */ +#define CAN_TSR_TSTAT_L_0 (0x1UL << CAN_TSR_TSTAT_L_Pos) /*!< 0x00000100 */ +#define CAN_TSR_TSTAT_L_1 (0x2UL << CAN_TSR_TSTAT_L_Pos) /*!< 0x00000200 */ +#define CAN_TSR_TSTAT_L_2 (0x4UL << CAN_TSR_TSTAT_L_Pos) /*!< 0x00000400 */ +#define CAN_TSR_HANDLE_H_Pos (16U) +#define CAN_TSR_HANDLE_H_Msk (0xFFUL << CAN_TSR_HANDLE_H_Pos) /*!< 0x00FF0000 */ +#define CAN_TSR_HANDLE_H CAN_TSR_HANDLE_H_Msk /*!< HANDLE_H[23:16] bits (desc HANDLE_H) */ +#define CAN_TSR_TSTAT_H_Pos (24U) +#define CAN_TSR_TSTAT_H_Msk (0x7UL << CAN_TSR_TSTAT_H_Pos) /*!< 0x07000000 */ +#define CAN_TSR_TSTAT_H CAN_TSR_TSTAT_H_Msk /*!< TSTAT_H[26:24] bits (desc TSTAT_H) */ +#define CAN_TSR_TSTAT_H_0 (0x1UL << CAN_TSR_TSTAT_H_Pos) /*!< 0x01000000 */ +#define CAN_TSR_TSTAT_H_1 (0x2UL << CAN_TSR_TSTAT_H_Pos) /*!< 0x02000000 */ +#define CAN_TSR_TSTAT_H_2 (0x4UL << CAN_TSR_TSTAT_H_Pos) /*!< 0x04000000 */ + +/*!< CAN_TTSL */ +#define CAN_TTSL_TTS_Pos (0U) +#define CAN_TTSL_TTS_Msk (0xFFFFFFFFUL << CAN_TTSL_TTS_Pos) /*!< 0xFFFFFFFF */ +#define CAN_TTSL_TTS CAN_TTSL_TTS_Msk /*!< TTS[31:0] bits (desc TTS) */ + +/*!< CAN_TTSH */ +#define CAN_TTSH_TTS_Pos (0U) +#define CAN_TTSH_TTS_Msk (0xFFFFFFFFUL << CAN_TTSH_TTS_Pos) /*!< 0xFFFFFFFF */ +#define CAN_TTSH_TTS CAN_TTSH_TTS_Msk /*!< TTS[31:0] bits (desc TTS) */ + +/*!< CAN_MCR */ +#define CAN_MCR_BUSOFF_Pos (0U) +#define CAN_MCR_BUSOFF_Msk (0x1UL << CAN_MCR_BUSOFF_Pos) /*!< 0x00000001 */ +#define CAN_MCR_BUSOFF CAN_MCR_BUSOFF_Msk /*!< desc BUSOFF */ +#define CAN_MCR_LBMI_Pos (5U) +#define CAN_MCR_LBMI_Msk (0x1UL << CAN_MCR_LBMI_Pos) /*!< 0x00000020 */ +#define CAN_MCR_LBMI CAN_MCR_LBMI_Msk /*!< desc LBMI */ +#define CAN_MCR_LBME_Pos (6U) +#define CAN_MCR_LBME_Msk (0x1UL << CAN_MCR_LBME_Pos) /*!< 0x00000040 */ +#define CAN_MCR_LBME CAN_MCR_LBME_Msk /*!< desc LBME */ +#define CAN_MCR_RESET_Pos (7U) +#define CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos) /*!< 0x00000080 */ +#define CAN_MCR_RESET CAN_MCR_RESET_Msk /*!< desc RESET */ +#define CAN_MCR_TSA_Pos (8U) +#define CAN_MCR_TSA_Msk (0x1UL << CAN_MCR_TSA_Pos) /*!< 0x00000100 */ +#define CAN_MCR_TSA CAN_MCR_TSA_Msk /*!< desc TSA */ +#define CAN_MCR_TSALL_Pos (9U) +#define CAN_MCR_TSALL_Msk (0x1UL << CAN_MCR_TSALL_Pos) /*!< 0x00000200 */ +#define CAN_MCR_TSALL CAN_MCR_TSALL_Msk /*!< desc TSALL */ +#define CAN_MCR_TSONE_Pos (10U) +#define CAN_MCR_TSONE_Msk (0x1UL << CAN_MCR_TSONE_Pos) /*!< 0x00000400 */ +#define CAN_MCR_TSONE CAN_MCR_TSONE_Msk /*!< desc TSONE */ +#define CAN_MCR_TPA_Pos (11U) +#define CAN_MCR_TPA_Msk (0x1UL << CAN_MCR_TPA_Pos) /*!< 0x00000800 */ +#define CAN_MCR_TPA CAN_MCR_TPA_Msk /*!< desc TPA */ +#define CAN_MCR_TPE_Pos (12U) +#define CAN_MCR_TPE_Msk (0x1UL << CAN_MCR_TPE_Pos) /*!< 0x00001000 */ +#define CAN_MCR_TPE CAN_MCR_TPE_Msk /*!< desc TPE */ +#define CAN_MCR_STBY_Pos (13U) +#define CAN_MCR_STBY_Msk (0x1UL << CAN_MCR_STBY_Pos) /*!< 0x00002000 */ +#define CAN_MCR_STBY CAN_MCR_STBY_Msk /*!< desc STBY */ +#define CAN_MCR_LOM_Pos (14U) +#define CAN_MCR_LOM_Msk (0x1UL << CAN_MCR_LOM_Pos) /*!< 0x00004000 */ +#define CAN_MCR_LOM CAN_MCR_LOM_Msk /*!< desc LOM */ +#define CAN_MCR_TBSEL_Pos (15U) +#define CAN_MCR_TBSEL_Msk (0x1UL << CAN_MCR_TBSEL_Pos) /*!< 0x00008000 */ +#define CAN_MCR_TBSEL CAN_MCR_TBSEL_Msk /*!< desc TBSEL */ +#define CAN_MCR_TSSTAT_Pos (16U) +#define CAN_MCR_TSSTAT_Msk (0x3UL << CAN_MCR_TSSTAT_Pos) /*!< 0x00030000 */ +#define CAN_MCR_TSSTAT CAN_MCR_TSSTAT_Msk /*!< TSSTAT[17:16] bits (desc TSSTAT) */ +#define CAN_MCR_TSSTAT_0 (0x1UL << CAN_MCR_TSSTAT_Pos) /*!< 0x00010000 */ +#define CAN_MCR_TSSTAT_1 (0x2UL << CAN_MCR_TSSTAT_Pos) /*!< 0x00020000 */ +#define CAN_MCR_TSFF_Pos (18U) +#define CAN_MCR_TSFF_Msk (0x1UL << CAN_MCR_TSFF_Pos) /*!< 0x00040000 */ +#define CAN_MCR_TSFF CAN_MCR_TSFF_Msk /*!< desc TSFF */ +#define CAN_MCR_TTTBM_Pos (20U) +#define CAN_MCR_TTTBM_Msk (0x1UL << CAN_MCR_TTTBM_Pos) /*!< 0x00100000 */ +#define CAN_MCR_TTTBM CAN_MCR_TTTBM_Msk /*!< desc TTTBM */ +#define CAN_MCR_TSMODE_Pos (21U) +#define CAN_MCR_TSMODE_Msk (0x1UL << CAN_MCR_TSMODE_Pos) /*!< 0x00200000 */ +#define CAN_MCR_TSMODE CAN_MCR_TSMODE_Msk /*!< desc TSMODE */ +#define CAN_MCR_TSNEXT_Pos (22U) +#define CAN_MCR_TSNEXT_Msk (0x1UL << CAN_MCR_TSNEXT_Pos) /*!< 0x00400000 */ +#define CAN_MCR_TSNEXT CAN_MCR_TSNEXT_Msk /*!< desc TSNEXT */ +#define CAN_MCR_FD_ISO_Pos (23U) +#define CAN_MCR_FD_ISO_Msk (0x1UL << CAN_MCR_FD_ISO_Pos) /*!< 0x00800000 */ +#define CAN_MCR_FD_ISO CAN_MCR_FD_ISO_Msk /*!< desc FD_ISO */ +#define CAN_MCR_RSTAT_Pos (24U) +#define CAN_MCR_RSTAT_Msk (0x3UL << CAN_MCR_RSTAT_Pos) /*!< 0x03000000 */ +#define CAN_MCR_RSTAT CAN_MCR_RSTAT_Msk /*!< RSTAT[25:24] bits (desc RSTAT) */ +#define CAN_MCR_RSTAT_0 (0x1UL << CAN_MCR_RSTAT_Pos) /*!< 0x01000000 */ +#define CAN_MCR_RSTAT_1 (0x2UL << CAN_MCR_RSTAT_Pos) /*!< 0x02000000 */ +#define CAN_MCR_RBALL_Pos (27U) +#define CAN_MCR_RBALL_Msk (0x1UL << CAN_MCR_RBALL_Pos) /*!< 0x08000000 */ +#define CAN_MCR_RBALL CAN_MCR_RBALL_Msk /*!< desc RBALL */ +#define CAN_MCR_RREL_Pos (28U) +#define CAN_MCR_RREL_Msk (0x1UL << CAN_MCR_RREL_Pos) /*!< 0x10000000 */ +#define CAN_MCR_RREL CAN_MCR_RREL_Msk /*!< desc RREL */ +#define CAN_MCR_ROV_Pos (29U) +#define CAN_MCR_ROV_Msk (0x1UL << CAN_MCR_ROV_Pos) /*!< 0x20000000 */ +#define CAN_MCR_ROV CAN_MCR_ROV_Msk /*!< desc ROV */ +#define CAN_MCR_ROM_Pos (30U) +#define CAN_MCR_ROM_Msk (0x1UL << CAN_MCR_ROM_Pos) /*!< 0x40000000 */ +#define CAN_MCR_ROM CAN_MCR_ROM_Msk /*!< desc ROM */ +#define CAN_MCR_SACK_Pos (31U) +#define CAN_MCR_SACK_Msk (0x1UL << CAN_MCR_SACK_Pos) /*!< 0x80000000 */ +#define CAN_MCR_SACK CAN_MCR_SACK_Msk /*!< desc SACK */ + +/*!< CAN_WECR */ +#define CAN_WECR_EWL_Pos (0U) +#define CAN_WECR_EWL_Msk (0xFUL << CAN_WECR_EWL_Pos) /*!< 0x0000000F */ +#define CAN_WECR_EWL CAN_WECR_EWL_Msk /*!< EWL[3:0] bits (desc EWL) */ +#define CAN_WECR_EWL_0 (0x1UL << CAN_WECR_EWL_Pos) /*!< 0x00000001 */ +#define CAN_WECR_EWL_1 (0x2UL << CAN_WECR_EWL_Pos) /*!< 0x00000002 */ +#define CAN_WECR_EWL_2 (0x4UL << CAN_WECR_EWL_Pos) /*!< 0x00000004 */ +#define CAN_WECR_EWL_3 (0x8UL << CAN_WECR_EWL_Pos) /*!< 0x00000008 */ +#define CAN_WECR_AFWL_Pos (4U) +#define CAN_WECR_AFWL_Msk (0xFUL << CAN_WECR_AFWL_Pos) /*!< 0x000000F0 */ +#define CAN_WECR_AFWL CAN_WECR_AFWL_Msk /*!< AFWL[7:4] bits (desc AFWL) */ +#define CAN_WECR_AFWL_0 (0x1UL << CAN_WECR_AFWL_Pos) /*!< 0x00000010 */ +#define CAN_WECR_AFWL_1 (0x2UL << CAN_WECR_AFWL_Pos) /*!< 0x00000020 */ +#define CAN_WECR_AFWL_2 (0x4UL << CAN_WECR_AFWL_Pos) /*!< 0x00000040 */ +#define CAN_WECR_AFWL_3 (0x8UL << CAN_WECR_AFWL_Pos) /*!< 0x00000080 */ +#define CAN_WECR_ALC_Pos (8U) +#define CAN_WECR_ALC_Msk (0x1FUL << CAN_WECR_ALC_Pos) /*!< 0x00001F00 */ +#define CAN_WECR_ALC CAN_WECR_ALC_Msk /*!< ALC[12:8] bits (desc ALC) */ +#define CAN_WECR_ALC_0 (0x1UL << CAN_WECR_ALC_Pos) /*!< 0x00000100 */ +#define CAN_WECR_ALC_1 (0x2UL << CAN_WECR_ALC_Pos) /*!< 0x00000200 */ +#define CAN_WECR_ALC_2 (0x4UL << CAN_WECR_ALC_Pos) /*!< 0x00000400 */ +#define CAN_WECR_ALC_3 (0x8UL << CAN_WECR_ALC_Pos) /*!< 0x00000800 */ +#define CAN_WECR_ALC_4 (0x10UL << CAN_WECR_ALC_Pos) /*!< 0x00001000 */ +#define CAN_WECR_KOER_Pos (13U) +#define CAN_WECR_KOER_Msk (0x7UL << CAN_WECR_KOER_Pos) /*!< 0x0000E000 */ +#define CAN_WECR_KOER CAN_WECR_KOER_Msk /*!< KOER[15:13] bits (desc KOER) */ +#define CAN_WECR_KOER_0 (0x1UL << CAN_WECR_KOER_Pos) /*!< 0x00002000 */ +#define CAN_WECR_KOER_1 (0x2UL << CAN_WECR_KOER_Pos) /*!< 0x00004000 */ +#define CAN_WECR_KOER_2 (0x4UL << CAN_WECR_KOER_Pos) /*!< 0x00008000 */ +#define CAN_WECR_RECNT_Pos (16U) +#define CAN_WECR_RECNT_Msk (0xFFUL << CAN_WECR_RECNT_Pos) /*!< 0x00FF0000 */ +#define CAN_WECR_RECNT CAN_WECR_RECNT_Msk /*!< RECNT[23:16] bits (desc RECNT) */ +#define CAN_WECR_TECNT_Pos (24U) +#define CAN_WECR_TECNT_Msk (0xFFUL << CAN_WECR_TECNT_Pos) /*!< 0xFF000000 */ +#define CAN_WECR_TECNT CAN_WECR_TECNT_Msk /*!< TECNT[31:24] bits (desc TECNT) */ + +/*!< CAN_REFMSG */ +#define CAN_REFMSG_REF_ID_Pos (0U) +#define CAN_REFMSG_REF_ID_Msk (0x1FFFFFFFUL << CAN_REFMSG_REF_ID_Pos) /*!< 0x1FFFFFFF */ +#define CAN_REFMSG_REF_ID CAN_REFMSG_REF_ID_Msk /*!< REF_ID[28:0] bits (desc REF_ID) */ +#define CAN_REFMSG_REF_IDE_Pos (31U) +#define CAN_REFMSG_REF_IDE_Msk (0x1UL << CAN_REFMSG_REF_IDE_Pos) /*!< 0x80000000 */ +#define CAN_REFMSG_REF_IDE CAN_REFMSG_REF_IDE_Msk /*!< desc REF_IDE */ + +/*!< CAN_TTCR */ +#define CAN_TTCR_TTPTR_Pos (0U) +#define CAN_TTCR_TTPTR_Msk (0x3FUL << CAN_TTCR_TTPTR_Pos) /*!< 0x0000003F */ +#define CAN_TTCR_TTPTR CAN_TTCR_TTPTR_Msk /*!< TTPTR[5:0] bits (desc TTPTR) */ +#define CAN_TTCR_TTPTR_0 (0x1UL << CAN_TTCR_TTPTR_Pos) /*!< 0x00000001 */ +#define CAN_TTCR_TTPTR_1 (0x2UL << CAN_TTCR_TTPTR_Pos) /*!< 0x00000002 */ +#define CAN_TTCR_TTPTR_2 (0x4UL << CAN_TTCR_TTPTR_Pos) /*!< 0x00000004 */ +#define CAN_TTCR_TTPTR_3 (0x8UL << CAN_TTCR_TTPTR_Pos) /*!< 0x00000008 */ +#define CAN_TTCR_TTPTR_4 (0x10UL << CAN_TTCR_TTPTR_Pos) /*!< 0x00000010 */ +#define CAN_TTCR_TTPTR_5 (0x20UL << CAN_TTCR_TTPTR_Pos) /*!< 0x00000020 */ +#define CAN_TTCR_TTYPE_Pos (8U) +#define CAN_TTCR_TTYPE_Msk (0x7UL << CAN_TTCR_TTYPE_Pos) /*!< 0x00000700 */ +#define CAN_TTCR_TTYPE CAN_TTCR_TTYPE_Msk /*!< TTYPE[10:8] bits (desc TTYPE) */ +#define CAN_TTCR_TTYPE_0 (0x1UL << CAN_TTCR_TTYPE_Pos) /*!< 0x00000100 */ +#define CAN_TTCR_TTYPE_1 (0x2UL << CAN_TTCR_TTYPE_Pos) /*!< 0x00000200 */ +#define CAN_TTCR_TTYPE_2 (0x4UL << CAN_TTCR_TTYPE_Pos) /*!< 0x00000400 */ +#define CAN_TTCR_TEW_Pos (12U) +#define CAN_TTCR_TEW_Msk (0xFUL << CAN_TTCR_TEW_Pos) /*!< 0x0000F000 */ +#define CAN_TTCR_TEW CAN_TTCR_TEW_Msk /*!< TEW[15:12] bits (desc TEW) */ +#define CAN_TTCR_TEW_0 (0x1UL << CAN_TTCR_TEW_Pos) /*!< 0x00001000 */ +#define CAN_TTCR_TEW_1 (0x2UL << CAN_TTCR_TEW_Pos) /*!< 0x00002000 */ +#define CAN_TTCR_TEW_2 (0x4UL << CAN_TTCR_TEW_Pos) /*!< 0x00004000 */ +#define CAN_TTCR_TEW_3 (0x8UL << CAN_TTCR_TEW_Pos) /*!< 0x00008000 */ +#define CAN_TTCR_TBPTR_Pos (16U) +#define CAN_TTCR_TBPTR_Msk (0x3FUL << CAN_TTCR_TBPTR_Pos) /*!< 0x003F0000 */ +#define CAN_TTCR_TBPTR CAN_TTCR_TBPTR_Msk /*!< TBPTR[21:16] bits (desc TBPTR) */ +#define CAN_TTCR_TBPTR_0 (0x1UL << CAN_TTCR_TBPTR_Pos) /*!< 0x00010000 */ +#define CAN_TTCR_TBPTR_1 (0x2UL << CAN_TTCR_TBPTR_Pos) /*!< 0x00020000 */ +#define CAN_TTCR_TBPTR_2 (0x4UL << CAN_TTCR_TBPTR_Pos) /*!< 0x00040000 */ +#define CAN_TTCR_TBPTR_3 (0x8UL << CAN_TTCR_TBPTR_Pos) /*!< 0x00080000 */ +#define CAN_TTCR_TBPTR_4 (0x10UL << CAN_TTCR_TBPTR_Pos) /*!< 0x00100000 */ +#define CAN_TTCR_TBPTR_5 (0x20UL << CAN_TTCR_TBPTR_Pos) /*!< 0x00200000 */ +#define CAN_TTCR_TBF_Pos (22U) +#define CAN_TTCR_TBF_Msk (0x1UL << CAN_TTCR_TBF_Pos) /*!< 0x00400000 */ +#define CAN_TTCR_TBF CAN_TTCR_TBF_Msk /*!< desc TBF */ +#define CAN_TTCR_TBE_Pos (23U) +#define CAN_TTCR_TBE_Msk (0x1UL << CAN_TTCR_TBE_Pos) /*!< 0x00800000 */ +#define CAN_TTCR_TBE CAN_TTCR_TBE_Msk /*!< desc TBE */ +#define CAN_TTCR_TTEN_Pos (24U) +#define CAN_TTCR_TTEN_Msk (0x1UL << CAN_TTCR_TTEN_Pos) /*!< 0x01000000 */ +#define CAN_TTCR_TTEN CAN_TTCR_TTEN_Msk /*!< desc TTEN */ +#define CAN_TTCR_T_PRESC_Pos (25U) +#define CAN_TTCR_T_PRESC_Msk (0x3UL << CAN_TTCR_T_PRESC_Pos) /*!< 0x06000000 */ +#define CAN_TTCR_T_PRESC CAN_TTCR_T_PRESC_Msk /*!< T_PRESC[26:25] bits (desc T_PRESC) */ +#define CAN_TTCR_T_PRESC_0 (0x1UL << CAN_TTCR_T_PRESC_Pos) /*!< 0x02000000 */ +#define CAN_TTCR_T_PRESC_1 (0x2UL << CAN_TTCR_T_PRESC_Pos) /*!< 0x04000000 */ + +/*!< CAN_TTTR */ +#define CAN_TTTR_TT_TRIG_Pos (0U) +#define CAN_TTTR_TT_TRIG_Msk (0xFFFFUL << CAN_TTTR_TT_TRIG_Pos) /*!< 0x0000FFFF */ +#define CAN_TTTR_TT_TRIG CAN_TTTR_TT_TRIG_Msk /*!< TT_TRIG[15:0] bits (desc TT_TRIG) */ +#define CAN_TTTR_TT_WTRIG_Pos (16U) +#define CAN_TTTR_TT_WTRIG_Msk (0xFFFFUL << CAN_TTTR_TT_WTRIG_Pos) /*!< 0xFFFF0000 */ +#define CAN_TTTR_TT_WTRIG CAN_TTTR_TT_WTRIG_Msk /*!< TT_WTRIG[31:16] bits (desc TT_WTRIG) */ + +/*!< CAN_SCMS */ +#define CAN_SCMS_XMREN_Pos (0U) +#define CAN_SCMS_XMREN_Msk (0x1UL << CAN_SCMS_XMREN_Pos) /*!< 0x00000001 */ +#define CAN_SCMS_XMREN CAN_SCMS_XMREN_Msk /*!< desc XMREN */ +#define CAN_SCMS_FSTIM_Pos (1U) +#define CAN_SCMS_FSTIM_Msk (0x7UL << CAN_SCMS_FSTIM_Pos) /*!< 0x0000000E */ +#define CAN_SCMS_FSTIM CAN_SCMS_FSTIM_Msk /*!< FSTIM[3:1] bits (desc FSTIM) */ +#define CAN_SCMS_FSTIM_0 (0x1UL << CAN_SCMS_FSTIM_Pos) /*!< 0x00000002 */ +#define CAN_SCMS_FSTIM_1 (0x2UL << CAN_SCMS_FSTIM_Pos) /*!< 0x00000004 */ +#define CAN_SCMS_FSTIM_2 (0x4UL << CAN_SCMS_FSTIM_Pos) /*!< 0x00000008 */ +#define CAN_SCMS_ACFA_Pos (24U) +#define CAN_SCMS_ACFA_Msk (0x1UL << CAN_SCMS_ACFA_Pos) /*!< 0x01000000 */ +#define CAN_SCMS_ACFA CAN_SCMS_ACFA_Msk /*!< desc ACFA */ +#define CAN_SCMS_TXS_Pos (25U) +#define CAN_SCMS_TXS_Msk (0x1UL << CAN_SCMS_TXS_Pos) /*!< 0x02000000 */ +#define CAN_SCMS_TXS CAN_SCMS_TXS_Msk /*!< desc TXS */ +#define CAN_SCMS_TXB_Pos (26U) +#define CAN_SCMS_TXB_Msk (0x1UL << CAN_SCMS_TXB_Pos) /*!< 0x04000000 */ +#define CAN_SCMS_TXB CAN_SCMS_TXB_Msk /*!< desc TXB */ +#define CAN_SCMS_HELOC_Pos (27U) +#define CAN_SCMS_HELOC_Msk (0x3UL << CAN_SCMS_HELOC_Pos) /*!< 0x18000000 */ +#define CAN_SCMS_HELOC CAN_SCMS_HELOC_Msk /*!< HELOC[28:27] bits (desc HELOC) */ +#define CAN_SCMS_HELOC_0 (0x1UL << CAN_SCMS_HELOC_Pos) /*!< 0x08000000 */ +#define CAN_SCMS_HELOC_1 (0x2UL << CAN_SCMS_HELOC_Pos) /*!< 0x10000000 */ +#define CAN_SCMS_MPEN_Pos (31U) +#define CAN_SCMS_MPEN_Msk (0x1UL << CAN_SCMS_MPEN_Pos) /*!< 0x80000000 */ +#define CAN_SCMS_MPEN CAN_SCMS_MPEN_Msk /*!< desc MPEN */ + +/*!< CAN_MESR */ +#define CAN_MESR_MEBP1_Pos (0U) +#define CAN_MESR_MEBP1_Msk (0x3FUL << CAN_MESR_MEBP1_Pos) /*!< 0x0000003F */ +#define CAN_MESR_MEBP1 CAN_MESR_MEBP1_Msk /*!< MEBP1[5:0] bits (desc MEBP1) */ +#define CAN_MESR_MEBP1_0 (0x1UL << CAN_MESR_MEBP1_Pos) /*!< 0x00000001 */ +#define CAN_MESR_MEBP1_1 (0x2UL << CAN_MESR_MEBP1_Pos) /*!< 0x00000002 */ +#define CAN_MESR_MEBP1_2 (0x4UL << CAN_MESR_MEBP1_Pos) /*!< 0x00000004 */ +#define CAN_MESR_MEBP1_3 (0x8UL << CAN_MESR_MEBP1_Pos) /*!< 0x00000008 */ +#define CAN_MESR_MEBP1_4 (0x10UL << CAN_MESR_MEBP1_Pos) /*!< 0x00000010 */ +#define CAN_MESR_MEBP1_5 (0x20UL << CAN_MESR_MEBP1_Pos) /*!< 0x00000020 */ +#define CAN_MESR_ME1EE_Pos (6U) +#define CAN_MESR_ME1EE_Msk (0x1UL << CAN_MESR_ME1EE_Pos) /*!< 0x00000040 */ +#define CAN_MESR_ME1EE CAN_MESR_ME1EE_Msk /*!< desc ME1EE */ +#define CAN_MESR_MEAEE_Pos (7U) +#define CAN_MESR_MEAEE_Msk (0x1UL << CAN_MESR_MEAEE_Pos) /*!< 0x00000080 */ +#define CAN_MESR_MEAEE CAN_MESR_MEAEE_Msk /*!< desc MEAEE */ +#define CAN_MESR_MEBP2_Pos (8U) +#define CAN_MESR_MEBP2_Msk (0x3FUL << CAN_MESR_MEBP2_Pos) /*!< 0x00003F00 */ +#define CAN_MESR_MEBP2 CAN_MESR_MEBP2_Msk /*!< MEBP2[13:8] bits (desc MEBP2) */ +#define CAN_MESR_MEBP2_0 (0x1UL << CAN_MESR_MEBP2_Pos) /*!< 0x00000100 */ +#define CAN_MESR_MEBP2_1 (0x2UL << CAN_MESR_MEBP2_Pos) /*!< 0x00000200 */ +#define CAN_MESR_MEBP2_2 (0x4UL << CAN_MESR_MEBP2_Pos) /*!< 0x00000400 */ +#define CAN_MESR_MEBP2_3 (0x8UL << CAN_MESR_MEBP2_Pos) /*!< 0x00000800 */ +#define CAN_MESR_MEBP2_4 (0x10UL << CAN_MESR_MEBP2_Pos) /*!< 0x00001000 */ +#define CAN_MESR_MEBP2_5 (0x20UL << CAN_MESR_MEBP2_Pos) /*!< 0x00002000 */ +#define CAN_MESR_ME2EE_Pos (14U) +#define CAN_MESR_ME2EE_Msk (0x1UL << CAN_MESR_ME2EE_Pos) /*!< 0x00004000 */ +#define CAN_MESR_ME2EE CAN_MESR_ME2EE_Msk /*!< desc ME2EE */ +#define CAN_MESR_MEEEC_Pos (16U) +#define CAN_MESR_MEEEC_Msk (0xFUL << CAN_MESR_MEEEC_Pos) /*!< 0x000F0000 */ +#define CAN_MESR_MEEEC CAN_MESR_MEEEC_Msk /*!< MEEEC[19:16] bits (desc MEEEC) */ +#define CAN_MESR_MEEEC_0 (0x1UL << CAN_MESR_MEEEC_Pos) /*!< 0x00010000 */ +#define CAN_MESR_MEEEC_1 (0x2UL << CAN_MESR_MEEEC_Pos) /*!< 0x00020000 */ +#define CAN_MESR_MEEEC_2 (0x4UL << CAN_MESR_MEEEC_Pos) /*!< 0x00040000 */ +#define CAN_MESR_MEEEC_3 (0x8UL << CAN_MESR_MEEEC_Pos) /*!< 0x00080000 */ +#define CAN_MESR_MENEC_Pos (20U) +#define CAN_MESR_MENEC_Msk (0xFUL << CAN_MESR_MENEC_Pos) /*!< 0x00F00000 */ +#define CAN_MESR_MENEC CAN_MESR_MENEC_Msk /*!< MENEC[23:20] bits (desc MENEC) */ +#define CAN_MESR_MENEC_0 (0x1UL << CAN_MESR_MENEC_Pos) /*!< 0x00100000 */ +#define CAN_MESR_MENEC_1 (0x2UL << CAN_MESR_MENEC_Pos) /*!< 0x00200000 */ +#define CAN_MESR_MENEC_2 (0x4UL << CAN_MESR_MENEC_Pos) /*!< 0x00400000 */ +#define CAN_MESR_MENEC_3 (0x8UL << CAN_MESR_MENEC_Pos) /*!< 0x00800000 */ +#define CAN_MESR_MEL_Pos (24U) +#define CAN_MESR_MEL_Msk (0x3UL << CAN_MESR_MEL_Pos) /*!< 0x03000000 */ +#define CAN_MESR_MEL CAN_MESR_MEL_Msk /*!< MEL[25:24] bits (desc MEL) */ +#define CAN_MESR_MEL_0 (0x1UL << CAN_MESR_MEL_Pos) /*!< 0x01000000 */ +#define CAN_MESR_MEL_1 (0x2UL << CAN_MESR_MEL_Pos) /*!< 0x02000000 */ +#define CAN_MESR_MES_Pos (26U) +#define CAN_MESR_MES_Msk (0x1UL << CAN_MESR_MES_Pos) /*!< 0x04000000 */ +#define CAN_MESR_MES CAN_MESR_MES_Msk /*!< desc MES */ + +/*!< CAN_ACFCR */ +#define CAN_ACFCR_ACFADR_Pos (0U) +#define CAN_ACFCR_ACFADR_Msk (0xFUL << CAN_ACFCR_ACFADR_Pos) /*!< 0x0000000F */ +#define CAN_ACFCR_ACFADR CAN_ACFCR_ACFADR_Msk /*!< ACFADR[3:0] bits (desc ACFADR) */ +#define CAN_ACFCR_ACFADR_0 (0x1UL << CAN_ACFCR_ACFADR_Pos) /*!< 0x00000001 */ +#define CAN_ACFCR_ACFADR_1 (0x2UL << CAN_ACFCR_ACFADR_Pos) /*!< 0x00000002 */ +#define CAN_ACFCR_ACFADR_2 (0x4UL << CAN_ACFCR_ACFADR_Pos) /*!< 0x00000004 */ +#define CAN_ACFCR_ACFADR_3 (0x8UL << CAN_ACFCR_ACFADR_Pos) /*!< 0x00000008 */ +#define CAN_ACFCR_AE_0_Pos (16U) +#define CAN_ACFCR_AE_0_Msk (0x1UL << CAN_ACFCR_AE_0_Pos) /*!< 0x00010000 */ +#define CAN_ACFCR_AE_0 CAN_ACFCR_AE_0_Msk /*!< desc AE_0 */ +#define CAN_ACFCR_AE_1_Pos (17U) +#define CAN_ACFCR_AE_1_Msk (0x1UL << CAN_ACFCR_AE_1_Pos) /*!< 0x00020000 */ +#define CAN_ACFCR_AE_1 CAN_ACFCR_AE_1_Msk /*!< desc AE_1 */ +#define CAN_ACFCR_AE_2_Pos (18U) +#define CAN_ACFCR_AE_2_Msk (0x1UL << CAN_ACFCR_AE_2_Pos) /*!< 0x00040000 */ +#define CAN_ACFCR_AE_2 CAN_ACFCR_AE_2_Msk /*!< desc AE_2 */ +#define CAN_ACFCR_AE_3_Pos (19U) +#define CAN_ACFCR_AE_3_Msk (0x1UL << CAN_ACFCR_AE_3_Pos) /*!< 0x00080000 */ +#define CAN_ACFCR_AE_3 CAN_ACFCR_AE_3_Msk /*!< desc AE_3 */ +#define CAN_ACFCR_AE_4_Pos (20U) +#define CAN_ACFCR_AE_4_Msk (0x1UL << CAN_ACFCR_AE_4_Pos) /*!< 0x00100000 */ +#define CAN_ACFCR_AE_4 CAN_ACFCR_AE_4_Msk /*!< desc AE_4 */ +#define CAN_ACFCR_AE_5_Pos (21U) +#define CAN_ACFCR_AE_5_Msk (0x1UL << CAN_ACFCR_AE_5_Pos) /*!< 0x00200000 */ +#define CAN_ACFCR_AE_5 CAN_ACFCR_AE_5_Msk /*!< desc AE_5 */ +#define CAN_ACFCR_AE_6_Pos (22U) +#define CAN_ACFCR_AE_6_Msk (0x1UL << CAN_ACFCR_AE_6_Pos) /*!< 0x00400000 */ +#define CAN_ACFCR_AE_6 CAN_ACFCR_AE_6_Msk /*!< desc AE_6 */ +#define CAN_ACFCR_AE_7_Pos (23U) +#define CAN_ACFCR_AE_7_Msk (0x1UL << CAN_ACFCR_AE_7_Pos) /*!< 0x00800000 */ +#define CAN_ACFCR_AE_7 CAN_ACFCR_AE_7_Msk /*!< desc AE_7 */ +#define CAN_ACFCR_AE_8_Pos (24U) +#define CAN_ACFCR_AE_8_Msk (0x1UL << CAN_ACFCR_AE_8_Pos) /*!< 0x01000000 */ +#define CAN_ACFCR_AE_8 CAN_ACFCR_AE_8_Msk /*!< desc AE_8 */ +#define CAN_ACFCR_AE_9_Pos (25U) +#define CAN_ACFCR_AE_9_Msk (0x1UL << CAN_ACFCR_AE_9_Pos) /*!< 0x02000000 */ +#define CAN_ACFCR_AE_9 CAN_ACFCR_AE_9_Msk /*!< desc AE_9 */ +#define CAN_ACFCR_AE_10_Pos (26U) +#define CAN_ACFCR_AE_10_Msk (0x1UL << CAN_ACFCR_AE_10_Pos) /*!< 0x04000000 */ +#define CAN_ACFCR_AE_10 CAN_ACFCR_AE_10_Msk /*!< desc AE_10 */ +#define CAN_ACFCR_AE_11_Pos (27U) +#define CAN_ACFCR_AE_11_Msk (0x1UL << CAN_ACFCR_AE_11_Pos) /*!< 0x08000000 */ +#define CAN_ACFCR_AE_11 CAN_ACFCR_AE_11_Msk /*!< desc AE_11 */ +#define CAN_ACFCR_AE_12_Pos (28U) +#define CAN_ACFCR_AE_12_Msk (0x1UL << CAN_ACFCR_AE_12_Pos) /*!< 0x10000000 */ +#define CAN_ACFCR_AE_12 CAN_ACFCR_AE_12_Msk /*!< desc AE_12 */ +#define CAN_ACFCR_AE_13_Pos (29U) +#define CAN_ACFCR_AE_13_Msk (0x1UL << CAN_ACFCR_AE_13_Pos) /*!< 0x20000000 */ +#define CAN_ACFCR_AE_13 CAN_ACFCR_AE_13_Msk /*!< desc AE_13 */ +#define CAN_ACFCR_AE_14_Pos (30U) +#define CAN_ACFCR_AE_14_Msk (0x1UL << CAN_ACFCR_AE_14_Pos) /*!< 0x40000000 */ +#define CAN_ACFCR_AE_14 CAN_ACFCR_AE_14_Msk /*!< desc AE_14 */ +#define CAN_ACFCR_AE_15_Pos (31U) +#define CAN_ACFCR_AE_15_Msk (0x1UL << CAN_ACFCR_AE_15_Pos) /*!< 0x80000000 */ +#define CAN_ACFCR_AE_15 CAN_ACFCR_AE_15_Msk /*!< desc AE_15 */ + +/*!< CAN_PWMCR */ +#define CAN_PWMCR_PWMO_Pos (0U) +#define CAN_PWMCR_PWMO_Msk (0x3FUL << CAN_PWMCR_PWMO_Pos) /*!< 0x0000003F */ +#define CAN_PWMCR_PWMO CAN_PWMCR_PWMO_Msk /*!< PWMO[5:0] bits (desc PWMO) */ +#define CAN_PWMCR_PWMO_0 (0x1UL << CAN_PWMCR_PWMO_Pos) /*!< 0x00000001 */ +#define CAN_PWMCR_PWMO_1 (0x2UL << CAN_PWMCR_PWMO_Pos) /*!< 0x00000002 */ +#define CAN_PWMCR_PWMO_2 (0x4UL << CAN_PWMCR_PWMO_Pos) /*!< 0x00000004 */ +#define CAN_PWMCR_PWMO_3 (0x8UL << CAN_PWMCR_PWMO_Pos) /*!< 0x00000008 */ +#define CAN_PWMCR_PWMO_4 (0x10UL << CAN_PWMCR_PWMO_Pos) /*!< 0x00000010 */ +#define CAN_PWMCR_PWMO_5 (0x20UL << CAN_PWMCR_PWMO_Pos) /*!< 0x00000020 */ +#define CAN_PWMCR_PWMS_Pos (8U) +#define CAN_PWMCR_PWMS_Msk (0x3FUL << CAN_PWMCR_PWMS_Pos) /*!< 0x00003F00 */ +#define CAN_PWMCR_PWMS CAN_PWMCR_PWMS_Msk /*!< PWMS[13:8] bits (desc PWMS) */ +#define CAN_PWMCR_PWMS_0 (0x1UL << CAN_PWMCR_PWMS_Pos) /*!< 0x00000100 */ +#define CAN_PWMCR_PWMS_1 (0x2UL << CAN_PWMCR_PWMS_Pos) /*!< 0x00000200 */ +#define CAN_PWMCR_PWMS_2 (0x4UL << CAN_PWMCR_PWMS_Pos) /*!< 0x00000400 */ +#define CAN_PWMCR_PWMS_3 (0x8UL << CAN_PWMCR_PWMS_Pos) /*!< 0x00000800 */ +#define CAN_PWMCR_PWMS_4 (0x10UL << CAN_PWMCR_PWMS_Pos) /*!< 0x00001000 */ +#define CAN_PWMCR_PWMS_5 (0x20UL << CAN_PWMCR_PWMS_Pos) /*!< 0x00002000 */ +#define CAN_PWMCR_PWML_Pos (16U) +#define CAN_PWMCR_PWML_Msk (0x3FUL << CAN_PWMCR_PWML_Pos) /*!< 0x003F0000 */ +#define CAN_PWMCR_PWML CAN_PWMCR_PWML_Msk /*!< PWML[21:16] bits (desc PWML) */ +#define CAN_PWMCR_PWML_0 (0x1UL << CAN_PWMCR_PWML_Pos) /*!< 0x00010000 */ +#define CAN_PWMCR_PWML_1 (0x2UL << CAN_PWMCR_PWML_Pos) /*!< 0x00020000 */ +#define CAN_PWMCR_PWML_2 (0x4UL << CAN_PWMCR_PWML_Pos) /*!< 0x00040000 */ +#define CAN_PWMCR_PWML_3 (0x8UL << CAN_PWMCR_PWML_Pos) /*!< 0x00080000 */ +#define CAN_PWMCR_PWML_4 (0x10UL << CAN_PWMCR_PWML_Pos) /*!< 0x00100000 */ +#define CAN_PWMCR_PWML_5 (0x20UL << CAN_PWMCR_PWML_Pos) /*!< 0x00200000 */ + +/****************************************************************************/ +/* */ +/* Analog Comparators (COMP) */ +/* */ +/****************************************************************************/ +/********************** Bit definition for COMP_CSR register **************/ +#define COMP_CSR_EN_Pos (0U) +#define COMP_CSR_EN_Msk (0x1UL << COMP_CSR_EN_Pos) /*!< 0x00000001 */ +#define COMP_CSR_EN COMP_CSR_EN_Msk /*!< Comparator enable */ +#define COMP_CSR_COMP1_EN COMP_CSR_EN +#define COMP_CSR_COMP2_EN COMP_CSR_EN + +//#define COMP_CSR_SCALER_EN_Pos (1U) +//#define COMP_CSR_SCALER_EN_Msk (0x1UL << COMP_CSR_SCALER_EN_Pos) /*!< 0x00000001 */ +//#define COMP_CSR_SCALER_EN COMP_CSR_SCALER_EN_Msk /*!< Comparator enable */ + +//#define COMP_CSR_INMSEL_Pos (4U) +//#define COMP_CSR_INMSEL_Msk (0xFUL << COMP_CSR_INMSEL_Pos) /*!< 0x000000F0 */ +//#define COMP_CSR_INMSEL COMP_CSR_INMSEL_Msk /*!< Comparator input minus selection */ +//#define COMP_CSR_INMSEL_0 (0x1UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000010 */ +//#define COMP_CSR_INMSEL_1 (0x2UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000020 */ +//#define COMP_CSR_INMSEL_2 (0x4UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000040 */ +//#define COMP_CSR_INMSEL_3 (0x8UL << COMP_CSR_INMSEL_Pos) /*!< 0x00000080 */ + +#define COMP_CSR_INNSEL_Pos (2U) +#define COMP_CSR_INNSEL_Msk (0xFUL << COMP_CSR_INNSEL_Pos) /*!< 0x0000003C */ +#define COMP_CSR_INNSEL COMP_CSR_INNSEL_Msk /*!< desc INNSEL */ +#define COMP_CSR_INNSEL_0 (0x1UL << COMP_CSR_INNSEL_Pos) /*!< 0x00000004 */ +#define COMP_CSR_INNSEL_1 (0x2UL << COMP_CSR_INNSEL_Pos) /*!< 0x00000008 */ +#define COMP_CSR_INNSEL_2 (0x4UL << COMP_CSR_INNSEL_Pos) /*!< 0x00000010 */ +#define COMP_CSR_INNSEL_3 (0x8UL << COMP_CSR_INNSEL_Pos) /*!< 0x00000020 */ + +#define COMP_CSR_INPSEL_Pos (6U) +#define COMP_CSR_INPSEL_Msk (0xFUL << COMP_CSR_INPSEL_Pos) /*!< 0x000003C0 */ +#define COMP_CSR_INPSEL COMP_CSR_INPSEL_Msk /*!< Comparator plus minus selection */ +#define COMP_CSR_INPSEL_0 (0x1UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000040 */ +#define COMP_CSR_INPSEL_1 (0x2UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000080 */ +#define COMP_CSR_INPSEL_2 (0x4UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000100 */ +#define COMP_CSR_INPSEL_3 (0x8UL << COMP_CSR_INPSEL_Pos) /*!< 0x00000200 */ + +#define COMP_CSR_WINMODE_Pos (11U) +#define COMP_CSR_WINMODE_Msk (0x1UL << COMP_CSR_WINMODE_Pos) /*!< 0x00000800 */ +#define COMP_CSR_WINMODE COMP_CSR_WINMODE_Msk /*!< Pair of comparators window mode. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ +//#define COMP_CSR_WINOUT_Pos (14U) +//#define COMP_CSR_WINOUT_Msk (0x1UL << COMP_CSR_WINOUT_Pos) /*!< 0x00004000 */ +//#define COMP_CSR_WINOUT COMP_CSR_WINOUT_Msk /*!< Pair of comparators window output level. Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */ + +#define COMP_CSR_POLARITY_Pos (15U) +#define COMP_CSR_POLARITY_Msk (0x1UL << COMP_CSR_POLARITY_Pos) /*!< 0x00008000 */ +#define COMP_CSR_POLARITY COMP_CSR_POLARITY_Msk /*!< Comparator output polarity */ + +#define COMP_CSR_HYST_Pos (16U) +#define COMP_CSR_HYST_Msk (0x1UL << COMP_CSR_HYST_Pos) /*!< 0x00010000 */ +#define COMP_CSR_HYST COMP_CSR_HYST_Msk /*!< Comparator hysteresis enable */ + +#define COMP_CSR_PWRMODE_Pos (18U) +#define COMP_CSR_PWRMODE_Msk (0x3UL << COMP_CSR_PWRMODE_Pos) /*!< 0x000C0000 */ +#define COMP_CSR_PWRMODE COMP_CSR_PWRMODE_Msk /*!< Comparator power mode */ +#define COMP_CSR_PWRMODE_0 (0x1UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00040000 */ +#define COMP_CSR_PWRMODE_1 (0x2UL << COMP_CSR_PWRMODE_Pos) /*!< 0x00080000 */ + +#define COMP_CSR_VCDIV_Pos (20U) +#define COMP_CSR_VCDIV_Msk (0x3FUL << COMP_CSR_VCDIV_Pos) /*!< 0x03F00000 */ +#define COMP_CSR_VCDIV COMP_CSR_VCDIV_Msk /*!< VCDIV[25:20] bits (desc VCDIV) */ +#define COMP_CSR_VCDIV_0 (0x1UL << COMP_CSR_VCDIV_Pos) /*!< 0x00100000 */ +#define COMP_CSR_VCDIV_1 (0x2UL << COMP_CSR_VCDIV_Pos) /*!< 0x00200000 */ +#define COMP_CSR_VCDIV_2 (0x4UL << COMP_CSR_VCDIV_Pos) /*!< 0x00400000 */ +#define COMP_CSR_VCDIV_3 (0x8UL << COMP_CSR_VCDIV_Pos) /*!< 0x00800000 */ +#define COMP_CSR_VCDIV_4 (0x10UL << COMP_CSR_VCDIV_Pos) /*!< 0x01000000 */ +#define COMP_CSR_VCDIV_5 (0x20UL << COMP_CSR_VCDIV_Pos) /*!< 0x02000000 */ + +#define COMP_CSR_VCDIV_EN_Pos (26U) +#define COMP_CSR_VCDIV_EN_Msk (0x1UL << COMP_CSR_VCDIV_EN_Pos) /*!< 0x04000000 */ +#define COMP_CSR_VCDIV_EN COMP_CSR_VCDIV_EN_Msk /*!< desc VCDIV_EN */ + +#define COMP_CSR_VCSEL_Pos (27U) +#define COMP_CSR_VCSEL_Msk (0x1UL << COMP_CSR_VCSEL_Pos) /*!< 0x08000000 */ +#define COMP_CSR_VCSEL COMP_CSR_VCSEL_Msk /*!< desc VCSEL */ + +#define COMP_CSR_COMP_OUT_Pos (30U) +#define COMP_CSR_COMP_OUT_Msk (0x1UL << COMP_CSR_COMP_OUT_Pos) /*!< 0x40000000 */ +#define COMP_CSR_COMP_OUT COMP_CSR_COMP_OUT_Msk /*!< desc COMP_OUT */ + +//#define COMP_CSR_LOCK_Pos (31U) +//#define COMP_CSR_LOCK_Msk (0x1UL << COMP_CSR_LOCK_Pos) /*!< 0x80000000 */ +//#define COMP_CSR_LOCK COMP_CSR_LOCK_Msk /*!< Comparator lock */ + +/********************** Bit definition for COMP_FR register ***************/ +#define COMP_FR_FLTEN_Pos (0U) +#define COMP_FR_FLTEN_Msk (0x1UL << COMP_FR_FLTEN_Pos) /*!< 0x00000001 */ +#define COMP_FR_FLTEN COMP_FR_FLTEN_Msk /*!< Comparator filter enable */ +#define COMP_FR_FLTCNT_Pos (16U) +#define COMP_FR_FLTCNT_Msk (0xFFFFUL << COMP_FR_FLTCNT_Pos) /*!< 0xFFFF0000 */ +#define COMP_FR_FLTCNT COMP_FR_FLTCNT_Msk /*!< Comparator filter counter */ + +/****************************************************************************/ +/* */ +/* CRC calculation unit (CRC) */ +/* */ +/****************************************************************************/ +/******************* Bit definition for CRC_DR register *******************/ +#define CRC_DR_DR_Pos (0U) +#define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ + +/******************* Bit definition for CRC_IDR register ******************/ +#define CRC_IDR_IDR_Pos (0U) +#define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ +#define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ + +/******************** Bit definition for CRC_CR register ******************/ +#define CRC_CR_RESET_Pos (0U) +#define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ +#define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ + +/****************************************************************************/ +/* */ +/* Clock Triming Controller(CTC) */ +/* */ +/****************************************************************************/ +/********************* Bits Define For Peripheral CTC *********************/ +/*!< CTC_CTL0 */ +#define CTC_CTL0_CKOKIE_Pos (0U) +#define CTC_CTL0_CKOKIE_Msk (0x1UL << CTC_CTL0_CKOKIE_Pos) /*!< 0x00000001 */ +#define CTC_CTL0_CKOKIE CTC_CTL0_CKOKIE_Msk /*!< desc CKOKIE */ +#define CTC_CTL0_CKWARNIE_Pos (1U) +#define CTC_CTL0_CKWARNIE_Msk (0x1UL << CTC_CTL0_CKWARNIE_Pos) /*!< 0x00000002 */ +#define CTC_CTL0_CKWARNIE CTC_CTL0_CKWARNIE_Msk /*!< desc CKWARNIE */ +#define CTC_CTL0_ERRIE_Pos (2U) +#define CTC_CTL0_ERRIE_Msk (0x1UL << CTC_CTL0_ERRIE_Pos) /*!< 0x00000004 */ +#define CTC_CTL0_ERRIE CTC_CTL0_ERRIE_Msk /*!< desc ERRIE */ +#define CTC_CTL0_EREFIE_Pos (3U) +#define CTC_CTL0_EREFIE_Msk (0x1UL << CTC_CTL0_EREFIE_Pos) /*!< 0x00000008 */ +#define CTC_CTL0_EREFIE CTC_CTL0_EREFIE_Msk /*!< desc EREFIE */ +#define CTC_CTL0_CNTEN_Pos (5U) +#define CTC_CTL0_CNTEN_Msk (0x1UL << CTC_CTL0_CNTEN_Pos) /*!< 0x00000020 */ +#define CTC_CTL0_CNTEN CTC_CTL0_CNTEN_Msk /*!< desc CNTEN */ +#define CTC_CTL0_AUTOTRIM_Pos (6U) +#define CTC_CTL0_AUTOTRIM_Msk (0x1UL << CTC_CTL0_AUTOTRIM_Pos) /*!< 0x00000040 */ +#define CTC_CTL0_AUTOTRIM CTC_CTL0_AUTOTRIM_Msk /*!< desc AUTOTRIM */ +#define CTC_CTL0_SWREFPUL_Pos (7U) +#define CTC_CTL0_SWREFPUL_Msk (0x1UL << CTC_CTL0_SWREFPUL_Pos) /*!< 0x00000080 */ +#define CTC_CTL0_SWREFPUL CTC_CTL0_SWREFPUL_Msk /*!< desc SWREFPUL */ +#define CTC_CTL0_TRIMVALUE_Pos (8U) +#define CTC_CTL0_TRIMVALUE_Msk (0x3FUL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00003F00 */ +#define CTC_CTL0_TRIMVALUE CTC_CTL0_TRIMVALUE_Msk /*!< TRIMVALUE[13:8] bits (desc TRIMVALUE) */ +#define CTC_CTL0_TRIMVALUE_0 (0x1UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00000100 */ +#define CTC_CTL0_TRIMVALUE_1 (0x2UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00000200 */ +#define CTC_CTL0_TRIMVALUE_2 (0x4UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00000400 */ +#define CTC_CTL0_TRIMVALUE_3 (0x8UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00000800 */ +#define CTC_CTL0_TRIMVALUE_4 (0x10UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00001000 */ +#define CTC_CTL0_TRIMVALUE_5 (0x20UL << CTC_CTL0_TRIMVALUE_Pos) /*!< 0x00002000 */ + + +/*!< CTC_CTL1 */ +#define CTC_CTL1_RLVALUE_Pos (0U) +#define CTC_CTL1_RLVALUE_Msk (0xFFFFUL << CTC_CTL1_RLVALUE_Pos) /*!< 0x0000FFFF */ +#define CTC_CTL1_RLVALUE CTC_CTL1_RLVALUE_Msk /*!< RLVALUE[15:0] bits (desc RLVALUE) */ +#define CTC_CTL1_CKLIM_Pos (16U) +#define CTC_CTL1_CKLIM_Msk (0xFFUL << CTC_CTL1_CKLIM_Pos) /*!< 0x00FF0000 */ +#define CTC_CTL1_CKLIM CTC_CTL1_CKLIM_Msk /*!< CKLIM[23:16] bits (desc CKLIM) */ +#define CTC_CTL1_REFPSC_Pos (24U) +#define CTC_CTL1_REFPSC_Msk (0x7UL << CTC_CTL1_REFPSC_Pos) /*!< 0x07000000 */ +#define CTC_CTL1_REFPSC CTC_CTL1_REFPSC_Msk /*!< REFPSC[26:24] bits (desc REFPSC) */ +#define CTC_CTL1_REFPSC_0 (0x1UL << CTC_CTL1_REFPSC_Pos) /*!< 0x01000000 */ +#define CTC_CTL1_REFPSC_1 (0x2UL << CTC_CTL1_REFPSC_Pos) /*!< 0x02000000 */ +#define CTC_CTL1_REFPSC_2 (0x4UL << CTC_CTL1_REFPSC_Pos) /*!< 0x04000000 */ +#define CTC_CTL1_REFSEL_Pos (28U) +#define CTC_CTL1_REFSEL_Msk (0x3UL << CTC_CTL1_REFSEL_Pos) /*!< 0x30000000 */ +#define CTC_CTL1_REFSEL CTC_CTL1_REFSEL_Msk /*!< REFSEL[29:28] bits (desc REFSEL) */ +#define CTC_CTL1_REFSEL_0 (0x1UL << CTC_CTL1_REFSEL_Pos) /*!< 0x10000000 */ +#define CTC_CTL1_REFSEL_1 (0x2UL << CTC_CTL1_REFSEL_Pos) /*!< 0x20000000 */ +#define CTC_CTL1_REFPOL_Pos (31U) +#define CTC_CTL1_REFPOL_Msk (0x1UL << CTC_CTL1_REFPOL_Pos) /*!< 0x80000000 */ +#define CTC_CTL1_REFPOL CTC_CTL1_REFPOL_Msk /*!< desc REFPOL */ + +/*!< CTC_SR */ +#define CTC_SR_CKOKIF_Pos (0U) +#define CTC_SR_CKOKIF_Msk (0x1UL << CTC_SR_CKOKIF_Pos) /*!< 0x00000001 */ +#define CTC_SR_CKOKIF CTC_SR_CKOKIF_Msk /*!< desc CKOKIF */ +#define CTC_SR_CKWARNIF_Pos (1U) +#define CTC_SR_CKWARNIF_Msk (0x1UL << CTC_SR_CKWARNIF_Pos) /*!< 0x00000002 */ +#define CTC_SR_CKWARNIF CTC_SR_CKWARNIF_Msk /*!< desc CKWARNIF */ +#define CTC_SR_ERRIF_Pos (2U) +#define CTC_SR_ERRIF_Msk (0x1UL << CTC_SR_ERRIF_Pos) /*!< 0x00000004 */ +#define CTC_SR_ERRIF CTC_SR_ERRIF_Msk /*!< desc ERRIF */ +#define CTC_SR_EREFIF_Pos (3U) +#define CTC_SR_EREFIF_Msk (0x1UL << CTC_SR_EREFIF_Pos) /*!< 0x00000008 */ +#define CTC_SR_EREFIF CTC_SR_EREFIF_Msk /*!< desc EREFIF */ +#define CTC_SR_CKERR_Pos (8U) +#define CTC_SR_CKERR_Msk (0x1UL << CTC_SR_CKERR_Pos) /*!< 0x00000100 */ +#define CTC_SR_CKERR CTC_SR_CKERR_Msk /*!< desc CKERR */ +#define CTC_SR_REFMISS_Pos (9U) +#define CTC_SR_REFMISS_Msk (0x1UL << CTC_SR_REFMISS_Pos) /*!< 0x00000200 */ +#define CTC_SR_REFMISS CTC_SR_REFMISS_Msk /*!< desc REFMISS */ +#define CTC_SR_TRIMERR_Pos (10U) +#define CTC_SR_TRIMERR_Msk (0x1UL << CTC_SR_TRIMERR_Pos) /*!< 0x00000400 */ +#define CTC_SR_TRIMERR CTC_SR_TRIMERR_Msk /*!< desc TRIMERR */ +#define CTC_SR_REFDIR_Pos (15U) +#define CTC_SR_REFDIR_Msk (0x1UL << CTC_SR_REFDIR_Pos) /*!< 0x00008000 */ +#define CTC_SR_REFDIR CTC_SR_REFDIR_Msk /*!< desc REFDIR */ +#define CTC_SR_REFCAP_Pos (16U) +#define CTC_SR_REFCAP_Msk (0xFFFFUL << CTC_SR_REFCAP_Pos) /*!< 0xFFFF0000 */ +#define CTC_SR_REFCAP CTC_SR_REFCAP_Msk /*!< REFCAP[31:16] bits (desc REFCAP) */ + +/*!< CTC_INTC */ +#define CTC_INTC_CKOKIC_Pos (0U) +#define CTC_INTC_CKOKIC_Msk (0x1UL << CTC_INTC_CKOKIC_Pos) /*!< 0x00000001 */ +#define CTC_INTC_CKOKIC CTC_INTC_CKOKIC_Msk /*!< desc CKOKIC */ +#define CTC_INTC_CKWARNIC_Pos (1U) +#define CTC_INTC_CKWARNIC_Msk (0x1UL << CTC_INTC_CKWARNIC_Pos) /*!< 0x00000002 */ +#define CTC_INTC_CKWARNIC CTC_INTC_CKWARNIC_Msk /*!< desc CKWARNIC */ +#define CTC_INTC_ERRIC_Pos (2U) +#define CTC_INTC_ERRIC_Msk (0x1UL << CTC_INTC_ERRIC_Pos) /*!< 0x00000004 */ +#define CTC_INTC_ERRIC CTC_INTC_ERRIC_Msk /*!< desc ERRIC */ +#define CTC_INTC_EREFIC_Pos (3U) +#define CTC_INTC_EREFIC_Msk (0x1UL << CTC_INTC_EREFIC_Pos) /*!< 0x00000008 */ +#define CTC_INTC_EREFIC CTC_INTC_EREFIC_Msk /*!< desc EREFIC */ + +/****************************************************************************/ +/* */ +/* Digital to Analog Converter(DAC) */ +/* */ +/****************************************************************************/ +/********************* Bits Define For Peripheral DAC *********************/ +/*!< DAC_CR */ +#define DAC_CR_EN1_Pos (0U) +#define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */ +#define DAC_CR_EN1 DAC_CR_EN1_Msk /*!< desc EN1 */ +#define DAC_CR_BOFF1_Pos (1U) +#define DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos) /*!< 0x00000002 */ +#define DAC_CR_BOFF1 DAC_CR_BOFF1_Msk /*!< desc BOFF1 */ +#define DAC_CR_TEN1_Pos (2U) +#define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000004 */ +#define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!< desc TEN1 */ +#define DAC_CR_TSEL1_Pos (3U) +#define DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos) /*!< 0x00000038 */ +#define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!< TSEL1[5:3] bits (desc TSEL1) */ +#define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */ +#define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */ +#define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */ +#define DAC_CR_WAVE1_Pos (6U) +#define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */ +#define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!< WAVE1[7:6] bits (desc WAVE1) */ +#define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */ +#define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */ +#define DAC_CR_MAMP1_Pos (8U) +#define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */ +#define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!< MAMP1[11:8] bits (desc MAMP1) */ +#define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */ +#define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */ +#define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */ +#define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */ +#define DAC_CR_DMAEN1_Pos (12U) +#define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */ +#define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!< desc DMAEN1 */ +#define DAC_CR_DMAUDRIE1_Pos (13U) +#define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */ +#define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!< desc DMAUDRIE1 */ +#define DAC_CR_DAC1CEN_Pos (14U) +#define DAC_CR_DAC1CEN_Msk (0x1UL << DAC_CR_DAC1CEN_Pos) /*!< 0x00004000 */ +#define DAC_CR_DAC1CEN DAC_CR_DAC1CEN_Msk /*!< desc DAC1CEN */ +#define DAC_CR_EN2_Pos (16U) +#define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */ +#define DAC_CR_EN2 DAC_CR_EN2_Msk /*!< desc EN2 */ +#define DAC_CR_BOFF2_Pos (17U) +#define DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos) /*!< 0x00020000 */ +#define DAC_CR_BOFF2 DAC_CR_BOFF2_Msk /*!< desc BOFF2 */ +#define DAC_CR_TEN2_Pos (18U) +#define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00040000 */ +#define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!< desc TEN2 */ +#define DAC_CR_TSEL2_Pos (19U) +#define DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos) /*!< 0x00380000 */ +#define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!< TSEL2[21:19] bits (desc TSEL2) */ +#define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */ +#define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */ +#define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */ +#define DAC_CR_WAVE2_Pos (22U) +#define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */ +#define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!< WAVE2[23:22] bits (desc WAVE2) */ +#define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */ +#define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */ +#define DAC_CR_MAMP2_Pos (24U) +#define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */ +#define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!< MAMP2[27:24] bits (desc MAMP2) */ +#define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */ +#define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */ +#define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */ +#define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */ +#define DAC_CR_DMAEN2_Pos (28U) +#define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */ +#define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!< desc DMAEN2 */ +#define DAC_CR_DMAUDRIE2_Pos (29U) +#define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */ +#define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!< desc DMAUDRIE2 */ +#define DAC_CR_DAC2CEN_Pos (30U) +#define DAC_CR_DAC2CEN_Msk (0x1UL << DAC_CR_DAC2CEN_Pos) /*!< 0x40000000 */ +#define DAC_CR_DAC2CEN DAC_CR_DAC2CEN_Msk /*!< desc DAC2CEN */ + +/*!< DAC_SWTRIGR */ +#define DAC_SWTRIGR_SWTRIG1_Pos (0U) +#define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */ +#define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!< desc SWTRIG1 */ +#define DAC_SWTRIGR_SWTRIG2_Pos (1U) +#define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */ +#define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!< desc SWTRIG2 */ + +/*!< DAC_DHR12R1 */ +#define DAC_DHR12R1_DACC1DHR_Pos (0U) +#define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!< DACC1DHR[11:0] bits (desc DACC1DHR) */ + +/*!< DAC_DHR12L1 */ +#define DAC_DHR12L1_DACC1DHR_Pos (3U) +#define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x00007FF8 */ +#define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!< DACC1DHR[14:3] bits (desc DACC1DHR) */ + +/*!< DAC_DHR8R1 */ +#define DAC_DHR8R1_DACC1DHR_Pos (0U) +#define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!< DACC1DHR[7:0] bits (desc DACC1DHR) */ + +/*!< DAC_DHR12R2 */ +#define DAC_DHR12R2_DACC2DHR_Pos (0U) +#define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!< DACC2DHR[11:0] bits (desc DACC2DHR) */ + +/*!< DAC_DHR12L2 */ +#define DAC_DHR12L2_DACC2DHR_Pos (4U) +#define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!< DACC2DHR[15:4] bits (desc DACC2DHR) */ + +/*!< DAC_DHR8R2 */ +#define DAC_DHR8R2_DACC2DHR_Pos (0U) +#define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!< DACC2DHR[7:0] bits (desc DACC2DHR) */ + +/*!< DAC_DHR12RD */ +#define DAC_DHR12RD_DACC1DHR_Pos (0U) +#define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */ +#define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!< DACC1DHR[11:0] bits (desc DACC1DHR) */ +#define DAC_DHR12RD_DACC2DHR_Pos (16U) +#define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */ +#define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!< DACC2DHR[27:16] bits (desc DACC2DHR) */ + +/*!< DAC_DHR12LD */ +#define DAC_DHR12LD_DACC1DHR_Pos (4U) +#define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */ +#define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!< DACC1DHR[15:4] bits (desc DACC1DHR) */ +#define DAC_DHR12LD_DACC2DHR_Pos (20U) +#define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */ +#define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!< DACC2DHR[31:20] bits (desc DACC2DHR) */ + +/*!< DAC_DHR8RD */ +#define DAC_DHR8RD_DACC1DHR_Pos (0U) +#define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */ +#define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!< DACC1DHR[7:0] bits (desc DACC1DHR) */ +#define DAC_DHR8RD_DACC2DHR_Pos (8U) +#define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */ +#define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!< DACC2DHR[15:8] bits (desc DACC2DHR) */ + +/*!< DAC_DOR1 */ +#define DAC_DOR1_DACC1DOR_Pos (0U) +#define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!< DACC1DOR[11:0] bits (desc DACC1DOR) */ + +/*!< DAC_DOR2 */ +#define DAC_DOR2_DACC2DOR_Pos (0U) +#define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */ +#define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!< DACC2DOR[11:0] bits (desc DACC2DOR) */ + +/*!< DAC_SR */ +#define DAC_SR_DMAUDR1_Pos (13U) +#define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */ +#define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!< desc DMAUDR1 */ +#define DAC_SR_DMAUDR2_Pos (29U) +#define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */ +#define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!< desc DMAUDR2 */ + +/****************************************************************************/ +/* */ +/* Debug MCU (DBGMCU) */ +/* */ +/****************************************************************************/ +/******************** Bit definition for DBG_IDCODE register **************/ +#define DBGMCU_IDCODE_DEV_ID_Pos (0U) +#define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ +#define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk +#define DBGMCU_IDCODE_REV_ID_Pos (16U) +#define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ +#define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk +#define DBGMCU_IDCODE_DBG_ID_Pos (0U) +#define DBGMCU_IDCODE_DBG_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_DBG_ID_Pos) /*!< 0xFFFFFFFF */ +#define DBGMCU_IDCODE_DBG_ID DBGMCU_IDCODE_DBG_ID_Msk + +/******************** Bit definition for DBGMCU_CR register ***************/ +#define DBGMCU_CR_DBG_SLEEP_Pos (0U) +#define DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos) /*!< 0x00000001 */ +#define DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk +#define DBGMCU_CR_DBG_STOP_Pos (1U) +#define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk + +/******************** Bit definition for DBGMCU_APB_FZ1 register **********/ +#define DBGMCU_APB_FZ1_DBG_TIM2_STOP_Pos (0U) +#define DBGMCU_APB_FZ1_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_TIM2_STOP_Pos) /*!< 0x00000001 */ +#define DBGMCU_APB_FZ1_DBG_TIM2_STOP DBGMCU_APB_FZ1_DBG_TIM2_STOP_Msk +#define DBGMCU_APB_FZ1_DBG_TIM3_STOP_Pos (1U) +#define DBGMCU_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ +#define DBGMCU_APB_FZ1_DBG_TIM3_STOP DBGMCU_APB_FZ1_DBG_TIM3_STOP_Msk +#define DBGMCU_APB_FZ1_DBG_TIM6_STOP_Pos (4U) +#define DBGMCU_APB_FZ1_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_TIM6_STOP_Pos) /*!< 0x00000010 */ +#define DBGMCU_APB_FZ1_DBG_TIM6_STOP DBGMCU_APB_FZ1_DBG_TIM6_STOP_Msk +#define DBGMCU_APB_FZ1_DBG_TIM7_STOP_Pos (5U) +#define DBGMCU_APB_FZ1_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_TIM7_STOP_Pos) /*!< 0x00000020 */ +#define DBGMCU_APB_FZ1_DBG_TIM7_STOP DBGMCU_APB_FZ1_DBG_TIM7_STOP_Msk +#define DBGMCU_APB_FZ1_DBG_RTC_STOP_Pos (10U) +#define DBGMCU_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ +#define DBGMCU_APB_FZ1_DBG_RTC_STOP DBGMCU_APB_FZ1_DBG_RTC_STOP_Msk +#define DBGMCU_APB_FZ1_DBG_WWDG_STOP_Pos (11U) +#define DBGMCU_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB_FZ1_DBG_WWDG_STOP DBGMCU_APB_FZ1_DBG_WWDG_STOP_Msk +#define DBGMCU_APB_FZ1_DBG_IWDG_STOP_Pos (12U) +#define DBGMCU_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB_FZ1_DBG_IWDG_STOP DBGMCU_APB_FZ1_DBG_IWDG_STOP_Msk +#define DBGMCU_APB_FZ1_DBG_CAN_STOP_Pos (19U) +#define DBGMCU_APB_FZ1_DBG_CAN_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_CAN_STOP_Pos) /*!< 0x00080000 */ +#define DBGMCU_APB_FZ1_DBG_CAN_STOP DBGMCU_APB_FZ1_DBG_CAN_STOP_Msk +#define DBGMCU_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_Pos (21U) +#define DBGMCU_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_Pos) /*!< 0x00200000 */ +#define DBGMCU_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_APB_FZ1_DBG_I2C1_SMBUS_TIMEOUT_Msk +#define DBGMCU_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_Pos (22U) +#define DBGMCU_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_Pos) /*!< 0x00400000 */ +#define DBGMCU_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_APB_FZ1_DBG_I2C2_SMBUS_TIMEOUT_Msk +#define DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Pos (31U) +#define DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Pos) /*!< 0x00001000 */ +#define DBGMCU_APB_FZ1_DBG_LPTIM_STOP DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Msk + +/******************** Bit definition for DBGMCU_APB_FZ2 register **********/ +#define DBGMCU_APB_FZ2_DBG_TIM1_STOP_Pos (11U) +#define DBGMCU_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ +#define DBGMCU_APB_FZ2_DBG_TIM1_STOP DBGMCU_APB_FZ2_DBG_TIM1_STOP_Msk +#define DBGMCU_APB_FZ2_DBG_TIM14_STOP_Pos (15U) +#define DBGMCU_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ +#define DBGMCU_APB_FZ2_DBG_TIM14_STOP DBGMCU_APB_FZ2_DBG_TIM14_STOP_Msk +#define DBGMCU_APB_FZ2_DBG_TIM15_STOP_Pos (16U) +#define DBGMCU_APB_FZ2_DBG_TIM15_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM15_STOP_Pos) /*!< 0x00010000 */ +#define DBGMCU_APB_FZ2_DBG_TIM15_STOP DBGMCU_APB_FZ2_DBG_TIM15_STOP_Msk +#define DBGMCU_APB_FZ2_DBG_TIM16_STOP_Pos (17U) +#define DBGMCU_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ +#define DBGMCU_APB_FZ2_DBG_TIM16_STOP DBGMCU_APB_FZ2_DBG_TIM16_STOP_Msk +#define DBGMCU_APB_FZ2_DBG_TIM17_STOP_Pos (18U) +#define DBGMCU_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ +#define DBGMCU_APB_FZ2_DBG_TIM17_STOP DBGMCU_APB_FZ2_DBG_TIM17_STOP_Msk + +/****************************************************************************/ +/* */ +/* DMA Controller (DMA) */ +/* */ +/****************************************************************************/ +/******************* Bit definition for DMA_ISR register ******************/ +#define DMA_ISR_GIF1_Pos (0U) +#define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ +#define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ +#define DMA_ISR_TCIF1_Pos (1U) +#define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ +#define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ +#define DMA_ISR_HTIF1_Pos (2U) +#define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ +#define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ +#define DMA_ISR_TEIF1_Pos (3U) +#define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ +#define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ +#define DMA_ISR_GIF2_Pos (4U) +#define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ +#define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ +#define DMA_ISR_TCIF2_Pos (5U) +#define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ +#define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ +#define DMA_ISR_HTIF2_Pos (6U) +#define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ +#define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ +#define DMA_ISR_TEIF2_Pos (7U) +#define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ +#define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ +#define DMA_ISR_GIF3_Pos (8U) +#define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ +#define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ +#define DMA_ISR_TCIF3_Pos (9U) +#define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ +#define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ +#define DMA_ISR_HTIF3_Pos (10U) +#define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ +#define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ +#define DMA_ISR_TEIF3_Pos (11U) +#define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ +#define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ +#define DMA_ISR_GIF4_Pos (12U) +#define DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos) /*!< 0x00001000 */ +#define DMA_ISR_GIF4 DMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */ +#define DMA_ISR_TCIF4_Pos (13U) +#define DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos) /*!< 0x00002000 */ +#define DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */ +#define DMA_ISR_HTIF4_Pos (14U) +#define DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos) /*!< 0x00004000 */ +#define DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */ +#define DMA_ISR_TEIF4_Pos (15U) +#define DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos) /*!< 0x00008000 */ +#define DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */ +#define DMA_ISR_GIF5_Pos (16U) +#define DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos) /*!< 0x00010000 */ +#define DMA_ISR_GIF5 DMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */ +#define DMA_ISR_TCIF5_Pos (17U) +#define DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos) /*!< 0x00020000 */ +#define DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */ +#define DMA_ISR_HTIF5_Pos (18U) +#define DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos) /*!< 0x00040000 */ +#define DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */ +#define DMA_ISR_TEIF5_Pos (19U) +#define DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos) /*!< 0x00080000 */ +#define DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */ +#define DMA_ISR_GIF6_Pos (20U) +#define DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos) /*!< 0x00100000 */ +#define DMA_ISR_GIF6 DMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */ +#define DMA_ISR_TCIF6_Pos (21U) +#define DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos) /*!< 0x00200000 */ +#define DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */ +#define DMA_ISR_HTIF6_Pos (22U) +#define DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos) /*!< 0x00400000 */ +#define DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */ +#define DMA_ISR_TEIF6_Pos (23U) +#define DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos) /*!< 0x00800000 */ +#define DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */ +#define DMA_ISR_GIF7_Pos (24U) +#define DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos) /*!< 0x01000000 */ +#define DMA_ISR_GIF7 DMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */ +#define DMA_ISR_TCIF7_Pos (25U) +#define DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos) /*!< 0x02000000 */ +#define DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */ +#define DMA_ISR_HTIF7_Pos (26U) +#define DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos) /*!< 0x04000000 */ +#define DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */ +#define DMA_ISR_TEIF7_Pos (27U) +#define DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos) /*!< 0x08000000 */ +#define DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */ + +/******************* Bit definition for DMA_IFCR register *****************/ +#define DMA_IFCR_CGIF1_Pos (0U) +#define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ +#define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */ +#define DMA_IFCR_CTCIF1_Pos (1U) +#define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ +#define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ +#define DMA_IFCR_CHTIF1_Pos (2U) +#define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ +#define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ +#define DMA_IFCR_CTEIF1_Pos (3U) +#define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ +#define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ +#define DMA_IFCR_CGIF2_Pos (4U) +#define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ +#define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ +#define DMA_IFCR_CTCIF2_Pos (5U) +#define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ +#define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ +#define DMA_IFCR_CHTIF2_Pos (6U) +#define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ +#define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ +#define DMA_IFCR_CTEIF2_Pos (7U) +#define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ +#define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ +#define DMA_IFCR_CGIF3_Pos (8U) +#define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ +#define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ +#define DMA_IFCR_CTCIF3_Pos (9U) +#define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ +#define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ +#define DMA_IFCR_CHTIF3_Pos (10U) +#define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ +#define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ +#define DMA_IFCR_CTEIF3_Pos (11U) +#define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ +#define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ +#define DMA_IFCR_CGIF4_Pos (12U) +#define DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos) /*!< 0x00001000 */ +#define DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */ +#define DMA_IFCR_CTCIF4_Pos (13U) +#define DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos) /*!< 0x00002000 */ +#define DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */ +#define DMA_IFCR_CHTIF4_Pos (14U) +#define DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos) /*!< 0x00004000 */ +#define DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */ +#define DMA_IFCR_CTEIF4_Pos (15U) +#define DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos) /*!< 0x00008000 */ +#define DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */ +#define DMA_IFCR_CGIF5_Pos (16U) +#define DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos) /*!< 0x00010000 */ +#define DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */ +#define DMA_IFCR_CTCIF5_Pos (17U) +#define DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos) /*!< 0x00020000 */ +#define DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */ +#define DMA_IFCR_CHTIF5_Pos (18U) +#define DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos) /*!< 0x00040000 */ +#define DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */ +#define DMA_IFCR_CTEIF5_Pos (19U) +#define DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos) /*!< 0x00080000 */ +#define DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */ +#define DMA_IFCR_CGIF6_Pos (20U) +#define DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos) /*!< 0x00100000 */ +#define DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */ +#define DMA_IFCR_CTCIF6_Pos (21U) +#define DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos) /*!< 0x00200000 */ +#define DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */ +#define DMA_IFCR_CHTIF6_Pos (22U) +#define DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos) /*!< 0x00400000 */ +#define DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */ +#define DMA_IFCR_CTEIF6_Pos (23U) +#define DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos) /*!< 0x00800000 */ +#define DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */ +#define DMA_IFCR_CGIF7_Pos (24U) +#define DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos) /*!< 0x01000000 */ +#define DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */ +#define DMA_IFCR_CTCIF7_Pos (25U) +#define DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos) /*!< 0x02000000 */ +#define DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */ +#define DMA_IFCR_CHTIF7_Pos (26U) +#define DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos) /*!< 0x04000000 */ +#define DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */ +#define DMA_IFCR_CTEIF7_Pos (27U) +#define DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos) /*!< 0x08000000 */ +#define DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */ + +/******************* Bit definition for DMA_CCR register ******************/ +#define DMA_CCR_EN_Pos (0U) +#define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ +#define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ +#define DMA_CCR_TCIE_Pos (1U) +#define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ +#define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ +#define DMA_CCR_HTIE_Pos (2U) +#define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ +#define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ +#define DMA_CCR_TEIE_Pos (3U) +#define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ +#define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ +#define DMA_CCR_DIR_Pos (4U) +#define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ +#define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ +#define DMA_CCR_CIRC_Pos (5U) +#define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ +#define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ +#define DMA_CCR_PINC_Pos (6U) +#define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ +#define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ +#define DMA_CCR_MINC_Pos (7U) +#define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ +#define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ +#define DMA_CCR_PSIZE_Pos (8U) +#define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ +#define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ +#define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ +#define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ +#define DMA_CCR_MSIZE_Pos (10U) +#define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ +#define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ +#define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ +#define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ +#define DMA_CCR_PL_Pos (12U) +#define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ +#define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ +#define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ +#define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ +#define DMA_CCR_MEM2MEM_Pos (14U) +#define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ +#define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ + +/****************** Bit definition for DMA_CNDTR register *****************/ +#define DMA_CNDTR_NDT_Pos (0U) +#define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ +#define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ + +/****************** Bit definition for DMA_CPAR register ******************/ +#define DMA_CPAR_PA_Pos (0U) +#define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ + +/****************** Bit definition for DMA_CMAR register ******************/ +#define DMA_CMAR_MA_Pos (0U) +#define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ +#define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ + +/****************************************************************************/ +/* */ +/* External Interrupt/Event Controller (EXTI) */ +/* */ +/****************************************************************************/ +/****************** Bit definition for EXTI_RTSR register *****************/ +#define EXTI_RTSR_RT0_Pos (0U) +#define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ +#define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger configuration for input line 0 */ +#define EXTI_RTSR_RT1_Pos (1U) +#define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ +#define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger configuration for input line 1 */ +#define EXTI_RTSR_RT2_Pos (2U) +#define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ +#define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger configuration for input line 2 */ +#define EXTI_RTSR_RT3_Pos (3U) +#define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ +#define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger configuration for input line 3 */ +#define EXTI_RTSR_RT4_Pos (4U) +#define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ +#define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger configuration for input line 4 */ +#define EXTI_RTSR_RT5_Pos (5U) +#define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ +#define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger configuration for input line 5 */ +#define EXTI_RTSR_RT6_Pos (6U) +#define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ +#define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger configuration for input line 6 */ +#define EXTI_RTSR_RT7_Pos (7U) +#define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ +#define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger configuration for input line 7 */ +#define EXTI_RTSR_RT8_Pos (8U) +#define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ +#define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger configuration for input line 8 */ +#define EXTI_RTSR_RT9_Pos (9U) +#define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ +#define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger configuration for input line 9 */ +#define EXTI_RTSR_RT10_Pos (10U) +#define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ +#define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger configuration for input line 10 */ +#define EXTI_RTSR_RT11_Pos (11U) +#define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ +#define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger configuration for input line 11 */ +#define EXTI_RTSR_RT12_Pos (12U) +#define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ +#define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger configuration for input line 12 */ +#define EXTI_RTSR_RT13_Pos (13U) +#define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ +#define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger configuration for input line 13 */ +#define EXTI_RTSR_RT14_Pos (14U) +#define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ +#define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger configuration for input line 14 */ +#define EXTI_RTSR_RT15_Pos (15U) +#define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ +#define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger configuration for input line 15 */ +#define EXTI_RTSR_RT16_Pos (16U) +#define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ +#define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger configuration for input line 16 */ +#define EXTI_RTSR_RT17_Pos (17U) +#define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00020000 */ +#define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger configuration for input line 17 */ +#define EXTI_RTSR_RT18_Pos (18U) +#define EXTI_RTSR_RT18_Msk (0x1UL << EXTI_RTSR_RT18_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR_RT18 EXTI_RTSR_RT18_Msk /*!< Rising trigger configuration for input line 18 */ +#define EXTI_RTSR_RT20_Pos (20U) +#define EXTI_RTSR_RT20_Msk (0x1UL << EXTI_RTSR_RT20_Pos) /*!< 0x00040000 */ +#define EXTI_RTSR_RT20 EXTI_RTSR_RT20_Msk /*!< Rising trigger configuration for input line 20 */ + +/****************** Bit definition for EXTI_FTSR register *****************/ +#define EXTI_FTSR_FT0_Pos (0U) +#define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ +#define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger configuration for input line 0 */ +#define EXTI_FTSR_FT1_Pos (1U) +#define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ +#define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger configuration for input line 1 */ +#define EXTI_FTSR_FT2_Pos (2U) +#define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ +#define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger configuration for input line 2 */ +#define EXTI_FTSR_FT3_Pos (3U) +#define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ +#define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger configuration for input line 3 */ +#define EXTI_FTSR_FT4_Pos (4U) +#define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ +#define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger configuration for input line 4 */ +#define EXTI_FTSR_FT5_Pos (5U) +#define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ +#define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger configuration for input line 5 */ +#define EXTI_FTSR_FT6_Pos (6U) +#define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ +#define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger configuration for input line 6 */ +#define EXTI_FTSR_FT7_Pos (7U) +#define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ +#define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger configuration for input line 7 */ +#define EXTI_FTSR_FT8_Pos (8U) +#define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ +#define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger configuration for input line 8 */ +#define EXTI_FTSR_FT9_Pos (9U) +#define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ +#define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger configuration for input line 9 */ +#define EXTI_FTSR_FT10_Pos (10U) +#define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ +#define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger configuration for input line 10 */ +#define EXTI_FTSR_FT11_Pos (11U) +#define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ +#define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger configuration for input line 11 */ +#define EXTI_FTSR_FT12_Pos (12U) +#define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ +#define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger configuration for input line 12 */ +#define EXTI_FTSR_FT13_Pos (13U) +#define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ +#define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger configuration for input line 13 */ +#define EXTI_FTSR_FT14_Pos (14U) +#define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ +#define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger configuration for input line 14 */ +#define EXTI_FTSR_FT15_Pos (15U) +#define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ +#define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger configuration for input line 15 */ +#define EXTI_FTSR_FT16_Pos (16U) +#define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ +#define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger configuration for input line 16 */ +#define EXTI_FTSR_FT17_Pos (17U) +#define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ +#define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger configuration for input line 17 */ +#define EXTI_FTSR_FT18_Pos (18U) +#define EXTI_FTSR_FT18_Msk (0x1UL << EXTI_FTSR_FT18_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR_FT18 EXTI_FTSR_FT18_Msk /*!< Falling trigger configuration for input line 18 */ +#define EXTI_FTSR_FT20_Pos (20U) +#define EXTI_FTSR_FT20_Msk (0x1UL << EXTI_FTSR_FT20_Pos) /*!< 0x00040000 */ +#define EXTI_FTSR_FT20 EXTI_FTSR_FT20_Msk /*!< Falling trigger configuration for input line 20 */ + +/****************** Bit definition for EXTI_SWIER register ****************/ +#define EXTI_SWIER_SWI0_Pos (0U) +#define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ +#define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ +#define EXTI_SWIER_SWI1_Pos (1U) +#define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ +#define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ +#define EXTI_SWIER_SWI2_Pos (2U) +#define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ +#define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ +#define EXTI_SWIER_SWI3_Pos (3U) +#define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ +#define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ +#define EXTI_SWIER_SWI4_Pos (4U) +#define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ +#define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ +#define EXTI_SWIER_SWI5_Pos (5U) +#define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ +#define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ +#define EXTI_SWIER_SWI6_Pos (6U) +#define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ +#define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ +#define EXTI_SWIER_SWI7_Pos (7U) +#define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ +#define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ +#define EXTI_SWIER_SWI8_Pos (8U) +#define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ +#define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ +#define EXTI_SWIER_SWI9_Pos (9U) +#define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ +#define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ +#define EXTI_SWIER_SWI10_Pos (10U) +#define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ +#define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ +#define EXTI_SWIER_SWI11_Pos (11U) +#define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ +#define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ +#define EXTI_SWIER_SWI12_Pos (12U) +#define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ +#define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ +#define EXTI_SWIER_SWI13_Pos (13U) +#define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ +#define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ +#define EXTI_SWIER_SWI14_Pos (14U) +#define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ +#define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ +#define EXTI_SWIER_SWI15_Pos (15U) +#define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ +#define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ +#define EXTI_SWIER_SWI16_Pos (16U) +#define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ +#define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ +#define EXTI_SWIER_SWI17_Pos (17U) +#define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ +#define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ +#define EXTI_SWIER_SWI18_Pos (18U) +#define EXTI_SWIER_SWI18_Msk (0x1UL << EXTI_SWIER_SWI18_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER_SWI18 EXTI_SWIER_SWI18_Msk /*!< Software Interrupt on line 18*/ +#define EXTI_SWIER_SWI20_Pos (20U) +#define EXTI_SWIER_SWI20_Msk (0x1UL << EXTI_SWIER_SWI20_Pos) /*!< 0x00040000 */ +#define EXTI_SWIER_SWI20 EXTI_SWIER_SWI20_Msk /*!< Software Interrupt on line 20*/ + +/******************* Bit definition for EXTI_PR register ******************/ +#define EXTI_PR_PR0_Pos (0U) +#define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ +#define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ +#define EXTI_PR_PR1_Pos (1U) +#define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ +#define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ +#define EXTI_PR_PR2_Pos (2U) +#define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ +#define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ +#define EXTI_PR_PR3_Pos (3U) +#define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ +#define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ +#define EXTI_PR_PR_Pos (4U) +#define EXTI_PR_PR_Msk (0x1UL <
© Copyright (c) Puya Semiconductor Co. + * All rights reserved.
+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* This file refers the CMSIS standard, some adjustments are made according to Puya chips */ +#ifndef SYSTEM_PY32F003XX_H +#define SYSTEM_PY32F003XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/* Exported variables --------------------------------------------------------*/ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/* Exported constants --------------------------------------------------------*/ +extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint32_t HSIFreqTable[8]; /*!< HSI frequency table values */ + +/** + * Initialize the system + * @param none + * @return none + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * @param none + * @return none + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_PY32F003XX_H */ diff --git a/Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f030xx.h b/Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f030xx.h new file mode 100644 index 0000000..6ec4262 --- /dev/null +++ b/Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f030xx.h @@ -0,0 +1,66 @@ +/** + ****************************************************************************** + * @file system_py32f030xx.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File for + * PY32F030xx Device Series + * @version v1.0.0 + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* This file refers the CMSIS standard, some adjustments are made according to Puya chips */ +#ifndef SYSTEM_PY32F030XX_H +#define SYSTEM_PY32F030XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +/* Includes ------------------------------------------------------------------*/ +#include + +/* Exported variables --------------------------------------------------------*/ +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +/* Exported constants --------------------------------------------------------*/ +extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ +extern const uint32_t HSIFreqTable[8]; /*!< HSI frequency table values */ + +/** + * Initialize the system + * @param none + * @return none + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * @param none + * @return none + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_PY32F030XX_H */ diff --git a/Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f072xx.h b/Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f072xx.h new file mode 100644 index 0000000..08b8385 --- /dev/null +++ b/Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f072xx.h @@ -0,0 +1,67 @@ +/** + ****************************************************************************** + * @file system_py32f072xx.h + * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File for + * PY32F072xx Device Series + * @version v1.0.0 + * + ****************************************************************************** + * @attention + * + *

© Copyright (c) Puya Semiconductor Co. + * All rights reserved.

+ * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* This file refers the CMSIS standard, some adjustments are made according to Puya chips */ + +#ifndef SYSTEM_PY32F072XX_H +#define SYSTEM_PY32F072XX_H + +#ifdef __cplusplus +extern "C" { +#endif + +#include + +extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */ + +extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */ +extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */ + +/** + * Initialize the system + * + * @param none + * @return none + * + * @brief Setup the microcontroller system. + * Initialize the System and update the SystemCoreClock variable. + */ +extern void SystemInit(void); + +/** + * Update SystemCoreClock variable + * + * @param none + * @return none + * + * @brief Updates the SystemCoreClock with current core Clock + * retrieved from cpu registers. + */ +extern void SystemCoreClockUpdate(void); + +#ifdef __cplusplus +} +#endif + +#endif /* SYSTEM_PY32F072XX_H */ diff --git a/Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f0xx.h b/Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f0xx.h old mode 100755 new mode 100644 index 1242576..4f088a1 --- a/Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f0xx.h +++ b/Libraries/CMSIS/Device/PY32F0xx/Include/system_py32f0xx.h @@ -2,7 +2,7 @@ ****************************************************************************** * @file system_py32f0xx.h * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File for - * PY32F0xx Device Series + * PY32F030xx Device Series * @version v1.0.0 * ****************************************************************************** diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f002ax5.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f002ax5.s old mode 100755 new mode 100644 index 72a3ff8..7a80da8 --- a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f002ax5.s +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f002ax5.s @@ -9,22 +9,38 @@ ;* calls main()). ;* After Reset the CortexM0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) Puya Semiconductor Co. -;* All rights reserved.

+;* Copyright (c) 2021, Puya Semiconductor Inc. ;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

+;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* ;****************************************************************************** -;* <<< Use Configuration Wizard in Context Menu >>> ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f002x5.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f002x5.s new file mode 100644 index 0000000..09f1989 --- /dev/null +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f002x5.s @@ -0,0 +1,233 @@ +;****************************************************************************** +;* @file : startup_py32f002x5.s +;* @brief : PY32F002xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2021, Puya Semiconductor Inc. +;* +;* All rights reserved. +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;****************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD 0 ; 0Reserved + DCD 0 ; 1Reserved + DCD 0 ; 2Reserved + DCD FLASH_IRQHandler ; 3FLASH + DCD RCC_IRQHandler ; 4RCC + DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15 + DCD 0 ; 8Reserved + DCD 0 ; 9Reserved + DCD 0 ; 10Reserved + DCD 0 ; 11Reserved + DCD ADC_IRQHandler ; 12ADC + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare + DCD 0 ; 15Reserved + DCD 0 ; 16Reserved + DCD LPTIM1_IRQHandler ; 17LPTIM1 + DCD 0 ; 18Reserved + DCD 0 ; 19Reserved + DCD 0 ; 20Reserved + DCD TIM16_IRQHandler ; 21TIM16 + DCD 0 ; 22Reserved + DCD I2C1_IRQHandler ; 23I2C1 + DCD 0 ; 24Reserved + DCD SPI1_IRQHandler ; 25SPI1 + DCD 0 ; 26Reserved + DCD USART1_IRQHandler ; 27USART1 + DCD 0 ; 28Reserved + DCD 0 ; 29Reserved + DCD 0 ; 30Reserved + DCD 0 ; 31Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +ADC_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +LPTIM1_IRQHandler +TIM16_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x4.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x4.s old mode 100755 new mode 100644 index 9e59d9b..c941281 --- a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x4.s +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x4.s @@ -9,22 +9,38 @@ ;* calls main()). ;* After Reset the CortexM0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) Puya Semiconductor Co. -;* All rights reserved.

+;* Copyright (c) 2021, Puya Semiconductor Inc. ;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

+;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* ;****************************************************************************** -;* <<< Use Configuration Wizard in Context Menu >>> ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x6.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x6.s old mode 100755 new mode 100644 index 9e59d9b..c941281 --- a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x6.s +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x6.s @@ -9,22 +9,38 @@ ;* calls main()). ;* After Reset the CortexM0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) Puya Semiconductor Co. -;* All rights reserved.

+;* Copyright (c) 2021, Puya Semiconductor Inc. ;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

+;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* ;****************************************************************************** -;* <<< Use Configuration Wizard in Context Menu >>> ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x8.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x8.s old mode 100755 new mode 100644 index 9e59d9b..c941281 --- a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x8.s +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f003x8.s @@ -9,22 +9,38 @@ ;* calls main()). ;* After Reset the CortexM0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) Puya Semiconductor Co. -;* All rights reserved.

+;* Copyright (c) 2021, Puya Semiconductor Inc. ;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

+;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* ;****************************************************************************** -;* <<< Use Configuration Wizard in Context Menu >>> ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x3.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x3.s old mode 100755 new mode 100644 index 5645f94..3b4953d --- a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x3.s +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x3.s @@ -9,22 +9,38 @@ ;* calls main()). ;* After Reset the CortexM0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) Puya Semiconductor Co. -;* All rights reserved.

+;* Copyright (c) 2021, Puya Semiconductor Inc. ;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

+;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* ;****************************************************************************** -;* <<< Use Configuration Wizard in Context Menu >>> ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x4.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x4.s old mode 100755 new mode 100644 index 5645f94..3b4953d --- a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x4.s +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x4.s @@ -9,22 +9,38 @@ ;* calls main()). ;* After Reset the CortexM0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) Puya Semiconductor Co. -;* All rights reserved.

+;* Copyright (c) 2021, Puya Semiconductor Inc. ;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

+;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* ;****************************************************************************** -;* <<< Use Configuration Wizard in Context Menu >>> ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x6.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x6.s old mode 100755 new mode 100644 index 5645f94..3b4953d --- a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x6.s +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x6.s @@ -9,22 +9,38 @@ ;* calls main()). ;* After Reset the CortexM0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) Puya Semiconductor Co. -;* All rights reserved.

+;* Copyright (c) 2021, Puya Semiconductor Inc. ;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

+;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* ;****************************************************************************** -;* <<< Use Configuration Wizard in Context Menu >>> ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x7.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x7.s old mode 100755 new mode 100644 index 5645f94..3b4953d --- a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x7.s +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x7.s @@ -9,22 +9,38 @@ ;* calls main()). ;* After Reset the CortexM0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) Puya Semiconductor Co. -;* All rights reserved.

+;* Copyright (c) 2021, Puya Semiconductor Inc. ;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

+;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* ;****************************************************************************** -;* <<< Use Configuration Wizard in Context Menu >>> ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x8.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x8.s old mode 100755 new mode 100644 index 5645f94..3b4953d --- a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x8.s +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f030x8.s @@ -9,22 +9,38 @@ ;* calls main()). ;* After Reset the CortexM0+ processor is in Thread mode, ;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> ;****************************************************************************** ;* @attention ;* -;*

© Copyright (c) Puya Semiconductor Co. -;* All rights reserved.

+;* Copyright (c) 2021, Puya Semiconductor Inc. ;* -;*

© Copyright (c) 2016 STMicroelectronics. -;* All rights reserved.

+;* All rights reserved. ;* -;* This software component is licensed by ST under BSD 3-Clause license, -;* the "License"; You may not use this file except in compliance with the -;* License. You may obtain a copy of the License at: -;* opensource.org/licenses/BSD-3-Clause +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ;* ;****************************************************************************** -;* <<< Use Configuration Wizard in Context Menu >>> ; Amount of memory (in bytes) allocated for Stack ; Tailor this value to your application needs diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f072xB.s b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f072xB.s new file mode 100644 index 0000000..4d66e03 --- /dev/null +++ b/Libraries/CMSIS/Device/PY32F0xx/Source/arm/startup_py32f072xB.s @@ -0,0 +1,268 @@ +;****************************************************************************** +;* @file : startup_py32f030xx.s +;* @brief : P32F030xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0+ processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;****************************************************************************** +;* @attention +;* +;* Copyright (c) 2021, Puya Semiconductor Inc. +;* +;* All rights reserved. +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of the copyright holder nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;****************************************************************************** + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; 0Window Watchdog + DCD PVD_IRQHandler ; 1PVD through EXTI Line detect + DCD RTC_IRQHandler ; 2RTC through EXTI Line + DCD FLASH_IRQHandler ; 3FLASH + DCD RCC_CTC_IRQHandler ; 4RCC, CTC + DCD EXTI0_1_IRQHandler ; 5EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; 6EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; 7EXTI Line 4 to 15 + DCD LCD_IRQHandler ; 8LCD + DCD DMA1_Channel1_IRQHandler ; 9DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; 10DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_6_7_IRQHandler ; 11DMA1 Channel 4, 5, 6, 7 + DCD ADC_COMP_IRQHandler ; 12ADC&COMP1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; 13TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; 14TIM1 Capture Compare + DCD TIM2_IRQHandler ; 15TIM2 + DCD TIM3_IRQHandler ; 16TIM3 + DCD TIM6_LPTIM1_DAC_IRQHandler ; 17TIM6, LPTIM1, DAC + DCD TIM7_IRQHandler ; 18TIM7 + DCD TIM14_IRQHandler ; 19TIM14 + DCD TIM15_IRQHandler ; 20TIM15 + DCD TIM16_IRQHandler ; 21TIM16 + DCD TIM17_IRQHandler ; 22TIM17 + DCD I2C1_IRQHandler ; 23I2C1 + DCD I2C2_IRQHandler ; 24I2C2 + DCD SPI1_IRQHandler ; 25SPI1 + DCD SPI2_IRQHandler ; 26SPI2 + DCD USART1_IRQHandler ; 27USART1 + DCD USART2_IRQHandler ; 28USART2 + DCD USART3_4_IRQHandler ; 29USART3, USART4 + DCD 0 ; 30Reserved + DCD USB_IRQHandler ; 31Reserved +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CTC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_6_7_IRQHandler [WEAK] + EXPORT ADC_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_LPTIM1_DAC_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_4_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CTC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +LCD_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_6_7_IRQHandler +ADC_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_LPTIM1_DAC_IRQHandler +TIM7_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_4_IRQHandler +USB_IRQHandler + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/iar/startup_py32f002axx.s b/Libraries/CMSIS/Device/PY32F0xx/Source/iar/startup_py32f002axx.s old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/iar/startup_py32f003xx.s b/Libraries/CMSIS/Device/PY32F0xx/Source/iar/startup_py32f003xx.s old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/iar/startup_py32f030xx.s b/Libraries/CMSIS/Device/PY32F0xx/Source/iar/startup_py32f030xx.s old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Device/PY32F0xx/Source/system_py32f0xx.c b/Libraries/CMSIS/Device/PY32F0xx/Source/system_py32f0xx.c old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/arm_common_tables.h b/Libraries/CMSIS/Include/arm_common_tables.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/arm_const_structs.h b/Libraries/CMSIS/Include/arm_const_structs.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/arm_math.h b/Libraries/CMSIS/Include/arm_math.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/cmsis_armcc.h b/Libraries/CMSIS/Include/cmsis_armcc.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/cmsis_armcc_V6.h b/Libraries/CMSIS/Include/cmsis_armcc_V6.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/cmsis_gcc.h b/Libraries/CMSIS/Include/cmsis_gcc.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/core_cm0.h b/Libraries/CMSIS/Include/core_cm0.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/core_cm0plus.h b/Libraries/CMSIS/Include/core_cm0plus.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/core_cm3.h b/Libraries/CMSIS/Include/core_cm3.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/core_cm4.h b/Libraries/CMSIS/Include/core_cm4.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/core_cm7.h b/Libraries/CMSIS/Include/core_cm7.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/core_cmFunc.h b/Libraries/CMSIS/Include/core_cmFunc.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/core_cmInstr.h b/Libraries/CMSIS/Include/core_cmInstr.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/core_cmSimd.h b/Libraries/CMSIS/Include/core_cmSimd.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/core_sc000.h b/Libraries/CMSIS/Include/core_sc000.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/Include/core_sc300.h b/Libraries/CMSIS/Include/core_sc300.h old mode 100755 new mode 100644 diff --git a/Libraries/CMSIS/RTOS/Template/cmsis_os.h b/Libraries/CMSIS/RTOS/Template/cmsis_os.h old mode 100755 new mode 100644 diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal.h b/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal.h old mode 100755 new mode 100644 diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_adc.h b/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_adc.h old mode 100755 new mode 100644 diff --git a/Libraries/PY32F0xx_HAL_Driver/Inc/py32f0xx_hal_adc_ex.h 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a/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_utils.c b/Libraries/PY32F0xx_LL_Driver/Src/py32f0xx_ll_utils.c old mode 100755 new mode 100644 diff --git a/Misc/Devices/Puya/PY32F003xx_16.FLM b/Misc/Flash/Devices/Puya/PY32F003xx_16.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F003xx_16.FLM rename to Misc/Flash/Devices/Puya/PY32F003xx_16.FLM diff --git a/Misc/Devices/Puya/PY32F003xx_32.FLM b/Misc/Flash/Devices/Puya/PY32F003xx_32.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F003xx_32.FLM rename to Misc/Flash/Devices/Puya/PY32F003xx_32.FLM diff --git a/Misc/Devices/Puya/PY32F003xx_64.FLM b/Misc/Flash/Devices/Puya/PY32F003xx_64.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F003xx_64.FLM rename to Misc/Flash/Devices/Puya/PY32F003xx_64.FLM diff --git a/Misc/Devices/Puya/PY32F003xx_OPT.FLM b/Misc/Flash/Devices/Puya/PY32F003xx_OPT.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F003xx_OPT.FLM rename to Misc/Flash/Devices/Puya/PY32F003xx_OPT.FLM diff --git a/Misc/Devices/Puya/PY32F030xx_16.FLM b/Misc/Flash/Devices/Puya/PY32F030xx_16.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F030xx_16.FLM rename to Misc/Flash/Devices/Puya/PY32F030xx_16.FLM diff --git a/Misc/Devices/Puya/PY32F030xx_32.FLM b/Misc/Flash/Devices/Puya/PY32F030xx_32.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F030xx_32.FLM rename to Misc/Flash/Devices/Puya/PY32F030xx_32.FLM diff --git a/Misc/Devices/Puya/PY32F030xx_48.FLM b/Misc/Flash/Devices/Puya/PY32F030xx_48.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F030xx_48.FLM rename to Misc/Flash/Devices/Puya/PY32F030xx_48.FLM diff --git a/Misc/Devices/Puya/PY32F030xx_64.FLM b/Misc/Flash/Devices/Puya/PY32F030xx_64.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F030xx_64.FLM rename to Misc/Flash/Devices/Puya/PY32F030xx_64.FLM diff --git a/Misc/Devices/Puya/PY32F030xx_8.FLM b/Misc/Flash/Devices/Puya/PY32F030xx_8.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F030xx_8.FLM rename to Misc/Flash/Devices/Puya/PY32F030xx_8.FLM diff --git a/Misc/Devices/Puya/PY32F030xx_OPT.FLM b/Misc/Flash/Devices/Puya/PY32F030xx_OPT.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F030xx_OPT.FLM rename to Misc/Flash/Devices/Puya/PY32F030xx_OPT.FLM diff --git a/Misc/Devices/Puya/PY32F072xx_128.FLM b/Misc/Flash/Devices/Puya/PY32F072xx_128.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F072xx_128.FLM rename to Misc/Flash/Devices/Puya/PY32F072xx_128.FLM diff --git a/Misc/Devices/Puya/PY32F072xx_OPT.FLM b/Misc/Flash/Devices/Puya/PY32F072xx_OPT.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F072xx_OPT.FLM rename to Misc/Flash/Devices/Puya/PY32F072xx_OPT.FLM diff --git a/Misc/Devices/Puya/PY32F0xx_16.FLM b/Misc/Flash/Devices/Puya/PY32F0xx_16.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F0xx_16.FLM rename to Misc/Flash/Devices/Puya/PY32F0xx_16.FLM diff --git a/Misc/Devices/Puya/PY32F0xx_20.FLM b/Misc/Flash/Devices/Puya/PY32F0xx_20.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F0xx_20.FLM rename to Misc/Flash/Devices/Puya/PY32F0xx_20.FLM diff --git a/Misc/Devices/Puya/PY32F0xx_32.FLM b/Misc/Flash/Devices/Puya/PY32F0xx_32.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F0xx_32.FLM rename to Misc/Flash/Devices/Puya/PY32F0xx_32.FLM diff --git a/Misc/Devices/Puya/PY32F0xx_48.FLM b/Misc/Flash/Devices/Puya/PY32F0xx_48.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F0xx_48.FLM rename to Misc/Flash/Devices/Puya/PY32F0xx_48.FLM diff --git a/Misc/Devices/Puya/PY32F0xx_64.FLM b/Misc/Flash/Devices/Puya/PY32F0xx_64.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F0xx_64.FLM rename to Misc/Flash/Devices/Puya/PY32F0xx_64.FLM diff --git a/Misc/Devices/Puya/PY32F0xx_8.FLM b/Misc/Flash/Devices/Puya/PY32F0xx_8.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F0xx_8.FLM rename to Misc/Flash/Devices/Puya/PY32F0xx_8.FLM diff --git a/Misc/Devices/Puya/PY32F0xx_OPT.FLM b/Misc/Flash/Devices/Puya/PY32F0xx_OPT.FLM similarity index 100% rename from Misc/Devices/Puya/PY32F0xx_OPT.FLM rename to Misc/Flash/Devices/Puya/PY32F0xx_OPT.FLM diff --git a/Misc/Flash/Sources/PY32F072xx/FlashDev.c b/Misc/Flash/Sources/PY32F072xx/FlashDev.c new file mode 100644 index 0000000..3347166 --- /dev/null +++ b/Misc/Flash/Sources/PY32F072xx/FlashDev.c @@ -0,0 +1,175 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2014 - 2019 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 2021-7-1 + * $Revision: V1.0.0 + * + * Project: Flash Device Description for Puya PY32F030xx Flash + * --------------------------------------------------------------------------- */ + +/* History: + * Version 1.0.0 + * Initial release + */ +#include "FlashOS.h" // FlashOS Structures + +#ifdef FLASH_MEM + +#ifdef PY32F072xB +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F072xx 128kB Flash", // Device Name (128kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x00020000, // Device Size in Bytes (128kB) + 0x100, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x2000, 0x000000, // Sector Size 4kB (2 sectors) + SECTOR_END +}; +#endif // PY32F072xB + +#ifdef PY32F030xx_8 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F030xx 8kB Flash", // Device Name (8kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x00002000, // Device Size in Bytes (8kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (2 sectors) + SECTOR_END +}; +#endif // PY32F030xx_8 + +#ifdef PY32F030xx_16 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F030xx 16kB Flash", // Device Name (16kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x00004000, // Device Size in Bytes (16kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (4 sectors) + SECTOR_END +}; +#endif // PY32F030xx_16 + +#ifdef PY32F030xx_32 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F030xx 32kB Flash", // Device Name (32kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x00008000, // Device Size in Bytes (32kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (8 sectors) + SECTOR_END +}; +#endif // PY32F030xx_32 + +#ifdef PY32F030xx_48 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F030xx 48kB Flash", // Device Name (48kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x0000C000, // Device Size in Bytes (48kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (12 sectors) + SECTOR_END +}; +#endif // PY32F030xx_48 + +#ifdef PY32F030xx_64 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F030xx 64kB Flash", // Device Name (64kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x00010000, // Device Size in Bytes (64kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (16 sectors) + SECTOR_END +}; +#endif // PY32F030xx_64 + +#endif // FLASH_MEM + +#ifdef FLASH_OPT +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F030xx Flash Options", // Device Name + ONCHIP, // Device Type + 0x1FFF0E80, // Device Start Address + 0x00000010, // Device Size in Bytes (16) + 0x10, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 3000, // Program Page Timeout 3 Sec + 3000, // Erase Sector Timeout 3 Sec + +//Specify Size and Address of Sectors + 0x00010, 0x000000, // Sector Size 16B (1 sectors) + SECTOR_END +}; +#endif // FLASH_OPT diff --git a/Misc/Flash/Sources/PY32F072xx/FlashOS.h b/Misc/Flash/Sources/PY32F072xx/FlashOS.h new file mode 100644 index 0000000..87e97f6 --- /dev/null +++ b/Misc/Flash/Sources/PY32F072xx/FlashOS.h @@ -0,0 +1,84 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 14. Jan 2014 + * $Revision: V1.00 + * + * Project: FlashOS Headerfile for Flash drivers + * --------------------------------------------------------------------------- */ + +/* History: + * Version 1.00 + * Initial release + */ + +#define VERS 1 // Interface Version 1.01 + +#define UNKNOWN 0 // Unknown +#define ONCHIP 1 // On-chip Flash Memory +#define EXT8BIT 2 // External Flash Device on 8-bit Bus +#define EXT16BIT 3 // External Flash Device on 16-bit Bus +#define EXT32BIT 4 // External Flash Device on 32-bit Bus +#define EXTSPI 5 // External Flash Device on SPI + +#define SECTOR_NUM 512 // Max Number of Sector Items +#define PAGE_MAX 65536 // Max Page Size for Programming + +struct FlashSectors { + unsigned long szSector; // Sector Size in Bytes + unsigned long AddrSector; // Address of Sector +}; + +#define SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF + +struct FlashDevice { + unsigned short Vers; // Version Number and Architecture + char DevName[128]; // Device Name and Description + unsigned short DevType; // Device Type: ONCHIP, EXT8BIT, EXT16BIT, ... + unsigned long DevAdr; // Default Device Start Address + unsigned long szDev; // Total Size of Device + unsigned long szPage; // Programming Page Size + unsigned long Res; // Reserved for future Extension + unsigned char valEmpty; // Content of Erased Memory + + unsigned long toProg; // Time Out of Program Page Function + unsigned long toErase; // Time Out of Erase Sector Function + + struct FlashSectors sectors[SECTOR_NUM]; +}; + +#define FLASH_DRV_VERS (0x0100+VERS) // Driver Version, do not modify! + +// Flash Programming Functions (Called by FlashOS) +extern int Init (unsigned long adr, // Initialize Flash + unsigned long clk, + unsigned long fnc); +extern int UnInit (unsigned long fnc); // De-initialize Flash +extern int BlankCheck (unsigned long adr, // Blank Check + unsigned long sz, + unsigned char pat); +extern int EraseChip (void); // Erase complete Device +extern int EraseSector (unsigned long adr); // Erase Sector Function +extern int ProgramPage (unsigned long adr, // Program Page Function + unsigned long sz, + unsigned char *buf); +extern unsigned long Verify (unsigned long adr, // Verify Function + unsigned long sz, + unsigned char *buf); diff --git a/Misc/Flash/Sources/PY32F072xx/FlashPrg.c b/Misc/Flash/Sources/PY32F072xx/FlashPrg.c new file mode 100644 index 0000000..fbdbc1e --- /dev/null +++ b/Misc/Flash/Sources/PY32F072xx/FlashPrg.c @@ -0,0 +1,452 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2014 - 2019 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 2021-7-1 + * $Revision: V1.0.0 + * + * Project: Flash Programming Functions for Puya PY32F030xx Flash + * --------------------------------------------------------------------------- */ + +/* History: + * Version 1.0.0 + * Initial release + */ + +#include "FlashOS.h" // FlashOS Structures +#include "py32f0xx.h" + +typedef volatile unsigned char vu8; +typedef unsigned char u8; +typedef volatile unsigned short vu16; +typedef unsigned short u16; +typedef volatile unsigned long vu32; +typedef unsigned long u32; + +#define M8(adr) (*((vu8 *) (adr))) +#define M16(adr) (*((vu16 *) (adr))) +#define M32(adr) (*((vu32 *) (adr))) + +//uint32_t gdw_HSI_FS; + +//#define USE_HSI_24MHZ + +////uiOffset = 0(4MHz), 1(8MHz), 2(16MHz), 3(22.12MHz), 4(24MHz) +//void SetFlashParameter(uint32_t uiOffset) +//{ +// FLASH->TS0 = ((M32(0x1FFF0F1C + uiOffset * 0x14) >> 0) & 0x000000FF); +// FLASH->TS3 = ((M32(0x1FFF0F1C + uiOffset * 0x14) >> 8) & 0x000000FF); +// FLASH->TS1 = ((M32(0x1FFF0F1C + uiOffset * 0x14) >> 16) & 0x000001FF); +// FLASH->TS2P = ((M32(0x1FFF0F20 + uiOffset * 0x14) >> 0) & 0x000000FF); +// FLASH->TPS3 = ((M32(0x1FFF0F20 + uiOffset * 0x14) >> 16) & 0x000007FF); +// FLASH->PERTPE = ((M32(0x1FFF0F24 + uiOffset * 0x14) >> 0) & 0x0001FFFF); +// FLASH->SMERTPE = ((M32(0x1FFF0F28 + uiOffset * 0x14) >> 0) & 0x0001FFFF); +// FLASH->PRGTPE = ((M32(0x1FFF0F2C + uiOffset * 0x14) >> 0) & 0x0000FFFF); +// FLASH->PRETPE = ((M32(0x1FFF0F2C + uiOffset * 0x14) >> 16) & 0x0000FFFF); +//} + +//void InitRccAndFlashParam(void) +//{ +//#ifdef USE_HSI_24MHZ +// gdw_HSI_FS = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS); +// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_FS, RCC_ICSCR_HSI_FS_2);//HSI_24MHz +// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F10)&RCC_ICSCR_HSI_TRIM); +// while (RCC_CR_HSIRDY != READ_BIT(RCC->CR, RCC_CR_HSIRDY)); +// SetFlashParameter(4); +//#else +// uint32_t dwOffset; +// switch (READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS)) +// { +// default://4MHz +// dwOffset = 0x00; +// break; +// case RCC_ICSCR_HSI_FS_0://8MHz +// dwOffset = 0x01; +// break; +// case RCC_ICSCR_HSI_FS_1://16MHz +// dwOffset = 0x02; +// break; +// case (RCC_ICSCR_HSI_FS_1|RCC_ICSCR_HSI_FS_0)://22.12MHz +// dwOffset = 0x03; +// break; +// case RCC_ICSCR_HSI_FS_2://24MHz +// dwOffset = 0x04; +// break; +// } +// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F00 + dwOffset * 4)&RCC_ICSCR_HSI_TRIM); +// WRITE_REG(FLASH->TS0, ((M32(0x1FFF0F1C + dwOffset * 0x14) >> 0) & 0x000000FF)); +// WRITE_REG(FLASH->TS1, ((M32(0x1FFF0F1C + dwOffset * 0x14) >> 8) & 0x000000FF)); +// WRITE_REG(FLASH->TS3, ((M32(0x1FFF0F1C + dwOffset * 0x14) >> 16) & 0x000001FF)); +// WRITE_REG(FLASH->TS2P, ((M32(0x1FFF0F20 + dwOffset * 0x14) >> 0) & 0x000000FF)); +// WRITE_REG(FLASH->TPS3, ((M32(0x1FFF0F20 + dwOffset * 0x14) >> 16) & 0x000007FF)); +// WRITE_REG(FLASH->PERTPE, ((M32(0x1FFF0F24 + dwOffset * 0x14) >> 0) & 0x0001FFFF)); +// WRITE_REG(FLASH->SMERTPE, ((M32(0x1FFF0F28 + dwOffset * 0x14) >> 0) & 0x0001FFFF)); +// WRITE_REG(FLASH->PRGTPE, ((M32(0x1FFF0F2C + dwOffset * 0x14) >> 0) & 0x0000FFFF)); +// WRITE_REG(FLASH->PRETPE, ((M32(0x1FFF0F2C + dwOffset * 0x14) >> 16) & 0x00000FFF)); +//#endif +//} + +//void UnInitRccAndFlashParam(void) +//{ +//#ifdef USE_HSI_24MHZ +// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_FS, gdw_HSI_FS); +// switch (gdw_HSI_FS) +// { +// case RCC_ICSCR_HSI_FS_2://24MHz +// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F10)&RCC_ICSCR_HSI_TRIM); +// break; +// case (RCC_ICSCR_HSI_FS_1|RCC_ICSCR_HSI_FS_0)://22.12MHz +// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F0C)&RCC_ICSCR_HSI_TRIM); +// break; +// case RCC_ICSCR_HSI_FS_1://16MHz +// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F08)&RCC_ICSCR_HSI_TRIM); +// break; +// case RCC_ICSCR_HSI_FS_0://8MHz +// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F04)&RCC_ICSCR_HSI_TRIM); +// break; +// default://4MHz +// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F00)&RCC_ICSCR_HSI_TRIM); +// break; +// } +// while (RCC_CR_HSIRDY != READ_BIT(RCC->CR, RCC_CR_HSIRDY)); +//#endif +//} + +/* + * Initialize Flash Programming Functions + * Parameter: adr: Device Base Address + * clk: Clock Frequency (Hz) + * fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify) + * Return Value: 0 - OK, 1 - Failed + */ + +#ifdef FLASH_MEM +int Init(unsigned long adr, unsigned long clk, unsigned long fnc) +{ + +// InitRccAndFlashParam(); + + FLASH->KEYR = FLASH_KEY1; // Unlock Flash + FLASH->KEYR = FLASH_KEY2; + + FLASH->ACR = 0x00000000; // Zero Wait State, no Prefetch + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + if ((FLASH->OPTR & FLASH_OPTR_IWDG_SW) == 0x00) // Test if IWDG is running (IWDG in HW mode) + { + // Set IWDG time out to ~32.768 second + IWDG->KR = 0x5555; // Enable write access to IWDG_PR and IWDG_RLR + IWDG->PR = 0x06; // Set prescaler to 256 + IWDG->RLR = 0xFFF; // Set reload value to 4095 + } + + return (0); +} +#endif + +#ifdef FLASH_OPT +int Init(unsigned long adr, unsigned long clk, unsigned long fnc) +{ + + InitRccAndFlashParam(); + + FLASH->KEYR = FLASH_KEY1; // Unlock Flash + FLASH->KEYR = FLASH_KEY2; + + FLASH->OPTKEYR = FLASH_OPTKEY1; // Unlock Option Bytes + FLASH->OPTKEYR = FLASH_OPTKEY2; + + FLASH->ACR = 0x00000000; // Zero Wait State, no Prefetch + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + + if ((FLASH->OPTR & 0x1000) == 0x00) // Test if IWDG is running (IWDG in HW mode) + { + // Set IWDG time out to ~32.768 second + IWDG->KR = 0x5555; // Enable write access to IWDG_PR and IWDG_RLR + IWDG->PR = 0x06; // Set prescaler to 256 + IWDG->RLR = 0xFFF; // Set reload value to 4095 + } + + return (0); +} +#endif + + +/* + * De-Initialize Flash Programming Functions + * Parameter: fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify) + * Return Value: 0 - OK, 1 - Failed + */ + +#ifdef FLASH_MEM +int UnInit(unsigned long fnc) +{ + +// UnInitRccAndFlashParam(); + + FLASH->CR |= FLASH_CR_LOCK; // Lock Flash + + return (0); +} +#endif + +#ifdef FLASH_OPT +int UnInit(unsigned long fnc) +{ + + UnInitRccAndFlashParam(); + + FLASH->CR |= FLASH_CR_LOCK; // Lock Flash + FLASH->CR |= FLASH_CR_OPTLOCK; // Lock Option Bytes + + return (0); +} +#endif + +/* + * Erase complete Flash Memory + * Return Value: 0 - OK, 1 - Failed + */ + +#ifdef FLASH_MEM +int EraseChip(void) +{ + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + FLASH->CR |= FLASH_CR_MER; // Mass Erase Enabled + FLASH->CR |= FLASH_CR_EOPIE; + M32(0x08000000) = 0xFF; + __asm("DSB"); + + while (FLASH->SR & FLASH_SR_BSY) + { + IWDG->KR = 0xAAAA; // Reload IWDG + } + + FLASH->CR &= ~FLASH_CR_MER; // Mass Erase Disabled + FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE + + if (FLASH_SR_EOP != (FLASH->SR & FLASH_SR_EOP)) // Check for FLASH_SR_EOP + { + FLASH->SR |= FLASH_SR_EOP; + return (1); // Failed + } + + return (0); // Done +} +#endif + +#ifdef FLASH_OPT +int EraseChip(void) +{ + + /* erase chip is not needed for + - Flash Option bytes + - Flash One Time Programmable bytes + */ + return (0); // Done +} +#endif + +/* + * Erase Sector in Flash Memory + * Parameter: adr: Sector Address + * Return Value: 0 - OK, 1 - Failed + */ + +#ifdef FLASH_MEM +int EraseSector(unsigned long adr) +{ + + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + FLASH->CR |= FLASH_CR_SER; // Sector Erase Enabled + FLASH->CR |= FLASH_CR_EOPIE; + M32(adr) = 0xFF; // Sector Address + __asm("DSB"); + + while (FLASH->SR & FLASH_SR_BSY) + { + IWDG->KR = 0xAAAA; // Reload IWDG + } + + FLASH->CR &= ~FLASH_CR_SER; // Sector Erase Disabled + FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE + +// if (FLASH_EOP != (FLASH->SR & FLASH_EOP)) { // Check for FLASH_SR_EOP +// FLASH->SR |= FLASH_EOP; +// return (1); // Failed +// } + + return (0); // Done +} +#endif + + +#ifdef FLASH_OPT +int EraseSector(unsigned long adr) +{ + /* erase sector is not needed for + - Flash Option bytes + - Flash One Time Programmable bytes + */ + return (0); // Done +} +#endif + +/* + * Blank Check Checks if Memory is Blank + * Parameter: adr: Block Start Address + * sz: Block Size (in bytes) + * pat: Block Pattern + * Return Value: 0 - OK, 1 - Failed + */ + +int BlankCheck(unsigned long adr, unsigned long sz, unsigned char pat) +{ + return (1); // Always Force Erase +} + + +/* + * Program Page in Flash Memory + * Parameter: adr: Page Start Address + * sz: Page Size + * buf: Page Data + * Return Value: 0 - OK, 1 - Failed + */ + +#ifdef FLASH_MEM +int ProgramPage(unsigned long adr, unsigned long sz, unsigned char *buf) +{ + + sz = (sz + 127) & ~127; // Adjust size for 32 Words + + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + while (sz) + { + FLASH->CR |= FLASH_CR_PG; // Programming Enabled + FLASH->CR |= FLASH_CR_EOPIE; + + for (u8 i = 0; i < 32; i++) + { + + M32(adr + i * 4) = *((u32 *)(buf + i * 4)); // Program the first word of the Double Word + if (i == 30) + { + FLASH->CR |= FLASH_CR_PGSTRT; + } + } + __asm("DSB"); + + while (FLASH->SR & FLASH_SR_BSY) + { + IWDG->KR = 0xAAAA; // Reload IWDG + } + + FLASH->CR &= ~FLASH_CR_PG; // Programming Disabled + FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE + + //ΪÁËÄܹ»Program SRAM£¬ÆÁ±ÎÏÂÃæµÄEOP¼ì²é +// if (FLASH_EOP != (FLASH->SR & FLASH_EOP)) { // Check for FLASH_SR_EOP +// FLASH->SR |= FLASH_EOP; +// return (1); // Failed +// } + + adr += 128; // Go to next Page + buf += 128; + sz -= 128; + } + + return (0); // Done +} +#endif // PY32F030xx_64 || FLASH_OTP + +#ifdef FLASH_OPT +int ProgramPage(unsigned long adr, unsigned long sz, unsigned char *buf) +{ + + u32 optr; + u32 sdkr; + u32 wrpr; + + optr = *((u32 *)(buf + 0x00)); + sdkr = *((u32 *)(buf + 0x04)); + wrpr = *((u32 *)(buf + 0x0C)); + + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + FLASH->OPTR = (optr & 0x0000FFFF); // Write OPTR values + FLASH->SDKR = (sdkr & 0x0000FFFF); // Write SDKR values + FLASH->WRPR = (wrpr & 0x0000FFFF); // Write WRPR values + + FLASH->CR |= FLASH_CR_OPTSTRT; + FLASH->CR |= FLASH_CR_EOPIE; + M32(0x40022080) = 0xFF; + __asm("DSB"); + + FLASH->CR &= ~FLASH_CR_OPTSTRT; // Programming Disabled + FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE + +#ifdef FLASH_OPT_OBL_LAUNCH + FLASH->CR |= FLASH_CR_OBL_LAUNCH; +#endif + + return (0); // Done +} +#endif // FLASH_OPT + + +/* + * Verify Flash Contents + * Parameter: adr: Start Address + * sz: Size (in bytes) + * buf: Data + * Return Value: (adr+sz) - OK, Failed Address + */ + +#ifdef FLASH_OPT +unsigned long Verify(unsigned long adr, unsigned long sz, unsigned char *buf) +{ + u32 optr; + u32 sdkr; + u32 wrpr; + + optr = *((u32 *)(buf + 0x00)); + sdkr = *((u32 *)(buf + 0x04)); + wrpr = *((u32 *)(buf + 0x0C)); + + if (M32(adr + 0x00) != optr) + { + return (adr + 0x00); + } + if (M32(adr + 0x04) != sdkr) + { + return (adr + 0x04); + } + if (M32(adr + 0x0C) != wrpr) + { + return (adr + 0x0C); + } + + return (adr + sz); +} +#endif // FLASH_OPT diff --git a/Misc/Flash/Sources/PY32F072xx/PY32F072xx.uvoptx b/Misc/Flash/Sources/PY32F072xx/PY32F072xx.uvoptx new file mode 100644 index 0000000..3f81e1b --- /dev/null +++ b/Misc/Flash/Sources/PY32F072xx/PY32F072xx.uvoptx @@ -0,0 +1,1254 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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L6305 + + + + + + + + Program Functions + + + FlashPrg.c + 1 + .\FlashPrg.c + + + + + Device Description + + + FlashDev.c + 1 + .\FlashDev.c + + + + + + + + + + + + + + diff --git a/Misc/Flash/Sources/PY32F072xx/Target.lin b/Misc/Flash/Sources/PY32F072xx/Target.lin new file mode 100644 index 0000000..3190469 --- /dev/null +++ b/Misc/Flash/Sources/PY32F072xx/Target.lin @@ -0,0 +1,22 @@ +; Linker Control File (scatter-loading) +; + +PRG 0 PI ; Programming Functions +{ + PrgCode +0 ; Code + { + * (+RO) + } + PrgData +0 ; Data + { + * (+RW,+ZI) + } +} + +DSCR +0 ; Device Description +{ + DevDscr +0 + { + FlashDev.o + } +} diff --git a/Misc/Flash/Sources/PY32F0xx/FlashDev.c b/Misc/Flash/Sources/PY32F0xx/FlashDev.c new file mode 100644 index 0000000..ce279a2 --- /dev/null +++ b/Misc/Flash/Sources/PY32F0xx/FlashDev.c @@ -0,0 +1,175 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2014 - 2019 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 2021-7-1 + * $Revision: V1.0.0 + * + * Project: Flash Device Description for Puya PY32F0xx Flash + * --------------------------------------------------------------------------- */ + +/* History: + * Version 1.0.0 + * Initial release + */ +#include "FlashOS.h" // FlashOS Structures + +#ifdef FLASH_MEM + +#ifdef PY32F0xx_8 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F0xx 8kB Flash", // Device Name (8kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x00002000, // Device Size in Bytes (8kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (2 sectors) + SECTOR_END +}; +#endif // PY32F0xx_8 + +#ifdef PY32F0xx_16 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F0xx 16kB Flash", // Device Name (16kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x00004000, // Device Size in Bytes (16kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (4 sectors) + SECTOR_END +}; +#endif // PY32F0xx_16 + +#ifdef PY32F0xx_20 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F0xx 20kB Flash", // Device Name (20kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x00005000, // Device Size in Bytes (20kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (5 sectors) + SECTOR_END +}; +#endif // PY32F0xx_20 + +#ifdef PY32F0xx_32 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F0xx 32kB Flash", // Device Name (32kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x00008000, // Device Size in Bytes (32kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (8 sectors) + SECTOR_END +}; +#endif // PY32F0xx_32 + +#ifdef PY32F0xx_48 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F0xx 48kB Flash", // Device Name (48kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x0000C000, // Device Size in Bytes (48kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (12 sectors) + SECTOR_END +}; +#endif // PY32F0xx_48 + +#ifdef PY32F0xx_64 +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F0xx 64kB Flash", // Device Name (64kB) + ONCHIP, // Device Type + 0x08000000, // Device Start Address + 0x00010000, // Device Size in Bytes (64kB) + 0x80, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 600, // Program Page Timeout 600 mSec + 6000, // Erase Sector Timeout 6000 mSec + +//Specify Size and Address of Sectors + 0x1000, 0x000000, // Sector Size 4kB (16 sectors) + SECTOR_END +}; +#endif // PY32F0xx_64 + +#endif // FLASH_MEM + +#ifdef FLASH_OPT +struct FlashDevice const FlashDevice = +{ + FLASH_DRV_VERS, // Driver Version, do not modify! + "PY32F0xx Flash Options", // Device Name + ONCHIP, // Device Type + 0x1FFF0E80, // Device Start Address + 0x00000010, // Device Size in Bytes (16) + 0x10, // Programming Page Size + 0, // Reserved, must be 0 + 0xFF, // Initial Content of Erased Memory + 3000, // Program Page Timeout 3 Sec + 3000, // Erase Sector Timeout 3 Sec + +//Specify Size and Address of Sectors + 0x00010, 0x000000, // Sector Size 16B (1 sectors) + SECTOR_END +}; +#endif // FLASH_OPT diff --git a/Misc/Flash/Sources/PY32F0xx/FlashOS.h b/Misc/Flash/Sources/PY32F0xx/FlashOS.h new file mode 100644 index 0000000..87e97f6 --- /dev/null +++ b/Misc/Flash/Sources/PY32F0xx/FlashOS.h @@ -0,0 +1,84 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2014 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 14. Jan 2014 + * $Revision: V1.00 + * + * Project: FlashOS Headerfile for Flash drivers + * --------------------------------------------------------------------------- */ + +/* History: + * Version 1.00 + * Initial release + */ + +#define VERS 1 // Interface Version 1.01 + +#define UNKNOWN 0 // Unknown +#define ONCHIP 1 // On-chip Flash Memory +#define EXT8BIT 2 // External Flash Device on 8-bit Bus +#define EXT16BIT 3 // External Flash Device on 16-bit Bus +#define EXT32BIT 4 // External Flash Device on 32-bit Bus +#define EXTSPI 5 // External Flash Device on SPI + +#define SECTOR_NUM 512 // Max Number of Sector Items +#define PAGE_MAX 65536 // Max Page Size for Programming + +struct FlashSectors { + unsigned long szSector; // Sector Size in Bytes + unsigned long AddrSector; // Address of Sector +}; + +#define SECTOR_END 0xFFFFFFFF, 0xFFFFFFFF + +struct FlashDevice { + unsigned short Vers; // Version Number and Architecture + char DevName[128]; // Device Name and Description + unsigned short DevType; // Device Type: ONCHIP, EXT8BIT, EXT16BIT, ... + unsigned long DevAdr; // Default Device Start Address + unsigned long szDev; // Total Size of Device + unsigned long szPage; // Programming Page Size + unsigned long Res; // Reserved for future Extension + unsigned char valEmpty; // Content of Erased Memory + + unsigned long toProg; // Time Out of Program Page Function + unsigned long toErase; // Time Out of Erase Sector Function + + struct FlashSectors sectors[SECTOR_NUM]; +}; + +#define FLASH_DRV_VERS (0x0100+VERS) // Driver Version, do not modify! + +// Flash Programming Functions (Called by FlashOS) +extern int Init (unsigned long adr, // Initialize Flash + unsigned long clk, + unsigned long fnc); +extern int UnInit (unsigned long fnc); // De-initialize Flash +extern int BlankCheck (unsigned long adr, // Blank Check + unsigned long sz, + unsigned char pat); +extern int EraseChip (void); // Erase complete Device +extern int EraseSector (unsigned long adr); // Erase Sector Function +extern int ProgramPage (unsigned long adr, // Program Page Function + unsigned long sz, + unsigned char *buf); +extern unsigned long Verify (unsigned long adr, // Verify Function + unsigned long sz, + unsigned char *buf); diff --git a/Misc/Flash/Sources/PY32F0xx/FlashPrg.c b/Misc/Flash/Sources/PY32F0xx/FlashPrg.c new file mode 100644 index 0000000..a731782 --- /dev/null +++ b/Misc/Flash/Sources/PY32F0xx/FlashPrg.c @@ -0,0 +1,542 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2014 - 2019 ARM Ltd. + * + * This software is provided 'as-is', without any express or implied warranty. + * In no event will the authors be held liable for any damages arising from + * the use of this software. Permission is granted to anyone to use this + * software for any purpose, including commercial applications, and to alter + * it and redistribute it freely, subject to the following restrictions: + * + * 1. The origin of this software must not be misrepresented; you must not + * claim that you wrote the original software. If you use this software in + * a product, an acknowledgment in the product documentation would be + * appreciated but is not required. + * + * 2. Altered source versions must be plainly marked as such, and must not be + * misrepresented as being the original software. + * + * 3. This notice may not be removed or altered from any source distribution. + * + * + * $Date: 2021-7-1 + * $Revision: V1.0.0 + * + * Project: Flash Programming Functions for Puya PY32F0xx Flash + * --------------------------------------------------------------------------- */ + +/* History: + * Version 1.0.0 + * Initial release + */ + +#include "FlashOS.h" // FlashOS Structures + +typedef volatile unsigned char vu8; +typedef unsigned char u8; +typedef volatile unsigned short vu16; +typedef unsigned short u16; +typedef volatile unsigned long vu32; +typedef unsigned long u32; + +#define M8(adr) (*((vu8 *) (adr))) +#define M16(adr) (*((vu16 *) (adr))) +#define M32(adr) (*((vu32 *) (adr))) + +#define SET_BIT(REG, BIT) ((REG) |= (BIT)) +#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT)) +#define READ_BIT(REG, BIT) ((REG) & (BIT)) +#define CLEAR_REG(REG) ((REG) = (0x0)) +#define WRITE_REG(REG, VAL) ((REG) = (VAL)) +#define READ_REG(REG) ((REG)) +#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK))) + +// Peripheral Memory Map +#define RCC_BASE 0x40021000 +#define IWDG_BASE 0x40003000 +#define FLASH_BASE 0x40022000 + +#define RCC ((RCC_TypeDef*) RCC_BASE) +#define IWDG ((IWDG_TypeDef *) IWDG_BASE) +#define FLASH ((FLASH_TypeDef*) FLASH_BASE) + +typedef struct +{ + vu32 CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ + vu32 ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ +} RCC_TypeDef; + +// Independent WATCHDOG +typedef struct { + vu32 KR; /*!< IWDG Key register, Address offset: 0x00 */ + vu32 PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ + vu32 RLR; /*!< IWDG Reload register, Address offset: 0x08 */ + vu32 SR; /*!< IWDG Status register, Address offset: 0x0C */ +} IWDG_TypeDef; + +// Flash Registers +typedef struct { + vu32 ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ + vu32 RESERVED1; /*!< Reserved1, Address offset: 0x04 */ + vu32 KEYR; /*!< FLASH Key register, Address offset: 0x08 */ + vu32 OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ + vu32 SR; /*!< FLASH Status register, Address offset: 0x10 */ + vu32 CR; /*!< FLASH Control register, Address offset: 0x14 */ + vu32 RESERVED2[2]; /*!< Reserved2, Address offset: 0x18-0x1C */ + vu32 OPTR; /*!< FLASH Option register, Address offset: 0x20 */ + vu32 SDKR; /*!< FLASH SDK address register, Address offset: 0x24 */ + vu32 RESERVED3; /*!< Reserved2, Address offset: 0x28 */ + vu32 WRPR; /*!< FLASH WRP address register, Address offset: 0x2C */ + vu32 RESERVED4[(0x90 - 0x2C) / 4 - 1]; + vu32 STCR; /*!< FLASH sleep time config register, Address offset: 0x90 */ + vu32 RESERVED5[(0x100 - 0x90) / 4 - 1]; + vu32 TS0; /*!< FLASH TS0 register, Address offset: 0x100 */ + vu32 TS1; /*!< FLASH TS1 register, Address offset: 0x104 */ + vu32 TS2P; /*!< FLASH TS2P register, Address offset: 0x108 */ + vu32 TPS3; /*!< FLASH TPS3 register, Address offset: 0x10C */ + vu32 TS3; /*!< FLASH TS3 register, Address offset: 0x110 */ + vu32 PERTPE; /*!< FLASH PERTPE register, Address offset: 0x114 */ + vu32 SMERTPE; /*!< FLASH SMERTPE register, Address offset: 0x118 */ + vu32 PRGTPE; /*!< FLASH PRGTPE register, Address offset: 0x11C */ + vu32 PRETPE; /*!< FLASH PRETPE register, Address offset: 0x120 */ +} FLASH_TypeDef; + + +// Flash Keys +#define FLASH_KEY1 ((unsigned int)0x45670123) +#define FLASH_KEY2 ((unsigned int)0xCDEF89AB) +#define FLASH_OPTKEY1 ((unsigned int)0x08192A3B) +#define FLASH_OPTKEY2 ((unsigned int)0x4C5D6E7F) + +// Flash Control Register definitions +#define FLASH_CR_PG_Pos (0U) +#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */ +#define FLASH_CR_PG FLASH_CR_PG_Msk +#define FLASH_CR_PER_Pos (1U) +#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */ +#define FLASH_CR_PER FLASH_CR_PER_Msk +#define FLASH_CR_MER_Pos (2U) +#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */ +#define FLASH_CR_MER FLASH_CR_MER_Msk +#define FLASH_CR_SER_Pos (11U) +#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000800 */ +#define FLASH_CR_SER FLASH_CR_SER_Msk +#define FLASH_CR_OPTSTRT_Pos (17U) +#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */ +#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk +#define FLASH_CR_PGSTRT_Pos (19U) +#define FLASH_CR_PGSTRT_Msk (0x1UL << FLASH_CR_PGSTRT_Pos) /*!< 0x00080000 */ +#define FLASH_CR_PGSTRT FLASH_CR_PGSTRT_Msk +#define FLASH_CR_EOPIE_Pos (24U) +#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */ +#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk +#define FLASH_CR_ERRIE_Pos (25U) +#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */ +#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk +#define FLASH_CR_OBL_LAUNCH_Pos (27U) +#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */ +#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk +#define FLASH_CR_OPTLOCK_Pos (30U) +#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */ +#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk +#define FLASH_CR_LOCK_Pos (31U) +#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */ +#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk + +// Flash Status Register definitions +#define FLASH_SR_EOP_Pos (0U) +#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */ +#define FLASH_SR_EOP FLASH_SR_EOP_Msk +#define FLASH_SR_WRPERR_Pos (4U) +#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */ +#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk +#define FLASH_SR_OPTVERR_Pos (15U) +#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */ +#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk +#define FLASH_SR_BSY_Pos (16U) +#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */ +#define FLASH_SR_BSY FLASH_SR_BSY_Msk + +#define FLASH_OPTR_IWDG_SW_Pos (12U) +#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */ +#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk +#define FLASH_OPTR_WWDG_SW_Pos (13U) +#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */ +#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk + +u32 RCC_ICSCR_HSI_FS_RESTORE; +void InitRccAndFlashParam(void); +void UnInitRccAndFlashParam(void); + +/* + * Initialize Flash Programming Functions + * Parameter: adr: Device Base Address + * clk: Clock Frequency (Hz) + * fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify) + * Return Value: 0 - OK, 1 - Failed + */ + +#ifdef FLASH_MEM +int Init(unsigned long adr, unsigned long clk, unsigned long fnc) +{ + FLASH->KEYR = FLASH_KEY1; // Unlock Flash + FLASH->KEYR = FLASH_KEY2; + + InitRccAndFlashParam(); + + FLASH->ACR = 0x00000000; // Zero Wait State, no Prefetch + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + if ((FLASH->OPTR & FLASH_OPTR_IWDG_SW) == 0x00) // Test if IWDG is running (IWDG in HW mode) + { + // Set IWDG time out to ~32.768 second + IWDG->KR = 0x5555; // Enable write access to IWDG_PR and IWDG_RLR + IWDG->PR = 0x06; // Set prescaler to 256 + IWDG->RLR = 0xFFF; // Set reload value to 4095 + } + + return (0); +} +#endif + +#ifdef FLASH_OPT +int Init(unsigned long adr, unsigned long clk, unsigned long fnc) +{ + FLASH->KEYR = FLASH_KEY1; // Unlock Flash + FLASH->KEYR = FLASH_KEY2; + + InitRccAndFlashParam(); + + FLASH->OPTKEYR = FLASH_OPTKEY1; // Unlock Option Bytes + FLASH->OPTKEYR = FLASH_OPTKEY2; + + FLASH->ACR = 0x00000000; // Zero Wait State, no Prefetch + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + + if ((FLASH->OPTR & 0x1000) == 0x00) // Test if IWDG is running (IWDG in HW mode) + { + // Set IWDG time out to ~32.768 second + IWDG->KR = 0x5555; // Enable write access to IWDG_PR and IWDG_RLR + IWDG->PR = 0x06; // Set prescaler to 256 + IWDG->RLR = 0xFFF; // Set reload value to 4095 + } + + return (0); +} +#endif + + +/* + * De-Initialize Flash Programming Functions + * Parameter: fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify) + * Return Value: 0 - OK, 1 - Failed + */ + +#ifdef FLASH_MEM +int UnInit(unsigned long fnc) +{ + + UnInitRccAndFlashParam(); + + FLASH->CR |= FLASH_CR_LOCK; // Lock Flash + + return (0); +} +#endif + +#ifdef FLASH_OPT +int UnInit(unsigned long fnc) +{ + + UnInitRccAndFlashParam(); + + FLASH->CR |= FLASH_CR_LOCK; // Lock Flash + FLASH->CR |= FLASH_CR_OPTLOCK; // Lock Option Bytes + + return (0); +} +#endif + +/* + * Erase complete Flash Memory + * Return Value: 0 - OK, 1 - Failed + */ + +#ifdef FLASH_MEM +int EraseChip(void) +{ + + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + FLASH->CR |= FLASH_CR_MER; // Mass Erase Enabled + FLASH->CR |= FLASH_CR_EOPIE; + M32(0x08000000) = 0xFF; + __asm("DSB"); + + while (FLASH->SR & FLASH_SR_BSY) + { + IWDG->KR = 0xAAAA; // Reload IWDG + } + + FLASH->CR &= ~FLASH_CR_MER; // Mass Erase Disabled + FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE + + if (FLASH_SR_EOP != (FLASH->SR & FLASH_SR_EOP)) // Check for FLASH_SR_EOP + { + FLASH->SR |= FLASH_SR_EOP; + return (1); // Failed + } + + return (0); // Done +} +#endif + +#ifdef FLASH_OPT +int EraseChip(void) +{ + + /* erase chip is not needed for + - Flash Option bytes + - Flash One Time Programmable bytes + */ + return (0); // Done +} +#endif + +/* + * Erase Sector in Flash Memory + * Parameter: adr: Sector Address + * Return Value: 0 - OK, 1 - Failed + */ + +#ifdef FLASH_MEM +int EraseSector(unsigned long adr) +{ + + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + FLASH->CR |= FLASH_CR_SER; // Sector Erase Enabled + FLASH->CR |= FLASH_CR_EOPIE; + M32(adr) = 0xFF; // Sector Address + __asm("DSB"); + + while (FLASH->SR & FLASH_SR_BSY) + { + IWDG->KR = 0xAAAA; // Reload IWDG + } + + FLASH->CR &= ~FLASH_CR_SER; // Sector Erase Disabled + FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE + +// if (FLASH_EOP != (FLASH->SR & FLASH_EOP)) { // Check for FLASH_SR_EOP +// FLASH->SR |= FLASH_EOP; +// return (1); // Failed +// } + + return (0); // Done +} +#endif + + +#ifdef FLASH_OPT +int EraseSector(unsigned long adr) +{ + /* erase sector is not needed for + - Flash Option bytes + - Flash One Time Programmable bytes + */ + return (0); // Done +} +#endif + +/* + * Blank Check Checks if Memory is Blank + * Parameter: adr: Block Start Address + * sz: Block Size (in bytes) + * pat: Block Pattern + * Return Value: 0 - OK, 1 - Failed + */ + +int BlankCheck(unsigned long adr, unsigned long sz, unsigned char pat) +{ + return (1); // Always Force Erase +} + + +/* + * Program Page in Flash Memory + * Parameter: adr: Page Start Address + * sz: Page Size + * buf: Page Data + * Return Value: 0 - OK, 1 - Failed + */ + +#ifdef FLASH_MEM +int ProgramPage(unsigned long adr, unsigned long sz, unsigned char *buf) +{ + + sz = (sz + 127) & ~127; // Adjust size for 32 Words + + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + while (sz) + { + FLASH->CR |= FLASH_CR_PG; // Programming Enabled + FLASH->CR |= FLASH_CR_EOPIE; + + for (u8 i = 0; i < 32; i++) + { + + M32(adr + i * 4) = *((u32 *)(buf + i * 4)); // Program the first word of the Double Word + if (i == 30) + { + FLASH->CR |= FLASH_CR_PGSTRT; + } + } + __asm("DSB"); + + while (FLASH->SR & FLASH_SR_BSY) + { + IWDG->KR = 0xAAAA; // Reload IWDG + } + + FLASH->CR &= ~FLASH_CR_PG; // Programming Disabled + FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE + +// if (FLASH_EOP != (FLASH->SR & FLASH_EOP)) { // Check for FLASH_SR_EOP +// FLASH->SR |= FLASH_EOP; +// return (1); // Failed +// } + + adr += 128; // Go to next Page + buf += 128; + sz -= 128; + } + + return (0); // Done +} +#endif // FLASH_MEM + +#ifdef FLASH_OPT +int ProgramPage(unsigned long adr, unsigned long sz, unsigned char *buf) +{ + u32 optr; + u32 sdkr; + u32 wrpr; + + optr = *((u32 *)(buf + 0x00)); + sdkr = *((u32 *)(buf + 0x04)); + wrpr = *((u32 *)(buf + 0x0C)); + + FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP + + FLASH->OPTR = (optr & 0x0000FFFF); // Write OPTR values + FLASH->SDKR = (sdkr & 0x0000FFFF); // Write SDKR values + FLASH->WRPR = (wrpr & 0x0000FFFF); // Write WRPR values + + FLASH->CR |= FLASH_CR_OPTSTRT; + FLASH->CR |= FLASH_CR_EOPIE; + M32(0x40022080) = 0xFF; + __asm("DSB"); + + FLASH->CR &= ~FLASH_CR_OPTSTRT; // Programming Disabled + FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE + + //FLASH->CR |= FLASH_CR_OBL_LAUNCH; + + return (0); // Done +} +#endif // FLASH_OPT + + +/* + * Verify Flash Contents + * Parameter: adr: Start Address + * sz: Size (in bytes) + * buf: Data + * Return Value: (adr+sz) - OK, Failed Address + */ + +#ifdef FLASH_OPT +unsigned long Verify(unsigned long adr, unsigned long sz, unsigned char *buf) +{ + u32 optr; + u32 sdkr; + u32 wrpr; + + optr = *((u32 *)(buf + 0x00)); + sdkr = *((u32 *)(buf + 0x04)); + wrpr = *((u32 *)(buf + 0x0C)); + + if (M32(adr + 0x00) != optr) + { + return (adr + 0x00); + } + if (M32(adr + 0x04) != sdkr) + { + return (adr + 0x04); + } + if (M32(adr + 0x0C) != wrpr) + { + return (adr + 0x0C); + } + + return (adr + sz); +} +#endif // FLASH_OPT + + +#define RCC_CR_HSIRDY_Pos (10U) +#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */ +#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */ +#define RCC_ICSCR_HSI_TRIM_Pos (0U) +#define RCC_ICSCR_HSI_TRIM_Msk (0x1FFFUL << RCC_ICSCR_HSI_TRIM_Pos) /*!< 0x00001FFF */ +#define RCC_ICSCR_HSI_TRIM RCC_ICSCR_HSI_TRIM_Msk /*!< HSITRIM[14:8] bits */ +#define RCC_ICSCR_HSI_FS_Pos (13U) +#define RCC_ICSCR_HSI_FS_Msk (0x7UL << RCC_ICSCR_HSI_FS_Pos) /*!< 0x0000E000 */ +#define RCC_ICSCR_HSI_FS RCC_ICSCR_HSI_FS_Msk /*!< HSIFS[15:13] bits */ +#define RCC_ICSCR_HSI_FS_0 (0x01UL << RCC_ICSCR_HSI_FS_Pos) /*!< 0x00002000 */ +#define RCC_ICSCR_HSI_FS_1 (0x02UL << RCC_ICSCR_HSI_FS_Pos) /*!< 0x00004000 */ +#define RCC_ICSCR_HSI_FS_2 (0x04UL << RCC_ICSCR_HSI_FS_Pos) /*!< 0x00008000 */ + +void InitRccAndFlashParam(void) +{ + RCC_ICSCR_HSI_FS_RESTORE = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS); + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_FS, RCC_ICSCR_HSI_FS_2);//HSI_24MHz + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F10)&RCC_ICSCR_HSI_TRIM); + while (RCC_CR_HSIRDY != READ_BIT(RCC->CR, RCC_CR_HSIRDY)); + + FLASH->TS0 = ((M32(0x1FFF0F1C + 4 * 0x14) >> 0) & 0x000000FF); + FLASH->TS3 = ((M32(0x1FFF0F1C + 4 * 0x14) >> 8) & 0x000000FF); + FLASH->TS1 = ((M32(0x1FFF0F1C + 4 * 0x14) >> 16) & 0x000001FF); + FLASH->TS2P = ((M32(0x1FFF0F20 + 4 * 0x14) >> 0) & 0x000000FF); + FLASH->TPS3 = ((M32(0x1FFF0F20 + 4 * 0x14) >> 16) & 0x000007FF); + FLASH->PERTPE = ((M32(0x1FFF0F24 + 4 * 0x14) >> 0) & 0x0001FFFF); + FLASH->SMERTPE = ((M32(0x1FFF0F28 + 4 * 0x14) >> 0) & 0x0001FFFF); + FLASH->PRGTPE = ((M32(0x1FFF0F2C + 4 * 0x14) >> 0) & 0x0000FFFF); + FLASH->PRETPE = ((M32(0x1FFF0F2C + 4 * 0x14) >> 16) & 0x0000FFFF); +} + +void UnInitRccAndFlashParam(void) +{ + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_FS, RCC_ICSCR_HSI_FS_RESTORE); + switch (RCC_ICSCR_HSI_FS_RESTORE) + { + case RCC_ICSCR_HSI_FS_2://24MHz + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F10)&RCC_ICSCR_HSI_TRIM); + break; + case (RCC_ICSCR_HSI_FS_1|RCC_ICSCR_HSI_FS_0)://22.12MHz + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F0C)&RCC_ICSCR_HSI_TRIM); + break; + case RCC_ICSCR_HSI_FS_1://16MHz + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F08)&RCC_ICSCR_HSI_TRIM); + break; + case RCC_ICSCR_HSI_FS_0://8MHz + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F04)&RCC_ICSCR_HSI_TRIM); + break; + default://4MHz + MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F00)&RCC_ICSCR_HSI_TRIM); + break; + } + while (RCC_CR_HSIRDY != READ_BIT(RCC->CR, RCC_CR_HSIRDY)); +} diff --git a/Misc/Flash/Sources/PY32F0xx/PY32F0xx.uvoptx b/Misc/Flash/Sources/PY32F0xx/PY32F0xx.uvoptx new file mode 100644 index 0000000..6f8bd7c --- /dev/null +++ b/Misc/Flash/Sources/PY32F0xx/PY32F0xx.uvoptx @@ -0,0 +1,1205 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
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### uVision Project, (C) Keil Software
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index 96% rename from Misc/py32f002axx.svd rename to Misc/SVD/py32f002axx.svd index 1679653..9db4822 100644 --- a/Misc/py32f002axx.svd +++ b/Misc/SVD/py32f002axx.svd @@ -1,7707 +1,7978 @@ - - - - Puya - Puya - PY32F0xx_DFP - - PY32F0 - 1.0.0 - Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. - - - - CM0+ - r0p1 - little - false - false - 4 - false - - - - 8 - 32 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ADC - Analog to Digital Converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC - ADC Interrupt through EXTI Lines 17 and 18 - 12 - - - - ISR - ISR - ADC interrupt and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - AWD - ADC analog watchdog flag - 7 - 1 - - - OVR - ADC group regular overrun - flag - 4 - 1 - - - EOSEQ - ADC group regular end of sequence - conversions flag - 3 - 1 - - - EOC - ADC group regular end of unitary - conversion flag - 2 - 1 - - - EOSMP - ADC group regular end of sampling - flag - 1 - 1 - - - - - IER - IER - ADC interrupt enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - AWDIE - ADC analog watchdog - interrupt - 7 - 1 - - - OVRIE - ADC group regular overrun - interrupt - 4 - 1 - - - EOSEQIE - ADC group regular end of sequence - conversions interrupt - 3 - 1 - - - EOCIE - ADC group regular end of unitary - conversion interrupt - 2 - 1 - - - EOSMPIE - ADC group regular end of sampling - interrupt - 1 - 1 - - - - - CR - CR - ADC control register - 0x8 - 0x20 - read-write - 0x00000000 - - - ADCAL - ADC group regular conversion - calibration - 31 - 1 - - - ADSTP - ADC group regular conversion - stop - 4 - 1 - - - ADSTART - ADC group regular conversion - start - 2 - 1 - - - ADEN - ADC enable - 0 - 1 - - - - - CFGR1 - CFGR1 - ADC configuration register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - AWDCH - ADC analog watchdog monitored channel - selection - 26 - 4 - - - AWDEN - ADC analog watchdog enable on scope - ADC group regular - 23 - 1 - - - AWDSGL - ADC analog watchdog monitoring a - single channel or all channels - 22 - 1 - - - DISCEN - ADC group regular sequencer - discontinuous mode - 16 - 1 - - - WAIT - Wait conversion mode - 14 - 1 - - - CONT - ADC group regular continuous conversion - mode - 13 - 1 - - - OVRMOD - ADC group regular overrun - configuration - 12 - 1 - - - EXTEN - ADC group regular external trigger - polarity - 10 - 2 - - - EXTSEL - ADC group regular external trigger - source - 6 - 3 - - - ALIGN - ADC data alignement - 5 - 1 - - - RESSEL - ADC data resolution - 3 - 2 - - - SCANDIR - Scan sequence direction - 2 - 1 - - - - - CFGR2 - CFGR2 - ADC configuration register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CKMODE - ADC clock mode - 28 - 4 - - - - - SMPR - SMPR - ADC sampling time register - 0x14 - 0x20 - read-write - 0x00000000 - - - SMP - Sampling time selection - 0 - 3 - - - - - TR - TR - ADC analog watchdog 1 threshold register - 0x20 - 0x20 - read-write - 0x0FFF0000 - - - HT - ADC analog watchdog threshold - high - 16 - 12 - - - LT - ADC analog watchdog threshold - low - 0 - 12 - - - - - CHSELR - CHSELR - ADC group regular sequencer register - 0x28 - 0x20 - read-write - 0x0FFF0000 - - - CHSEL12 - Channel-12 selection - 12 - 1 - - - CHSEL11 - Channel-11 selection - 11 - 1 - - - CHSEL9 - Channel-9 selection - 9 - 1 - - - CHSEL8 - Channel-8 selection - 8 - 1 - - - CHSEL7 - Channel-7 selection - 7 - 1 - - - CHSEL6 - Channel-6 selection - 6 - 1 - - - CHSEL5 - Channel-5 selection - 5 - 1 - - - CHSEL4 - Channel-4 selection - 4 - 1 - - - CHSEL3 - Channel-3 selection - 3 - 1 - - - CHSEL2 - Channel-2 selection - 2 - 1 - - - CHSEL1 - Channel-1 selection - 1 - 1 - - - CHSEL0 - Channel-0 selection - 0 - 1 - - - - - DR - DR - ADC group regular data register - 0x40 - 0x20 - read-only - 0x00000000 - - - DATA - ADC group regular conversion - data - 0 - 16 - - - - - CCSR - CCSR - ADC calibration configuration and status register - 0x44 - 0x20 - read-write - 0x00000000 - - - CALON - Calibration flag - 31 - 1 - read-only - - - CALFAIL - Calibration fail flag - 30 - 1 - - - CALSET - Calibration factor selection - 15 - 1 - - - CALSMP - Calibration sample time selection - 12 - 2 - - - CALSEL - Calibration contents selection - 11 - 1 - - - - - CALRR1 - CALRR1 - ADC calibration result register 1 - 0x48 - 0x20 - read-only - 0x00000000 - - - CALBOUT - offset result - 16 - 7 - - - CALC5OUT - C5 result - 8 - 8 - - - CALC4OUT - C4 result - 0 - 8 - - - - - CALRR2 - CALRR2 - ADC calibration result register 2 - 0x4C - 0x20 - read-only - 0x00000000 - - - CALC3OUT - C3 result - 24 - 8 - - - CALC2OUT - C2 result - 16 - 8 - - - CALC1OUT - C1 result - 8 - 8 - - - CALC0OUT - C0 result - 0 - 8 - - - - - CALFIR1 - CALFIR1 - ADC calibration factor input register 1 - 0x50 - 0x20 - read-write - 0x00000000 - - - CALBIO - Calibration offset factor input - 16 - 7 - - - CALC5IO - Calibration C5 factor input - 8 - 8 - - - CALC4IO - Calibration C4 factor input - 0 - 8 - - - - - CALFIR2 - CALFIR2 - ADC calibration factor input register 2 - 0x54 - 0x20 - read-write - 0x00000000 - - - CALC3IO - Calibration C3 factor input - 24 - 8 - - - CALC2IO - Calibration C2 factor input - 16 - 8 - - - CALC1IO - Calibration C1 factor input - 8 - 8 - - - CALC0IO - Calibration C0 factor input - 0 - 8 - - - - - CCR - CCR - ADC common configuration register - 0x308 - 0x20 - read-write - 0x00000000 - - - TSEN - Temperature sensor enable - 23 - 1 - - - VREFEN - VREFINT enable - 22 - 1 - - - - - - - RCC - Reset and clock control - RCC - 0x40021000 - - 0x0 - 0x400 - registers - - - RCC - RCC global Interrupt - 4 - - - - CR - CR - Clock control register - 0x0 - 0x20 - read-write - 0x00000100 - - - CSSON - Clock security system - enable - 19 - 1 - - - HSEBYP - HSE crystal oscillator - bypass - 18 - 1 - - - HSERDY - HSE clock ready flag - 17 - 1 - - - HSEON - HSE clock enable - 16 - 1 - - - HSIDIV - HSI16 clock division - factor - 11 - 3 - - - HSIRDY - HSI16 clock ready flag - 10 - 1 - - - HSIKERON - HSI16 always enable for peripheral - kernels - 9 - 1 - - - HSION - HSI16 clock enable - 8 - 1 - - - - - ICSCR - ICSCR - Internal clock sources calibration - register - 0x4 - 0x20 - 0x10000000 - - - LSI_STARTUP - LSI startup time - 26 - 2 - read-write - - - LSI_TRIM - LSI clock trimming - 16 - 9 - read-write - - - HSI_FS - HSI frequency selection - 13 - 3 - read-write - - - HSI_TRIM - HSI clock trimming - 0 - 13 - read-write - - - - - CFGR - CFGR - Clock configuration register - 0x8 - 0x20 - 0x00000000 - - - MCOPRE - Microcontroller clock output - prescaler - 28 - 3 - read-write - - - MCOSEL - Microcontroller clock - output - 24 - 3 - read-write - - - PPRE - APB prescaler - 12 - 3 - read-write - - - HPRE - AHB prescaler - 8 - 4 - read-write - - - SWS - System clock switch status - 3 - 3 - read-only - - - SW - System clock switch - 0 - 3 - read-write - - - - - ECSCR - ECSCR - External clock source control register - 0x10 - 0x20 - 0x00000000 - - - HSE_FREQ - HSE clock freqency selection - 2 - 2 - read-write - - - - - CIER - CIER - Clock interrupt enable - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HSERDYIE - HSE ready interrupt enable - 4 - 1 - - - HSIRDYIE - HSI ready interrupt enable - 3 - 1 - - - LSIRDYIE - LSI ready interrupt enable - 0 - 1 - - - - - CIFR - CIFR - Clock interrupt flag register - 0x1C - 0x20 - read-only - 0x00000000 - - - CSSF - HSE clock secure system interrupt flag - 8 - 1 - - - HSERDYF - HSE ready interrupt flag - 4 - 1 - - - HSIRDYF - HSI ready interrupt flag - 3 - 1 - - - LSIRDYF - LSI ready interrupt flag - 0 - 1 - - - - - CICR - CICR - Clock interrupt clear register - 0x20 - 0x20 - write-only - 0x00000000 - - - CSSC - clock secure system interrupt flag clear - 8 - 1 - - - HSERDYC - HSE ready interrupt clear - 4 - 1 - - - HSIRDYC - HSI ready interrupt clear - 3 - 1 - - - LSIRDYC - LSI ready interrupt clear - 0 - 1 - - - - - IOPRSTR - IOPRSTR - GPIO reset register - 0x24 - 0x20 - read-write - 0x00000000 - - - GPIOFRST - I/O port F reset - 5 - 1 - - - GPIOBRST - I/O port B reset - 1 - 1 - - - GPIOARST - I/O port A reset - 0 - 1 - - - - - AHBRSTR - AHBRSTR - AHB peripheral reset register - 0x28 - 0x20 - read-write - 0x00000000 - - - CRCRST - CRC reset - 12 - 1 - - - - - APBRSTR1 - APBRSTR1 - APB peripheral reset register - 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - LPTIMRST - Low Power Timer reset - 31 - 1 - - - PWRRST - Power interface reset - 28 - 1 - - - DBGRST - Debug support reset - 27 - 1 - - - I2CRST - I2C reset - 21 - 1 - - - - - APBRSTR2 - APBRSTR2 - APB peripheral reset register - 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - ADCRST - ADC reset - 20 - 1 - - - TIM16RST - TIM16 timer reset - 17 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - TIM1RST - TIM1 timer reset - 11 - 1 - - - SYSCFGRST - SYSCFG and COMP - reset - 0 - 1 - - - - - IOPENR - IOPENR - GPIO clock enable register - 0x34 - 0x20 - read-write - 0x00000000 - - - GPIOFEN - I/O port F clock enable - 5 - 1 - - - GPIOBEN - I/O port B clock enable - 1 - 1 - - - GPIOAEN - I/O port A clock enable - 0 - 1 - - - - - AHBENR - AHBENR - AHB peripheral clock enable - register - 0x38 - 0x20 - read-write - 0x00000000 - - - CRCEN - CRC clock enable - 12 - 1 - - - SRAMEN - SRAM memory interface clock - enable - 9 - 1 - - - FLASHEN - Flash memory interface clock - enable - 8 - 1 - - - - - APBENR1 - APBENR1 - APB peripheral clock enable register - 1 - 0x3C - 0x20 - read-write - 0x00000000 - - - LPTIMEN - LPTIM clock enable - 31 - 1 - - - PWREN - Power interface clock - enable - 28 - 1 - - - DBGEN - Debug support clock enable - 27 - 1 - - - I2CEN - I2C clock enable - 21 - 1 - - - - - APBENR2 - APBENR2 - APB peripheral clock enable register - 2 - 0x40 - 0x20 - read-write - 0x00000000 - - - ADCEN - ADC clock enable - 20 - 1 - - - TIM16EN - TIM16 timer clock enable - 17 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - TIM1EN - TIM1 timer clock enable - 11 - 1 - - - SYSCFGEN - SYSCFG, COMP and VREFBUF clock - enable - 0 - 1 - - - - - CCIPR - CCIPR - Peripherals independent clock configuration - register - 0x54 - 0x20 - read-write - 0x00000000 - - - LPTIM1SEL - LPTIM1 clock source - selection - 18 - 2 - - - - - CSR - CSR - Control/status register - 0x60 - 0x20 - read-write - 0x00000000 - - - IWDGRSTF - Independent window watchdog reset - flag - 29 - 1 - - - SFTRSTF - Software reset flag - 28 - 1 - - - PWRRSTF - BOR or POR/PDR flag - 27 - 1 - - - PINRSTF - Pin reset flag - 26 - 1 - - - OBLRSTF - Option byte loader reset - flag - 25 - 1 - - - RMVF - Remove reset flags - 23 - 1 - - - LSIRDY - LSI oscillator ready - 1 - 1 - - - LSION - LSI oscillator enable - 0 - 1 - - - - - - - GPIOA - General-purpose I/Os - GPIO - 0x50000000 - - 0x0 - 0x400 - registers - - - - MODER - MODER - GPIO port mode register - 0x0 - 0x20 - read-write - 0xEBFFFFFF - - - MODE15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - MODE14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - MODE13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - MODE12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - MODE11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - MODE10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - MODE9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - MODE8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - MODE7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - MODE6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - MODE5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - MODE4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - MODE3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - MODE2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - MODE1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - MODE0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - OTYPER - OTYPER - GPIO port output type register - 0x4 - 0x20 - read-write - 0x00000000 - - - OT15 - Port x configuration bits (y = - 0..15) - 15 - 1 - - - OT14 - Port x configuration bits (y = - 0..15) - 14 - 1 - - - OT13 - Port x configuration bits (y = - 0..15) - 13 - 1 - - - OT12 - Port x configuration bits (y = - 0..15) - 12 - 1 - - - OT11 - Port x configuration bits (y = - 0..15) - 11 - 1 - - - OT10 - Port x configuration bits (y = - 0..15) - 10 - 1 - - - OT9 - Port x configuration bits (y = - 0..15) - 9 - 1 - - - OT8 - Port x configuration bits (y = - 0..15) - 8 - 1 - - - OT7 - Port x configuration bits (y = - 0..15) - 7 - 1 - - - OT6 - Port x configuration bits (y = - 0..15) - 6 - 1 - - - OT5 - Port x configuration bits (y = - 0..15) - 5 - 1 - - - OT4 - Port x configuration bits (y = - 0..15) - 4 - 1 - - - OT3 - Port x configuration bits (y = - 0..15) - 3 - 1 - - - OT2 - Port x configuration bits (y = - 0..15) - 2 - 1 - - - OT1 - Port x configuration bits (y = - 0..15) - 1 - 1 - - - OT0 - Port x configuration bits (y = - 0..15) - 0 - 1 - - - - - OSPEEDR - OSPEEDR - GPIO port output speed - register - 0x8 - 0x20 - read-write - 0x0C000000 - - - OSPEED15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - OSPEED14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - OSPEED13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - OSPEED12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - OSPEED11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - OSPEED10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - OSPEED9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - OSPEED8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - OSPEED7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - OSPEED6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - OSPEED5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - OSPEED4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - OSPEED3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - OSPEED2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - OSPEED1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - OSPEED0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - PUPDR - PUPDR - GPIO port pull-up/pull-down - register - 0xC - 0x20 - read-write - 0x24000000 - - - PUPD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - PUPD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - PUPD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - PUPD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - PUPD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - PUPD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - PUPD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - PUPD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - PUPD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - PUPD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - PUPD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - PUPD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - PUPD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - PUPD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - PUPD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - PUPD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - IDR - IDR - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ID15 - Port input data (y = - 0..15) - 15 - 1 - - - ID14 - Port input data (y = - 0..15) - 14 - 1 - - - ID13 - Port input data (y = - 0..15) - 13 - 1 - - - ID12 - Port input data (y = - 0..15) - 12 - 1 - - - ID11 - Port input data (y = - 0..15) - 11 - 1 - - - ID10 - Port input data (y = - 0..15) - 10 - 1 - - - ID9 - Port input data (y = - 0..15) - 9 - 1 - - - ID8 - Port input data (y = - 0..15) - 8 - 1 - - - ID7 - Port input data (y = - 0..15) - 7 - 1 - - - ID6 - Port input data (y = - 0..15) - 6 - 1 - - - ID5 - Port input data (y = - 0..15) - 5 - 1 - - - ID4 - Port input data (y = - 0..15) - 4 - 1 - - - ID3 - Port input data (y = - 0..15) - 3 - 1 - - - ID2 - Port input data (y = - 0..15) - 2 - 1 - - - ID1 - Port input data (y = - 0..15) - 1 - 1 - - - ID0 - Port input data (y = - 0..15) - 0 - 1 - - - - - ODR - ODR - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OD15 - Port output data (y = - 0..15) - 15 - 1 - - - OD14 - Port output data (y = - 0..15) - 14 - 1 - - - OD13 - Port output data (y = - 0..15) - 13 - 1 - - - OD12 - Port output data (y = - 0..15) - 12 - 1 - - - OD11 - Port output data (y = - 0..15) - 11 - 1 - - - OD10 - Port output data (y = - 0..15) - 10 - 1 - - - OD9 - Port output data (y = - 0..15) - 9 - 1 - - - OD8 - Port output data (y = - 0..15) - 8 - 1 - - - OD7 - Port output data (y = - 0..15) - 7 - 1 - - - OD6 - Port output data (y = - 0..15) - 6 - 1 - - - OD5 - Port output data (y = - 0..15) - 5 - 1 - - - OD4 - Port output data (y = - 0..15) - 4 - 1 - - - OD3 - Port output data (y = - 0..15) - 3 - 1 - - - OD2 - Port output data (y = - 0..15) - 2 - 1 - - - OD1 - Port output data (y = - 0..15) - 1 - 1 - - - OD0 - Port output data (y = - 0..15) - 0 - 1 - - - - - BSRR - BSRR - GPIO port bit set/reset - register - 0x18 - 0x20 - write-only - 0x00000000 - - - BR15 - Port x reset bit y (y = - 0..15) - 31 - 1 - - - BR14 - Port x reset bit y (y = - 0..15) - 30 - 1 - - - BR13 - Port x reset bit y (y = - 0..15) - 29 - 1 - - - BR12 - Port x reset bit y (y = - 0..15) - 28 - 1 - - - BR11 - Port x reset bit y (y = - 0..15) - 27 - 1 - - - BR10 - Port x reset bit y (y = - 0..15) - 26 - 1 - - - BR9 - Port x reset bit y (y = - 0..15) - 25 - 1 - - - BR8 - Port x reset bit y (y = - 0..15) - 24 - 1 - - - BR7 - Port x reset bit y (y = - 0..15) - 23 - 1 - - - BR6 - Port x reset bit y (y = - 0..15) - 22 - 1 - - - BR5 - Port x reset bit y (y = - 0..15) - 21 - 1 - - - BR4 - Port x reset bit y (y = - 0..15) - 20 - 1 - - - BR3 - Port x reset bit y (y = - 0..15) - 19 - 1 - - - BR2 - Port x reset bit y (y = - 0..15) - 18 - 1 - - - BR1 - Port x reset bit y (y = - 0..15) - 17 - 1 - - - BR0 - Port x set bit y (y= - 0..15) - 16 - 1 - - - BS15 - Port x set bit y (y= - 0..15) - 15 - 1 - - - BS14 - Port x set bit y (y= - 0..15) - 14 - 1 - - - BS13 - Port x set bit y (y= - 0..15) - 13 - 1 - - - BS12 - Port x set bit y (y= - 0..15) - 12 - 1 - - - BS11 - Port x set bit y (y= - 0..15) - 11 - 1 - - - BS10 - Port x set bit y (y= - 0..15) - 10 - 1 - - - BS9 - Port x set bit y (y= - 0..15) - 9 - 1 - - - BS8 - Port x set bit y (y= - 0..15) - 8 - 1 - - - BS7 - Port x set bit y (y= - 0..15) - 7 - 1 - - - BS6 - Port x set bit y (y= - 0..15) - 6 - 1 - - - BS5 - Port x set bit y (y= - 0..15) - 5 - 1 - - - BS4 - Port x set bit y (y= - 0..15) - 4 - 1 - - - BS3 - Port x set bit y (y= - 0..15) - 3 - 1 - - - BS2 - Port x set bit y (y= - 0..15) - 2 - 1 - - - BS1 - Port x set bit y (y= - 0..15) - 1 - 1 - - - BS0 - Port x set bit y (y= - 0..15) - 0 - 1 - - - - - LCKR - LCKR - GPIO port configuration lock - register - 0x1C - 0x20 - read-write - 0x00000000 - - - LCKK - Port x lock bit y (y= - 0..15) - 16 - 1 - - - LCK15 - Port x lock bit y (y= - 0..15) - 15 - 1 - - - LCK14 - Port x lock bit y (y= - 0..15) - 14 - 1 - - - LCK13 - Port x lock bit y (y= - 0..15) - 13 - 1 - - - LCK12 - Port x lock bit y (y= - 0..15) - 12 - 1 - - - LCK11 - Port x lock bit y (y= - 0..15) - 11 - 1 - - - LCK10 - Port x lock bit y (y= - 0..15) - 10 - 1 - - - LCK9 - Port x lock bit y (y= - 0..15) - 9 - 1 - - - LCK8 - Port x lock bit y (y= - 0..15) - 8 - 1 - - - LCK7 - Port x lock bit y (y= - 0..15) - 7 - 1 - - - LCK6 - Port x lock bit y (y= - 0..15) - 6 - 1 - - - LCK5 - Port x lock bit y (y= - 0..15) - 5 - 1 - - - LCK4 - Port x lock bit y (y= - 0..15) - 4 - 1 - - - LCK3 - Port x lock bit y (y= - 0..15) - 3 - 1 - - - LCK2 - Port x lock bit y (y= - 0..15) - 2 - 1 - - - LCK1 - Port x lock bit y (y= - 0..15) - 1 - 1 - - - LCK0 - Port x lock bit y (y= - 0..15) - 0 - 1 - - - - - AFRL - AFRL - GPIO alternate function low - register - 0x20 - 0x20 - read-write - 0x00000000 - - - AFSEL7 - Alternate function selection for port x - bit y (y = 0..7) - 28 - 4 - - - AFSEL6 - Alternate function selection for port x - bit y (y = 0..7) - 24 - 4 - - - AFSEL5 - Alternate function selection for port x - bit y (y = 0..7) - 20 - 4 - - - AFSEL4 - Alternate function selection for port x - bit y (y = 0..7) - 16 - 4 - - - AFSEL3 - Alternate function selection for port x - bit y (y = 0..7) - 12 - 4 - - - AFSEL2 - Alternate function selection for port x - bit y (y = 0..7) - 8 - 4 - - - AFSEL1 - Alternate function selection for port x - bit y (y = 0..7) - 4 - 4 - - - AFSEL0 - Alternate function selection for port x - bit y (y = 0..7) - 0 - 4 - - - - - AFRH - AFRH - GPIO alternate function high - register - 0x24 - 0x20 - read-write - 0x00000000 - - - AFSEL15 - Alternate function selection for port x - bit y (y = 8..15) - 28 - 4 - - - AFSEL14 - Alternate function selection for port x - bit y (y = 8..15) - 24 - 4 - - - AFSEL13 - Alternate function selection for port x - bit y (y = 8..15) - 20 - 4 - - - AFSEL12 - Alternate function selection for port x - bit y (y = 8..15) - 16 - 4 - - - AFSEL11 - Alternate function selection for port x - bit y (y = 8..15) - 12 - 4 - - - AFSEL10 - Alternate function selection for port x - bit y (y = 8..15) - 8 - 4 - - - AFSEL9 - Alternate function selection for port x - bit y (y = 8..15) - 4 - 4 - - - AFSEL8 - Alternate function selection for port x - bit y (y = 8..15) - 0 - 4 - - - - - BRR - BRR - port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - BR15 - Port Reset bit - 15 - 1 - - - BR14 - Port Reset bit - 14 - 1 - - - BR13 - Port Reset bit - 13 - 1 - - - BR12 - Port Reset bit - 12 - 1 - - - BR11 - Port Reset bit - 11 - 1 - - - BR10 - Port Reset bit - 10 - 1 - - - BR9 - Port Reset bit - 9 - 1 - - - BR8 - Port Reset bit - 8 - 1 - - - BR7 - Port Reset bit - 7 - 1 - - - BR6 - Port Reset bit - 6 - 1 - - - BR5 - Port Reset bit - 5 - 1 - - - BR4 - Port Reset bit - 4 - 1 - - - BR3 - Port Reset bit - 3 - 1 - - - BR2 - Port Reset bit - 2 - 1 - - - BR1 - Port Reset bit - 1 - 1 - - - BR0 - Port Reset bit - 0 - 1 - - - - - - - GPIOB - General-purpose I/Os - GPIO - 0x50000400 - - 0x0 - 0x400 - registers - - - - MODER - MODER - GPIO port mode register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - MODE8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - MODE7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - MODE6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - MODE5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - MODE4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - MODE3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - MODE2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - MODE1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - MODE0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - OTYPER - OTYPER - GPIO port output type register - 0x4 - 0x20 - read-write - 0x00000000 - - - OT8 - Port x configuration bits (y = - 0..15) - 8 - 1 - - - OT7 - Port x configuration bits (y = - 0..15) - 7 - 1 - - - OT6 - Port x configuration bits (y = - 0..15) - 6 - 1 - - - OT5 - Port x configuration bits (y = - 0..15) - 5 - 1 - - - OT4 - Port x configuration bits (y = - 0..15) - 4 - 1 - - - OT3 - Port x configuration bits (y = - 0..15) - 3 - 1 - - - OT2 - Port x configuration bits (y = - 0..15) - 2 - 1 - - - OT1 - Port x configuration bits (y = - 0..15) - 1 - 1 - - - OT0 - Port x configuration bits (y = - 0..15) - 0 - 1 - - - - - OSPEEDR - OSPEEDR - GPIO port output speed - register - 0x8 - 0x20 - read-write - 0x00000000 - - - OSPEED8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - OSPEED7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - OSPEED6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - OSPEED5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - OSPEED4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - OSPEED3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - OSPEED2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - OSPEED1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - OSPEED0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - PUPDR - PUPDR - GPIO port pull-up/pull-down - register - 0xC - 0x20 - read-write - 0x00000000 - - - PUPD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - PUPD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - PUPD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - PUPD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - PUPD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - PUPD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - PUPD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - PUPD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - PUPD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - IDR - IDR - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ID8 - Port input data (y = - 0..15) - 8 - 1 - - - ID7 - Port input data (y = - 0..15) - 7 - 1 - - - ID6 - Port input data (y = - 0..15) - 6 - 1 - - - ID5 - Port input data (y = - 0..15) - 5 - 1 - - - ID4 - Port input data (y = - 0..15) - 4 - 1 - - - ID3 - Port input data (y = - 0..15) - 3 - 1 - - - ID2 - Port input data (y = - 0..15) - 2 - 1 - - - ID1 - Port input data (y = - 0..15) - 1 - 1 - - - ID0 - Port input data (y = - 0..15) - 0 - 1 - - - - - ODR - ODR - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OD8 - Port output data (y = - 0..15) - 8 - 1 - - - OD7 - Port output data (y = - 0..15) - 7 - 1 - - - OD6 - Port output data (y = - 0..15) - 6 - 1 - - - OD5 - Port output data (y = - 0..15) - 5 - 1 - - - OD4 - Port output data (y = - 0..15) - 4 - 1 - - - OD3 - Port output data (y = - 0..15) - 3 - 1 - - - OD2 - Port output data (y = - 0..15) - 2 - 1 - - - OD1 - Port output data (y = - 0..15) - 1 - 1 - - - OD0 - Port output data (y = - 0..15) - 0 - 1 - - - - - BSRR - BSRR - GPIO port bit set/reset - register - 0x18 - 0x20 - write-only - 0x00000000 - - - BR8 - Port x reset bit y (y = - 0..15) - 24 - 1 - - - BR7 - Port x reset bit y (y = - 0..15) - 23 - 1 - - - BR6 - Port x reset bit y (y = - 0..15) - 22 - 1 - - - BR5 - Port x reset bit y (y = - 0..15) - 21 - 1 - - - BR4 - Port x reset bit y (y = - 0..15) - 20 - 1 - - - BR3 - Port x reset bit y (y = - 0..15) - 19 - 1 - - - BR2 - Port x reset bit y (y = - 0..15) - 18 - 1 - - - BR1 - Port x reset bit y (y = - 0..15) - 17 - 1 - - - BR0 - Port x set bit y (y= - 0..15) - 16 - 1 - - - BS8 - Port x set bit y (y= - 0..15) - 8 - 1 - - - BS7 - Port x set bit y (y= - 0..15) - 7 - 1 - - - BS6 - Port x set bit y (y= - 0..15) - 6 - 1 - - - BS5 - Port x set bit y (y= - 0..15) - 5 - 1 - - - BS4 - Port x set bit y (y= - 0..15) - 4 - 1 - - - BS3 - Port x set bit y (y= - 0..15) - 3 - 1 - - - BS2 - Port x set bit y (y= - 0..15) - 2 - 1 - - - BS1 - Port x set bit y (y= - 0..15) - 1 - 1 - - - BS0 - Port x set bit y (y= - 0..15) - 0 - 1 - - - - - LCKR - LCKR - GPIO port configuration lock - register - 0x1C - 0x20 - read-write - 0x00000000 - - - LCKK - Port x lock bit y (y= - 0..15) - 16 - 1 - - - LCK8 - Port x lock bit y (y= - 0..15) - 8 - 1 - - - LCK7 - Port x lock bit y (y= - 0..15) - 7 - 1 - - - LCK6 - Port x lock bit y (y= - 0..15) - 6 - 1 - - - LCK5 - Port x lock bit y (y= - 0..15) - 5 - 1 - - - LCK4 - Port x lock bit y (y= - 0..15) - 4 - 1 - - - LCK3 - Port x lock bit y (y= - 0..15) - 3 - 1 - - - LCK2 - Port x lock bit y (y= - 0..15) - 2 - 1 - - - LCK1 - Port x lock bit y (y= - 0..15) - 1 - 1 - - - LCK0 - Port x lock bit y (y= - 0..15) - 0 - 1 - - - - - AFRL - AFRL - GPIO alternate function low - register - 0x20 - 0x20 - read-write - 0x00000000 - - - AFSEL7 - Alternate function selection for port x - bit y (y = 0..7) - 28 - 4 - - - AFSEL6 - Alternate function selection for port x - bit y (y = 0..7) - 24 - 4 - - - AFSEL5 - Alternate function selection for port x - bit y (y = 0..7) - 20 - 4 - - - AFSEL4 - Alternate function selection for port x - bit y (y = 0..7) - 16 - 4 - - - AFSEL3 - Alternate function selection for port x - bit y (y = 0..7) - 12 - 4 - - - AFSEL2 - Alternate function selection for port x - bit y (y = 0..7) - 8 - 4 - - - AFSEL1 - Alternate function selection for port x - bit y (y = 0..7) - 4 - 4 - - - AFSEL0 - Alternate function selection for port x - bit y (y = 0..7) - 0 - 4 - - - - - AFRH - AFRH - GPIO alternate function high - register - 0x24 - 0x20 - read-write - 0x00000000 - - - AFSEL15 - Alternate function selection for port x - bit y (y = 8..15) - 28 - 4 - - - AFSEL14 - Alternate function selection for port x - bit y (y = 8..15) - 24 - 4 - - - AFSEL13 - Alternate function selection for port x - bit y (y = 8..15) - 20 - 4 - - - AFSEL12 - Alternate function selection for port x - bit y (y = 8..15) - 16 - 4 - - - AFSEL11 - Alternate function selection for port x - bit y (y = 8..15) - 12 - 4 - - - AFSEL10 - Alternate function selection for port x - bit y (y = 8..15) - 8 - 4 - - - AFSEL9 - Alternate function selection for port x - bit y (y = 8..15) - 4 - 4 - - - AFSEL8 - Alternate function selection for port x - bit y (y = 8..15) - 0 - 4 - - - - - BRR - BRR - port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - BR8 - Port Reset bit - 8 - 1 - - - BR7 - Port Reset bit - 7 - 1 - - - BR6 - Port Reset bit - 6 - 1 - - - BR5 - Port Reset bit - 5 - 1 - - - BR4 - Port Reset bit - 4 - 1 - - - BR3 - Port Reset bit - 3 - 1 - - - BR2 - Port Reset bit - 2 - 1 - - - BR1 - Port Reset bit - 1 - 1 - - - BR0 - Port Reset bit - 0 - 1 - - - - - - - GPIOF - 0x50001400 - - - EXTI - External interrupt/event - controller - EXTI - 0x40021800 - - 0x0 - 0x400 - registers - - - EXTI0_1 - EXTI Line 0 and 1 Interrupt - 5 - - - EXTI2_3 - EXTI Line 2 and 3 Interrupt - 6 - - - EXTI4_15 - EXTI Line 4 to 15 Interrupt - 7 - - - - RTSR - RTSR - EXTI rising trigger selection - register - 0x0 - 0x20 - read-write - 0x00000000 - - - RT18 - Rising trigger event configuration bit - of Configurable Event input - 18 - 1 - - - RT17 - Rising trigger event configuration bit - of Configurable Event input - 17 - 1 - - - RT16 - Rising trigger event configuration bit - of Configurable Event input - 16 - 1 - - - RT15 - Rising trigger event configuration bit - of Configurable Event input - 15 - 1 - - - RT14 - Rising trigger event configuration bit - of Configurable Event input - 14 - 1 - - - RT13 - Rising trigger event configuration bit - of Configurable Event input - 13 - 1 - - - RT12 - Rising trigger event configuration bit - of Configurable Event input - 12 - 1 - - - RT11 - Rising trigger event configuration bit - of Configurable Event input - 11 - 1 - - - RT10 - Rising trigger event configuration bit - of Configurable Event input - 10 - 1 - - - RT9 - Rising trigger event configuration bit - of Configurable Event input - 9 - 1 - - - RT8 - Rising trigger event configuration bit - of Configurable Event input - 8 - 1 - - - RT7 - Rising trigger event configuration bit - of Configurable Event input - 7 - 1 - - - RT6 - Rising trigger event configuration bit - of Configurable Event input - 6 - 1 - - - RT5 - Rising trigger event configuration bit - of Configurable Event input - 5 - 1 - - - RT4 - Rising trigger event configuration bit - of Configurable Event input - 4 - 1 - - - RT3 - Rising trigger event configuration bit - of Configurable Event input - 3 - 1 - - - RT2 - Rising trigger event configuration bit - of Configurable Event input - 2 - 1 - - - RT1 - Rising trigger event configuration bit - of Configurable Event input - 1 - 1 - - - RT0 - Rising trigger event configuration bit - of Configurable Event input - 0 - 1 - - - - - FTSR - FTSR - EXTI falling trigger selection - register - 0x4 - 0x20 - read-write - 0x00000000 - - - FT18 - Falling trigger event configuration bit - of Configurable Event input - 18 - 1 - - - FT17 - Falling trigger event configuration bit - of Configurable Event input - 17 - 1 - - - FT16 - Falling trigger event configuration bit - of Configurable Event input - 16 - 1 - - - FT15 - Falling trigger event configuration bit - of Configurable Event input - 15 - 1 - - - FT14 - Falling trigger event configuration bit - of Configurable Event input - 14 - 1 - - - FT13 - Falling trigger event configuration bit - of Configurable Event input - 13 - 1 - - - FT12 - Falling trigger event configuration bit - of Configurable Event input - 12 - 1 - - - FT11 - Falling trigger event configuration bit - of Configurable Event input - 11 - 1 - - - FT10 - Falling trigger event configuration bit - of Configurable Event input - 10 - 1 - - - FT9 - Falling trigger event configuration bit - of Configurable Event input - 9 - 1 - - - FT8 - Falling trigger event configuration bit - of Configurable Event input - 8 - 1 - - - FT7 - Falling trigger event configuration bit - of Configurable Event input - 7 - 1 - - - FT6 - Falling trigger event configuration bit - of Configurable Event input - 6 - 1 - - - FT5 - Falling trigger event configuration bit - of Configurable Event input - 5 - 1 - - - FT4 - Falling trigger event configuration bit - of Configurable Event input - 4 - 1 - - - FT3 - Falling trigger event configuration bit - of Configurable Event input - 3 - 1 - - - FT2 - Falling trigger event configuration bit - of Configurable Event input - 2 - 1 - - - FT1 - Falling trigger event configuration bit - of Configurable Event input - 1 - 1 - - - FT0 - Falling trigger event configuration bit - of Configurable Event input - 0 - 1 - - - - - SWIER - SWIER - EXTI software interrupt event - register - 0x8 - 0x20 - read-write - 0x00000000 - - - SWI18 - Rising trigger event configuration bit - of Configurable Event input - 18 - 1 - - - SWI17 - Rising trigger event configuration bit - of Configurable Event input - 17 - 1 - - - SWI16 - Rising trigger event configuration bit - of Configurable Event input - 16 - 1 - - - SWI15 - Rising trigger event configuration bit - of Configurable Event input - 15 - 1 - - - SWI14 - Rising trigger event configuration bit - of Configurable Event input - 14 - 1 - - - SWI13 - Rising trigger event configuration bit - of Configurable Event input - 13 - 1 - - - SWI12 - Rising trigger event configuration bit - of Configurable Event input - 12 - 1 - - - SWI11 - Rising trigger event configuration bit - of Configurable Event input - 11 - 1 - - - SWI10 - Rising trigger event configuration bit - of Configurable Event input - 10 - 1 - - - SWI9 - Rising trigger event configuration bit - of Configurable Event input - 9 - 1 - - - SWI8 - Rising trigger event configuration bit - of Configurable Event input - 8 - 1 - - - SWI7 - Rising trigger event configuration bit - of Configurable Event input - 7 - 1 - - - SWI6 - Rising trigger event configuration bit - of Configurable Event input - 6 - 1 - - - SWI5 - Rising trigger event configuration bit - of Configurable Event input - 5 - 1 - - - SWI4 - Rising trigger event configuration bit - of Configurable Event input - 4 - 1 - - - SWI3 - Rising trigger event configuration bit - of Configurable Event input - 3 - 1 - - - SWI2 - Rising trigger event configuration bit - of Configurable Event input - 2 - 1 - - - SWI1 - Rising trigger event configuration bit - of Configurable Event input - 1 - 1 - - - SWI0 - Rising trigger event configuration bit - of Configurable Event input - 0 - 1 - - - - - PR - PR - EXTI pending - register - 0xC - 0x20 - read-write - 0x00000000 - - - PR18 - configurable event inputs x rising edge - Pending bit. - 18 - 1 - - - PR17 - configurable event inputs x rising edge - Pending bit. - 17 - 1 - - - PR16 - configurable event inputs x rising edge - Pending bit. - 16 - 1 - - - PR15 - configurable event inputs x rising edge - Pending bit. - 15 - 1 - - - PR14 - configurable event inputs x rising edge - Pending bit. - 14 - 1 - - - PR13 - configurable event inputs x rising edge - Pending bit - 13 - 1 - - - PR12 - configurable event inputs x rising edge - Pending bit. - 12 - 1 - - - PR11 - configurable event inputs x rising edge - Pending bit. - 11 - 1 - - - PR10 - configurable event inputs x rising edge - Pending bit. - 10 - 1 - - - PR9 - configurable event inputs x rising edge - Pending bit. - 9 - 1 - - - PR8 - configurable event inputs x rising edge - Pending bit. - 8 - 1 - - - PR7 - configurable event inputs x rising edge - Pending bit. - 7 - 1 - - - PR6 - configurable event inputs x rising edge - Pending bit. - 6 - 1 - - - PR5 - configurable event inputs x rising edge - Pending bit. - 5 - 1 - - - PR4 - configurable event inputs x rising edge - Pending bit. - 4 - 1 - - - PR3 - configurable event inputs x rising edge - Pending bit. - 3 - 1 - - - PR2 - configurable event inputs x rising edge - Pending bit. - 2 - 1 - - - PR1 - configurable event inputs x rising edge - Pending bit. - 1 - 1 - - - PR0 - configurable event inputs x rising edge - Pending bit. - 0 - 1 - - - - - EXTICR1 - EXTICR1 - EXTI external interrupt selection - register - 0x60 - 0x20 - read-write - 0x00000000 - - - EXTI3 - GPIO port selection - 24 - 2 - - - EXTI2 - GPIO port selection - 16 - 2 - - - EXTI1 - GPIO port selection - 8 - 2 - - - EXTI0 - GPIO port selection - 0 - 2 - - - - - EXTICR2 - EXTICR2 - EXTI external interrupt selection - register - 0x64 - 0x20 - read-write - 0x00000000 - - - EXTI7 - GPIO port selection - 24 - 1 - - - EXTI6 - GPIO port selection - 16 - 1 - - - EXTI5 - GPIO port selection - 8 - 1 - - - EXTI4 - GPIO port selection - 0 - 2 - - - - - EXTICR3 - EXTICR3 - EXTI external interrupt selection - register - 0x68 - 0x20 - read-write - 0x00000000 - - - EXTI8 - GPIO port selection - 0 - 1 - - - - - IMR - IMR - EXTI CPU wakeup with interrupt mask - register - 0x80 - 0x20 - read-write - 0xFFF80000 - - - IM29 - CPU wakeup with interrupt mask on event - input - 29 - 1 - - - IM19 - CPU wakeup with interrupt mask on event - input - 19 - 1 - - - IM18 - CPU wakeup with interrupt mask on event - input - 18 - 1 - - - IM17 - CPU wakeup with interrupt mask on event - input - 17 - 1 - - - IM16 - CPU wakeup with interrupt mask on event - input - 16 - 1 - - - IM15 - CPU wakeup with interrupt mask on event - input - 15 - 1 - - - IM14 - CPU wakeup with interrupt mask on event - input - 14 - 1 - - - IM13 - CPU wakeup with interrupt mask on event - input - 13 - 1 - - - IM12 - CPU wakeup with interrupt mask on event - input - 12 - 1 - - - IM11 - CPU wakeup with interrupt mask on event - input - 11 - 1 - - - IM10 - CPU wakeup with interrupt mask on event - input - 10 - 1 - - - IM9 - CPU wakeup with interrupt mask on event - input - 9 - 1 - - - IM8 - CPU wakeup with interrupt mask on event - input - 8 - 1 - - - IM7 - CPU wakeup with interrupt mask on event - input - 7 - 1 - - - IM6 - CPU wakeup with interrupt mask on event - input - 6 - 1 - - - IM5 - CPU wakeup with interrupt mask on event - input - 5 - 1 - - - IM4 - CPU wakeup with interrupt mask on event - input - 4 - 1 - - - IM3 - CPU wakeup with interrupt mask on event - input - 3 - 1 - - - IM2 - CPU wakeup with interrupt mask on event - input - 2 - 1 - - - IM1 - CPU wakeup with interrupt mask on event - input - 1 - 1 - - - IM0 - CPU wakeup with interrupt mask on event - input - 0 - 1 - - - - - EMR - EMR - EXTI CPU wakeup with event mask - register - 0x84 - 0x20 - read-write - 0x00000000 - - - EM29 - CPU wakeup with event mask on event - input - 29 - 1 - - - EM19 - CPU wakeup with event mask on event - input - 19 - 1 - - - EM18 - CPU wakeup with event mask on event - input - 18 - 1 - - - EM17 - CPU wakeup with event mask on event - input - 17 - 1 - - - EM16 - CPU wakeup with event mask on event - input - 16 - 1 - - - EM15 - CPU wakeup with event mask on event - input - 15 - 1 - - - EM14 - CPU wakeup with event mask on event - input - 14 - 1 - - - EM13 - CPU wakeup with event mask on event - input - 13 - 1 - - - EM12 - CPU wakeup with event mask on event - input - 12 - 1 - - - EM11 - CPU wakeup with event mask on event - input - 11 - 1 - - - EM10 - CPU wakeup with event mask on event - input - 10 - 1 - - - EM9 - CPU wakeup with event mask on event - input - 9 - 1 - - - EM8 - CPU wakeup with event mask on event - input - 8 - 1 - - - EM7 - CPU wakeup with event mask on event - input - 7 - 1 - - - EM6 - CPU wakeup with event mask on event - input - 6 - 1 - - - EM5 - CPU wakeup with event mask on event - input - 5 - 1 - - - EM4 - CPU wakeup with event mask on event - input - 4 - 1 - - - EM3 - CPU wakeup with event mask on event - input - 3 - 1 - - - EM2 - CPU wakeup with event mask on event - input - 2 - 1 - - - EM1 - CPU wakeup with event mask on event - input - 1 - 1 - - - EM0 - CPU wakeup with event mask on event - input - 0 - 1 - - - - - - - LPTIM - Low power timer - LPTIM - 0x40007C00 - - 0x0 - 0x400 - registers - - - - ISR - ISR - Interrupt and Status Register - 0x0 - 0x20 - read-only - 0x00000000 - - - ARRM - Autoreload match - 1 - 1 - - - - - ICR - ICR - Interrupt Clear Register - 0x4 - 0x20 - write-only - 0x00000000 - - - ARRMCF - Autoreload match Clear - Flag - 1 - 1 - - - - - IER - IER - Interrupt Enable Register - 0x8 - 0x20 - read-write - 0x00000000 - - - ARRMIE - Autoreload match Interrupt - Enable - 1 - 1 - - - - - CFGR - CFGR - Configuration Register - 0xC - 0x20 - read-write - 0x00000000 - - - PRELOAD - Registers update mode - 22 - 1 - - - PRESC - Clock prescaler - 9 - 3 - - - - - CR - CR - Control Register - 0x10 - 0x20 - read-write - 0x00000000 - - - RSTARE - Reset after read enable - 4 - 1 - - - SNGSTRT - LPTIM start in single mode - 1 - 1 - - - ENABLE - LPTIM Enable - 0 - 1 - - - - - ARR - ARR - Autoreload Register - 0x18 - 0x20 - read-write - 0x00000001 - - - ARR - Auto reload value - 0 - 16 - - - - - CNT - CNT - Counter Register - 0x1C - 0x20 - read-only - 0x00000000 - - - CNT - Counter value - 0 - 16 - - - - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global Interrupt - 27 - - - - SR - SR - Status register - 0x0 - 0x20 - 0x00C0 - - - ABRRQ - Automate baudrate detection requeset - 12 - 1 - write-only - - - ABRE - Automate baudrate detection error flag - 11 - 1 - read-only - - - ABRF - Automate baudrate detection flag - 10 - 1 - read-only - - - CTS - CTS flag - 9 - 1 - read-write - - - TXE - Transmit data register - empty - 7 - 1 - read-only - - - TC - Transmission complete - 6 - 1 - read-write - - - RXNE - Read data register not - empty - 5 - 1 - read-write - - - IDLE - IDLE line detected - 4 - 1 - read-only - - - ORE - Overrun error - 3 - 1 - read-only - - - NE - Noise error flag - 2 - 1 - read-only - - - FE - Framing error - 1 - 1 - read-only - - - PE - Parity error - 0 - 1 - read-only - - - - - DR - DR - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DR - Data value - 0 - 9 - - - - - BRR - BRR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV_Mantissa - mantissa of USARTDIV - 4 - 12 - - - DIV_Fraction - fraction of USARTDIV - 0 - 4 - - - - - CR1 - CR1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UE - USART enable - 13 - 1 - - - M - Word length - 12 - 1 - - - WAKE - Wakeup method - 11 - 1 - - - PCE - Parity control enable - 10 - 1 - - - PS - Parity selection - 9 - 1 - - - PEIE - PE interrupt enable - 8 - 1 - - - TXEIE - TXE interrupt enable - 7 - 1 - - - TCIE - Transmission complete interrupt - enable - 6 - 1 - - - RXNEIE - RXNE interrupt enable - 5 - 1 - - - IDLEIE - IDLE interrupt enable - 4 - 1 - - - TE - Transmitter enable - 3 - 1 - - - RE - Receiver enable - 2 - 1 - - - RWU - Receiver wakeup - 1 - 1 - - - SBK - Send break - 0 - 1 - - - - - CR2 - CR2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - STOP - STOP bits - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CPOL - Clock polarity - 10 - 1 - - - CPHA - Clock phase - 9 - 1 - - - LBCL - Last bit clock pulse - 8 - 1 - - - ADD - Address of the USART node - 0 - 4 - - - - - CR3 - CR3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - ABRMOD - Auto baudrate mode - 13 - 2 - - - ABREN - Auto baudrate enable - 12 - 1 - - - OVER8 - Oversampling mode - 11 - 1 - - - CTSIE - CTS interrupt enable - 10 - 1 - - - CTSE - CTS enable - 9 - 1 - - - RTSE - RTS enable - 8 - 1 - - - HDSEL - Half-duplex selection - 3 - 1 - - - IRLP - IrDA low-power - 2 - 1 - - - IREN - IrDA mode enable - 1 - 1 - - - EIE - Error interrupt enable - 0 - 1 - - - - - - - IWDG - Independent watchdog - IWDG - 0x40003000 - - 0x0 - 0x400 - registers - - - - KR - KR - Key register (IWDG_KR) - 0x0 - 0x20 - write-only - 0x00000000 - - - KEY - Key value - 0 - 16 - - - - - PR - PR - Prescaler register (IWDG_PR) - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Prescaler divider - 0 - 3 - - - - - RLR - RLR - Reload register (IWDG_RLR) - 0x8 - 0x20 - read-write - 0x00000FFF - - - RL - Watchdog counter reload - value - 0 - 12 - - - - - SR - SR - Status register (IWDG_SR) - 0xC - 0x20 - read-only - 0x00000000 - - - WVU - Watchdog counter window value update - 2 - 1 - - - RVU - Watchdog counter reload value - update - 1 - 1 - - - PVU - Watchdog prescaler value - update - 0 - 1 - - - - - WINR - WINR - Window register (IWDG_SR) - 0x10 - 0x20 - read-only - 0x00000000 - - - WIN - window counter - 0 - 12 - - - - - - - TIM1 - Advanced timer - TIM - 0x40012C00 - - 0x0 - 0x400 - registers - - - TIM1_BRK_UP_TRG_COM - TIM1 Break, Update, Trigger and Commutation Interrupt - 13 - - - TIM1_CC - TIM1 Capture Compare Interrupt - 14 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - CMS - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - OIS4 - Output Idle state 4 - 14 - 1 - - - OIS3N - Output Idle state 3 - 13 - 1 - - - OIS3 - Output Idle state 3 - 12 - 1 - - - OIS2N - Output Idle state 2 - 11 - 1 - - - OIS2 - Output Idle state 2 - 10 - 1 - - - OIS1N - Output Idle state 1 - 9 - 1 - - - OIS1 - Output Idle state 1 - 8 - 1 - - - TI1S - TI1 selection - 7 - 1 - - - MMS - Master mode selection - 4 - 3 - - - CCUS - Capture/compare control update - selection - 2 - 1 - - - CCPC - Capture/compare preloaded - control - 0 - 1 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - ETP - External trigger polarity - 15 - 1 - - - ECE - External clock enable - 14 - 1 - - - ETPS - External trigger prescaler - 12 - 2 - - - ETF - External trigger filter - 8 - 4 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - OCCS - OCREF clear selection bit - 3 - 1 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - BIE - Break interrupt enable - 7 - 1 - - - TIE - Trigger interrupt enable - 6 - 1 - - - COMIE - COM interrupt enable - 5 - 1 - - - CC4IE - Capture/Compare 4 interrupt - enable - 4 - 1 - - - CC3IE - Capture/Compare 3 interrupt - enable - 3 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC4OF - Capture/Compare 4 overcapture - flag - 12 - 1 - - - CC3OF - Capture/Compare 3 overcapture - flag - 11 - 1 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - BIF - Break interrupt flag - 7 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - COMIF - COM interrupt flag - 5 - 1 - - - CC4IF - Capture/Compare 4 interrupt - flag - 4 - 1 - - - CC3IF - Capture/Compare 3 interrupt - flag - 3 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - BG - Break generation - 7 - 1 - - - TG - Trigger generation - 6 - 1 - - - COMG - Capture/Compare control update - generation - 5 - 1 - - - CC4G - Capture/compare 4 - generation - 4 - 1 - - - CC3G - Capture/compare 3 - generation - 3 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - Output Compare 2 clear - enable - 15 - 1 - - - OC2M - Output Compare 2 mode - 12 - 3 - - - OC2PE - Output Compare 2 preload - enable - 11 - 1 - - - OC2FE - Output Compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1CE - Output Compare 1 clear - enable - 7 - 1 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - ICPSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register (output - mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - Output compare 4 clear - enable - 15 - 1 - - - OC4M - Output compare 4 mode - 12 - 3 - - - OC4PE - Output compare 4 preload - enable - 11 - 1 - - - OC4FE - Output compare 4 fast - enable - 10 - 1 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - OC3CE - Output compare 3 clear - enable - 7 - 1 - - - OC3M - Output compare 3 mode - 4 - 3 - - - OC3PE - Output compare 3 preload - enable - 3 - 1 - - - OC3FE - Output compare 3 fast - enable - 2 - 1 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input - mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - IC3F - Input capture 3 filter - 4 - 4 - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - CC3S - Capture/compare 3 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC4P - Capture/Compare 3 output - Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output - enable - 12 - 1 - - - CC3NP - Capture/Compare 3 output - Polarity - 11 - 1 - - - CC3NE - Capture/Compare 3 complementary output - enable - 10 - 1 - - - CC3P - Capture/Compare 3 output - Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output - enable - 8 - 1 - - - CC2NP - Capture/Compare 2 output - Polarity - 7 - 1 - - - CC2NE - Capture/Compare 2 complementary output - enable - 6 - 1 - - - CC2P - Capture/Compare 2 output - Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output - enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1NE - Capture/Compare 1 complementary output - enable - 2 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - RCR - RCR - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - REP - Repetition counter value - 0 - 8 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - CCR3 - CCR3 - capture/compare register 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - CCR3 - Capture/Compare value - 0 - 16 - - - - - CCR4 - CCR4 - capture/compare register 4 - 0x40 - 0x20 - read-write - 0x00000000 - - - CCR4 - Capture/Compare value - 0 - 16 - - - - - BDTR - BDTR - break and dead-time register - 0x44 - 0x20 - read-write - 0x0000 - - - MOE - Main output enable - 15 - 1 - - - AOE - Automatic output enable - 14 - 1 - - - BKP - Break polarity - 13 - 1 - - - BKE - Break enable - 12 - 1 - - - OSSR - Off-state selection for Run - mode - 11 - 1 - - - OSSI - Off-state selection for Idle - mode - 10 - 1 - - - LOCK - Lock configuration - 8 - 2 - - - DTG - Dead-time generator setup - 0 - 8 - - - - - - - TIM16 - General purpose timer - TIM - 0x40014400 - - 0x00 - 0x400 - registers - - - TIM16 - TIM16 global Interrupt - 21 - - - - CR1 - CR1 - TIM16 control register1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Prescaler factor - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - OPM - One pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - UG - Update generation - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - RCR - RCR - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - REP - Repetition counter value - 0 - 8 - - - - - - - SYSCFG - System configuration controller - SYSCFG - 0x40010000 - - 0x0 - 0x30 - registers - - - - CFGR1 - CFGR1 - SYSCFG configuration register - 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - I2C_PF1_ANF - Analog filter enable control driving capability - activation bits PF1 - 30 - 1 - - - I2C_PF0_ANF - Analog filter enable control driving capability - activation bits PF0 - 29 - 1 - - - I2C_PB8_ANF - Analog filter enable control driving capability - activation bits PB8 - 28 - 1 - - - I2C_PB7_ANF - Analog filter enable control driving capability - activation bits PB7 - 27 - 1 - - I2C_PB6_ANF - Analog filter enable control driving capability - activation bits PB6 - 26 - 1 - - - I2C_PA12_ANF - Analog filter enable control driving capability - activation bits PA12 - 25 - 1 - - - I2C_PA11_ANF - Analog filter enable control driving capability - activation bits PA11 - 24 - 1 - - - I2C_PA10_ANF - Analog filter enable control driving capability - activation bits PA10 - 23 - 1 - - - I2C_PA9_ANF - Analog filter enable control driving capability - activation bits PA9 - 22 - 1 - - - I2C_PA8_ANF - Analog filter enable control driving capability - activation bits PA8 - 21 - 1 - - - I2C_PA7_ANF - Analog filter enable control driving capability - activation bits PA7 - 20 - 1 - - - I2C_PA3_ANF - Analog filter enable control driving capability - activation bits PA3 - 19 - 1 - - - I2C_PA2_ANF - Analog filter enable control driving capability - activation bits PA2 - 18 - 1 - - - MEM_MODE - Memory mapping selection - bits - 0 - 2 - - - - - CFGR2 - CFGR2 - SYSCFG configuration register - 2 - 0x18 - 0x20 - read-write - 0x00000000 - - - ETR_SRC_TIM1 - TIM1 ETR source selection - 9 - 2 - - - LOCKUP_LOCK - Cortex-M0+ LOCKUP bit enable - bit - 0 - 1 - - - - - - - FLASH - Flash - Flash - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - FLASH global Interrupt - 3 - - - - ACR - ACR - Access control register - 0x0 - 0x20 - read-write - 0x00000600 - - - LATENCY - Latency - 0 - 1 - - - - - KEYR - KEYR - Flash key register - 0x8 - 0x20 - write-only - 0x00000000 - - - KEY - Flash key - 0 - 32 - - - - - OPTKEYR - OPTKEYR - Option byte key register - 0xC - 0x20 - write-only - 0x00000000 - - - OPTKEY - Option byte key - 0 - 32 - - - - - SR - SR - Status register - 0x10 - 0x20 - read-write - 0x00000000 - - - BSY - Busy - 16 - 1 - - - OPTVERR - Option and Engineering bits loading - validity error - 15 - 1 - - - WRPERR - Write protected error - 4 - 1 - - - EOP - End of operation - 0 - 1 - - - - - CR - CR - Flash control register - 0x14 - 0x20 - read-write - 0xC0000000 - - - LOCK - FLASH_CR Lock - 31 - 1 - - - OPTLOCK - Options Lock - 30 - 1 - - - OBL_LAUNCH - Force the option byte - loading - 27 - 1 - - - ERRIE - Error interrupt enable - 25 - 1 - - - EOPIE - End of operation interrupt - enable - 24 - 1 - - - PGTSTRT - Flash main memory program start - 19 - 1 - - - OPTSTRT - Option byte program start - 17 - 1 - - - SER - Sector erase - 11 - 1 - - - MER - Mass erase - 2 - 1 - - - PER - Page erase - 1 - 1 - - - PG - Programming - 0 - 1 - - - - - OPTR - OPTR - Flash option register - 0x20 - 0x20 - read-write - 0x4F55B0AA - - - nBOOT1 - Boot configuration - 15 - 1 - - - NRST_MODE - NRST_MODE - 14 - 1 - - - IDWG_SW - Independent watchdog - selection - 12 - 1 - - - BORF_LEV - These bits contain the VDD supply level - threshold that activates the reset - 9 - 3 - - - BOREN - BOR reset Level - 8 - 1 - - - RDP - Read Protection - 0 - 8 - - - - - SDKR - SDKR - Flash SDK address - register - 0x24 - 0x20 - read-write - 0xFFE0001F - - - SDK_END - SDK area end address - 8 - 5 - - - SDK_STRT - SDK area start address - 0 - 5 - - - - - WRPR - WRPR - Flash WRP address - register - 0x2C - 0x20 - read-write - 0x0000FFFF - - - WRP - WRP address - 0 - 16 - - - - - STCR - STCR - Flash sleep time config - register - 0x90 - 0x20 - read-write - 0x00006400 - - - SLEEP_TIME - FLash sleep time configuration(counter based on HSI_10M) - 8 - 8 - - - SLEEP_EN - FLash sleep enable - 0 - 1 - - - - - TS0 - TS0 - Flash TS0 - register - 0x100 - 0x20 - read-write - 0x000000B4 - - - TS0 - FLash TS0 register - 0 - 8 - - - - - TS1 - TS1 - Flash TS1 - register - 0x104 - 0x20 - read-write - 0x000001B0 - - - TS1 - FLash TS1 register - 0 - 9 - - - - - TS2P - TS2P - Flash TS2P - register - 0x108 - 0x20 - read-write - 0x000000B4 - - - TS2P - FLash TS2P register - 0 - 8 - - - - - TPS3 - TPS3 - Flash TPS3 - register - 0x10C - 0x20 - read-write - 0x000006C0 - - - TPS3 - FLash TPS3 register - 0 - 11 - - - - - TS3 - TS3 - Flash TS3 - register - 0x110 - 0x20 - read-write - 0x000000B4 - - - TS3 - FLash TS3 register - 0 - 8 - - - - - PERTPE - PERTPE - Flash PERTPE - register - 0x114 - 0x20 - read-write - 0x0000EA60 - - - PERTPE - FLash PERTPE register - 0 - 17 - - - - - SMERTPE - SMERTPE - Flash SMERTPE - register - 0x118 - 0x20 - read-write - 0x0000FD20 - - - SMERTPE - FLash SMERTPE register - 0 - 17 - - - - - PRGTPE - PRGTPE - Flash PRGTPE - register - 0x11C - 0x20 - read-write - 0x00008CA0 - - - PRGTPE - FLash PRGTPE register - 0 - 16 - - - - - PRETPE - PRETPE - Flash PRETPE - register - 0x120 - 0x20 - read-write - 0x000012C0 - - - PRETPE - FLash PRETPE register - 0 - 13 - - - - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DR - DR - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DR - Data Register - 0 - 32 - - - - - IDR - IDR - Independent Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - IDR - Independent Data register - 0 - 8 - - - - - CR - CR - Control register - 0x8 - 0x20 - write-only - 0x00000000 - - - RESET - Reset bit - 0 - 1 - - - - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global Interrupt - 25 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - BIDIMODE - Bidirectional data mode - enable - 15 - 1 - - - BIDIOE - Output enable in bidirectional - mode - 14 - 1 - - - RXONLY - Receive only - 10 - 1 - - - SSM - Software slave management - 9 - 1 - - - SSI - Internal slave selection - 8 - 1 - - - LSBFIRST - Frame format - 7 - 1 - - - SPE - SPI enable - 6 - 1 - - - BR - Baud rate control - 3 - 3 - - - MSTR - Master selection - 2 - 1 - - - CPOL - Clock polarity - 1 - 1 - - - CPHA - Clock phase - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - SLVFM - Slave fast mode enable - 15 - 1 - - - FRXTH - FIFO reception threshold - 12 - 1 - - - DS - Data length - - 11 - 1 - - - TXEIE - Tx buffer empty interrupt - enable - 7 - 1 - - - RXNEIE - RX buffer not empty interrupt - enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - SSOE - SS output enable - 2 - 1 - - - - - SR - SR - status register - 0x8 - 0x20 - 0x0002 - - - FTLVL - FIFO transmission level - 11 - 2 - read-only - - - FRLVL - FIFO reception level - 9 - 2 - read-only - - - BSY - Busy flag - 7 - 1 - read-only - - - OVR - Overrun flag - 6 - 1 - read-only - - - MODF - Mode fault - 5 - 1 - read-only - - - TXE - Transmit buffer empty - 1 - 1 - read-only - - - RXNE - Receive buffer not empty - 0 - 1 - read-only - - - - - DR - DR - data register - 0xC - 0x20 - read-write - 0x0000 - - - DR - Data register - 0 - 16 - - - - - - - I2C - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1 - I2C1 global Interrupt - 23 - - - - CR1 - CR1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SWRST - Software reset - 15 - 1 - - - PEC - Packet error checking - 12 - 1 - - - POS - Acknowledge/PEC Position (for data - reception) - 11 - 1 - - - ACK - Acknowledge enable - 10 - 1 - - - STOP - Stop generation - 9 - 1 - - - START - Start generation - 8 - 1 - - - NOSTRETCH - Clock stretching disable (Slave - mode) - 7 - 1 - - - ENGC - General call enable - 6 - 1 - - - ENPEC - PEC enable - 5 - 1 - - - PE - Peripheral enable - 0 - 1 - - - - - CR2 - CR2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - ITBUFEN - Buffer interrupt enable - 10 - 1 - - - ITEVTEN - Event interrupt enable - 9 - 1 - - - ITERREN - Error interrupt enable - 8 - 1 - - - FREQ - Peripheral clock frequency - 0 - 6 - - - - - OAR1 - OAR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADD - Interface address - 1 - 7 - - - - - DR - DR - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DR - 8-bit data register - 0 - 8 - - - - - SR1 - SR1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - PECERR - PEC Error in reception - 12 - 1 - read-write - - - OVR - Overrun/Underrun - 11 - 1 - read-write - - - AF - Acknowledge failure - 10 - 1 - read-write - - - ARLO - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BERR - Bus error - 8 - 1 - read-write - - - TxE - Data register empty - (transmitters) - 7 - 1 - read-only - - - RxNE - Data register not empty - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - BTF - Byte transfer finished - 2 - 1 - read-only - - - ADDR - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - SB - Start bit (Master mode) - 0 - 1 - read-only - - - - - SR2 - SR2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PEC - acket error checking - register - 8 - 8 - - - DUALF - Dual flag (Slave mode) - 7 - 1 - - - GENCALL - General call address (Slave - mode) - 4 - 1 - - - TRA - Transmitter/receiver - 2 - 1 - - - BUSY - Bus busy - 1 - 1 - - - MSL - Master/slave - 0 - 1 - - - - - CCR - CCR - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - F_S - I2C master mode selection - 15 - 1 - - - DUTY - Fast mode duty cycle - 14 - 1 - - - CCR - Clock control register in Fast/Standard - mode (Master mode) - 0 - 12 - - - - - TRISE - TRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - TRISE - Maximum rise time in Fast/Standard mode - (Master mode) - 0 - 6 - - - - - - - DBGMCU - Debug support - DBGMCU - 0x40015800 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - MCU Device ID Code Register - 0x0 - 0x20 - read-only - 0x0 - - - - - - CR - CR - Debug MCU Configuration - Register - 0x4 - 0x20 - read-write - 0x0 - - - DBG_STOP - Debug Stop Mode - 1 - 1 - - - - - APB_FZ1 - APB_FZ1 - APB Freeze Register1 - 0x8 - 0x20 - read-write - 0x0 - - - DBG_IWDG_STOP - Debug Independent Wachdog stopped when - Core is halted - 12 - 1 - - - DBG_LPTIM_STOP - Debug LPTIM stopped when Core is - halted - 31 - 1 - - - - - APB_FZ2 - APB_FZ2 - APB Freeze Register2 - 0xC - 0x20 - read-write - 0x0 - - - DBG_TIMER1_STOP - Debug Timer 1 stopped when Core is - halted - 11 - 1 - - - DBG_TIMER16_STOP - Debug Timer 16 stopped when Core is - halted - 17 - 1 - - - - - - - + + + + Puya + Puya + PY32F0xx_DFP + + PY32F0 + 1.0.0 + Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. + + + + CM0+ + r0p1 + little + false + false + 4 + false + + + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADC + Analog to Digital Converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + ISR + ISR + ADC interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + AWD + ADC analog watchdog flag + 7 + 1 + + + OVR + ADC group regular overrun + flag + 4 + 1 + + + EOSEQ + ADC group regular end of sequence + conversions flag + 3 + 1 + + + EOC + ADC group regular end of unitary + conversion flag + 2 + 1 + + + EOSMP + ADC group regular end of sampling + flag + 1 + 1 + + + + + IER + IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + AWDIE + ADC analog watchdog + interrupt + 7 + 1 + + + OVRIE + ADC group regular overrun + interrupt + 4 + 1 + + + EOSEQIE + ADC group regular end of sequence + conversions interrupt + 3 + 1 + + + EOCIE + ADC group regular end of unitary + conversion interrupt + 2 + 1 + + + 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0x00000000 + + + LSCOEN + Low-speed clock output (LSCO) + enable + 24 + 1 + + + + + CSR + CSR + Control/status register + 0x60 + 0x20 + read-write + 0x00000000 + + + IWDGRSTF + Independent window watchdog reset + flag + 29 + 1 + + + SFTRSTF + Software reset flag + 28 + 1 + + + PWRRSTF + BOR or POR/PDR flag + 27 + 1 + + + PINRSTF + Pin reset flag + 26 + 1 + + + OBLRSTF + Option byte loader reset + flag + 25 + 1 + + + RMVF + Remove reset flags + 23 + 1 + + + LSIRDY + LSI oscillator ready + 1 + 1 + + + LSION + LSI oscillator enable + 0 + 1 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x50000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xEBFFFFFF + + + MODE15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODE14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODE13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODE12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODE11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODE10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODE9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODE8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODE7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODE6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODE5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODE4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODE3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODE2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODE1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODE0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEED15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEED14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEED13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEED12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEED11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEED10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEED9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEED8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEED7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEED6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEED5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEED4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEED3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEED2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEED1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEED0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x24000000 + + + PUPD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID15 + Port input data (y = + 0..15) + 15 + 1 + + + ID14 + Port input data (y = + 0..15) + 14 + 1 + + + ID13 + Port input data (y = + 0..15) + 13 + 1 + + + ID12 + Port input data (y = + 0..15) + 12 + 1 + + + ID11 + Port input data (y = + 0..15) + 11 + 1 + + + ID10 + Port input data (y = + 0..15) + 10 + 1 + + + ID9 + Port input data (y = + 0..15) + 9 + 1 + + + ID8 + Port input data (y = + 0..15) + 8 + 1 + + + ID7 + Port input data (y = + 0..15) + 7 + 1 + + + ID6 + Port input data (y = + 0..15) + 6 + 1 + + + ID5 + Port input data (y = + 0..15) + 5 + 1 + + + ID4 + Port input data (y = + 0..15) + 4 + 1 + + + ID3 + Port input data (y = + 0..15) + 3 + 1 + + + ID2 + Port input data (y = + 0..15) + 2 + 1 + + + ID1 + Port input data (y = + 0..15) + 1 + 1 + + + ID0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD15 + Port output data (y = + 0..15) + 15 + 1 + + + OD14 + Port output data (y = + 0..15) + 14 + 1 + + + OD13 + Port output data (y = + 0..15) + 13 + 1 + + + OD12 + Port output data (y = + 0..15) + 12 + 1 + + + OD11 + Port output data (y = + 0..15) + 11 + 1 + + + OD10 + Port output data (y = + 0..15) + 10 + 1 + + + OD9 + Port output data (y = + 0..15) + 9 + 1 + + + OD8 + Port output data (y = + 0..15) + 8 + 1 + + + OD7 + Port output data (y = + 0..15) + 7 + 1 + + + OD6 + Port output data (y = + 0..15) + 6 + 1 + + + OD5 + Port output data (y = + 0..15) + 5 + 1 + + + OD4 + Port output data (y = + 0..15) + 4 + 1 + + + OD3 + Port output data (y = + 0..15) + 3 + 1 + + + OD2 + Port output data (y = + 0..15) + 2 + 1 + + + OD1 + Port output data (y = + 0..15) + 1 + 1 + + + OD0 + Port output data (y = + 0..15) + 0 + 1 + + + + + BSRR + BSRR + GPIO port bit set/reset + register + 0x18 + 0x20 + write-only + 0x00000000 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(y= + 0..15) + 13 + 1 + + + BS12 + Port x set bit y (y= + 0..15) + 12 + 1 + + + BS11 + Port x set bit y (y= + 0..15) + 11 + 1 + + + BS10 + Port x set bit y (y= + 0..15) + 10 + 1 + + + BS9 + Port x set bit y (y= + 0..15) + 9 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK15 + Port x lock bit y (y= + 0..15) + 15 + 1 + + + LCK14 + Port x lock bit y (y= + 0..15) + 14 + 1 + + + LCK13 + Port x lock bit y (y= + 0..15) + 13 + 1 + + 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0..15) + 21 + 1 + + + BR4 + Port x reset bit y (y = + 0..15) + 20 + 1 + + + BR3 + Port x reset bit y (y = + 0..15) + 19 + 1 + + + BR2 + Port x reset bit y (y = + 0..15) + 18 + 1 + + + BR1 + Port x reset bit y (y = + 0..15) + 17 + 1 + + + BR0 + Port x set bit y (y= + 0..15) + 16 + 1 + + + BS8 + Port x set bit y (y= + 0..15) + 8 + 1 + + + BS7 + Port x set bit y (y= + 0..15) + 7 + 1 + + + BS6 + Port x set bit y (y= + 0..15) + 6 + 1 + + + BS5 + Port x set bit y (y= + 0..15) + 5 + 1 + + + BS4 + Port x set bit y (y= + 0..15) + 4 + 1 + + + BS3 + Port x set bit y (y= + 0..15) + 3 + 1 + + + BS2 + Port x set bit y (y= + 0..15) + 2 + 1 + + + BS1 + Port x set bit y (y= + 0..15) + 1 + 1 + + + BS0 + Port x set bit y (y= + 0..15) + 0 + 1 + + + + + LCKR + LCKR + GPIO port configuration lock + register + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + Port x lock bit y (y= + 0..15) + 16 + 1 + + + LCK8 + Port x lock bit y (y= + 0..15) + 8 + 1 + + + LCK7 + Port x lock bit y (y= + 0..15) + 7 + 1 + + + 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0x00000000 + + + EM29 + CPU wakeup with event mask on event + input + 29 + 1 + + + EM19 + CPU wakeup with event mask on event + input + 19 + 1 + + + EM18 + CPU wakeup with event mask on event + input + 18 + 1 + + + EM17 + CPU wakeup with event mask on event + input + 17 + 1 + + + EM16 + CPU wakeup with event mask on event + input + 16 + 1 + + + EM15 + CPU wakeup with event mask on event + input + 15 + 1 + + + EM14 + CPU wakeup with event mask on event + input + 14 + 1 + + + EM13 + CPU wakeup with event mask on event + input + 13 + 1 + + + EM12 + CPU wakeup with event mask on event + input + 12 + 1 + + + EM11 + CPU wakeup with event mask on event + input + 11 + 1 + + + EM10 + CPU wakeup with event mask on event + input + 10 + 1 + + + EM9 + CPU wakeup with event mask on event + input + 9 + 1 + + + EM8 + CPU wakeup with event mask on event + input + 8 + 1 + + + EM7 + CPU wakeup with event mask on event + input + 7 + 1 + + + EM6 + CPU wakeup with event mask on event + input + 6 + 1 + + + EM5 + CPU wakeup with event mask on event + input + 5 + 1 + + + EM4 + CPU wakeup with event mask on event + input + 4 + 1 + + + EM3 + CPU wakeup with event mask on event + input + 3 + 1 + + + EM2 + CPU wakeup with event mask on event + input + 2 + 1 + + + EM1 + CPU wakeup with event mask on event + input + 1 + 1 + + + EM0 + CPU wakeup with event mask on event + input + 0 + 1 + + + + + + + LPTIM + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + ARRM + Autoreload match + 1 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + PRELOAD + Registers update mode + 22 + 1 + + + PRESC + Clock prescaler + 9 + 3 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + Reset after read enable + 4 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global Interrupt + 27 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C0 + + + ABRRQ + Automate baudrate detection requeset + 12 + 1 + write-only + + + ABRE + Automate baudrate detection error flag + 11 + 1 + read-only + + + ABRF + Automate baudrate detection flag + 10 + 1 + read-only + + + CTS + CTS flag + 9 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NE + Noise error flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + SBK + Send break + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + ABRMOD + Auto baudrate mode + 13 + 2 + + + ABREN + Auto baudrate enable + 12 + 1 + + + OVER8 + Oversampling mode + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register (IWDG_KR) + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value + 0 + 16 + + + + + PR + PR + Prescaler register (IWDG_PR) + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register (IWDG_RLR) + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register (IWDG_SR) + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value update + 2 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + + + WINR + WINR + Window register (IWDG_SR) + 0x10 + 0x20 + read-only + 0x00000000 + + + WIN + window counter + 0 + 12 + + + + + + + TIM1 + Advanced timer + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_UP_TRG_COM + TIM1 Break, Update, Trigger and Commutation Interrupt + 13 + + + TIM1_CC + TIM1 Capture Compare Interrupt + 14 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS4 + Output Idle state 4 + 14 + 1 + + + OIS3N + Output Idle state 3 + 13 + 1 + + + OIS3 + Output Idle state 3 + 12 + 1 + + + OIS2N + Output Idle state 2 + 11 + 1 + + + OIS2 + Output Idle state 2 + 10 + 1 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + TI1S + TI1 selection + 7 + 1 + + + MMS + Master mode selection + 4 + 3 + + + CCUS + Capture/compare control update + selection + 2 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + SMCR + SMCR + slave mode control register + 0x8 + 0x20 + read-write + 0x0000 + + + ETP + External trigger polarity + 15 + 1 + + + ECE + External clock enable + 14 + 1 + + + ETPS + External trigger prescaler + 12 + 2 + + + ETF + External trigger filter + 8 + 4 + + + MSM + Master/Slave mode + 7 + 1 + + + TS + Trigger selection + 4 + 3 + + + OCCS + OCREF clear selection bit + 3 + 1 + + + SMS + Slave mode selection + 0 + 3 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + BIE + Break interrupt enable + 7 + 1 + + + TIE + Trigger interrupt enable + 6 + 1 + + + COMIE + COM interrupt enable + 5 + 1 + + + CC4IE + Capture/Compare 4 interrupt + enable + 4 + 1 + + + CC3IE + Capture/Compare 3 interrupt + enable + 3 + 1 + + + CC2IE + Capture/Compare 2 interrupt + enable + 2 + 1 + + + CC1IE + Capture/Compare 1 interrupt + enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC4OF + Capture/Compare 4 overcapture + flag + 12 + 1 + + + CC3OF + Capture/Compare 3 overcapture + flag + 11 + 1 + + + CC2OF + Capture/compare 2 overcapture + flag + 10 + 1 + + + CC1OF + Capture/Compare 1 overcapture + flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + TIF + Trigger interrupt flag + 6 + 1 + + + COMIF + COM interrupt flag + 5 + 1 + + + CC4IF + Capture/Compare 4 interrupt + flag + 4 + 1 + + + CC3IF + Capture/Compare 3 interrupt + flag + 3 + 1 + + + CC2IF + Capture/Compare 2 interrupt + flag + 2 + 1 + + + CC1IF + Capture/compare 1 interrupt + flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break generation + 7 + 1 + + + TG + Trigger generation + 6 + 1 + + + COMG + Capture/Compare control update + generation + 5 + 1 + + + CC4G + Capture/compare 4 + generation + 4 + 1 + + + CC3G + Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output Compare 2 clear + enable + 15 + 1 + + + OC2M + Output Compare 2 mode + 12 + 3 + + + OC2PE + Output Compare 2 preload + enable + 11 + 1 + + + OC2FE + Output Compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output Compare 1 clear + enable + 7 + 1 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + ICPSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4P + Capture/Compare 3 output + Polarity + 13 + 1 + + + CC4E + Capture/Compare 4 output + enable + 12 + 1 + + + CC3NP + Capture/Compare 3 output + Polarity + 11 + 1 + + + CC3NE + Capture/Compare 3 complementary output + enable + 10 + 1 + + + CC3P + Capture/Compare 3 output + Polarity + 9 + 1 + + + CC3E + Capture/Compare 3 output + enable + 8 + 1 + + + CC2NP + Capture/Compare 2 output + Polarity + 7 + 1 + + + CC2NE + Capture/Compare 2 complementary output + enable + 6 + 1 + + + CC2P + Capture/Compare 2 output + Polarity + 5 + 1 + + + CC2E + Capture/Compare 2 output + enable + 4 + 1 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + + + TIM16 + General purpose timer + TIM + 0x40014400 + + 0x00 + 0x400 + registers + + + TIM16 + TIM16 global Interrupt + 21 + + + + CR1 + CR1 + TIM16 control register1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Prescaler factor + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + UG + Update generation + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x30 + registers + + + + CFGR1 + CFGR1 + SYSCFG configuration register + 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + I2C_PF1_ANF + Analog filter enable control driving capability + activation bits PF1 + 30 + 1 + + + I2C_PF0_ANF + Analog filter enable control driving capability + activation bits PF0 + 29 + 1 + + + I2C_PB8_ANF + Analog filter enable control driving capability + activation bits PB8 + 28 + 1 + + + I2C_PB7_ANF + Analog filter enable control driving capability + activation bits PB7 + 27 + 1 + + I2C_PB6_ANF + Analog filter enable control driving capability + activation bits PB6 + 26 + 1 + + + I2C_PA12_ANF + Analog filter enable control driving capability + activation bits PA12 + 25 + 1 + + + I2C_PA11_ANF + Analog filter enable control driving capability + activation bits PA11 + 24 + 1 + + + I2C_PA10_ANF + Analog filter enable control driving capability + activation bits PA10 + 23 + 1 + + + I2C_PA9_ANF + Analog filter enable control driving capability + activation bits PA9 + 22 + 1 + + + I2C_PA8_ANF + Analog filter enable control driving capability + activation bits PA8 + 21 + 1 + + + I2C_PA7_ANF + Analog filter enable control driving capability + activation bits PA7 + 20 + 1 + + + I2C_PA3_ANF + Analog filter enable control driving capability + activation bits PA3 + 19 + 1 + + + I2C_PA2_ANF + Analog filter enable control driving capability + activation bits PA2 + 18 + 1 + + + MEM_MODE + Memory mapping selection + bits + 0 + 2 + + + + + CFGR2 + CFGR2 + SYSCFG configuration register + 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + ETR_SRC_TIM1 + TIM1 ETR source selection + 9 + 2 + + + LOCKUP_LOCK + Cortex-M0+ LOCKUP bit enable + bit + 0 + 1 + + + + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH global Interrupt + 3 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 1 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEY + Flash key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + read-write + 0x00000000 + + + BSY + Busy + 16 + 1 + + + OPTVERR + Option and Engineering bits loading + validity error + 15 + 1 + + + WRPERR + Write protected error + 4 + 1 + + + EOP + End of operation + 0 + 1 + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + OBL_LAUNCH + Force the option byte + loading + 27 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + EOPIE + End of operation interrupt + enable + 24 + 1 + + + PGTSTRT + Flash main memory program start + 19 + 1 + + + OPTSTRT + Option byte program start + 17 + 1 + + + SER + Sector erase + 11 + 1 + + + MER + Mass erase + 2 + 1 + + + PER + Page erase + 1 + 1 + + + PG + Programming + 0 + 1 + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0x4F55B0AA + + + nBOOT1 + Boot configuration + 15 + 1 + + + NRST_MODE + NRST_MODE + 14 + 1 + + + IDWG_SW + Independent watchdog + selection + 12 + 1 + + + BORF_LEV + These bits contain the VDD supply level + threshold that activates the reset + 9 + 3 + + + BOREN + BOR reset Level + 8 + 1 + + + RDP + Read Protection + 0 + 8 + + + + + SDKR + SDKR + Flash SDK address + register + 0x24 + 0x20 + read-write + 0xFFE0001F + + + SDK_END + SDK area end address + 8 + 5 + + + SDK_STRT + SDK area start address + 0 + 5 + + + + + WRPR + WRPR + Flash WRP address + register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + WRP + WRP address + 0 + 16 + + + + + STCR + STCR + Flash sleep time config + register + 0x90 + 0x20 + read-write + 0x00006400 + + + SLEEP_TIME + FLash sleep time configuration(counter based on HSI_10M) + 8 + 8 + + + SLEEP_EN + FLash sleep enable + 0 + 1 + + + + + TS0 + TS0 + Flash TS0 + register + 0x100 + 0x20 + read-write + 0x000000B4 + + + TS0 + FLash TS0 register + 0 + 8 + + + + + TS1 + TS1 + Flash TS1 + register + 0x104 + 0x20 + read-write + 0x000001B0 + + + TS1 + FLash TS1 register + 0 + 9 + + + + + TS2P + TS2P + Flash TS2P + register + 0x108 + 0x20 + read-write + 0x000000B4 + + + TS2P + FLash TS2P register + 0 + 8 + + + + + TPS3 + TPS3 + Flash TPS3 + register + 0x10C + 0x20 + read-write + 0x000006C0 + + + TPS3 + FLash TPS3 register + 0 + 11 + + + + + TS3 + TS3 + Flash TS3 + register + 0x110 + 0x20 + read-write + 0x000000B4 + + + TS3 + FLash TS3 register + 0 + 8 + + + + + PERTPE + PERTPE + Flash PERTPE + register + 0x114 + 0x20 + read-write + 0x0000EA60 + + + PERTPE + FLash PERTPE register + 0 + 17 + + + + + SMERTPE + SMERTPE + Flash SMERTPE + register + 0x118 + 0x20 + read-write + 0x0000FD20 + + + SMERTPE + FLash SMERTPE register + 0 + 17 + + + + + PRGTPE + PRGTPE + Flash PRGTPE + register + 0x11C + 0x20 + read-write + 0x00008CA0 + + + PRGTPE + FLash PRGTPE register + 0 + 16 + + + + + PRETPE + PRETPE + Flash PRETPE + register + 0x120 + 0x20 + read-write + 0x000012C0 + + + PRETPE + FLash PRETPE register + 0 + 13 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global Interrupt + 25 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave selection + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + SLVFM + Slave fast mode enable + 15 + 1 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + DS + Data length + + 11 + 1 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + SSOE + SS output enable + 2 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + + + I2C + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 global Interrupt + 23 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADD + Interface address + 1 + 7 + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DR + 8-bit data register + 0 + 8 + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + + + + CR + CR + Debug MCU Configuration + Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + + + APB_FZ1 + APB_FZ1 + APB Freeze Register1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when + Core is halted + 12 + 1 + + + DBG_LPTIM_STOP + Debug LPTIM stopped when Core is + halted + 31 + 1 + + + + + APB_FZ2 + APB_FZ2 + APB Freeze Register2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIMER1_STOP + Debug Timer 1 stopped when Core is + halted + 11 + 1 + + + DBG_TIMER16_STOP + Debug Timer 16 stopped when Core is + halted + 17 + 1 + + + + + + + diff --git a/Misc/SVD/py32f002xx.svd b/Misc/SVD/py32f002xx.svd new file mode 100644 index 0000000..aebe47e --- /dev/null +++ b/Misc/SVD/py32f002xx.svd @@ -0,0 +1,7953 @@ + + + + Puya + Puya + PY32F0xx_DFP + + PY32F0 + 1.0.0 + Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. + + + + CM0+ + r0p1 + little + false + false + 4 + false + + + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADC + Analog to Digital Converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC + ADC Interrupt through EXTI Lines 17 and 18 + 12 + + + + ISR + ISR + ADC interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + AWD + ADC analog watchdog flag + 7 + 1 + + + OVR + ADC group regular overrun + flag + 4 + 1 + + + EOSEQ + ADC group regular end of sequence + conversions flag + 3 + 1 + + + EOC + ADC group regular end of unitary + conversion flag + 2 + 1 + + + EOSMP + ADC group regular end of sampling + flag + 1 + 1 + + + + + IER + IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + AWDIE + ADC analog watchdog + interrupt + 7 + 1 + + + OVRIE + ADC group regular overrun + interrupt + 4 + 1 + + + EOSEQIE + ADC group regular end of sequence + conversions interrupt + 3 + 1 + + + EOCIE + ADC group regular end of unitary + conversion interrupt + 2 + 1 + + + EOSMPIE + ADC group regular end of sampling + interrupt + 1 + 1 + + + + + CR + CR + ADC control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADC group regular conversion + calibration + 31 + 1 + + + VERBUFF_SEL + desc VERBUFF_SEL + 6 + 2 + + + VREF_BUFFERE + desc VREF_BUFFERE + 5 + 1 + + + ADSTP + ADC group regular conversion + stop + 4 + 1 + + + ADSTART + ADC group regular conversion + start + 2 + 1 + + + ADEN + ADC enable + 0 + 1 + + + + + CFGR1 + CFGR1 + ADC configuration register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + AWDCH + ADC analog watchdog monitored channel + selection + 26 + 4 + + + AWDEN + ADC analog watchdog enable on scope + ADC group regular + 23 + 1 + + + AWDSGL + ADC analog watchdog monitoring a + single channel or all channels + 22 + 1 + + + DISCEN + ADC group regular sequencer + discontinuous mode + 16 + 1 + + + WAIT + Wait conversion mode + 14 + 1 + + + CONT + ADC group regular continuous conversion + mode + 13 + 1 + + + OVRMOD + ADC group regular overrun + configuration + 12 + 1 + + + EXTEN + ADC group regular external trigger + polarity + 10 + 2 + + + EXTSEL + ADC group regular external trigger + source + 6 + 3 + + + ALIGN + ADC data alignement + 5 + 1 + + + RESSEL + ADC data resolution + 3 + 2 + + + SCANDIR + Scan sequence direction + 2 + 1 + + + + + CFGR2 + CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CKMODE + ADC clock mode + 28 + 4 + + + + + SMPR + SMPR + ADC sampling time register + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP + Sampling time selection + 0 + 3 + + + + + TR + TR + ADC analog watchdog 1 threshold register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT + ADC analog watchdog threshold + high + 16 + 12 + + + LT + ADC analog watchdog threshold + low + 0 + 12 + + + + + CHSELR + CHSELR + ADC group regular sequencer register + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + CHSEL12 + Channel-12 selection + 12 + 1 + + + CHSEL11 + Channel-11 selection + 11 + 1 + + + CHSEL9 + Channel-9 selection + 9 + 1 + + + CHSEL8 + Channel-8 selection + 8 + 1 + + + CHSEL7 + Channel-7 selection + 7 + 1 + + + CHSEL6 + Channel-6 selection + 6 + 1 + + + CHSEL5 + Channel-5 selection + 5 + 1 + + + CHSEL4 + Channel-4 selection + 4 + 1 + + + CHSEL3 + Channel-3 selection + 3 + 1 + + + CHSEL2 + Channel-2 selection + 2 + 1 + + + CHSEL1 + Channel-1 selection + 1 + 1 + + + CHSEL0 + Channel-0 selection + 0 + 1 + + + + + DR + DR + ADC group regular data register + 0x40 + 0x20 + read-only + 0x00000000 + + + DATA + ADC group regular conversion + data + 0 + 16 + + + + + CCSR + CCSR + ADC calibration configuration and status register + 0x44 + 0x20 + read-write + 0x00000000 + + + CALON + Calibration flag + 31 + 1 + read-only + + + CALFAIL + Calibration fail flag + 30 + 1 + + + OFFSUC + desc OFFSUC + 29 + 1 + + + CALSET + Calibration factor selection + 15 + 1 + + + CALBYP + desc CALBYP + 14 + 1 + + + CALSMP + Calibration sample time selection + 12 + 2 + + + CALSEL + Calibration contents selection + 11 + 1 + + + + + CALRR1 + CALRR1 + ADC calibration result register 1 + 0x48 + 0x20 + read-only + 0x00000000 + + + CALBOUT + offset result + 16 + 7 + + + CALC5OUT + C5 result + 8 + 8 + + + CALC4OUT + C4 result + 0 + 8 + + + + + CALRR2 + CALRR2 + ADC calibration result register 2 + 0x4C + 0x20 + read-only + 0x00000000 + + + CALC3OUT + C3 result + 24 + 8 + + + CALC2OUT + C2 result + 16 + 8 + + + CALC1OUT + C1 result + 8 + 8 + + + CALC0OUT + C0 result + 0 + 8 + + + + + CALFIR1 + CALFIR1 + ADC calibration factor input register 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + CALBIO + Calibration offset factor input + 16 + 7 + + + CALC5IO + Calibration C5 factor input + 8 + 8 + + + CALC4IO + Calibration C4 factor input + 0 + 8 + + + + + CALFIR2 + CALFIR2 + ADC calibration factor input register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + CALC3IO + Calibration C3 factor input + 24 + 8 + + + CALC2IO + Calibration C2 factor input + 16 + 8 + + + CALC1IO + Calibration C1 factor input + 8 + 8 + + + CALC0IO + Calibration C0 factor input + 0 + 8 + + + + + CCR + CCR + ADC common configuration register + 0x308 + 0x20 + read-write + 0x00000000 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VREFEN + VREFINT enable + 22 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global Interrupt + 4 + + + + CR + CR + Clock control register + 0x0 + 0x20 + read-write + 0x00000100 + + + HSIDIV + HSI16 clock division + factor + 11 + 3 + + + HSIRDY + HSI16 clock ready flag + 10 + 1 + + + HSION + HSI16 clock enable + 8 + 1 + + + + + ICSCR + ICSCR + Internal clock sources calibration + register + 0x4 + 0x20 + 0x10000000 + + + LSI_STARTUP + LSI startup time + 26 + 2 + read-write + + + LSI_TRIM + LSI clock trimming + 16 + 9 + read-write + + + HSI_FS + HSI frequency selection + 13 + 3 + read-write + + + HSI_TRIM + HSI clock trimming + 0 + 13 + read-write + + + + + CFGR + CFGR + Clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCOPRE + Microcontroller clock output + prescaler + 28 + 3 + read-write + + + MCOSEL + Microcontroller clock + output + 24 + 3 + read-write + + + PPRE + APB prescaler + 12 + 3 + read-write + + + HPRE + AHB prescaler + 8 + 4 + read-write + + + SWS + System clock switch status + 3 + 3 + read-only + + + SW + System clock switch + 0 + 3 + read-write + + + + + ECSCR + ECSCR + External clock source control register + 0x10 + 0x20 + 0x00000000 + + + LSE_DRIVER + desc LSE_DRIVER + 16 + 2 + read-write + + + + + CIER + CIER + Clock interrupt enable + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HSIRDYIE + HSI ready interrupt enable + 3 + 1 + + + LSERDYIE + LSE ready interrupt enable + 1 + 1 + + + LSIRDYIE + LSI ready interrupt enable + 0 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x1C + 0x20 + read-only + 0x00000000 + + + LSECSSF + LSE clock secure system interrupt flag + 9 + 1 + + + HSIRDYF + HSI ready interrupt flag + 3 + 1 + + + LSERDYF + LSE ready interrupt flag + 2 + 1 + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + LSECSSC + LSE clock secure system interrupt flag clear + 9 + 1 + + + HSIRDYC + HSI ready interrupt clear + 3 + 1 + + + LSERDYC + LSE ready interrupt clear + 1 + 1 + + + LSIRDYC + LSI ready interrupt clear + 0 + 1 + + + + + IOPRSTR + IOPRSTR + GPIO reset register + 0x24 + 0x20 + read-write + 0x00000000 + + + GPIOCRST + I/O port C reset + 2 + 1 + + + GPIOBRST + I/O port B reset + 1 + 1 + + + GPIOARST + I/O port A reset + 0 + 1 + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + CRCRST + CRC reset + 12 + 1 + + + FLASHRST + FLASH reset + 8 + 1 + + + DMARST + DMA reset + 0 + 1 + + + + + APBRSTR1 + APBRSTR1 + APB peripheral reset register 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + LPTIMRST + Low Power Timer reset + 31 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + DBGRST + Debug support reset + 27 + 1 + + + I2CRST + I2C reset + 21 + 1 + + + TIM6RST + TIM6 reset + 4 + 1 + + + + + APBRSTR2 + APBRSTR2 + APB peripheral reset register + 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + ADCRST + ADC reset + 20 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SYSCFGRST + SYSCFG and COMP + reset + 0 + 1 + + + + + IOPENR + IOPENR + GPIO clock enable register + 0x34 + 0x20 + read-write + 0x00000000 + + + GPIOCEN + I/O port C clock enable + 2 + 1 + + + GPIOBEN + I/O port B clock enable + 1 + 1 + + + GPIOAEN + I/O port A clock enable + 0 + 1 + + + + + AHBENR + AHBENR + AHB peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + CRCEN + CRC clock enable + 12 + 1 + + + SRAMEN + SRAM memory interface clock enable + 9 + 1 + + + FLASHEN + Flash memory interface clock enable + 8 + 1 + + + DMAEN + DMA interface clock enable + 0 + 1 + + + + + APBENR1 + APBENR1 + APB peripheral clock enable register + 1 + 0x3C + 0x20 + read-write + 0x00000000 + + + LPTIMEN + LPTIM clock enable + 31 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + DBGEN + Debug support clock enable + 27 + 1 + + + I2CEN + I2C clock enable + 21 + 1 + + + TIM6EN + TIM6 clock enable + 4 + 1 + + + + + APBENR2 + APBENR2 + APB peripheral clock enable register + 2 + 0x40 + 0x20 + read-write + 0x00000000 + + + ADCEN + ADC clock enable + 20 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TIM1EN + TIM1 timer clock enable + 11 + 1 + + + SYSCFGEN + SYSCFG, COMP and VREFBUF clock + enable + 0 + 1 + + + + + CCIPR + CCIPR + Peripherals independent clock configuration + register + 0x54 + 0x20 + read-write + 0x00000000 + + + LPTIM1SEL + LPTIM1 clock source + selection + 18 + 2 + + + + + BDCR + BDCR + RTC domain control register + 0x5C + 0x20 + read-write + 0x00000000 + + + LSCOSEL + + Low-speed clock output + selection + + 25 + 1 + + + LSCOEN + + Low-speed clock output (LSCO) + enable + + 24 + 1 + + + LSECSSD + LSE CSS detect + 6 + 1 + + + LSECSSON + LSE CSS enable + 5 + 1 + + + LSEBYP + LSE oscillator bypass + 2 + 1 + + + LSERDY + LSE oscillator ready + 1 + 1 + + + LSEON + LSE oscillator enable + 0 + 1 + + + + + CSR + CSR + Control/status register + 0x60 + 0x20 + read-write + 0x00000000 + + + IWDGRSTF + Independent window watchdog reset + flag + 29 + 1 + + + SFTRSTF + Software reset flag + 28 + 1 + + + PWRRSTF + BOR or POR/PDR flag + 27 + 1 + + + PINRSTF + Pin reset flag + 26 + 1 + + + OBLRSTF + Option byte loader reset + flag + 25 + 1 + + + RMVF + Remove reset flags + 23 + 1 + + + PINRST_FLTDIS + desc PINRST_FLTDIS + 8 + 1 + + + LSIRDY + LSI oscillator ready + 1 + 1 + + + LSION + LSI oscillator enable + 0 + 1 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Power control register 1 + 0x0 + 0x20 + read-write + 0x00030000 + + + HSION_CTRL + HSI open time control + 19 + 1 + + + SRAM_RETV + SRAM retention voltage control + 16 + 3 + + + LPR + Low-power run + 14 + 2 + + + FLS_SLPTIME + Flash wait time after wakeup from the stop mode + 12 + 2 + + + MRRDY_TIME + Time selection wakeup from LP to VR + 10 + 2 + + + VOS + Voltage scaling range + selection + 8 + 2 + + + DBP + Disable backup domain write + protection + 7 + 1 + + + BIAS_CR_SEL + MR Bias current selection + 4 + 1 + + + BIAS_CR + MR Bias current + 0 + 4 + + + + + CR2 + CR2 + Power control register 2 + 0x4 + 0x20 + read-write + 0x00000500 + + + FLT_TIME + Digital filter time configuration + 9 + 3 + + + FLTEN + Digital filter enable + 8 + 1 + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x50000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xEBFFFFFF + + + MODE15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + MODE14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + MODE13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + MODE12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + MODE11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + MODE10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + MODE9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + MODE8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + MODE7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + MODE6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + MODE5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + MODE4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + MODE3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + MODE2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + MODE1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + MODE0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + Port x configuration bits (y = + 0..15) + 15 + 1 + + + OT14 + Port x configuration bits (y = + 0..15) + 14 + 1 + + + OT13 + Port x configuration bits (y = + 0..15) + 13 + 1 + + + OT12 + Port x configuration bits (y = + 0..15) + 12 + 1 + + + OT11 + Port x configuration bits (y = + 0..15) + 11 + 1 + + + OT10 + Port x configuration bits (y = + 0..15) + 10 + 1 + + + OT9 + Port x configuration bits (y = + 0..15) + 9 + 1 + + + OT8 + Port x configuration bits (y = + 0..15) + 8 + 1 + + + OT7 + Port x configuration bits (y = + 0..15) + 7 + 1 + + + OT6 + Port x configuration bits (y = + 0..15) + 6 + 1 + + + OT5 + Port x configuration bits (y = + 0..15) + 5 + 1 + + + OT4 + Port x configuration bits (y = + 0..15) + 4 + 1 + + + OT3 + Port x configuration bits (y = + 0..15) + 3 + 1 + + + OT2 + Port x configuration bits (y = + 0..15) + 2 + 1 + + + OT1 + Port x configuration bits (y = + 0..15) + 1 + 1 + + + OT0 + Port x configuration bits (y = + 0..15) + 0 + 1 + + + + + OSPEEDR + OSPEEDR + GPIO port output speed + register + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEED15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + OSPEED14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + OSPEED13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + OSPEED12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + OSPEED11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + OSPEED10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + OSPEED9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + OSPEED8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + OSPEED7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + OSPEED6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + OSPEED5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + OSPEED4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + OSPEED3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + OSPEED2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + OSPEED1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + OSPEED0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + PUPDR + PUPDR + GPIO port pull-up/pull-down + register + 0xC + 0x20 + read-write + 0x24000000 + + + PUPD15 + Port x configuration bits (y = + 0..15) + 30 + 2 + + + PUPD14 + Port x configuration bits (y = + 0..15) + 28 + 2 + + + PUPD13 + Port x configuration bits (y = + 0..15) + 26 + 2 + + + PUPD12 + Port x configuration bits (y = + 0..15) + 24 + 2 + + + PUPD11 + Port x configuration bits (y = + 0..15) + 22 + 2 + + + PUPD10 + Port x configuration bits (y = + 0..15) + 20 + 2 + + + PUPD9 + Port x configuration bits (y = + 0..15) + 18 + 2 + + + PUPD8 + Port x configuration bits (y = + 0..15) + 16 + 2 + + + PUPD7 + Port x configuration bits (y = + 0..15) + 14 + 2 + + + PUPD6 + Port x configuration bits (y = + 0..15) + 12 + 2 + + + PUPD5 + Port x configuration bits (y = + 0..15) + 10 + 2 + + + PUPD4 + Port x configuration bits (y = + 0..15) + 8 + 2 + + + PUPD3 + Port x configuration bits (y = + 0..15) + 6 + 2 + + + PUPD2 + Port x configuration bits (y = + 0..15) + 4 + 2 + + + PUPD1 + Port x configuration bits (y = + 0..15) + 2 + 2 + + + PUPD0 + Port x configuration bits (y = + 0..15) + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID15 + Port input data (y = + 0..15) + 15 + 1 + + + ID14 + Port input data (y = + 0..15) + 14 + 1 + + + ID13 + Port input data (y = + 0..15) + 13 + 1 + + + ID12 + Port input data (y = + 0..15) + 12 + 1 + + + ID11 + Port input data (y = + 0..15) + 11 + 1 + + + ID10 + Port input data (y = + 0..15) + 10 + 1 + + + ID9 + Port input data (y = + 0..15) + 9 + 1 + + + ID8 + Port input data (y = + 0..15) + 8 + 1 + + + ID7 + Port input data (y = + 0..15) + 7 + 1 + + + ID6 + Port input data (y = + 0..15) + 6 + 1 + + + ID5 + Port input data (y = + 0..15) + 5 + 1 + + + ID4 + Port input data (y = + 0..15) + 4 + 1 + + + ID3 + Port input data (y = + 0..15) + 3 + 1 + + + ID2 + Port input data (y = + 0..15) + 2 + 1 + + + ID1 + Port input data (y = + 0..15) + 1 + 1 + + + ID0 + Port input data (y = + 0..15) + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD15 + Port output data (y = + 0..15) + 15 + 1 + + + OD14 + Port output data (y = + 0..15) + 14 + 1 + + + OD13 + Port output data (y = + 0..15) + 13 + 1 + + + OD12 + Port output data (y = + 0..15) + 12 + 1 + + + OD11 + Port output data (y = + 0..15) + 11 + 1 + + + OD10 + Port output data (y = + 0..15) + 10 + 1 + + + OD9 + Port output data (y = + 0..15) + 9 + 1 + + + OD8 + Port output data (y = + 0..15) + 8 + 1 + + + OD7 + Port output data (y = + 0..15) + 7 + 1 + + + OD6 + Port output data (y = + 0..15) + 6 + 1 + + + OD5 + Port output data (y = + 0..15) + 5 + 1 + + + OD4 + Port output data (y = + 0..15) + 4 + 1 + + + OD3 + Port output data (y = + 0..15) + 3 + 1 + + + OD2 + Port output data (y = + 0..15) + 2 + 1 + + + OD1 + Port output data (y = + 0..15) + 1 + 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function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR8 + Port Reset bit + 8 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR0 + Port Reset bit + 0 + 1 + + + + + + + GPIOC + 0x50000800 + + + EXTI + External interrupt/event + controller + EXTI + 0x40021800 + + 0x0 + 0x400 + registers + + + EXTI0_1 + EXTI Line 0 and 1 Interrupt + 5 + + + EXTI2_3 + EXTI Line 2 and 3 Interrupt + 6 + + + EXTI4_15 + EXTI Line 4 to 15 Interrupt + 7 + + + + RTSR + RTSR + EXTI rising trigger selection + register + 0x0 + 0x20 + read-write + 0x00000000 + + + RT7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + RT6 + Rising trigger event configuration bit + of Configurable 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DAC global Interrupts + 17 + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + ARRM + Autoreload match + 1 + 1 + + + ARROK + Autoreload match update OK + 4 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + ARRMCF + + Autoreload match Clear + Flag + + 1 + 1 + + + ARROKCF + + Autoreload match update OK + Clear Flag + + 4 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + ARRMIE + + Autoreload matchInterrupt + Enable + + 1 + 1 + + + ARROKIE + + Autoreload match update + OK Interrupt Enable + + 4 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + PRELOAD + Registers update mode + 22 + 1 + + + PRESC + Clock prescaler + 9 + 3 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + Reset after read enable + 4 + 1 + + + CNTSTRT + CNTSTRT + 2 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global Interrupt + 27 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C0 + + + ABRRQ + Automate baudrate detection requeset + 12 + 1 + write-only + + + ABRE + Automate baudrate detection error flag + 11 + 1 + read-only + + + ABRF + Automate baudrate detection flag + 10 + 1 + read-only + + + CTS + CTS flag + 9 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NE + Noise error flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE interrupt enable + 7 + 1 + + + TCIE + Transmission complete interrupt + enable + 6 + 1 + + + RXNEIE + RXNE interrupt enable + 5 + 1 + + + IDLEIE + IDLE interrupt enable + 4 + 1 + + + TE + Transmitter enable + 3 + 1 + + + RE + Receiver enable + 2 + 1 + + + RWU + Receiver wakeup + 1 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x10 + 0x20 + read-write + 0x0000 + + + STOP + STOP bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + ABRMOD + Auto baudrate mode + 13 + 2 + + + ABREN + Auto baudrate enable + 12 + 1 + + + OVER8 + Oversampling mode + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register (IWDG_KR) + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value + 0 + 16 + + + + + PR + PR + Prescaler register (IWDG_PR) + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register (IWDG_RLR) + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + + Watchdog counter reload + value + + 0 + 12 + + + + + SR + SR + Status register (IWDG_SR) + 0xC + 0x20 + read-only + 0x00000000 + + + RVU + + Watchdog counter reload value + update + + 1 + 1 + + + PVU + + Watchdog prescaler value + update + + 0 + 1 + + + + + + + TIM1 + Advanced timer + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_UP_TRG_COM + TIM1 Break, Update, Trigger and Commutation Interrupt + 13 + + + TIM1_CC + TIM1 Capture Compare Interrupt + 14 + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x0 + 0x3FF + + + CEN + desc CEN + 0 + 0 + read-write + + + UDIS + desc UDIS + 1 + 1 + read-write + + + URS + desc URS + 2 + 2 + read-write + + + OPM + desc OPM + 3 + 3 + read-write + + + DIR + desc DIR + 4 + 4 + read-write + + + CMS + desc CMS + 6 + 5 + read-write + + + ARPE + desc ARPE + 7 + 7 + read-write + + + CKD + desc CKD + 9 + 8 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + 0xF8 + + + CCDS + desc CCDS + 3 + 3 + read-write + + + MMS + desc MMS + 6 + 4 + read-write + + + TI1S + desc TI1S + 7 + 7 + read-write + + + + + SMCR + desc SMCR + 0x8 + 32 + read-write + 0x0 + 0xFFF7 + + + SMS + desc SMS + 2 + 0 + read-write + + + OCCS + desc OCCS + 3 + 3 + read-write + + + TS + desc TS + 6 + 4 + read-write + + + MSM + desc MSM + 7 + 7 + read-write + + + ETF + desc ETF + 11 + 8 + read-write + + + ETPS + desc ETPS + 13 + 12 + read-write + + + ECE + desc ECE + 14 + 14 + read-write + + + ETP + desc ETP + 15 + 15 + read-write + + + + + DIER + desc DIER + 0xC + 32 + read-write + 0x0 + 0x5F5F + + + UIE + desc UIE + 0 + 0 + read-write + + + CC1IE + desc CC1IE + 1 + 1 + read-write + + + CC2IE + desc CC2IE + 2 + 2 + read-write + + + CC3IE + desc CC3IE + 3 + 3 + read-write + + + CC4IE + desc CC4IE + 4 + 4 + read-write + + + TIE + desc TIE + 6 + 6 + read-write + + + BIE + desc BIE + 7 + 7 + read-write + + + + + SR + desc SR + 0x10 + 32 + read-write + 0x0 + 0x1E5F + + + UIF + desc UIF + 0 + 0 + read-write + + + CC1IF + desc CC1IF + 1 + 1 + read-write + + + CC2IF + desc CC2IF + 2 + 2 + read-write + + + CC3IF + desc CC3IF + 3 + 3 + read-write + + + CC4IF + desc CC4IF + 4 + 4 + read-write + + + COMIF + desc COMIF + 5 + 5 + read-write + + + TIF + desc TIF + 6 + 6 + read-write + + + BIF + desc BIF + 7 + 7 + read-write + + + CC1OF + desc CC1OF + 9 + 9 + read-write + + + CC2OF + desc CC2OF + 10 + 10 + read-write + + + CC3OF + desc CC3OF + 11 + 11 + read-write + + + CC4OF + desc CC4OF + 12 + 12 + read-write + + + IC1IR + desc IC1IR + 16 + 16 + read-write + + + IC2IR + desc IC2IR + 17 + 17 + read-write + + + IC3IR + desc IC3IR + 18 + 18 + read-write + + + IC4IR + desc IC3IR + 19 + 19 + read-write + + + IC1IF + desc IC1IF + 20 + 20 + read-write + + + IC2IF + desc IC2IF + 21 + 21 + read-write + + + IC3IF + desc IC3IF + 22 + 22 + read-write + + + IC4IF + desc IC3IF + 23 + 23 + read-write + + + + + EGR + desc EGR + 0x14 + 32 + write-only + 0x0 + 0x5F + + + UG + desc UG + 0 + 0 + write-only + + + CC1G + Capture/Compare 1 Generation + 1 + 1 + write-only + + + CC2G + desc CC2G + 2 + 2 + write-only + + + CC3G + desc CC3G + 3 + 3 + write-only + + + CC4G + desc CC4G + 4 + 4 + write-only + + + COMG + desc COMG + 5 + 5 + write-only + + + TG + desc TG + 6 + 6 + write-only + + + BG + desc BG + 7 + 7 + write-only + + + + + CCMR1_OUTPUT + desc CCMR1:OUTPUT + 0x18 + 32 + read-write + 0x0 + 0xFFFF + + + CC1S + desc CC1S + 1 + 0 + read-write + + + OC1FE + desc OC1FE + 2 + 2 + read-write + + + OC1PE + desc OC1PE + 3 + 3 + read-write + + + OC1M + desc OC1M + 6 + 4 + read-write + + + OC1CE + desc OC1CE + 7 + 7 + read-write + + + CC2S + desc CC2S + 9 + 8 + read-write + + + OC2FE + desc OC2FE + 10 + 10 + read-write + + + OC2PE + desc OC2PE + 11 + 11 + read-write + + + OC2M + desc OC2M + 14 + 12 + read-write + + + OC2CE + desc OC2CE + 15 + 15 + read-write + + + + + CCMR1_INPUT + desc CCMR1:INPUT + CCMR1_OUTPUT + 0x18 + 32 + read-write + 0x0 + 0xFFFF + + + CC1S + desc CC1S + 1 + 0 + read-write + + + IC1PSC + desc IC1PSC + 3 + 2 + read-write + + + IC1F + desc IC1F + 7 + 4 + read-write + + + CC2S + desc CC2S + 9 + 8 + read-write + + + IC2PSC + desc IC2PSC + 11 + 10 + read-write + + + IC2F + desc IC2F + 15 + 12 + read-write + + + + + CCMR2_OUTPUT + desc CCMR2:OUTPUT + 0x1C + 32 + read-write + 0x0 + 0xFFFF + + + CC3S + desc CC3S + 1 + 0 + read-write + + + OC3FE + desc OC3FE + 2 + 2 + read-write + + + OC3PE + desc OC3PE + 3 + 3 + read-write + + + OC3M + desc OC3M + 6 + 4 + read-write + + + OC3CE + desc OC3CE + 7 + 7 + read-write + + + CC4S + desc CC4S + 9 + 8 + read-write + + + OC4FE + desc OC4FE + 10 + 10 + read-write + + + OC4PE + desc OC4PE + 11 + 11 + read-write + + + OC4M + desc OC4M + 14 + 12 + read-write + + + OC4CE + desc OC4CE + 15 + 15 + read-write + + + + + CCMR2_INPUT + desc CCMR2:INPUT + CCMR2_OUTPUT + 0x1C + 32 + read-write + 0x0 + 0xFFFF + + + CC3S + desc CC3S + 1 + 0 + read-write + + + IC3PSC + desc IC3PSC + 3 + 2 + read-write + + + IC3F + desc IC3F + 7 + 4 + read-write + + + CC4S + desc CC4S + 9 + 8 + read-write + + + IC4PSC + desc IC4PSC + 11 + 10 + read-write + + + IC4F + desc IC4F + 15 + 12 + read-write + + + + + CCER + desc CCER + 0x20 + 32 + read-write + 0x0 + 0x3333 + + + CC1E + desc CC1E + 0 + 0 + read-write + + + CC1P + desc CC1P + 1 + 1 + read-write + + + CC2E + desc CC2E + 4 + 4 + read-write + + + CC2P + desc CC2P + 5 + 5 + read-write + + + CC3E + desc CC3E + 8 + 8 + read-write + + + CC3P + desc CC3P + 9 + 9 + read-write + + + CC4E + desc CC4E + 12 + 12 + read-write + + + CC4P + desc CC4P + 13 + 13 + read-write + + + + + CNT + desc CNT + 0x24 + 32 + read-write + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PSC + desc PSC + 0x28 + 32 + read-write + 0x0 + 0xFFFF + + + PSC + desc PSC + 15 + 0 + read-write + + + + + ARR + desc ARR + 0x2C + 32 + read-write + 0xFFFF + 0xFFFF + + + ARR + desc ARR + 15 + 0 + read-write + + + + + RCR + desc RCR + 0x30 + 32 + read-write + 0xFFFF + 0xFFFF + + + REP + desc REP + 7 + 0 + read-write + + + + + CCR1 + desc CCR1 + 0x34 + 32 + read-write + 0x0 + 0xFFFF + + + CCR1 + desc CCR1 + 15 + 0 + read-write + + + + + CCR2 + desc CCR2 + 0x38 + 32 + read-write + 0x0 + 0xFFFF + + + CCR2 + desc CCR2 + 15 + 0 + read-write + + + + + CCR3 + desc CCR3 + 0x3C + 32 + read-write + 0x0 + 0xFFFF + + + CCR3 + desc CCR3 + 15 + 0 + read-write + + + + + CCR4 + desc CCR4 + 0x40 + 32 + read-write + 0x0 + 0xFFFF + + + CCR4 + desc CCR4 + 15 + 0 + read-write + + + + + BDTR + desc BDTR + 0x44 + 32 + read-write + 0x0 + 0xFFFF + + + DTG + desc DTG + 7 + 0 + read-write + + + LOCK + desc LOCK + 9 + 8 + read-write + + + OSSI + desc OSSI + 10 + 10 + read-write + + + OSSR + desc OSSR + 11 + 11 + read-write + + + BKE + desc BKE + 12 + 12 + read-write + + + BKP + desc BKP + 13 + 13 + read-write + + + AOE + desc AOE + 14 + 14 + read-write + + + MOE + desc MOE + 15 + 15 + read-write + + + + + DCR + desc DCR + 0x48 + 32 + read-write + 0x0 + 0x1F1F + + + DBA + desc DBA + 4 + 0 + read-write + + + DBL + desc DBL + 12 + 8 + read-write + + + + + DMAR + desc DMAR + 0x4C + 32 + read-write + 0x0 + 0xFFFF + + + DMAB + desc DMAB + 15 + 0 + read-write + + + + + + + TIM6 + desc TIM + TIM + 0x40001000 + + 0x0 + 0x400 + registers + + + TIM6_LPTIM1_DAC + TIM6, LPTIM1, DAC global Interrupts + 17 + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x0 + 0x3FF + + + CEN + desc CEN + 0 + 0 + read-write + + + UDIS + desc UDIS + 1 + 1 + read-write + + + URS + desc URS + 2 + 2 + read-write + + + OPM + desc OPM + 3 + 3 + read-write + + + DIR + desc DIR + 4 + 4 + read-write + + + CMS + desc CMS + 6 + 5 + read-write + + + ARPE + desc ARPE + 7 + 7 + read-write + + + CKD + desc CKD + 9 + 8 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + 0xF8 + + + CCDS + desc CCDS + 3 + 3 + read-write + + + MMS + desc MMS + 6 + 4 + read-write + + + TI1S + desc TI1S + 7 + 7 + read-write + + + + + DIER + desc DIER + 0xC + 32 + read-write + 0x0 + 0x5F5F + + + UIE + desc UIE + 0 + 0 + read-write + + + CC1IE + desc CC1IE + 1 + 1 + read-write + + + CC2IE + desc CC2IE + 2 + 2 + read-write + + + CC3IE + desc CC3IE + 3 + 3 + read-write + + + CC4IE + desc CC4IE + 4 + 4 + read-write + + + TIE + desc TIE + 6 + 6 + read-write + + + UDE + desc UDE + 8 + 8 + read-write + + + CC1DE + desc CC1DE + 9 + 9 + read-write + + + CC2DE + desc CC2DE + 10 + 10 + read-write + + + CC3DE + desc CC3DE + 11 + 11 + read-write + + + CC4DE + desc CC4DE + 12 + 12 + read-write + + + TDE + desc TDE + 14 + 14 + read-write + + + + + SR + desc SR + 0x10 + 32 + read-write + 0x0 + 0x1E5F + + + UIF + desc UIF + 0 + 0 + read-write + + + CC1IF + desc CC1IF + 1 + 1 + read-write + + + CC2IF + desc CC2IF + 2 + 2 + read-write + + + CC3IF + desc CC3IF + 3 + 3 + read-write + + + CC4IF + desc CC4IF + 4 + 4 + read-write + + + COMIF + desc COMIF + 5 + 5 + read-write + + + TIF + desc TIF + 6 + 6 + read-write + + + BIF + desc BIF + 7 + 7 + read-write + + + CC1OF + desc CC1OF + 9 + 9 + read-write + + + CC2OF + desc CC2OF + 10 + 10 + read-write + + + CC3OF + desc CC3OF + 11 + 11 + read-write + + + CC4OF + desc CC4OF + 12 + 12 + read-write + + + IC1IR + desc IC1IR + 16 + 16 + read-write + + + IC2IR + desc IC2IR + 17 + 17 + read-write + + + IC3IR + desc IC3IR + 18 + 18 + read-write + + + IC4IR + desc IC3IR + 19 + 19 + read-write + + + IC1IF + desc IC1IF + 20 + 20 + read-write + + + IC2IF + desc IC2IF + 21 + 21 + read-write + + + IC3IF + desc IC3IF + 22 + 22 + read-write + + + IC4IF + desc IC3IF + 23 + 23 + read-write + + + + + EGR + desc EGR + 0x14 + 32 + write-only + 0x0 + 0x5F + + + UG + desc UG + 0 + 0 + write-only + + + CC1G + Capture/Compare 1 Generation + 1 + 1 + write-only + + + CC2G + desc CC2G + 2 + 2 + write-only + + + CC3G + desc CC3G + 3 + 3 + write-only + + + CC4G + desc CC4G + 4 + 4 + write-only + + + TG + desc TG + 6 + 6 + write-only + + + + + CNT + desc CNT + 0x24 + 32 + read-write + 0x0 + 0xFFFF + + + CNT + desc CNT + 15 + 0 + read-write + + + + + PSC + desc PSC + 0x28 + 32 + read-write + 0x0 + 0xFFFF + + + PSC + desc PSC + 15 + 0 + read-write + + + + + ARR + desc ARR + 0x2C + 32 + read-write + 0xFFFF + 0xFFFF + + + ARR + desc ARR + 15 + 0 + read-write + + + + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x30 + registers + + + + CFGR1 + CFGR1 + SYSCFG configuration register 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + I2C_PB6_FMP + desc I2C_PB6_FMP + 19 + 1 + + + I2C_PB4_FMP + desc I2C_PB4_FMP + 18 + 1 + + + I2C_PB3_FMP + desc I2C_PB3_FMP + 17 + 1 + + + I2C_PA2_FMP + desc I2C_PA2_FMP + 16 + 1 + + + MEM_MODE + Memory mapping selection bits + 0 + 2 + + + + + CFGR2 + CFGR2 + SYSCFG configuration register + 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + ETR_SRC_TIM1 + TIM1 ETR source selection + 9 + 2 + + + LOCKUP_LOCK + Cortex-M0+ LOCKUP bit enable + bit + 0 + 1 + + + + + GPIO_ENS + desc GPIO_ENS + 0x1C + 32 + read-write + 0x0 + + + PC_ENS + desc PC_ENS + 17 + 16 + read-write + + + PB_ENS + desc PB_ENS + 15 + 8 + read-write + + + PA_ENS + desc PA_ENS + 7 + 0 + read-write + + + + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH global Interrupt + 3 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 1 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEY + Flash key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + read-write + 0x00000000 + + + BSY + Busy + 16 + 1 + + + OPTVERR + Option and Engineering bits loading + validity error + 15 + 1 + + + WRPERR + Write protected error + 4 + 1 + + + EOP + End of operation + 0 + 1 + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + OBL_LAUNCH + Force the option byte + loading + 27 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + EOPIE + End of operation interrupt + enable + 24 + 1 + + + PGTSTRT + Flash main memory program start + 19 + 1 + + + OPTSTRT + Option byte program start + 17 + 1 + + + SER + Sector erase + 11 + 1 + + + MER + Mass erase + 2 + 1 + + + PER + Page erase + 1 + 1 + + + PG + Programming + 0 + 1 + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0x4F55B0AA + + + nBOOT1 + Boot configuration + 15 + 1 + + + NRST_MODE + NRST_MODE + 14 + 1 + + + WWDG_SW + Window watchdog selection + 13 + 1 + + + IWDG_SW + Independent watchdog + selection + 12 + 1 + + + BORF_LEV + These bits contain the VDD supply level + threshold that activates the reset + 9 + 3 + + + BOREN + BOR reset Level + 8 + 1 + + + RDP + Read Protection + 0 + 8 + + + + + SDKR + SDKR + Flash SDK address + register + 0x24 + 0x20 + read-write + 0xFFE0001F + + + SDK_END + SDK area end address + 8 + 4 + + + SDK_STRT + SDK area start address + 0 + 4 + + + + + BTCR + SDKR + FLASH boot control register + 0x28 + 0x20 + read-write + 0x0 + + + BOOT0 + desc BOOT0 + 15 + 1 + + + BOOT_SIZE + desc BOOT_SIZE + 0 + 3 + + + + + WRPR + WRPR + Flash WRP address + register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + WRP + WRP address + 0 + 6 + + + + + STCR + STCR + Flash sleep time config + register + 0x90 + 0x20 + read-write + 0x00006400 + + + SLEEP_TIME + FLash sleep time configuration(counter based on HSI_10M) + 8 + 8 + + + SLEEP_EN + FLash sleep enable + 0 + 1 + + + + + TS0 + TS0 + Flash TS0 + register + 0x100 + 0x20 + read-write + 0x000000B4 + + + TS0 + FLash TS0 register + 0 + 8 + + + + + TS1 + TS1 + Flash TS1 + register + 0x104 + 0x20 + read-write + 0x000001B0 + + + TS1 + FLash TS1 register + 0 + 9 + + + + + TS2P + TS2P + Flash TS2P + register + 0x108 + 0x20 + read-write + 0x000000B4 + + + TS2P + FLash TS2P register + 0 + 8 + + + + + TPS3 + TPS3 + Flash TPS3 + register + 0x10C + 0x20 + read-write + 0x000006C0 + + + TPS3 + FLash TPS3 register + 0 + 11 + + + + + TS3 + TS3 + Flash TS3 + register + 0x110 + 0x20 + read-write + 0x000000B4 + + + TS3 + FLash TS3 register + 0 + 8 + + + + + PERTPE + PERTPE + Flash PERTPE + register + 0x114 + 0x20 + read-write + 0x0000EA60 + + + PERTPE + FLash PERTPE register + 0 + 17 + + + + + SMERTPE + SMERTPE + Flash SMERTPE + register + 0x118 + 0x20 + read-write + 0x0000FD20 + + + SMERTPE + FLash SMERTPE register + 0 + 17 + + + + + PRGTPE + PRGTPE + Flash PRGTPE + register + 0x11C + 0x20 + read-write + 0x00008CA0 + + + PRGTPE + FLash PRGTPE register + 0 + 16 + + + + + PRETPE + PRETPE + Flash PRETPE + register + 0x120 + 0x20 + read-write + 0x000012C0 + + + PRETPE + FLash PRETPE register + 0 + 13 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global Interrupt + 25 + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x0 + + + CPHA + desc CPHA + 0 + 0 + read-write + + + CPOL + desc CPOL + 1 + 1 + read-write + + + MSTR + desc MSTR + 2 + 2 + read-write + + + BR + desc BR + 5 + 3 + read-write + + + SPE + desc SPE + 6 + 6 + read-write + + + LSBFIRST + desc LSBFIRST + 7 + 7 + read-write + + + SSI + desc SSI + 8 + 8 + read-write + + + SSM + desc SSM + 9 + 9 + read-write + + + RXONLY + desc RXONLY + 10 + 10 + read-write + + + DDF + desc DDF + 11 + 11 + read-write + + + CRCNEXT + desc CRCNEXT + 12 + 12 + read-write + + + CRCEN + desc CRCEN + 13 + 13 + read-write + + + BIDIOE + desc BIDIOE + 14 + 14 + read-write + + + BIDIMODE + desc BIDIMODE + 15 + 15 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + + + RXDMAEN + desc RXDMAEN + 0 + 0 + read-write + + + TXDMAEN + desc TXDMAEN + 1 + 1 + read-write + + + SSOE + desc SSOE + 2 + 2 + read-write + + + CLRTXFIFO + desc CLRTXFIFO + 4 + 4 + read-write + + + ERRIE + desc ERRIE + 5 + 5 + read-write + + + RXNEIE + desc RXNEIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + FRXTH + desc FRXTH + 12 + 12 + read-write + + + LDMA_RX + desc LDMA_RX + 13 + 13 + read-write + + + LDMA_TX + desc LDMA_TX + 14 + 14 + read-write + + + + + SR + desc SR + 0x8 + 32 + read-write + 0x2 + + + RXNE + desc RXNE + 0 + 0 + read-only + + + TXE + desc TXE + 1 + 1 + read-only + + + CHSIDE + desc CHSIDE + 2 + 2 + read-only + + + UDR + desc UDR + 3 + 3 + read-only + + + CRCERR + desc CRCERR + 4 + 4 + read-write + + + MODF + desc MODF + 5 + 5 + read-only + + + OVR + desc OVR + 6 + 6 + read-only + + + BSY + desc BSY + 7 + 7 + read-only + + + FRLVL + desc FRLVL + 10 + 9 + read-only + + + FTLVL + desc FTLVL + 12 + 11 + read-only + + + + + DR + desc DR + 0xC + 32 + read-write + 0x0 + + + DR + desc DR + 15 + 0 + read-write + + + + + CRCPR + desc CRCPR + 0x10 + 32 + read-write + 0x7 + + + CRCPOLY + desc CRCPOLY + 15 + 0 + read-write + + + + + RXCRCR + desc RXCRCR + 0x14 + 32 + read-only + 0x0 + + + RXCRC + desc RXCRC + 15 + 0 + read-only + + + + + TXCRCR + desc TXCRCR + 0x18 + 32 + read-only + 0x0 + + + TXCRC + desc TXCRC + 15 + 0 + read-only + + + + + I2SCFGR + desc I2SCFGR + 0x1C + 32 + read-write + 0x0 + + + CHLEN + desc CHLEN + 0 + 0 + read-write + + + DATLEN + desc DATLEN + 2 + 1 + read-write + + + CKPOL + desc CKPOL + 3 + 3 + read-write + + + I2SSTD + desc I2SSTD + 5 + 4 + read-write + + + PCMSYNC + desc PCMSYNC + 7 + 7 + read-write + + + I2SCFG + desc I2SCFG + 9 + 8 + read-write + + + I2SE + desc I2SE + 10 + 10 + read-write + + + I2SMOD + desc I2SMOD + 11 + 11 + read-write + + + + + I2SPR + desc I2SPR + 0x20 + 32 + read-write + 0x2 + + + I2SDIV + desc I2SDIV + 7 + 0 + read-write + + + ODD + desc ODD + 8 + 8 + read-write + + + MCKOE + desc MCKOE + 9 + 9 + read-write + + + + + + + I2C + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 global Interrupt + 23 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for datareception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slavemode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADD + Interface address + 1 + 7 + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DR + 8-bit data register + 0 + 8 + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (mastermode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty(transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty(receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slavemode) + 4 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched(slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checkingregister + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + GENCALL + General call address (Slavemode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standardmode (Master mode) + 0 + 12 + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode(Master mode) + 0 + 6 + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + REV_ID + REV_ID + 0 + 32 + + + + + CR + CR + Debug MCU Configuration Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + + + APB_FZ1 + APB_FZ1 + APB Freeze Register1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIM6_STOP + Debug TIM 6 stopped whenCore is halted + 4 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped whenCore is halted + 12 + 1 + + + DBG_I2C1_TIMEOUT + Debug I2C1 TIMEOUT stopped when Core ishalted + 21 + 1 + + + DBG_LPTIM_STOP + Debug LPTIM stopped when Core ishalted + 31 + 1 + + + + + APB_FZ2 + APB_FZ2 + APB Freeze Register2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIMER1_STOP + Debug Timer 1 stopped when Core ishalted + 11 + 1 + + + + + + + diff --git a/Misc/py32f003xx.svd b/Misc/SVD/py32f003xx.svd similarity index 96% rename from Misc/py32f003xx.svd rename to Misc/SVD/py32f003xx.svd index bb98bc6..f683f8c 100644 --- a/Misc/py32f003xx.svd +++ b/Misc/SVD/py32f003xx.svd @@ -1,11089 +1,11089 @@ - - - - Puya - Puya - PY32F0xx_DFP - - PY32F0 - 1.0.0 - Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. - - - - CM0+ - r0p1 - little - false - false - 4 - false - - - - 8 - 32 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ADC - Analog to Digital Converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC_COMP - ADC and COMP Interrupt through EXTI Lines 17 and 18 - 12 - - - - ISR - ISR - ADC interrupt and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - AWD - ADC analog watchdog flag - 7 - 1 - - - OVR - ADC group regular overrun - flag - 4 - 1 - - - EOSEQ - ADC group regular end of sequence - conversions flag - 3 - 1 - - - EOC - ADC group regular end of unitary - conversion flag - 2 - 1 - - - EOSMP - ADC group regular end of sampling - flag - 1 - 1 - - - - - IER - IER - ADC interrupt enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - AWDIE - ADC analog watchdog - interrupt - 7 - 1 - - - OVRIE - ADC group regular overrun - interrupt - 4 - 1 - - - EOSEQIE - ADC group regular end of sequence - conversions interrupt - 3 - 1 - - - EOCIE - ADC group regular end of unitary - conversion interrupt - 2 - 1 - - - EOSMPIE - ADC group regular end of sampling - interrupt - 1 - 1 - - - - - CR - CR - ADC control register - 0x8 - 0x20 - read-write - 0x00000000 - - - ADCAL - ADC group regular conversion - calibration - 31 - 1 - - - ADSTP - ADC group regular conversion - stop - 4 - 1 - - - ADSTART - ADC group regular conversion - start - 2 - 1 - - - ADEN - ADC enable - 0 - 1 - - - - - CFGR1 - CFGR1 - ADC configuration register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - AWDCH - ADC analog watchdog monitored channel - selection - 26 - 4 - - - AWDEN - ADC analog watchdog enable on scope - ADC group regular - 23 - 1 - - - AWDSGL - ADC analog watchdog monitoring a - single channel or all channels - 22 - 1 - - - DISCEN - ADC group regular sequencer - discontinuous mode - 16 - 1 - - - WAIT - Wait conversion mode - 14 - 1 - - - CONT - ADC group regular continuous conversion - mode - 13 - 1 - - - OVRMOD - ADC group regular overrun - configuration - 12 - 1 - - - EXTEN - ADC group regular external trigger - polarity - 10 - 2 - - - EXTSEL - ADC group regular external trigger - source - 6 - 3 - - - ALIGN - ADC data alignement - 5 - 1 - - - RESSEL - ADC data resolution - 3 - 2 - - - SCANDIR - Scan sequence direction - 2 - 1 - - - DMACFG - ADC DMA transfer - configuration - 1 - 1 - - - DMAEN - ADC DMA transfer enable - 0 - 1 - - - - - CFGR2 - CFGR2 - ADC configuration register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CKMODE - ADC clock mode - 28 - 4 - - - - - SMPR - SMPR - ADC sampling time register - 0x14 - 0x20 - read-write - 0x00000000 - - - SMP - Sampling time selection - 0 - 3 - - - - - TR - TR - ADC analog watchdog 1 threshold register - 0x20 - 0x20 - read-write - 0x0FFF0000 - - - HT - ADC analog watchdog threshold - high - 16 - 12 - - - LT - ADC analog watchdog threshold - low - 0 - 12 - - - - - CHSELR - CHSELR - ADC group regular sequencer register - 0x28 - 0x20 - read-write - 0x0FFF0000 - - - CHSEL12 - Channel-12 selection - 12 - 1 - - - CHSEL11 - Channel-11 selection - 11 - 1 - - - CHSEL9 - Channel-9 selection - 9 - 1 - - - CHSEL8 - Channel-8 selection - 8 - 1 - - - CHSEL7 - Channel-7 selection - 7 - 1 - - - CHSEL6 - Channel-6 selection - 6 - 1 - - - CHSEL5 - Channel-5 selection - 5 - 1 - - - CHSEL4 - Channel-4 selection - 4 - 1 - - - CHSEL3 - Channel-3 selection - 3 - 1 - - - CHSEL2 - Channel-2 selection - 2 - 1 - - - CHSEL1 - Channel-1 selection - 1 - 1 - - - CHSEL0 - Channel-0 selection - 0 - 1 - - - - - DR - DR - ADC group regular data register - 0x40 - 0x20 - read-only - 0x00000000 - - - DATA - ADC group regular conversion - data - 0 - 16 - - - - - CCSR - CCSR - ADC calibration configuration and status register - 0x44 - 0x20 - read-write - 0x00000000 - - - CALON - Calibration flag - 31 - 1 - read-only - - - CALFAIL - Calibration fail flag - 30 - 1 - - - CALSET - Calibration factor selection - 15 - 1 - - - CALSMP - Calibration sample time selection - 12 - 2 - - - CALSEL - Calibration contents selection - 11 - 1 - - - - - CALRR1 - CALRR1 - ADC calibration result register 1 - 0x48 - 0x20 - read-only - 0x00000000 - - - CALBOUT - offset result - 16 - 7 - - - CALC5OUT - C5 result - 8 - 8 - - - CALC4OUT - C4 result - 0 - 8 - - - - - CALRR2 - CALRR2 - ADC calibration result register 2 - 0x4C - 0x20 - read-only - 0x00000000 - - - CALC3OUT - C3 result - 24 - 8 - - - CALC2OUT - C2 result - 16 - 8 - - - CALC1OUT - C1 result - 8 - 8 - - - CALC0OUT - C0 result - 0 - 8 - - - - - CALFIR1 - CALFIR1 - ADC calibration factor input register 1 - 0x50 - 0x20 - read-write - 0x00000000 - - - CALBIO - Calibration offset factor input - 16 - 7 - - - CALC5IO - Calibration C5 factor input - 8 - 8 - - - CALC4IO - Calibration C4 factor input - 0 - 8 - - - - - CALFIR2 - CALFIR2 - ADC calibration factor input register 2 - 0x54 - 0x20 - read-write - 0x00000000 - - - CALC3IO - Calibration C3 factor input - 24 - 8 - - - CALC2IO - Calibration C2 factor input - 16 - 8 - - - CALC1IO - Calibration C1 factor input - 8 - 8 - - - CALC0IO - Calibration C0 factor input - 0 - 8 - - - - - CCR - CCR - ADC common configuration register - 0x308 - 0x20 - read-write - 0x00000000 - - - TSEN - Temperature sensor enable - 23 - 1 - - - VREFEN - VREFINT enable - 22 - 1 - - - - - - - COMP1 - Comparator - COMP - 0x40010200 - - 0x0 - 0x10 - registers - - - - CSR - CSR - COMP control and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - LOCK - CSR register lock - 31 - 1 - - - COMP_OUT - Comparator output status - 30 - 1 - - - PWRMODE - Comparator power mode - selector - 18 - 2 - - - HYST - Comparator hysteresis enable - selector - 16 - 1 - - - POLARITY - Comparator polarity - selector - 15 - 1 - - - WINMODE - Comparator non-inverting input - selector for window mode - 11 - 1 - - - INPSEL - Comparator signal selector for - non-inverting input - 8 - 2 - - - INMSEL - Comparator signal selector for - inverting input INM - 4 - 4 - - - SCALER_EN - SCALER enable bit - 1 - 1 - - - COMP_EN - COMP enable bit - 0 - 1 - - - - - FR - FR - Comparator Filter - register - 0x4 - 0x20 - read-write - 0x00000000 - - - FLTCNT - Comparator filter and counter - 16 - 16 - - - FLTEN - Filter enable bit - 0 - 1 - - - - - - - COMP2 - Comparator - COMP - 0x40010210 - - 0x0 - 0x10 - registers - - - - CSR - CSR - COMP control and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - LOCK - CSR register lock - 31 - 1 - - - COMP_OUT - Comparator output status - 30 - 1 - - - PWRMODE - Comparator power mode - selector - 18 - 2 - - - POLARITY - Comparator polarity - selector - 15 - 1 - - - WINMODE - Comparator non-inverting input - selector for window mode - 11 - 1 - - - INPSEL - Comparator signal selector for - non-inverting input - 8 - 2 - - - INMSEL - Comparator signal selector for - inverting input INM - 4 - 4 - - - COMP_EN - COMP enable bit - 0 - 1 - - - - - FR - FR - Comparator Filter - register - 0x4 - 0x20 - read-write - 0x00000000 - - - FLTCNT - Comparator filter and counter - 16 - 16 - - - FLTEN - Filter enable bit - 0 - 1 - - - - - - - RCC - Reset and clock control - RCC - 0x40021000 - - 0x0 - 0x400 - registers - - - RCC - RCC global Interrupt - 4 - - - - CR - CR - Clock control register - 0x0 - 0x20 - read-write - 0x00000100 - - - CSSON - Clock security system - enable - 19 - 1 - - - HSEBYP - HSE crystal oscillator - bypass - 18 - 1 - - - HSERDY - HSE clock ready flag - 17 - 1 - - - HSEON - HSE clock enable - 16 - 1 - - - HSIDIV - HSI16 clock division - factor - 11 - 3 - - - HSIRDY - HSI16 clock ready flag - 10 - 1 - - - HSIKERON - HSI16 always enable for peripheral - kernels - 9 - 1 - - - HSION - HSI16 clock enable - 8 - 1 - - - - - ICSCR - ICSCR - Internal clock sources calibration - register - 0x4 - 0x20 - 0x10000000 - - - LSI_STARTUP - LSI startup time - 26 - 2 - read-write - - - LSI_TRIM - LSI clock trimming - 16 - 9 - read-write - - - HSI_FS - HSI frequency selection - 13 - 3 - read-write - - - HSI_TRIM - HSI clock trimming - 0 - 13 - read-write - - - - - CFGR - CFGR - Clock configuration register - 0x8 - 0x20 - 0x00000000 - - - MCOPRE - Microcontroller clock output - prescaler - 28 - 3 - read-write - - - MCOSEL - Microcontroller clock - output - 24 - 3 - read-write - - - PPRE - APB prescaler - 12 - 3 - read-write - - - HPRE - AHB prescaler - 8 - 4 - read-write - - - SWS - System clock switch status - 3 - 3 - read-only - - - SW - System clock switch - 0 - 3 - read-write - - - - - ECSCR - ECSCR - External clock source control register - 0x10 - 0x20 - 0x00000000 - - - HSE_FREQ - HSE clock freqency selection - 2 - 2 - read-write - - - - - CIER - CIER - Clock interrupt enable - register - 0x18 - 0x20 - read-write - 0x00000000 - - - HSERDYIE - HSE ready interrupt enable - 4 - 1 - - - HSIRDYIE - HSI ready interrupt enable - 3 - 1 - - - LSIRDYIE - LSI ready interrupt enable - 0 - 1 - - - - - CIFR - CIFR - Clock interrupt flag register - 0x1C - 0x20 - read-only - 0x00000000 - - - CSSF - HSE clock secure system interrupt flag - 8 - 1 - - - HSERDYF - HSE ready interrupt flag - 4 - 1 - - - HSIRDYF - HSI ready interrupt flag - 3 - 1 - - - LSIRDYF - LSI ready interrupt flag - 0 - 1 - - - - - CICR - CICR - Clock interrupt clear register - 0x20 - 0x20 - write-only - 0x00000000 - - - CSSC - clock secure system interrupt flag clear - 8 - 1 - - - HSERDYC - HSE ready interrupt clear - 4 - 1 - - - HSIRDYC - HSI ready interrupt clear - 3 - 1 - - - LSIRDYC - LSI ready interrupt clear - 0 - 1 - - - - - IOPRSTR - IOPRSTR - GPIO reset register - 0x24 - 0x20 - read-write - 0x00000000 - - - GPIOFRST - I/O port F reset - 5 - 1 - - - GPIOBRST - I/O port B reset - 1 - 1 - - - GPIOARST - I/O port A reset - 0 - 1 - - - - - AHBRSTR - AHBRSTR - AHB peripheral reset register - 0x28 - 0x20 - read-write - 0x00000000 - - - CRCRST - CRC reset - 12 - 1 - - - DMARST - DMA reset - 0 - 1 - - - - - APBRSTR1 - APBRSTR1 - APB peripheral reset register - 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - LPTIMRST - Low Power Timer reset - 31 - 1 - - - PWRRST - Power interface reset - 28 - 1 - - - DBGRST - Debug support reset - 27 - 1 - - - I2CRST - I2C reset - 21 - 1 - - - USART2RST - USART2 reset - 17 - 1 - - - TIM3RST - TIM3 timer reset - 1 - 1 - - - - - APBRSTR2 - APBRSTR2 - APB peripheral reset register - 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - COMP2RST - COMP2 reset - 22 - 1 - - - COMP1RST - COMP1 reset - 21 - 1 - - - ADCRST - ADC reset - 20 - 1 - - - TIM17RST - TIM17 timer reset - 18 - 1 - - - TIM16RST - TIM16 timer reset - 17 - 1 - - - TIM14RST - TIM14 timer reset - 15 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - TIM1RST - TIM1 timer reset - 11 - 1 - - - SYSCFGRST - SYSCFG and COMP - reset - 0 - 1 - - - - - IOPENR - IOPENR - GPIO clock enable register - 0x34 - 0x20 - read-write - 0x00000000 - - - GPIOFEN - I/O port F clock enable - 5 - 1 - - - GPIOBEN - I/O port B clock enable - 1 - 1 - - - GPIOAEN - I/O port A clock enable - 0 - 1 - - - - - AHBENR - AHBENR - AHB peripheral clock enable - register - 0x38 - 0x20 - read-write - 0x00000000 - - - CRCEN - CRC clock enable - 12 - 1 - - - SRAMEN - SRAM memory interface clock - enable - 9 - 1 - - - FLASHEN - Flash memory interface clock - enable - 8 - 1 - - - DMAEN - DMA clock enable - 0 - 1 - - - - - APBENR1 - APBENR1 - APB peripheral clock enable register - 1 - 0x3C - 0x20 - read-write - 0x00000000 - - - LPTIMEN - LPTIM clock enable - 31 - 1 - - - PWREN - Power interface clock - enable - 28 - 1 - - - DBGEN - Debug support clock enable - 27 - 1 - - - I2CEN - I2C clock enable - 21 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - WWDGEN - WWDG clock enable - 11 - 1 - - - RTCAPBEN - RTC APB clock enable - 10 - 1 - - - TIM3EN - TIM3 timer clock enable - 1 - 1 - - - - - APBENR2 - APBENR2 - APB peripheral clock enable register - 2 - 0x40 - 0x20 - read-write - 0x00000000 - - - COMP2EN - COMP2 clock enable - 22 - 1 - - - COMP1EN - COMP1 clock enable - 21 - 1 - - - ADCEN - ADC clock enable - 20 - 1 - - - TIM17EN - TIM16 timer clock enable - 18 - 1 - - - TIM16EN - TIM16 timer clock enable - 17 - 1 - - - TIM14EN - TIM14 timer clock enable - 15 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - TIM1EN - TIM1 timer clock enable - 11 - 1 - - - SYSCFGEN - SYSCFG, COMP and VREFBUF clock - enable - 0 - 1 - - - - - CCIPR - CCIPR - Peripherals independent clock configuration - register - 0x54 - 0x20 - read-write - 0x00000000 - - - LPTIM1SEL - LPTIM1 clock source - selection - 18 - 2 - - - COMP2SEL - COMP2 clock source - selection - 9 - 1 - - - COMP1SEL - COMP1 clock source - selection - 8 - 1 - - - PVDSEL - PVD detect clock source - selection - 7 - 1 - - - - - BDCR - BDCR - RTC domain control register - 0x5C - 0x20 - read-write - 0x00000000 - - - LSCOSEL - Low-speed clock output - selection - 25 - 1 - - - LSCOEN - Low-speed clock output (LSCO) - enable - 24 - 1 - - - BDRST - RTC domain software reset - 16 - 1 - - - RTCEN - RTC clock source enable - 15 - 1 - - - RTCSEL - RTC clock source selection - 8 - 2 - - - - - CSR - CSR - Control/status register - 0x60 - 0x20 - read-write - 0x00000000 - - - WWDGRSTF - Window watchdog reset flag - 30 - 1 - - - IWDGRSTF - Independent window watchdog reset - flag - 29 - 1 - - - SFTRSTF - Software reset flag - 28 - 1 - - - PWRRSTF - BOR or POR/PDR flag - 27 - 1 - - - PINRSTF - Pin reset flag - 26 - 1 - - - OBLRSTF - Option byte loader reset - flag - 25 - 1 - - - RMVF - Remove reset flags - 23 - 1 - - - LSIRDY - LSI oscillator ready - 1 - 1 - - - LSION - LSI oscillator enable - 0 - 1 - - - - - - - PWR - Power control - PWR - 0x40007000 - - 0x0 - 0x400 - registers - - - - CR1 - CR1 - Power control register 1 - 0x0 - 0x20 - read-write - 0x00030000 - - - HSION_CTRL - HSI open time control - 19 - 1 - - - SRAM_RETV - SRAM retention voltage control - 16 - 3 - - - LPR - Low-power run - 14 - 1 - - - FLS_SLPTIME - Flash wait time after wakeup from the stop mode - 12 - 2 - - - MRRDY_TIME - Time selection wakeup from LP to VR - 10 - 2 - - - VOS - Voltage scaling range - selection - 9 - 1 - - - DBP - Disable backup domain write - protection - 8 - 1 - - - BIAS_CR_SEL - MR Bias current selection - 4 - 1 - - - BIAS_CR - MR Bias current - 0 - 4 - - - - - CR2 - CR2 - Power control register 2 - 0x4 - 0x20 - read-write - 0x00000500 - - - FLT_TIME - Digital filter time configuration - 9 - 3 - - - FLTEN - Digital filter enable - 8 - 1 - - - PVDT - Power voltage detector threshold - selection - 4 - 3 - - - SRCSEL - Power voltage detector volatage - selection - 2 - 1 - - - PVDE - Power voltage detector - enable - 0 - 1 - - - - - SR - SR - Power status register - 0x14 - 0x20 - read-only - 0x00000000 - - - PVDO - PVD output - 11 - 1 - - - - - - - GPIOA - General-purpose I/Os - GPIO - 0x50000000 - - 0x0 - 0x400 - registers - - - - MODER - MODER - GPIO port mode register - 0x0 - 0x20 - read-write - 0xEBFFFFFF - - - MODE15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - MODE14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - MODE13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - MODE12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - MODE11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - MODE10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - MODE9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - MODE8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - MODE7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - MODE6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - MODE5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - MODE4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - MODE3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - MODE2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - MODE1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - MODE0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - OTYPER - OTYPER - GPIO port output type register - 0x4 - 0x20 - read-write - 0x00000000 - - - OT15 - Port x configuration bits (y = - 0..15) - 15 - 1 - - - OT14 - Port x configuration bits (y = - 0..15) - 14 - 1 - - - OT13 - Port x configuration bits (y = - 0..15) - 13 - 1 - - - OT12 - Port x configuration bits (y = - 0..15) - 12 - 1 - - - OT11 - Port x configuration bits (y = - 0..15) - 11 - 1 - - - OT10 - Port x configuration bits (y = - 0..15) - 10 - 1 - - - OT9 - Port x configuration bits (y = - 0..15) - 9 - 1 - - - OT8 - Port x configuration bits (y = - 0..15) - 8 - 1 - - - OT7 - Port x configuration bits (y = - 0..15) - 7 - 1 - - - OT6 - Port x configuration bits (y = - 0..15) - 6 - 1 - - - OT5 - Port x configuration bits (y = - 0..15) - 5 - 1 - - - OT4 - Port x configuration bits (y = - 0..15) - 4 - 1 - - - OT3 - Port x configuration bits (y = - 0..15) - 3 - 1 - - - OT2 - Port x configuration bits (y = - 0..15) - 2 - 1 - - - OT1 - Port x configuration bits (y = - 0..15) - 1 - 1 - - - OT0 - Port x configuration bits (y = - 0..15) - 0 - 1 - - - - - OSPEEDR - OSPEEDR - GPIO port output speed - register - 0x8 - 0x20 - read-write - 0x0C000000 - - - OSPEED15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - OSPEED14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - OSPEED13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - OSPEED12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - OSPEED11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - OSPEED10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - OSPEED9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - OSPEED8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - OSPEED7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - OSPEED6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - OSPEED5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - OSPEED4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - OSPEED3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - OSPEED2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - OSPEED1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - OSPEED0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - PUPDR - PUPDR - GPIO port pull-up/pull-down - register - 0xC - 0x20 - read-write - 0x24000000 - - - PUPD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - PUPD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - PUPD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - PUPD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - PUPD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - PUPD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - PUPD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - PUPD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - PUPD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - PUPD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - PUPD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - PUPD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - PUPD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - PUPD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - PUPD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - PUPD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - IDR - IDR - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ID15 - Port input data (y = - 0..15) - 15 - 1 - - - ID14 - Port input data (y = - 0..15) - 14 - 1 - - - ID13 - Port input data (y = - 0..15) - 13 - 1 - - - ID12 - Port input data (y = - 0..15) - 12 - 1 - - - ID11 - Port input data (y = - 0..15) - 11 - 1 - - - ID10 - Port input data (y = - 0..15) - 10 - 1 - - - ID9 - Port input data (y = - 0..15) - 9 - 1 - - - ID8 - Port input data (y = - 0..15) - 8 - 1 - - - ID7 - Port input data (y = - 0..15) - 7 - 1 - - - ID6 - Port input data (y = - 0..15) - 6 - 1 - - - ID5 - Port input data (y = - 0..15) - 5 - 1 - - - ID4 - Port input data (y = - 0..15) - 4 - 1 - - - ID3 - Port input data (y = - 0..15) - 3 - 1 - - - ID2 - Port input data (y = - 0..15) - 2 - 1 - - - ID1 - Port input data (y = - 0..15) - 1 - 1 - - - ID0 - Port input data (y = - 0..15) - 0 - 1 - - - - - ODR - ODR - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OD15 - Port output data (y = - 0..15) - 15 - 1 - - - OD14 - Port output data (y = - 0..15) - 14 - 1 - - - OD13 - Port output data (y = - 0..15) - 13 - 1 - - - OD12 - Port output data (y = - 0..15) - 12 - 1 - - - OD11 - Port output data (y = - 0..15) - 11 - 1 - - - OD10 - Port output data (y = - 0..15) - 10 - 1 - - - OD9 - Port output data (y = - 0..15) - 9 - 1 - - - OD8 - Port output data (y = - 0..15) - 8 - 1 - - - OD7 - Port output data (y = - 0..15) - 7 - 1 - - - OD6 - Port output data (y = - 0..15) - 6 - 1 - - - OD5 - Port output data (y = - 0..15) - 5 - 1 - - - OD4 - Port output data (y = - 0..15) - 4 - 1 - - - OD3 - Port output data (y = - 0..15) - 3 - 1 - - - OD2 - Port output data (y = - 0..15) - 2 - 1 - - - OD1 - Port output data (y = - 0..15) - 1 - 1 - - - OD0 - Port output data (y = - 0..15) - 0 - 1 - - - - - BSRR - BSRR - GPIO port bit set/reset - register - 0x18 - 0x20 - write-only - 0x00000000 - - - BR15 - Port x reset bit y (y = - 0..15) - 31 - 1 - - - BR14 - Port x reset bit y (y = - 0..15) - 30 - 1 - - - BR13 - Port x reset bit y (y = - 0..15) - 29 - 1 - - - BR12 - Port x reset bit y (y = - 0..15) - 28 - 1 - - - BR11 - Port x reset bit y (y = - 0..15) - 27 - 1 - - - BR10 - Port x reset bit y (y = - 0..15) - 26 - 1 - - - BR9 - Port x reset bit y (y = - 0..15) - 25 - 1 - - - BR8 - Port x reset bit y (y = - 0..15) - 24 - 1 - - - BR7 - Port x reset bit y (y = - 0..15) - 23 - 1 - - - BR6 - Port x reset bit y (y = - 0..15) - 22 - 1 - - - BR5 - Port x reset bit y (y = - 0..15) - 21 - 1 - - - BR4 - Port x reset bit y (y = - 0..15) - 20 - 1 - - - BR3 - Port x reset bit y (y = - 0..15) - 19 - 1 - - - BR2 - Port x reset bit y (y = - 0..15) - 18 - 1 - - - BR1 - Port x reset bit y (y = - 0..15) - 17 - 1 - - - BR0 - Port x set bit y (y= - 0..15) - 16 - 1 - - - BS15 - Port x set bit y (y= - 0..15) - 15 - 1 - - - BS14 - Port x set bit y (y= - 0..15) - 14 - 1 - - - BS13 - Port x set bit y (y= - 0..15) - 13 - 1 - - - BS12 - Port x set bit y (y= - 0..15) - 12 - 1 - - - BS11 - Port x set bit y (y= - 0..15) - 11 - 1 - - - BS10 - Port x set bit y (y= - 0..15) - 10 - 1 - - - BS9 - Port x set bit y (y= - 0..15) - 9 - 1 - - - BS8 - Port x set bit y (y= - 0..15) - 8 - 1 - - - BS7 - Port x set bit y (y= - 0..15) - 7 - 1 - - - BS6 - Port x set bit y (y= - 0..15) - 6 - 1 - - - BS5 - Port x set bit y (y= - 0..15) - 5 - 1 - - - BS4 - Port x set bit y (y= - 0..15) - 4 - 1 - - - BS3 - Port x set bit y (y= - 0..15) - 3 - 1 - - - BS2 - Port x set bit y (y= - 0..15) - 2 - 1 - - - BS1 - Port x set bit y (y= - 0..15) - 1 - 1 - - - BS0 - Port x set bit y (y= - 0..15) - 0 - 1 - - - - - LCKR - LCKR - GPIO port configuration lock - register - 0x1C - 0x20 - read-write - 0x00000000 - - - LCKK - Port x lock bit y (y= - 0..15) - 16 - 1 - - - LCK15 - Port x lock bit y (y= - 0..15) - 15 - 1 - - - LCK14 - Port x lock bit y (y= - 0..15) - 14 - 1 - - - LCK13 - Port x lock bit y (y= - 0..15) - 13 - 1 - - - LCK12 - Port x lock bit y (y= - 0..15) - 12 - 1 - - - LCK11 - Port x lock bit y (y= - 0..15) - 11 - 1 - - - LCK10 - Port x lock bit y (y= - 0..15) - 10 - 1 - - - LCK9 - Port x lock bit y (y= - 0..15) - 9 - 1 - - - LCK8 - Port x lock bit y (y= - 0..15) - 8 - 1 - - - LCK7 - Port x lock bit y (y= - 0..15) - 7 - 1 - - - LCK6 - Port x lock bit y (y= - 0..15) - 6 - 1 - - - LCK5 - Port x lock bit y (y= - 0..15) - 5 - 1 - - - LCK4 - Port x lock bit y (y= - 0..15) - 4 - 1 - - - LCK3 - Port x lock bit y (y= - 0..15) - 3 - 1 - - - LCK2 - Port x lock bit y (y= - 0..15) - 2 - 1 - - - LCK1 - Port x lock bit y (y= - 0..15) - 1 - 1 - - - LCK0 - Port x lock bit y (y= - 0..15) - 0 - 1 - - - - - AFRL - AFRL - GPIO alternate function low - register - 0x20 - 0x20 - read-write - 0x00000000 - - - AFSEL7 - Alternate function selection for port x - bit y (y = 0..7) - 28 - 4 - - - AFSEL6 - Alternate function selection for port x - bit y (y = 0..7) - 24 - 4 - - - AFSEL5 - Alternate function selection for port x - bit y (y = 0..7) - 20 - 4 - - - AFSEL4 - Alternate function selection for port x - bit y (y = 0..7) - 16 - 4 - - - AFSEL3 - Alternate function selection for port x - bit y (y = 0..7) - 12 - 4 - - - AFSEL2 - Alternate function selection for port x - bit y (y = 0..7) - 8 - 4 - - - AFSEL1 - Alternate function selection for port x - bit y (y = 0..7) - 4 - 4 - - - AFSEL0 - Alternate function selection for port x - bit y (y = 0..7) - 0 - 4 - - - - - AFRH - AFRH - GPIO alternate function high - register - 0x24 - 0x20 - read-write - 0x00000000 - - - AFSEL15 - Alternate function selection for port x - bit y (y = 8..15) - 28 - 4 - - - AFSEL14 - Alternate function selection for port x - bit y (y = 8..15) - 24 - 4 - - - AFSEL13 - Alternate function selection for port x - bit y (y = 8..15) - 20 - 4 - - - AFSEL12 - Alternate function selection for port x - bit y (y = 8..15) - 16 - 4 - - - AFSEL11 - Alternate function selection for port x - bit y (y = 8..15) - 12 - 4 - - - AFSEL10 - Alternate function selection for port x - bit y (y = 8..15) - 8 - 4 - - - AFSEL9 - Alternate function selection for port x - bit y (y = 8..15) - 4 - 4 - - - AFSEL8 - Alternate function selection for port x - bit y (y = 8..15) - 0 - 4 - - - - - BRR - BRR - port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - BR15 - Port Reset bit - 15 - 1 - - - BR14 - Port Reset bit - 14 - 1 - - - BR13 - Port Reset bit - 13 - 1 - - - BR12 - Port Reset bit - 12 - 1 - - - BR11 - Port Reset bit - 11 - 1 - - - BR10 - Port Reset bit - 10 - 1 - - - BR9 - Port Reset bit - 9 - 1 - - - BR8 - Port Reset bit - 8 - 1 - - - BR7 - Port Reset bit - 7 - 1 - - - BR6 - Port Reset bit - 6 - 1 - - - BR5 - Port Reset bit - 5 - 1 - - - BR4 - Port Reset bit - 4 - 1 - - - BR3 - Port Reset bit - 3 - 1 - - - BR2 - Port Reset bit - 2 - 1 - - - BR1 - Port Reset bit - 1 - 1 - - - BR0 - Port Reset bit - 0 - 1 - - - - - - - GPIOB - General-purpose I/Os - GPIO - 0x50000400 - - 0x0 - 0x400 - registers - - - - MODER - MODER - GPIO port mode register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - MODE8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - MODE7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - MODE6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - MODE5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - MODE4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - MODE3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - MODE2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - MODE1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - MODE0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - OTYPER - OTYPER - GPIO port output type register - 0x4 - 0x20 - read-write - 0x00000000 - - - OT8 - Port x configuration bits (y = - 0..15) - 8 - 1 - - - OT7 - Port x configuration bits (y = - 0..15) - 7 - 1 - - - OT6 - Port x configuration bits (y = - 0..15) - 6 - 1 - - - OT5 - Port x configuration bits (y = - 0..15) - 5 - 1 - - - OT4 - Port x configuration bits (y = - 0..15) - 4 - 1 - - - OT3 - Port x configuration bits (y = - 0..15) - 3 - 1 - - - OT2 - Port x configuration bits (y = - 0..15) - 2 - 1 - - - OT1 - Port x configuration bits (y = - 0..15) - 1 - 1 - - - OT0 - Port x configuration bits (y = - 0..15) - 0 - 1 - - - - - OSPEEDR - OSPEEDR - GPIO port output speed - register - 0x8 - 0x20 - read-write - 0x00000000 - - - OSPEED8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - OSPEED7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - OSPEED6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - OSPEED5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - OSPEED4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - OSPEED3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - OSPEED2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - OSPEED1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - OSPEED0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - PUPDR - PUPDR - GPIO port pull-up/pull-down - register - 0xC - 0x20 - read-write - 0x00000000 - - - PUPD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - PUPD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - PUPD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - PUPD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - PUPD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - PUPD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - PUPD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - PUPD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - PUPD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - IDR - IDR - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ID8 - Port input data (y = - 0..15) - 8 - 1 - - - ID7 - Port input data (y = - 0..15) - 7 - 1 - - - ID6 - Port input data (y = - 0..15) - 6 - 1 - - - ID5 - Port input data (y = - 0..15) - 5 - 1 - - - ID4 - Port input data (y = - 0..15) - 4 - 1 - - - ID3 - Port input data (y = - 0..15) - 3 - 1 - - - ID2 - Port input data (y = - 0..15) - 2 - 1 - - - ID1 - Port input data (y = - 0..15) - 1 - 1 - - - ID0 - Port input data (y = - 0..15) - 0 - 1 - - - - - ODR - ODR - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OD8 - Port output data (y = - 0..15) - 8 - 1 - - - OD7 - Port output data (y = - 0..15) - 7 - 1 - - - OD6 - Port output data (y = - 0..15) - 6 - 1 - - - OD5 - Port output data (y = - 0..15) - 5 - 1 - - - OD4 - Port output data (y = - 0..15) - 4 - 1 - - - OD3 - Port output data (y = - 0..15) - 3 - 1 - - - OD2 - Port output data (y = - 0..15) - 2 - 1 - - - OD1 - Port output data (y = - 0..15) - 1 - 1 - - - OD0 - Port output data (y = - 0..15) - 0 - 1 - - - - - BSRR - BSRR - GPIO port bit set/reset - register - 0x18 - 0x20 - write-only - 0x00000000 - - - BR8 - Port x reset bit y (y = - 0..15) - 24 - 1 - - - BR7 - Port x reset bit y (y = - 0..15) - 23 - 1 - - - BR6 - Port x reset bit y (y = - 0..15) - 22 - 1 - - - BR5 - Port x reset bit y (y = - 0..15) - 21 - 1 - - - BR4 - Port x reset bit y (y = - 0..15) - 20 - 1 - - - BR3 - Port x reset bit y (y = - 0..15) - 19 - 1 - - - BR2 - Port x reset bit y (y = - 0..15) - 18 - 1 - - - BR1 - Port x reset bit y (y = - 0..15) - 17 - 1 - - - BR0 - Port x set bit y (y= - 0..15) - 16 - 1 - - - BS8 - Port x set bit y (y= - 0..15) - 8 - 1 - - - BS7 - Port x set bit y (y= - 0..15) - 7 - 1 - - - BS6 - Port x set bit y (y= - 0..15) - 6 - 1 - - - BS5 - Port x set bit y (y= - 0..15) - 5 - 1 - - - BS4 - Port x set bit y (y= - 0..15) - 4 - 1 - - - BS3 - Port x set bit y (y= - 0..15) - 3 - 1 - - - BS2 - Port x set bit y (y= - 0..15) - 2 - 1 - - - BS1 - Port x set bit y (y= - 0..15) - 1 - 1 - - - BS0 - Port x set bit y (y= - 0..15) - 0 - 1 - - - - - LCKR - LCKR - GPIO port configuration lock - register - 0x1C - 0x20 - read-write - 0x00000000 - - - LCKK - Port x lock bit y (y= - 0..15) - 16 - 1 - - - LCK8 - Port x lock bit y (y= - 0..15) - 8 - 1 - - - LCK7 - Port x lock bit y (y= - 0..15) - 7 - 1 - - - LCK6 - Port x lock bit y (y= - 0..15) - 6 - 1 - - - LCK5 - Port x lock bit y (y= - 0..15) - 5 - 1 - - - LCK4 - Port x lock bit y (y= - 0..15) - 4 - 1 - - - LCK3 - Port x lock bit y (y= - 0..15) - 3 - 1 - - - LCK2 - Port x lock bit y (y= - 0..15) - 2 - 1 - - - LCK1 - Port x lock bit y (y= - 0..15) - 1 - 1 - - - LCK0 - Port x lock bit y (y= - 0..15) - 0 - 1 - - - - - AFRL - AFRL - GPIO alternate function low - register - 0x20 - 0x20 - read-write - 0x00000000 - - - AFSEL7 - Alternate function selection for port x - bit y (y = 0..7) - 28 - 4 - - - AFSEL6 - Alternate function selection for port x - bit y (y = 0..7) - 24 - 4 - - - AFSEL5 - Alternate function selection for port x - bit y (y = 0..7) - 20 - 4 - - - AFSEL4 - Alternate function selection for port x - bit y (y = 0..7) - 16 - 4 - - - AFSEL3 - Alternate function selection for port x - bit y (y = 0..7) - 12 - 4 - - - AFSEL2 - Alternate function selection for port x - bit y (y = 0..7) - 8 - 4 - - - AFSEL1 - Alternate function selection for port x - bit y (y = 0..7) - 4 - 4 - - - AFSEL0 - Alternate function selection for port x - bit y (y = 0..7) - 0 - 4 - - - - - AFRH - AFRH - GPIO alternate function high - register - 0x24 - 0x20 - read-write - 0x00000000 - - - AFSEL15 - Alternate function selection for port x - bit y (y = 8..15) - 28 - 4 - - - AFSEL14 - Alternate function selection for port x - bit y (y = 8..15) - 24 - 4 - - - AFSEL13 - Alternate function selection for port x - bit y (y = 8..15) - 20 - 4 - - - AFSEL12 - Alternate function selection for port x - bit y (y = 8..15) - 16 - 4 - - - AFSEL11 - Alternate function selection for port x - bit y (y = 8..15) - 12 - 4 - - - AFSEL10 - Alternate function selection for port x - bit y (y = 8..15) - 8 - 4 - - - AFSEL9 - Alternate function selection for port x - bit y (y = 8..15) - 4 - 4 - - - AFSEL8 - Alternate function selection for port x - bit y (y = 8..15) - 0 - 4 - - - - - BRR - BRR - port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - BR8 - Port Reset bit - 8 - 1 - - - BR7 - Port Reset bit - 7 - 1 - - - BR6 - Port Reset bit - 6 - 1 - - - BR5 - Port Reset bit - 5 - 1 - - - BR4 - Port Reset bit - 4 - 1 - - - BR3 - Port Reset bit - 3 - 1 - - - BR2 - Port Reset bit - 2 - 1 - - - BR1 - Port Reset bit - 1 - 1 - - - BR0 - Port Reset bit - 0 - 1 - - - - - - - GPIOF - 0x50001400 - - - EXTI - External interrupt/event - controller - EXTI - 0x40021800 - - 0x0 - 0x400 - registers - - - PVD - PVD Interrupt through EXTI Lines 16 - 1 - - - EXTI0_1 - EXTI Line 0 and 1 Interrupt - 5 - - - EXTI2_3 - EXTI Line 2 and 3 Interrupt - 6 - - - EXTI4_15 - EXTI Line 4 to 15 Interrupt - 7 - - - - RTSR - RTSR - EXTI rising trigger selection - register - 0x0 - 0x20 - read-write - 0x00000000 - - - RT18 - Rising trigger event configuration bit - of Configurable Event input - 18 - 1 - - - RT17 - Rising trigger event configuration bit - of Configurable Event input - 17 - 1 - - - RT16 - Rising trigger event configuration bit - of Configurable Event input - 16 - 1 - - - RT15 - Rising trigger event configuration bit - of Configurable Event input - 15 - 1 - - - RT14 - Rising trigger event configuration bit - of Configurable Event input - 14 - 1 - - - RT13 - Rising trigger event configuration bit - of Configurable Event input - 13 - 1 - - - RT12 - Rising trigger event configuration bit - of Configurable Event input - 12 - 1 - - - RT11 - Rising trigger event configuration bit - of Configurable Event input - 11 - 1 - - - RT10 - Rising trigger event configuration bit - of Configurable Event input - 10 - 1 - - - RT9 - Rising trigger event configuration bit - of Configurable Event input - 9 - 1 - - - RT8 - Rising trigger event configuration bit - of Configurable Event input - 8 - 1 - - - RT7 - Rising trigger event configuration bit - of Configurable Event input - 7 - 1 - - - RT6 - Rising trigger event configuration bit - of Configurable Event input - 6 - 1 - - - RT5 - Rising trigger event configuration bit - of Configurable Event input - 5 - 1 - - - RT4 - Rising trigger event configuration bit - of Configurable Event input - 4 - 1 - - - RT3 - Rising trigger event configuration bit - of Configurable Event input - 3 - 1 - - - RT2 - Rising trigger event configuration bit - of Configurable Event input - 2 - 1 - - - RT1 - Rising trigger event configuration bit - of Configurable Event input - 1 - 1 - - - RT0 - Rising trigger event configuration bit - of Configurable Event input - 0 - 1 - - - - - FTSR - FTSR - EXTI falling trigger selection - register - 0x4 - 0x20 - read-write - 0x00000000 - - - FT18 - Falling trigger event configuration bit - of Configurable Event input - 18 - 1 - - - FT17 - Falling trigger event configuration bit - of Configurable Event input - 17 - 1 - - - FT16 - Falling trigger event configuration bit - of Configurable Event input - 16 - 1 - - - FT15 - Falling trigger event configuration bit - of Configurable Event input - 15 - 1 - - - FT14 - Falling trigger event configuration bit - of Configurable Event input - 14 - 1 - - - FT13 - Falling trigger event configuration bit - of Configurable Event input - 13 - 1 - - - FT12 - Falling trigger event configuration bit - of Configurable Event input - 12 - 1 - - - FT11 - Falling trigger event configuration bit - of Configurable Event input - 11 - 1 - - - FT10 - Falling trigger event configuration bit - of Configurable Event input - 10 - 1 - - - FT9 - Falling trigger event configuration bit - of Configurable Event input - 9 - 1 - - - FT8 - Falling trigger event configuration bit - of Configurable Event input - 8 - 1 - - - FT7 - Falling trigger event configuration bit - of Configurable Event input - 7 - 1 - - - FT6 - Falling trigger event configuration bit - of Configurable Event input - 6 - 1 - - - FT5 - Falling trigger event configuration bit - of Configurable Event input - 5 - 1 - - - FT4 - Falling trigger event configuration bit - of Configurable Event input - 4 - 1 - - - FT3 - Falling trigger event configuration bit - of Configurable Event input - 3 - 1 - - - FT2 - Falling trigger event configuration bit - of Configurable Event input - 2 - 1 - - - FT1 - Falling trigger event configuration bit - of Configurable Event input - 1 - 1 - - - FT0 - Falling trigger event configuration bit - of Configurable Event input - 0 - 1 - - - - - SWIER - SWIER - EXTI software interrupt event - register - 0x8 - 0x20 - read-write - 0x00000000 - - - SWI18 - Rising trigger event configuration bit - of Configurable Event input - 18 - 1 - - - SWI17 - Rising trigger event configuration bit - of Configurable Event input - 17 - 1 - - - SWI16 - Rising trigger event configuration bit - of Configurable Event input - 16 - 1 - - - SWI15 - Rising trigger event configuration bit - of Configurable Event input - 15 - 1 - - - SWI14 - Rising trigger event configuration bit - of Configurable Event input - 14 - 1 - - - SWI13 - Rising trigger event configuration bit - of Configurable Event input - 13 - 1 - - - SWI12 - Rising trigger event configuration bit - of Configurable Event input - 12 - 1 - - - SWI11 - Rising trigger event configuration bit - of Configurable Event input - 11 - 1 - - - SWI10 - Rising trigger event configuration bit - of Configurable Event input - 10 - 1 - - - SWI9 - Rising trigger event configuration bit - of Configurable Event input - 9 - 1 - - - SWI8 - Rising trigger event configuration bit - of Configurable Event input - 8 - 1 - - - SWI7 - Rising trigger event configuration bit - of Configurable Event input - 7 - 1 - - - SWI6 - Rising trigger event configuration bit - of Configurable Event input - 6 - 1 - - - SWI5 - Rising trigger event configuration bit - of Configurable Event input - 5 - 1 - - - SWI4 - Rising trigger event configuration bit - of Configurable Event input - 4 - 1 - - - SWI3 - Rising trigger event configuration bit - of Configurable Event input - 3 - 1 - - - SWI2 - Rising trigger event configuration bit - of Configurable Event input - 2 - 1 - - - SWI1 - Rising trigger event configuration bit - of Configurable Event input - 1 - 1 - - - SWI0 - Rising trigger event configuration bit - of Configurable Event input - 0 - 1 - - - - - PR - PR - EXTI pending - register - 0xC - 0x20 - read-write - 0x00000000 - - - PR18 - configurable event inputs x rising edge - Pending bit. - 18 - 1 - - - PR17 - configurable event inputs x rising edge - Pending bit. - 17 - 1 - - - PR16 - configurable event inputs x rising edge - Pending bit. - 16 - 1 - - - PR15 - configurable event inputs x rising edge - Pending bit. - 15 - 1 - - - PR14 - configurable event inputs x rising edge - Pending bit. - 14 - 1 - - - PR13 - configurable event inputs x rising edge - Pending bit - 13 - 1 - - - PR12 - configurable event inputs x rising edge - Pending bit. - 12 - 1 - - - PR11 - configurable event inputs x rising edge - Pending bit. - 11 - 1 - - - PR10 - configurable event inputs x rising edge - Pending bit. - 10 - 1 - - - PR9 - configurable event inputs x rising edge - Pending bit. - 9 - 1 - - - PR8 - configurable event inputs x rising edge - Pending bit. - 8 - 1 - - - PR7 - configurable event inputs x rising edge - Pending bit. - 7 - 1 - - - PR6 - configurable event inputs x rising edge - Pending bit. - 6 - 1 - - - PR5 - configurable event inputs x rising edge - Pending bit. - 5 - 1 - - - PR4 - configurable event inputs x rising edge - Pending bit. - 4 - 1 - - - PR3 - configurable event inputs x rising edge - Pending bit. - 3 - 1 - - - PR2 - configurable event inputs x rising edge - Pending bit. - 2 - 1 - - - PR1 - configurable event inputs x rising edge - Pending bit. - 1 - 1 - - - PR0 - configurable event inputs x rising edge - Pending bit. - 0 - 1 - - - - - EXTICR1 - EXTICR1 - EXTI external interrupt selection - register - 0x60 - 0x20 - read-write - 0x00000000 - - - EXTI3 - GPIO port selection - 24 - 2 - - - EXTI2 - GPIO port selection - 16 - 2 - - - EXTI1 - GPIO port selection - 8 - 2 - - - EXTI0 - GPIO port selection - 0 - 2 - - - - - EXTICR2 - EXTICR2 - EXTI external interrupt selection - register - 0x64 - 0x20 - read-write - 0x00000000 - - - EXTI7 - GPIO port selection - 24 - 1 - - - EXTI6 - GPIO port selection - 16 - 1 - - - EXTI5 - GPIO port selection - 8 - 1 - - - EXTI4 - GPIO port selection - 0 - 2 - - - - - EXTICR3 - EXTICR3 - EXTI external interrupt selection - register - 0x68 - 0x20 - read-write - 0x00000000 - - - EXTI8 - GPIO port selection - 0 - 1 - - - - - IMR - IMR - EXTI CPU wakeup with interrupt mask - register - 0x80 - 0x20 - read-write - 0xFFF80000 - - - IM29 - CPU wakeup with interrupt mask on event - input - 29 - 1 - - - IM19 - CPU wakeup with interrupt mask on event - input - 19 - 1 - - - IM18 - CPU wakeup with interrupt mask on event - input - 18 - 1 - - - IM17 - CPU wakeup with interrupt mask on event - input - 17 - 1 - - - IM16 - CPU wakeup with interrupt mask on event - input - 16 - 1 - - - IM15 - CPU wakeup with interrupt mask on event - input - 15 - 1 - - - IM14 - CPU wakeup with interrupt mask on event - input - 14 - 1 - - - IM13 - CPU wakeup with interrupt mask on event - input - 13 - 1 - - - IM12 - CPU wakeup with interrupt mask on event - input - 12 - 1 - - - IM11 - CPU wakeup with interrupt mask on event - input - 11 - 1 - - - IM10 - CPU wakeup with interrupt mask on event - input - 10 - 1 - - - IM9 - CPU wakeup with interrupt mask on event - input - 9 - 1 - - - IM8 - CPU wakeup with interrupt mask on event - input - 8 - 1 - - - IM7 - CPU wakeup with interrupt mask on event - input - 7 - 1 - - - IM6 - CPU wakeup with interrupt mask on event - input - 6 - 1 - - - IM5 - CPU wakeup with interrupt mask on event - input - 5 - 1 - - - IM4 - CPU wakeup with interrupt mask on event - input - 4 - 1 - - - IM3 - CPU wakeup with interrupt mask on event - input - 3 - 1 - - - IM2 - CPU wakeup with interrupt mask on event - input - 2 - 1 - - - IM1 - CPU wakeup with interrupt mask on event - input - 1 - 1 - - - IM0 - CPU wakeup with interrupt mask on event - input - 0 - 1 - - - - - EMR - EMR - EXTI CPU wakeup with event mask - register - 0x84 - 0x20 - read-write - 0x00000000 - - - EM29 - CPU wakeup with event mask on event - input - 29 - 1 - - - EM19 - CPU wakeup with event mask on event - input - 19 - 1 - - - EM18 - CPU wakeup with event mask on event - input - 18 - 1 - - - EM17 - CPU wakeup with event mask on event - input - 17 - 1 - - - EM16 - CPU wakeup with event mask on event - input - 16 - 1 - - - EM15 - CPU wakeup with event mask on event - input - 15 - 1 - - - EM14 - CPU wakeup with event mask on event - input - 14 - 1 - - - EM13 - CPU wakeup with event mask on event - input - 13 - 1 - - - EM12 - CPU wakeup with event mask on event - input - 12 - 1 - - - EM11 - CPU wakeup with event mask on event - input - 11 - 1 - - - EM10 - CPU wakeup with event mask on event - input - 10 - 1 - - - EM9 - CPU wakeup with event mask on event - input - 9 - 1 - - - EM8 - CPU wakeup with event mask on event - input - 8 - 1 - - - EM7 - CPU wakeup with event mask on event - input - 7 - 1 - - - EM6 - CPU wakeup with event mask on event - input - 6 - 1 - - - EM5 - CPU wakeup with event mask on event - input - 5 - 1 - - - EM4 - CPU wakeup with event mask on event - input - 4 - 1 - - - EM3 - CPU wakeup with event mask on event - input - 3 - 1 - - - EM2 - CPU wakeup with event mask on event - input - 2 - 1 - - - EM1 - CPU wakeup with event mask on event - input - 1 - 1 - - - EM0 - CPU wakeup with event mask on event - input - 0 - 1 - - - - - - - LPTIM - Low power timer - LPTIM - 0x40007C00 - - 0x0 - 0x400 - registers - - - - ISR - ISR - Interrupt and Status Register - 0x0 - 0x20 - read-only - 0x00000000 - - - ARRM - Autoreload match - 1 - 1 - - - - - ICR - ICR - Interrupt Clear Register - 0x4 - 0x20 - write-only - 0x00000000 - - - ARRMCF - Autoreload match Clear - Flag - 1 - 1 - - - - - IER - IER - Interrupt Enable Register - 0x8 - 0x20 - read-write - 0x00000000 - - - ARRMIE - Autoreload match Interrupt - Enable - 1 - 1 - - - - - CFGR - CFGR - Configuration Register - 0xC - 0x20 - read-write - 0x00000000 - - - PRELOAD - Registers update mode - 22 - 1 - - - PRESC - Clock prescaler - 9 - 3 - - - - - CR - CR - Control Register - 0x10 - 0x20 - read-write - 0x00000000 - - - RSTARE - Reset after read enable - 4 - 1 - - - SNGSTRT - LPTIM start in single mode - 1 - 1 - - - ENABLE - LPTIM Enable - 0 - 1 - - - - - ARR - ARR - Autoreload Register - 0x18 - 0x20 - read-write - 0x00000001 - - - ARR - Auto reload value - 0 - 16 - - - - - CNT - CNT - Counter Register - 0x1C - 0x20 - read-only - 0x00000000 - - - CNT - Counter value - 0 - 16 - - - - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global Interrupt - 27 - - - - SR - SR - Status register - 0x0 - 0x20 - 0x00C0 - - - ABRRQ - Automate baudrate detection requeset - 12 - 1 - write-only - - - ABRE - Automate baudrate detection error flag - 11 - 1 - read-only - - - ABRF - Automate baudrate detection flag - 10 - 1 - read-only - - - CTS - CTS flag - 9 - 1 - read-write - - - TXE - Transmit data register - empty - 7 - 1 - read-only - - - TC - Transmission complete - 6 - 1 - read-write - - - RXNE - Read data register not - empty - 5 - 1 - read-write - - - IDLE - IDLE line detected - 4 - 1 - read-only - - - ORE - Overrun error - 3 - 1 - read-only - - - NE - Noise error flag - 2 - 1 - read-only - - - FE - Framing error - 1 - 1 - read-only - - - PE - Parity error - 0 - 1 - read-only - - - - - DR - DR - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DR - Data value - 0 - 9 - - - - - BRR - BRR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV_Mantissa - mantissa of USARTDIV - 4 - 12 - - - DIV_Fraction - fraction of USARTDIV - 0 - 4 - - - - - CR1 - CR1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UE - USART enable - 13 - 1 - - - M - Word length - 12 - 1 - - - WAKE - Wakeup method - 11 - 1 - - - PCE - Parity control enable - 10 - 1 - - - PS - Parity selection - 9 - 1 - - - PEIE - PE interrupt enable - 8 - 1 - - - TXEIE - TXE interrupt enable - 7 - 1 - - - TCIE - Transmission complete interrupt - enable - 6 - 1 - - - RXNEIE - RXNE interrupt enable - 5 - 1 - - - IDLEIE - IDLE interrupt enable - 4 - 1 - - - TE - Transmitter enable - 3 - 1 - - - RE - Receiver enable - 2 - 1 - - - RWU - Receiver wakeup - 1 - 1 - - - SBK - Send break - 0 - 1 - - - - - CR2 - CR2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - STOP - STOP bits - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CPOL - Clock polarity - 10 - 1 - - - CPHA - Clock phase - 9 - 1 - - - LBCL - Last bit clock pulse - 8 - 1 - - - ADD - Address of the USART node - 0 - 4 - - - - - CR3 - CR3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - ABRMOD - Auto baudrate mode - 13 - 2 - - - ABREN - Auto baudrate enable - 12 - 1 - - - OVER8 - Oversampling mode - 11 - 1 - - - CTSIE - CTS interrupt enable - 10 - 1 - - - CTSE - CTS enable - 9 - 1 - - - RTSE - RTS enable - 8 - 1 - - - DMAT - DMA enable transmitter - 7 - 1 - - - DMAR - DMA enable receiver - 6 - 1 - - - HDSEL - Half-duplex selection - 3 - 1 - - - IRLP - IrDA low-power - 2 - 1 - - - IREN - IrDA mode enable - 1 - 1 - - - EIE - Error interrupt enable - 0 - 1 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global Interrupt - 28 - - - - RTC - Real time clock - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC - RTC Interrupt through EXTI Lines 19 - 2 - - - - CRH - CRH - RTC Control Register High - 0x0 - 0x20 - read-write - 0x00000000 - - - OWIE - Overflow interrupt Enable - 2 - 1 - - - ALRIE - Alarm interrupt Enable - 1 - 1 - - - SECIE - Second interrupt Enable - 0 - 1 - - - - - CRL - CRL - RTC Control Register Low - 0x4 - 0x20 - 0x00000020 - - - RTOFF - RTC operation OFF - 5 - 1 - read-only - - - CNF - Configuration Flag - 4 - 1 - read-write - - - RSF - Registers Synchronized - Flag - 3 - 1 - read-write - - - OWF - Overflow Flag - 2 - 1 - read-write - - - ALRF - Alarm Flag - 1 - 1 - read-write - - - SECF - Second Flag - 0 - 1 - read-write - - - - - PRLH - PRLH - RTC Prescaler Load Register - High - 0x8 - 0x20 - write-only - 0x00000000 - - - PRLH - RTC Prescaler Load Register - High - 0 - 4 - - - - - PRLL - PRLL - RTC Prescaler Load Register - Low - 0xC - 0x20 - write-only - 0x8000 - - - PRLL - RTC Prescaler Divider Register - Low - 0 - 16 - - - - - DIVH - DIVH - RTC Prescaler Divider Register - High - 0x10 - 0x20 - read-only - 0x00000000 - - - DIVH - RTC prescaler divider register - high - 0 - 4 - - - - - DIVL - DIVL - RTC Prescaler Divider Register - Low - 0x14 - 0x20 - read-only - 0x8000 - - - DIVL - RTC prescaler divider register - Low - 0 - 16 - - - - - CNTH - CNTH - RTC Counter Register High - 0x18 - 0x20 - read-write - 0x00000000 - - - CNTH - RTC counter register high - 0 - 16 - - - - - CNTL - CNTL - RTC Counter Register Low - 0x1C - 0x20 - read-write - 0x00000000 - - - CNTL - RTC counter register Low - 0 - 16 - - - - - ALRH - ALRH - RTC Alarm Register High - 0x20 - 0x20 - write-only - 0xFFFF - - - ALRH - RTC alarm register high - 0 - 16 - - - - - ALRL - ALRL - RTC Alarm Register Low - 0x24 - 0x20 - write-only - 0xFFFF - - - ALRL - RTC alarm register low - 0 - 16 - - - - - RTCCR - RTCCR - RTC clock calibration - 0x2C - 0x20 - read-write - 0x0000 - - - ASOS - Alarm or second output selection - 9 - 1 - - - ASOE - Alarm or second output enable - 8 - 1 - - - CCO - Calibration clock output - 7 - 1 - - - CAL - Calibration value - 0 - 7 - - - - - - - IWDG - Independent watchdog - IWDG - 0x40003000 - - 0x0 - 0x400 - registers - - - - KR - KR - Key register (IWDG_KR) - 0x0 - 0x20 - write-only - 0x00000000 - - - KEY - Key value - 0 - 16 - - - - - PR - PR - Prescaler register (IWDG_PR) - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Prescaler divider - 0 - 3 - - - - - RLR - RLR - Reload register (IWDG_RLR) - 0x8 - 0x20 - read-write - 0x00000FFF - - - RL - Watchdog counter reload - value - 0 - 12 - - - - - SR - SR - Status register (IWDG_SR) - 0xC - 0x20 - read-only - 0x00000000 - - - WVU - Watchdog counter window value update - 2 - 1 - - - RVU - Watchdog counter reload value - update - 1 - 1 - - - PVU - Watchdog prescaler value - update - 0 - 1 - - - - - WINR - WINR - Window register (IWDG_SR) - 0x10 - 0x20 - read-only - 0x00000000 - - - WIN - window counter - 0 - 12 - - - - - - - WWDG - Window watchdog - WWDG - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDG - Window WatchDog Interrupt - 0 - - - - CR - CR - Control register (WWDG_CR) - 0x0 - 0x20 - read-write - 0x0000007F - - - WDGA - Activation bit - 7 - 1 - - - T - 7-bit counter (MSB to LSB) - 0 - 7 - - - - - CFR - CFR - Configuration register - (WWDG_CFR) - 0x4 - 0x20 - read-write - 0x0000007F - - - EWI - Early Wakeup Interrupt - 9 - 1 - - - WDGTB - Timer Base - 7 - 2 - - - W - 7-bit window value - 0 - 7 - - - - - SR - SR - Status register (WWDG_SR) - 0x8 - 0x20 - read-write - 0x00000000 - - - EWIF - Early Wakeup Interrupt flag - 0 - 1 - - - - - - - TIM1 - Advanced timer - TIM - 0x40012C00 - - 0x0 - 0x400 - registers - - - TIM1_BRK_UP_TRG_COM - TIM1 Break, Update, Trigger and Commutation Interrupt - 13 - - - TIM1_CC - TIM1 Capture Compare Interrupt - 14 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - CMS - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - OIS4 - Output Idle state 4 - 14 - 1 - - - OIS3N - Output Idle state 3 - 13 - 1 - - - OIS3 - Output Idle state 3 - 12 - 1 - - - OIS2N - Output Idle state 2 - 11 - 1 - - - OIS2 - Output Idle state 2 - 10 - 1 - - - OIS1N - Output Idle state 1 - 9 - 1 - - - OIS1 - Output Idle state 1 - 8 - 1 - - - TI1S - TI1 selection - 7 - 1 - - - MMS - Master mode selection - 4 - 3 - - - CCDS - Capture/compare DMA - selection - 3 - 1 - - - CCUS - Capture/compare control update - selection - 2 - 1 - - - CCPC - Capture/compare preloaded - control - 0 - 1 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - ETP - External trigger polarity - 15 - 1 - - - ECE - External clock enable - 14 - 1 - - - ETPS - External trigger prescaler - 12 - 2 - - - ETF - External trigger filter - 8 - 4 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - OCCS - OCREF clear selection bit - 3 - 1 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDE - Trigger DMA request enable - 14 - 1 - - - COMDE - COM DMA request enable - 13 - 1 - - - CC4DE - Capture/Compare 4 DMA request - enable - 12 - 1 - - - CC3DE - Capture/Compare 3 DMA request - enable - 11 - 1 - - - CC2DE - Capture/Compare 2 DMA request - enable - 10 - 1 - - - CC1DE - Capture/Compare 1 DMA request - enable - 9 - 1 - - - UDE - Update DMA request enable - 8 - 1 - - - BIE - Break interrupt enable - 7 - 1 - - - TIE - Trigger interrupt enable - 6 - 1 - - - COMIE - COM interrupt enable - 5 - 1 - - - CC4IE - Capture/Compare 4 interrupt - enable - 4 - 1 - - - CC3IE - Capture/Compare 3 interrupt - enable - 3 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC4OF - Capture/Compare 4 overcapture - flag - 12 - 1 - - - CC3OF - Capture/Compare 3 overcapture - flag - 11 - 1 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - BIF - Break interrupt flag - 7 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - COMIF - COM interrupt flag - 5 - 1 - - - CC4IF - Capture/Compare 4 interrupt - flag - 4 - 1 - - - CC3IF - Capture/Compare 3 interrupt - flag - 3 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - BG - Break generation - 7 - 1 - - - TG - Trigger generation - 6 - 1 - - - COMG - Capture/Compare control update - generation - 5 - 1 - - - CC4G - Capture/compare 4 - generation - 4 - 1 - - - CC3G - Capture/compare 3 - generation - 3 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - Output Compare 2 clear - enable - 15 - 1 - - - OC2M - Output Compare 2 mode - 12 - 3 - - - OC2PE - Output Compare 2 preload - enable - 11 - 1 - - - OC2FE - Output Compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1CE - Output Compare 1 clear - enable - 7 - 1 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - ICPSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register (output - mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - Output compare 4 clear - enable - 15 - 1 - - - OC4M - Output compare 4 mode - 12 - 3 - - - OC4PE - Output compare 4 preload - enable - 11 - 1 - - - OC4FE - Output compare 4 fast - enable - 10 - 1 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - OC3CE - Output compare 3 clear - enable - 7 - 1 - - - OC3M - Output compare 3 mode - 4 - 3 - - - OC3PE - Output compare 3 preload - enable - 3 - 1 - - - OC3FE - Output compare 3 fast - enable - 2 - 1 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input - mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - IC3F - Input capture 3 filter - 4 - 4 - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - CC3S - Capture/compare 3 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC4P - Capture/Compare 3 output - Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output - enable - 12 - 1 - - - CC3NP - Capture/Compare 3 output - Polarity - 11 - 1 - - - CC3NE - Capture/Compare 3 complementary output - enable - 10 - 1 - - - CC3P - Capture/Compare 3 output - Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output - enable - 8 - 1 - - - CC2NP - Capture/Compare 2 output - Polarity - 7 - 1 - - - CC2NE - Capture/Compare 2 complementary output - enable - 6 - 1 - - - CC2P - Capture/Compare 2 output - Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output - enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1NE - Capture/Compare 1 complementary output - enable - 2 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - RCR - RCR - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - REP - Repetition counter value - 0 - 8 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - CCR3 - CCR3 - capture/compare register 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - CCR3 - Capture/Compare value - 0 - 16 - - - - - CCR4 - CCR4 - capture/compare register 4 - 0x40 - 0x20 - read-write - 0x00000000 - - - CCR4 - Capture/Compare value - 0 - 16 - - - - - BDTR - BDTR - break and dead-time register - 0x44 - 0x20 - read-write - 0x0000 - - - MOE - Main output enable - 15 - 1 - - - AOE - Automatic output enable - 14 - 1 - - - BKP - Break polarity - 13 - 1 - - - BKE - Break enable - 12 - 1 - - - OSSR - Off-state selection for Run - mode - 11 - 1 - - - OSSI - Off-state selection for Idle - mode - 10 - 1 - - - LOCK - Lock configuration - 8 - 2 - - - DTG - Dead-time generator setup - 0 - 8 - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DBL - DMA burst length - 8 - 5 - - - DBA - DMA base address - 0 - 5 - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMAB - DMA register for burst - accesses - 0 - 16 - - - - - - - TIM3 - General purpose timer - TIM - 0x40000400 - - 0x00 - 0x400 - registers - - - TIM3 - TIM3 global Interrupt - 16 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - CMS - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TI1S - TI1 selection - 7 - 1 - - - MMS - Master mode selection - 4 - 3 - - - CCDS - Capture/compare DMA - selection - 3 - 1 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - OCCS - OCREF Clear Selection - 3 - 1 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDE - Trigger DMA request enable - 14 - 1 - - - CC4DE - Capture/Compare 4 DMA request - enable - 12 - 1 - - - CC3DE - Capture/Compare 3 DMA request - enable - 11 - 1 - - - CC2DE - Capture/Compare 2 DMA request - enable - 10 - 1 - - - CC1DE - Capture/Compare 1 DMA request - enable - 9 - 1 - - - UDE - Update DMA request enable - 8 - 1 - - - TIE - Trigger interrupt enable - 6 - 1 - - - CC4IE - Capture/Compare 4 interrupt - enable - 4 - 1 - - - CC3IE - Capture/Compare 3 interrupt - enable - 3 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC4OF - Capture/Compare 4 overcapture - flag - 12 - 1 - - - CC3OF - Capture/Compare 3 overcapture - flag - 11 - 1 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - CC4IF - Capture/Compare 4 interrupt - flag - 4 - 1 - - - CC3IF - Capture/Compare 3 interrupt - flag - 3 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - TG - Trigger generation - 6 - 1 - - - CC4G - Capture/compare 4 - generation - 4 - 1 - - - CC3G - Capture/compare 3 - generation - 3 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - Output compare 2 clear - enable - 15 - 1 - - - OC2M - Output compare 2 mode - 12 - 3 - - - OC2PE - Output compare 2 preload - enable - 11 - 1 - - - OC2FE - Output compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1CE - Output compare 1 clear - enable - 7 - 1 - - - OC1M - Output compare 1 mode - 4 - 3 - - - OC1PE - Output compare 1 preload - enable - 3 - 1 - - - OC1FE - Output compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register 2 (output - mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - Output compare 4 clear - enable - 15 - 1 - - - OC4M - Output compare 4 mode - 12 - 3 - - - OC4PE - Output compare 4 preload - enable - 11 - 1 - - - OC4FE - Output compare 4 fast - enable - 10 - 1 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - OC3CE - Output compare 3 clear - enable - 7 - 1 - - - OC3M - Output compare 3 mode - 4 - 3 - - - OC3PE - Output compare 3 preload - enable - 3 - 1 - - - OC3FE - Output compare 3 fast - enable - 2 - 1 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input - mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - IC3F - Input capture 3 filter - 4 - 4 - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC4NP - - Capture/Compare 4 output - Polarity - - 15 - 1 - - - CC4P - - Capture/Compare 4 output - Polarity - - 13 - 1 - - - CC4E - - Capture/Compare 4 output - enable - - 12 - 1 - - - CC3NP - - Capture/Compare 3 output - Polarity - - 11 - 1 - - - CC3P - - Capture/Compare 3 output - Polarity - - 9 - 1 - - - CC3E - - Capture/Compare 3 output - enable - - 8 - 1 - - - CC2NP - - Capture/Compare 2 output - Polarity - - 7 - 1 - - - CC2P - - Capture/Compare 2 output - Polarity - - 5 - 1 - - - CC2E - - Capture/Compare 2 output - enable - - 4 - 1 - - - CC1NP - - Capture/Compare 1 output - Polarity - - 3 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - CCR3 - CCR3 - capture/compare register 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - CCR3 - Capture/Compare value - 0 - 16 - - - - - CCR4 - CCR4 - capture/compare register 4 - 0x40 - 0x20 - read-write - 0x00000000 - - - CCR4 - Capture/Compare value - 0 - 16 - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DBL - DMA burst length - 8 - 5 - - - DBA - DMA base address - 0 - 5 - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMAB - DMA register for burst - accesses - 0 - 32 - - - - - - - TIM14 - General purpose timer - TIM - 0x40002000 - - 0x00 - 0x400 - registers - - - TIM14 - TIM14 global Interrupt - 19 - - - - CR1 - CR1 - TIM14 control register1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Prescaler factor - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - CC1IE - Compare/ - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC1OF - Compare/capture 1 flag - 9 - 1 - - - CC1IF - Compare/capture 1 interrupt flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - CC1G - Compare/capture1 event - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - OR - OR - Option register - 0x50 - 0x20 - read-write - 0x00000000 - - - TI1_RMP - TIM14 channel1 input remap - 0 - 2 - - - - - - - TIM16 - General purpose timer - TIM - 0x40014400 - - 0x00 - 0x400 - registers - - - TIM16 - TIM16 global Interrupt - 21 - - - - CR1 - CR1 - TIM16 control register1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Prescaler factor - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - OPM - One pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - OIS1N - Output Idle state 1 - 9 - 1 - - - OIS1 - Output Idle state 1 - 8 - 1 - - - CCDS - Capture/compare DMA - selection - 3 - 1 - - - CCPC - Capture/compare preloaded - control - 0 - 1 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - CC1DE - Compare/capture DMA requeset enable - 9 - 1 - - - UDE - Update DMA request enable - 8 - 1 - - - BIE - Break interrupt enable - 7 - 1 - - - COMIE - Com interrupt enable - 5 - 1 - - - CC1IE - Capture/Compare 1 interrupt enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC1OF - Update interrupt flag - 9 - 1 - - - BIF - Break interrupt flag - 7 - 1 - - - COMIF - Com interrupt flag - 5 - 1 - - - CC1IF - Capture/Compare 1 interrupt flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - BG - Break event generation - 7 - 1 - - - COMG - COM evnet generation - 5 - 1 - - - CC1G - Capture/Compare 1 generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1NE - Capture/Compare 1 complementary output - enable - 2 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - RCR - RCR - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - REP - Repetition counter value - 0 - 8 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - BDTR - BDTR - break and dead-time register - 0x44 - 0x20 - read-write - 0x0000 - - - MOE - Main output enable - 15 - 1 - - - AOE - Automatic output enable - 14 - 1 - - - BKP - Break polarity - 13 - 1 - - - BKE - Break enable - 12 - 1 - - - OSSR - Off-state selection for Run - mode - 11 - 1 - - - OSSI - Off-state selection for Idle - mode - 10 - 1 - - - LOCK - Lock configuration - 8 - 2 - - - DTG - Dead-time generator setup - 0 - 8 - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DBL - DMA burst length - 8 - 5 - - - DBA - DMA base address - 0 - 5 - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMAB - DMA register for burst - accesses - 0 - 32 - - - - - - - TIM17 - 0x40014800 - - TIM17 - TIM17 global Interrupt - 22 - - - - SYSCFG - System configuration controller - SYSCFG - 0x40010000 - - 0x0 - 0x30 - registers - - - - CFGR1 - CFGR1 - SYSCFG configuration register - 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - I2C_PF1_ANF - Analog filter enable control driving capability - activation bits PF1 - 30 - 1 - - - I2C_PF0_ANF - Analog filter enable control driving capability - activation bits PF0 - 29 - 1 - - - I2C_PB8_ANF - Analog filter enable control driving capability - activation bits PB8 - 28 - 1 - - - I2C_PB7_ANF - Analog filter enable control driving capability - activation bits PB7 - 27 - 1 - - I2C_PB6_ANF - Analog filter enable control driving capability - activation bits PB6 - 26 - 1 - - - I2C_PA12_ANF - Analog filter enable control driving capability - activation bits PA12 - 25 - 1 - - - I2C_PA11_ANF - Analog filter enable control driving capability - activation bits PA11 - 24 - 1 - - - I2C_PA10_ANF - Analog filter enable control driving capability - activation bits PA10 - 23 - 1 - - - I2C_PA9_ANF - Analog filter enable control driving capability - activation bits PA9 - 22 - 1 - - - I2C_PA8_ANF - Analog filter enable control driving capability - activation bits PA8 - 21 - 1 - - - I2C_PA7_ANF - Analog filter enable control driving capability - activation bits PA7 - 20 - 1 - - - I2C_PA3_ANF - Analog filter enable control driving capability - activation bits PA3 - 19 - 1 - - - I2C_PA2_ANF - Analog filter enable control driving capability - activation bits PA2 - 18 - 1 - - - MEM_MODE - Memory mapping selection - bits - 0 - 2 - - - - - CFGR2 - CFGR2 - SYSCFG configuration register - 2 - 0x18 - 0x20 - read-write - 0x00000000 - - - ETR_SRC_TIM1 - TIM1 ETR source selection - 9 - 2 - - - COMP2_BRK_TIM17 - COMP2 is enable to input of TIM17 break - 8 - 1 - - - COMP1_BRK_TIM17 - COMP1 is enable to input of TIM17 break - 7 - 1 - - - COMP2_BRK_TIM16 - COMP2 is enable to input of TIM16 break - 6 - 1 - - - COMP1_BRK_TIM16 - COMP1 is enable to input of TIM16 break - 5 - 1 - - - COMP2_BRK_TIM1 - COMP2 is enable to input of TIM1 break - 4 - 1 - - - COMP1_BRK_TIM1 - COMP1 is enable to input of TIM1 break - 3 - 1 - - - PVD_LOCK - PVD lock enable bit - 2 - 1 - - - LOCKUP_LOCK - Cortex-M0+ LOCKUP bit enable - bit - 0 - 1 - - - - - CFGR3 - CFGR3 - SYSCFG configuration register - 3 - 0x1C - 0x20 - read-write - 0x00000000 - - - DMA3_MAP - DMA channel3 requeset selection - 16 - 5 - - - DMA2_MAP - DMA channel2 requeset selection - 8 - 5 - - - DMA1_MAP - DMA channel1 requeset selection - 0 - 5 - - - - - - - DMA - Direct memory access - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA_Channel1 - DMA Channel 1 Interrupt - 9 - - - DMA_Channel2_3 - DMA Channel 2 and Channel 3 Interrupt - 10 - - - - ISR - ISR - DMA interrupt status register - (DMA_ISR) - 0x0 - 0x20 - read-only - 0x00000000 - - - TEIF3 - Channel 3 Transfer Error - flag - 11 - 1 - - - HTIF3 - Channel 3 Half Transfer Complete - flag - 10 - 1 - - - TCIF3 - Channel 3 Transfer Complete - flag - 9 - 1 - - - GIF3 - Channel 3 Global interrupt - flag - 8 - 1 - - - TEIF2 - Channel 2 Transfer Error - flag - 7 - 1 - - - HTIF2 - Channel 2 Half Transfer Complete - flag - 6 - 1 - - - TCIF2 - Channel 2 Transfer Complete - flag - 5 - 1 - - - GIF2 - Channel 2 Global interrupt - flag - 4 - 1 - - - TEIF1 - Channel 1 Transfer Error - flag - 3 - 1 - - - HTIF1 - Channel 1 Half Transfer Complete - flag - 2 - 1 - - - TCIF1 - Channel 1 Transfer Complete - flag - 1 - 1 - - - GIF1 - Channel 1 Global interrupt - flag - 0 - 1 - - - - - IFCR - IFCR - DMA interrupt flag clear register - (DMA_IFCR) - 0x4 - 0x20 - write-only - 0x00000000 - - - CTEIF3 - Channel 3 Transfer Error - clear - 11 - 1 - - - CHTIF3 - Channel 3 Half Transfer - clear - 10 - 1 - - - CTCIF3 - Channel 3 Transfer Complete - clear - 9 - 1 - - - CGIF3 - Channel 3 Global interrupt - clear - 8 - 1 - - - CTEIF2 - Channel 2 Transfer Error - clear - 7 - 1 - - - CHTIF2 - Channel 2 Half Transfer - clear - 6 - 1 - - - CTCIF2 - Channel 2 Transfer Complete - clear - 5 - 1 - - - CGIF2 - Channel 2 Global interrupt - clear - 4 - 1 - - - CTEIF1 - Channel 1 Transfer Error - clear - 3 - 1 - - - CHTIF1 - Channel 1 Half Transfer - clear - 2 - 1 - - - CTCIF1 - Channel 1 Transfer Complete - clear - 1 - 1 - - - CGIF1 - Channel 1 Global interrupt - clear - 0 - 1 - - - - - CCR1 - CCR1 - DMA channel configuration register - (DMA_CCR) - 0x8 - 0x20 - read-write - 0x00000000 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - PL - Channel Priority level - 12 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PSIZE - Peripheral size - 8 - 2 - - - MINC - Memory increment mode - 7 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - CIRC - Circular mode - 5 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - EN - Channel enable - 0 - 1 - - - - - CNDTR1 - CNDTR1 - DMA channel 1 number of data - register - 0xC - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR1 - CPAR1 - DMA channel 1 peripheral address - register - 0x10 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR1 - CMAR1 - DMA channel 1 memory address - register - 0x14 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR2 - CCR2 - DMA channel configuration register - (DMA_CCR) - 0x1C - 0x20 - read-write - 0x00000000 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - PL - Channel Priority level - 12 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PSIZE - Peripheral size - 8 - 2 - - - MINC - Memory increment mode - 7 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - CIRC - Circular mode - 5 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - EN - Channel enable - 0 - 1 - - - - - CNDTR2 - CNDTR2 - DMA channel 2 number of data - register - 0x20 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR2 - CPAR2 - DMA channel 2 peripheral address - register - 0x24 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR2 - CMAR2 - DMA channel 2 memory address - register - 0x28 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR3 - CCR3 - DMA channel configuration register - (DMA_CCR) - 0x30 - 0x20 - read-write - 0x00000000 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - PL - Channel Priority level - 12 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PSIZE - Peripheral size - 8 - 2 - - - MINC - Memory increment mode - 7 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - CIRC - Circular mode - 5 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - EN - Channel enable - 0 - 1 - - - - - CNDTR3 - CNDTR3 - DMA channel 3 number of data - register - 0x34 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR3 - CPAR3 - DMA channel 3 peripheral address - register - 0x38 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR3 - CMAR3 - DMA channel 3 memory address - register - 0x3C - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - - - FLASH - Flash - Flash - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - FLASH global Interrupt - 3 - - - - ACR - ACR - Access control register - 0x0 - 0x20 - read-write - 0x00000600 - - - LATENCY - Latency - 0 - 1 - - - - - KEYR - KEYR - Flash key register - 0x8 - 0x20 - write-only - 0x00000000 - - - KEY - Flash key - 0 - 32 - - - - - OPTKEYR - OPTKEYR - Option byte key register - 0xC - 0x20 - write-only - 0x00000000 - - - OPTKEY - Option byte key - 0 - 32 - - - - - SR - SR - Status register - 0x10 - 0x20 - read-write - 0x00000000 - - - BSY - Busy - 16 - 1 - - - OPTVERR - Option and Engineering bits loading - validity error - 15 - 1 - - - WRPERR - Write protected error - 4 - 1 - - - EOP - End of operation - 0 - 1 - - - - - CR - CR - Flash control register - 0x14 - 0x20 - read-write - 0xC0000000 - - - LOCK - FLASH_CR Lock - 31 - 1 - - - OPTLOCK - Options Lock - 30 - 1 - - - OBL_LAUNCH - Force the option byte - loading - 27 - 1 - - - ERRIE - Error interrupt enable - 25 - 1 - - - EOPIE - End of operation interrupt - enable - 24 - 1 - - - PGTSTRT - Flash main memory program start - 19 - 1 - - - OPTSTRT - Option byte program start - 17 - 1 - - - SER - Sector erase - 11 - 1 - - - MER - Mass erase - 2 - 1 - - - PER - Page erase - 1 - 1 - - - PG - Programming - 0 - 1 - - - - - OPTR - OPTR - Flash option register - 0x20 - 0x20 - read-write - 0x4F55B0AA - - - nBOOT1 - Boot configuration - 15 - 1 - - - NRST_MODE - NRST_MODE - 14 - 1 - - - WWDG_SW - Window watchdog selection - 13 - 1 - - - IDWG_SW - Independent watchdog - selection - 12 - 1 - - - BORF_LEV - These bits contain the VDD supply level - threshold that activates the reset - 9 - 3 - - - BOREN - BOR reset Level - 8 - 1 - - - RDP - Read Protection - 0 - 8 - - - - - SDKR - SDKR - Flash SDK address - register - 0x24 - 0x20 - read-write - 0xFFE0001F - - - SDK_END - SDK area end address - 8 - 5 - - - SDK_STRT - SDK area start address - 0 - 5 - - - - - WRPR - WRPR - Flash WRP address - register - 0x2C - 0x20 - read-write - 0x0000FFFF - - - WRP - WRP address - 0 - 16 - - - - - STCR - STCR - Flash sleep time config - register - 0x90 - 0x20 - read-write - 0x00006400 - - - SLEEP_TIME - FLash sleep time configuration(counter based on HSI_10M) - 8 - 8 - - - SLEEP_EN - FLash sleep enable - 0 - 1 - - - - - TS0 - TS0 - Flash TS0 - register - 0x100 - 0x20 - read-write - 0x000000B4 - - - TS0 - FLash TS0 register - 0 - 8 - - - - - TS1 - TS1 - Flash TS1 - register - 0x104 - 0x20 - read-write - 0x000001B0 - - - TS1 - FLash TS1 register - 0 - 9 - - - - - TS2P - TS2P - Flash TS2P - register - 0x108 - 0x20 - read-write - 0x000000B4 - - - TS2P - FLash TS2P register - 0 - 8 - - - - - TPS3 - TPS3 - Flash TPS3 - register - 0x10C - 0x20 - read-write - 0x000006C0 - - - TPS3 - FLash TPS3 register - 0 - 11 - - - - - TS3 - TS3 - Flash TS3 - register - 0x110 - 0x20 - read-write - 0x000000B4 - - - TS3 - FLash TS3 register - 0 - 8 - - - - - PERTPE - PERTPE - Flash PERTPE - register - 0x114 - 0x20 - read-write - 0x0000EA60 - - - PERTPE - FLash PERTPE register - 0 - 17 - - - - - SMERTPE - SMERTPE - Flash SMERTPE - register - 0x118 - 0x20 - read-write - 0x0000FD20 - - - SMERTPE - FLash SMERTPE register - 0 - 17 - - - - - PRGTPE - PRGTPE - Flash PRGTPE - register - 0x11C - 0x20 - read-write - 0x00008CA0 - - - PRGTPE - FLash PRGTPE register - 0 - 16 - - - - - PRETPE - PRETPE - Flash PRETPE - register - 0x120 - 0x20 - read-write - 0x000012C0 - - - PRETPE - FLash PRETPE register - 0 - 13 - - - - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DR - DR - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DR - Data Register - 0 - 32 - - - - - IDR - IDR - Independent Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - IDR - Independent Data register - 0 - 8 - - - - - CR - CR - Control register - 0x8 - 0x20 - write-only - 0x00000000 - - - RESET - Reset bit - 0 - 1 - - - - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global Interrupt - 25 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - BIDIMODE - Bidirectional data mode - enable - 15 - 1 - - - BIDIOE - Output enable in bidirectional - mode - 14 - 1 - - - RXONLY - Receive only - 10 - 1 - - - SSM - Software slave management - 9 - 1 - - - SSI - Internal slave selection - 8 - 1 - - - LSBFIRST - Frame format - 7 - 1 - - - SPE - SPI enable - 6 - 1 - - - BR - Baud rate control - 3 - 3 - - - MSTR - Master selection - 2 - 1 - - - CPOL - Clock polarity - 1 - 1 - - - CPHA - Clock phase - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - SLVFM - Slave fast mode enable - 15 - 1 - - - LDMA_TX - Last DAM Transmit(TX) - 14 - 1 - - - LDMA_RX - Last DAM Transmit(RX) - 13 - 1 - - - FRXTH - FIFO reception threshold - 12 - 1 - - - DS - Data length - - 11 - 1 - - - TXEIE - Tx buffer empty interrupt - enable - 7 - 1 - - - RXNEIE - RX buffer not empty interrupt - enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - SSOE - SS output enable - 2 - 1 - - - TXDMAEN - Tx buffer DMA enable - 1 - 1 - - - RXDMAEN - Rx buffer DMA enable - 0 - 1 - - - - - SR - SR - status register - 0x8 - 0x20 - 0x0002 - - - FTLVL - FIFO transmission level - 11 - 2 - read-only - - - FRLVL - FIFO reception level - 9 - 2 - read-only - - - BSY - Busy flag - 7 - 1 - read-only - - - OVR - Overrun flag - 6 - 1 - read-only - - - MODF - Mode fault - 5 - 1 - read-only - - - TXE - Transmit buffer empty - 1 - 1 - read-only - - - RXNE - Receive buffer not empty - 0 - 1 - read-only - - - - - DR - DR - data register - 0xC - 0x20 - read-write - 0x0000 - - - DR - Data register - 0 - 16 - - - - - - - I2C - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1 - I2C1 global Interrupt - 23 - - - - CR1 - CR1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SWRST - Software reset - 15 - 1 - - - PEC - Packet error checking - 12 - 1 - - - POS - Acknowledge/PEC Position (for data - reception) - 11 - 1 - - - ACK - Acknowledge enable - 10 - 1 - - - STOP - Stop generation - 9 - 1 - - - START - Start generation - 8 - 1 - - - NOSTRETCH - Clock stretching disable (Slave - mode) - 7 - 1 - - - ENGC - General call enable - 6 - 1 - - - ENPEC - PEC enable - 5 - 1 - - - PE - Peripheral enable - 0 - 1 - - - - - CR2 - CR2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - LAST - DMA last transfer - 12 - 1 - - - DMAEN - DMA requests enable - 11 - 1 - - - ITBUFEN - Buffer interrupt enable - 10 - 1 - - - ITEVTEN - Event interrupt enable - 9 - 1 - - - ITERREN - Error interrupt enable - 8 - 1 - - - FREQ - Peripheral clock frequency - 0 - 6 - - - - - OAR1 - OAR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADD - Interface address - 1 - 7 - - - - - DR - DR - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DR - 8-bit data register - 0 - 8 - - - - - SR1 - SR1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - PECERR - PEC Error in reception - 12 - 1 - read-write - - - OVR - Overrun/Underrun - 11 - 1 - read-write - - - AF - Acknowledge failure - 10 - 1 - read-write - - - ARLO - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BERR - Bus error - 8 - 1 - read-write - - - TxE - Data register empty - (transmitters) - 7 - 1 - read-only - - - RxNE - Data register not empty - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - BTF - Byte transfer finished - 2 - 1 - read-only - - - ADDR - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - SB - Start bit (Master mode) - 0 - 1 - read-only - - - - - SR2 - SR2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PEC - acket error checking - register - 8 - 8 - - - DUALF - Dual flag (Slave mode) - 7 - 1 - - - GENCALL - General call address (Slave - mode) - 4 - 1 - - - TRA - Transmitter/receiver - 2 - 1 - - - BUSY - Bus busy - 1 - 1 - - - MSL - Master/slave - 0 - 1 - - - - - CCR - CCR - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - F_S - I2C master mode selection - 15 - 1 - - - DUTY - Fast mode duty cycle - 14 - 1 - - - CCR - Clock control register in Fast/Standard - mode (Master mode) - 0 - 12 - - - - - TRISE - TRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - TRISE - Maximum rise time in Fast/Standard mode - (Master mode) - 0 - 6 - - - - - - - DBGMCU - Debug support - DBGMCU - 0x40015800 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - MCU Device ID Code Register - 0x0 - 0x20 - read-only - 0x0 - - - - - - CR - CR - Debug MCU Configuration - Register - 0x4 - 0x20 - read-write - 0x0 - - - DBG_STOP - Debug Stop Mode - 1 - 1 - - - - - APB_FZ1 - APB_FZ1 - APB Freeze Register1 - 0x8 - 0x20 - read-write - 0x0 - - - DBG_TIMER3_STOP - Debug Timer 3 stopped when Core is - halted - 1 - 1 - - - DBG_RTC_STOP - Debug RTC stopped when Core is - halted - 10 - 1 - - - DBG_WWDG_STOP - Debug Window Wachdog stopped when Core - is halted - 11 - 1 - - - DBG_IWDG_STOP - Debug Independent Wachdog stopped when - Core is halted - 12 - 1 - - - DBG_LPTIM_STOP - Debug LPTIM stopped when Core is - halted - 31 - 1 - - - - - APB_FZ2 - APB_FZ2 - APB Freeze Register2 - 0xC - 0x20 - read-write - 0x0 - - - DBG_TIMER1_STOP - Debug Timer 1 stopped when Core is - halted - 11 - 1 - - - DBG_TIMER14_STOP - Debug Timer 14 stopped when Core is - halted - 15 - 1 - - - DBG_TIMER16_STOP - Debug Timer 16 stopped when Core is - halted - 17 - 1 - - - DBG_TIMER17_STOP - Debug Timer 17 stopped when Core is - halted - 18 - 1 - - - - - - - + + + + Puya + Puya + PY32F0xx_DFP + + PY32F0 + 1.0.0 + Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. + + + + CM0+ + r0p1 + little + false + false + 4 + false + + + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADC + Analog to Digital Converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + ISR + ISR + ADC interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + AWD + ADC analog watchdog flag + 7 + 1 + + + OVR + ADC group regular overrun + flag + 4 + 1 + + + EOSEQ + ADC group regular end of sequence + conversions flag + 3 + 1 + + + EOC + ADC group regular end of unitary + conversion flag + 2 + 1 + + + EOSMP + ADC group regular end of sampling + flag + 1 + 1 + + + + + IER + IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + AWDIE + ADC analog watchdog + interrupt + 7 + 1 + + + OVRIE + ADC group regular overrun + interrupt + 4 + 1 + + + EOSEQIE + ADC group regular end of sequence + conversions interrupt + 3 + 1 + + + EOCIE + ADC group regular end of unitary + conversion interrupt + 2 + 1 + + + EOSMPIE + ADC group regular end of sampling + interrupt + 1 + 1 + + + + + CR + CR + ADC control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADC group regular conversion + calibration + 31 + 1 + + + ADSTP + ADC group regular conversion + stop + 4 + 1 + + + ADSTART + ADC group regular conversion + start + 2 + 1 + + + ADEN + ADC enable + 0 + 1 + + + + + CFGR1 + CFGR1 + ADC configuration register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + AWDCH + ADC analog watchdog monitored channel + selection + 26 + 4 + + + AWDEN + ADC analog watchdog enable on scope + ADC group regular + 23 + 1 + + + AWDSGL + ADC analog watchdog monitoring a + single channel or all channels + 22 + 1 + + + DISCEN + ADC group regular sequencer + discontinuous mode + 16 + 1 + + + WAIT + Wait conversion mode + 14 + 1 + + + CONT + ADC group regular continuous conversion + mode + 13 + 1 + + + OVRMOD + ADC group regular overrun + configuration + 12 + 1 + + + EXTEN + ADC group regular external trigger + polarity + 10 + 2 + + + EXTSEL + ADC group regular external trigger + source + 6 + 3 + + + ALIGN + ADC data alignement + 5 + 1 + + + RESSEL + ADC data resolution + 3 + 2 + + + SCANDIR + Scan sequence direction + 2 + 1 + + + DMACFG + ADC DMA transfer + configuration + 1 + 1 + + + DMAEN + ADC DMA transfer enable + 0 + 1 + + + + + CFGR2 + CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CKMODE + ADC clock mode + 28 + 4 + + + + + SMPR + SMPR + ADC sampling time register + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP + Sampling time selection + 0 + 3 + + + + + TR + TR + ADC analog watchdog 1 threshold register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT + ADC analog watchdog threshold + high + 16 + 12 + + + LT + ADC analog watchdog threshold + low + 0 + 12 + + + + + CHSELR + CHSELR + ADC group regular sequencer register + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + CHSEL12 + Channel-12 selection + 12 + 1 + + + CHSEL11 + Channel-11 selection + 11 + 1 + + + CHSEL9 + Channel-9 selection + 9 + 1 + + + CHSEL8 + Channel-8 selection + 8 + 1 + + + CHSEL7 + Channel-7 selection + 7 + 1 + + + CHSEL6 + Channel-6 selection + 6 + 1 + + + CHSEL5 + Channel-5 selection + 5 + 1 + + + CHSEL4 + Channel-4 selection + 4 + 1 + + + CHSEL3 + Channel-3 selection + 3 + 1 + + + CHSEL2 + Channel-2 selection + 2 + 1 + + + CHSEL1 + Channel-1 selection + 1 + 1 + + + CHSEL0 + Channel-0 selection + 0 + 1 + + + + + DR + DR + ADC group regular data register + 0x40 + 0x20 + read-only + 0x00000000 + + + DATA + ADC group regular conversion + data + 0 + 16 + + + + + CCSR + CCSR + ADC calibration configuration and status register + 0x44 + 0x20 + read-write + 0x00000000 + + + CALON + Calibration flag + 31 + 1 + read-only + + + CALFAIL + Calibration fail flag + 30 + 1 + + + CALSET + Calibration factor selection + 15 + 1 + + + CALSMP + Calibration sample time selection + 12 + 2 + + + CALSEL + Calibration contents selection + 11 + 1 + + + + + CALRR1 + CALRR1 + ADC calibration result register 1 + 0x48 + 0x20 + read-only + 0x00000000 + + + CALBOUT + offset result + 16 + 7 + + + CALC5OUT + C5 result + 8 + 8 + + + CALC4OUT + C4 result + 0 + 8 + + + + + CALRR2 + CALRR2 + ADC calibration result register 2 + 0x4C + 0x20 + read-only + 0x00000000 + + + CALC3OUT + C3 result + 24 + 8 + + + CALC2OUT + C2 result + 16 + 8 + + + CALC1OUT + C1 result + 8 + 8 + + + CALC0OUT + C0 result + 0 + 8 + + + + + CALFIR1 + CALFIR1 + ADC calibration factor input register 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + CALBIO + Calibration offset factor input + 16 + 7 + + + CALC5IO + Calibration C5 factor input + 8 + 8 + + + CALC4IO + Calibration C4 factor input + 0 + 8 + + + + + CALFIR2 + CALFIR2 + ADC calibration factor input register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + CALC3IO + Calibration C3 factor input + 24 + 8 + + + CALC2IO + Calibration C2 factor input + 16 + 8 + + + CALC1IO + Calibration C1 factor input + 8 + 8 + + + CALC0IO + Calibration C0 factor input + 0 + 8 + + + + + CCR + CCR + ADC common configuration register + 0x308 + 0x20 + read-write + 0x00000000 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VREFEN + VREFINT enable + 22 + 1 + + + + + + + COMP1 + Comparator + COMP + 0x40010200 + + 0x0 + 0x10 + registers + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + LOCK + CSR register lock + 31 + 1 + + + COMP_OUT + Comparator output status + 30 + 1 + + + PWRMODE + Comparator power mode + selector + 18 + 2 + + + HYST + Comparator hysteresis enable + selector + 16 + 1 + + + POLARITY + Comparator polarity + selector + 15 + 1 + + + WINMODE + Comparator non-inverting input + selector for window mode + 11 + 1 + + + INPSEL + Comparator signal selector for + non-inverting input + 8 + 2 + + + INMSEL + Comparator signal selector for + inverting input INM + 4 + 4 + + + SCALER_EN + SCALER enable bit + 1 + 1 + + + COMP_EN + COMP enable bit + 0 + 1 + + + + + FR + FR + Comparator Filter + register + 0x4 + 0x20 + read-write + 0x00000000 + + + FLTCNT + Comparator filter and counter + 16 + 16 + + + FLTEN + Filter enable bit + 0 + 1 + + + + + + + COMP2 + Comparator + COMP + 0x40010210 + + 0x0 + 0x10 + registers + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + LOCK + CSR register lock + 31 + 1 + + + COMP_OUT + Comparator output status + 30 + 1 + + + PWRMODE + Comparator power mode + selector + 18 + 2 + + + POLARITY + Comparator polarity + selector + 15 + 1 + + + WINMODE + Comparator non-inverting input + selector for window mode + 11 + 1 + + + INPSEL + Comparator signal selector for + non-inverting input + 8 + 2 + + + INMSEL + Comparator signal selector for + inverting input INM + 4 + 4 + + + COMP_EN + COMP enable bit + 0 + 1 + + + + + FR + FR + Comparator Filter + register + 0x4 + 0x20 + read-write + 0x00000000 + + + FLTCNT + Comparator filter and counter + 16 + 16 + + + FLTEN + Filter enable bit + 0 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global Interrupt + 4 + + + + CR + CR + Clock control register + 0x0 + 0x20 + read-write + 0x00000100 + + + CSSON + Clock security system + enable + 19 + 1 + + + HSEBYP + HSE crystal oscillator + bypass + 18 + 1 + + + HSERDY + HSE clock ready flag + 17 + 1 + + + HSEON + HSE clock enable + 16 + 1 + + + HSIDIV + HSI16 clock division + factor + 11 + 3 + + + HSIRDY + HSI16 clock ready flag + 10 + 1 + + + HSIKERON + HSI16 always enable for peripheral + kernels + 9 + 1 + + + HSION + HSI16 clock enable + 8 + 1 + + + + + ICSCR + ICSCR + Internal clock sources calibration + register + 0x4 + 0x20 + 0x10000000 + + + LSI_STARTUP + LSI startup time + 26 + 2 + read-write + + + LSI_TRIM + LSI clock trimming + 16 + 9 + read-write + + + HSI_FS + HSI frequency selection + 13 + 3 + read-write + + + HSI_TRIM + HSI clock trimming + 0 + 13 + read-write + + + + + CFGR + CFGR + Clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCOPRE + Microcontroller clock output + prescaler + 28 + 3 + read-write + + + MCOSEL + Microcontroller clock + output + 24 + 3 + read-write + + + PPRE + APB prescaler + 12 + 3 + read-write + + + HPRE + AHB prescaler + 8 + 4 + read-write + + + SWS + System clock switch status + 3 + 3 + read-only + + + SW + System clock switch + 0 + 3 + read-write + + + + + ECSCR + ECSCR + External clock source control register + 0x10 + 0x20 + 0x00000000 + + + HSE_FREQ + HSE clock freqency selection + 2 + 2 + read-write + + + + + CIER + CIER + Clock interrupt enable + register + 0x18 + 0x20 + read-write + 0x00000000 + + + HSERDYIE + HSE ready interrupt enable + 4 + 1 + + + HSIRDYIE + HSI ready interrupt enable + 3 + 1 + + + LSIRDYIE + LSI ready interrupt enable + 0 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x1C + 0x20 + read-only + 0x00000000 + + + CSSF + HSE clock secure system interrupt flag + 8 + 1 + + + HSERDYF + HSE ready interrupt flag + 4 + 1 + + + HSIRDYF + HSI ready interrupt flag + 3 + 1 + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + CSSC + clock secure system interrupt flag clear + 8 + 1 + + + HSERDYC + HSE ready interrupt clear + 4 + 1 + + + HSIRDYC + HSI ready interrupt clear + 3 + 1 + + + LSIRDYC + LSI ready interrupt clear + 0 + 1 + + + + + IOPRSTR + IOPRSTR + GPIO reset register + 0x24 + 0x20 + read-write + 0x00000000 + + + GPIOFRST + I/O port F reset + 5 + 1 + + + GPIOBRST + I/O port B reset + 1 + 1 + + + GPIOARST + I/O port A reset + 0 + 1 + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + CRCRST + CRC reset + 12 + 1 + + + DMARST + DMA reset + 0 + 1 + + + + + APBRSTR1 + APBRSTR1 + APB peripheral reset register + 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + LPTIMRST + Low Power Timer reset + 31 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + DBGRST + Debug support reset + 27 + 1 + + + I2CRST + I2C reset + 21 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + TIM3RST + TIM3 timer reset + 1 + 1 + + + + + APBRSTR2 + APBRSTR2 + APB peripheral reset register + 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + COMP2RST + COMP2 reset + 22 + 1 + + + COMP1RST + COMP1 reset + 21 + 1 + + + ADCRST + ADC reset + 20 + 1 + + + TIM17RST + TIM17 timer reset + 18 + 1 + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + TIM14RST + TIM14 timer reset + 15 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SYSCFGRST + SYSCFG and COMP + reset + 0 + 1 + + + + + IOPENR + IOPENR + GPIO clock enable register + 0x34 + 0x20 + read-write + 0x00000000 + + + GPIOFEN + I/O port F clock enable + 5 + 1 + + + GPIOBEN + I/O port B clock enable + 1 + 1 + + + GPIOAEN + I/O port A clock enable + 0 + 1 + + + + + AHBENR + AHBENR + AHB peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + CRCEN + CRC clock enable + 12 + 1 + + + SRAMEN + SRAM memory interface clock + enable + 9 + 1 + + + FLASHEN + Flash memory interface clock + enable + 8 + 1 + + + DMAEN + DMA clock enable + 0 + 1 + + + + + APBENR1 + APBENR1 + APB peripheral clock enable register + 1 + 0x3C + 0x20 + read-write + 0x00000000 + + + LPTIMEN + LPTIM clock enable + 31 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + DBGEN + Debug support clock enable + 27 + 1 + + + I2CEN + I2C clock enable + 21 + 1 + + + USART2EN + USART2 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0x20 + read-write + 0x00000000 + + + AFSEL7 + Alternate function selection for port x + bit y (y = 0..7) + 28 + 4 + + + AFSEL6 + Alternate function selection for port x + bit y (y = 0..7) + 24 + 4 + + + AFSEL5 + Alternate function selection for port x + bit y (y = 0..7) + 20 + 4 + + + AFSEL4 + Alternate function selection for port x + bit y (y = 0..7) + 16 + 4 + + + AFSEL3 + Alternate function selection for port x + bit y (y = 0..7) + 12 + 4 + + + AFSEL2 + Alternate function selection for port x + bit y (y = 0..7) + 8 + 4 + + + AFSEL1 + Alternate function selection for port x + bit y (y = 0..7) + 4 + 4 + + + AFSEL0 + Alternate function selection for port x + bit y (y = 0..7) + 0 + 4 + + + + + AFRH + AFRH + GPIO alternate function high + register + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + Alternate function selection for port x + bit y (y = 8..15) + 28 + 4 + + + AFSEL14 + Alternate function selection for port x + bit y (y = 8..15) + 24 + 4 + + + AFSEL13 + Alternate function selection for port x + bit y (y = 8..15) + 20 + 4 + + + AFSEL12 + Alternate function selection for port x + bit y (y = 8..15) + 16 + 4 + + + AFSEL11 + Alternate function selection for port x + bit y (y = 8..15) + 12 + 4 + + + AFSEL10 + Alternate function selection for port x + bit y (y = 8..15) + 8 + 4 + + + AFSEL9 + Alternate function selection for port x + bit y (y = 8..15) + 4 + 4 + + + AFSEL8 + Alternate function selection for port x + bit y (y = 8..15) + 0 + 4 + + + + + BRR + BRR + port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR8 + Port Reset bit + 8 + 1 + + + BR7 + Port Reset bit + 7 + 1 + + + BR6 + Port Reset bit + 6 + 1 + + + BR5 + Port Reset bit + 5 + 1 + + + BR4 + Port Reset bit + 4 + 1 + + + BR3 + Port Reset bit + 3 + 1 + + + BR2 + Port Reset bit + 2 + 1 + + + BR1 + Port Reset bit + 1 + 1 + + + BR0 + Port Reset bit + 0 + 1 + + + + + + + GPIOF + 0x50001400 + + + EXTI + External interrupt/event + controller + EXTI + 0x40021800 + + 0x0 + 0x400 + registers + + + PVD + PVD Interrupt through EXTI Lines 16 + 1 + + + EXTI0_1 + EXTI Line 0 and 1 Interrupt + 5 + + + EXTI2_3 + EXTI Line 2 and 3 Interrupt + 6 + + + EXTI4_15 + EXTI Line 4 to 15 Interrupt + 7 + + + + RTSR + RTSR + EXTI rising trigger selection + register + 0x0 + 0x20 + read-write + 0x00000000 + + + RT18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + RT17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + RT16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + RT15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + RT14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + RT13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + RT12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + RT11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + RT10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + RT9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + RT8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + RT7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + RT6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + RT5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + RT4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + RT3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + RT2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + RT1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + RT0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + + + FTSR + FTSR + EXTI falling trigger selection + register + 0x4 + 0x20 + read-write + 0x00000000 + + + FT18 + Falling trigger event configuration bit + of Configurable Event input + 18 + 1 + + + FT17 + Falling trigger event configuration bit + of Configurable Event input + 17 + 1 + + + FT16 + Falling trigger event configuration bit + of Configurable Event input + 16 + 1 + + + FT15 + Falling trigger event configuration bit + of Configurable Event input + 15 + 1 + + + FT14 + Falling trigger event configuration bit + of Configurable Event input + 14 + 1 + + + FT13 + Falling trigger event configuration bit + of Configurable Event input + 13 + 1 + + + FT12 + Falling trigger event configuration bit + of Configurable Event input + 12 + 1 + + + FT11 + Falling trigger event configuration bit + of Configurable Event input + 11 + 1 + + + FT10 + Falling trigger event configuration bit + of Configurable Event input + 10 + 1 + + + FT9 + Falling trigger event configuration bit + of Configurable Event input + 9 + 1 + + + FT8 + Falling trigger event configuration bit + of Configurable Event input + 8 + 1 + + + FT7 + Falling trigger event configuration bit + of Configurable Event input + 7 + 1 + + + FT6 + Falling trigger event configuration bit + of Configurable Event input + 6 + 1 + + + FT5 + Falling trigger event configuration bit + of Configurable Event input + 5 + 1 + + + FT4 + Falling trigger event configuration bit + of Configurable Event input + 4 + 1 + + + FT3 + Falling trigger event configuration bit + of Configurable Event input + 3 + 1 + + + FT2 + Falling trigger event configuration bit + of Configurable Event input + 2 + 1 + + + FT1 + Falling trigger event configuration bit + of Configurable Event input + 1 + 1 + + + FT0 + Falling trigger event configuration bit + of Configurable Event input + 0 + 1 + + + + + SWIER + SWIER + EXTI software interrupt event + register + 0x8 + 0x20 + read-write + 0x00000000 + + + SWI18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + SWI17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + SWI16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + SWI15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + SWI14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + SWI13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + SWI12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + SWI11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + SWI10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + SWI9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + SWI8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + SWI7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + SWI6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + SWI5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + SWI4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + SWI3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + SWI2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + SWI1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + SWI0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + + + PR + PR + EXTI pending + register + 0xC + 0x20 + read-write + 0x00000000 + + + PR18 + configurable event inputs x rising edge + Pending bit. + 18 + 1 + + + PR17 + configurable event inputs x rising edge + Pending bit. + 17 + 1 + + + PR16 + configurable event inputs x rising edge + Pending bit. + 16 + 1 + + + PR15 + configurable event inputs x rising edge + Pending bit. + 15 + 1 + + + PR14 + configurable event inputs x rising edge + Pending bit. + 14 + 1 + + + PR13 + configurable event inputs x rising edge + Pending bit + 13 + 1 + + + PR12 + configurable event inputs x rising edge + Pending bit. + 12 + 1 + + + PR11 + configurable event inputs x rising edge + Pending bit. + 11 + 1 + + + PR10 + configurable event inputs x rising edge + Pending bit. + 10 + 1 + + + PR9 + configurable event inputs x rising edge + Pending bit. + 9 + 1 + + + PR8 + configurable event inputs x rising edge + Pending bit. + 8 + 1 + + + PR7 + configurable event inputs x rising edge + Pending bit. + 7 + 1 + + + PR6 + configurable event inputs x rising edge + Pending bit. + 6 + 1 + + + PR5 + configurable event inputs x rising edge + Pending bit. + 5 + 1 + + + PR4 + configurable event inputs x rising edge + Pending bit. + 4 + 1 + + + PR3 + configurable event inputs x rising edge + Pending bit. + 3 + 1 + + + PR2 + configurable event inputs x rising edge + Pending bit. + 2 + 1 + + + PR1 + configurable event inputs x rising edge + Pending bit. + 1 + 1 + + + PR0 + configurable event inputs x rising edge + Pending bit. + 0 + 1 + + + + + EXTICR1 + EXTICR1 + EXTI external interrupt selection + register + 0x60 + 0x20 + read-write + 0x00000000 + + + EXTI3 + GPIO port selection + 24 + 2 + + + EXTI2 + GPIO port selection + 16 + 2 + + + EXTI1 + GPIO port selection + 8 + 2 + + + EXTI0 + GPIO port selection + 0 + 2 + + + + + EXTICR2 + EXTICR2 + EXTI external interrupt selection + register + 0x64 + 0x20 + read-write + 0x00000000 + + + EXTI7 + GPIO port selection + 24 + 1 + + + EXTI6 + GPIO port selection + 16 + 1 + + + EXTI5 + GPIO port selection + 8 + 1 + + + EXTI4 + GPIO port selection + 0 + 2 + + + + + EXTICR3 + EXTICR3 + EXTI external interrupt selection + register + 0x68 + 0x20 + read-write + 0x00000000 + + + EXTI8 + GPIO port selection + 0 + 1 + + + + + IMR + IMR + EXTI CPU wakeup with interrupt mask + register + 0x80 + 0x20 + read-write + 0xFFF80000 + + + IM29 + CPU wakeup with interrupt mask on event + input + 29 + 1 + + + IM19 + CPU wakeup with interrupt mask on event + input + 19 + 1 + + + IM18 + CPU wakeup with interrupt mask on event + input + 18 + 1 + + + IM17 + CPU wakeup with interrupt mask on event + input + 17 + 1 + + + IM16 + CPU wakeup with interrupt mask on event + input + 16 + 1 + + + IM15 + CPU wakeup with interrupt mask on event + input + 15 + 1 + + + IM14 + CPU wakeup with interrupt mask on event + input + 14 + 1 + + + IM13 + CPU wakeup with interrupt mask on event + input + 13 + 1 + + + IM12 + CPU wakeup with interrupt mask on event + input + 12 + 1 + + + IM11 + CPU wakeup with interrupt mask on event + input + 11 + 1 + + + IM10 + CPU wakeup with interrupt mask on event + input + 10 + 1 + + + IM9 + CPU wakeup with interrupt mask on event + input + 9 + 1 + + + IM8 + CPU wakeup with interrupt mask on event + input + 8 + 1 + + + IM7 + CPU wakeup with interrupt mask on event + input + 7 + 1 + + + IM6 + CPU wakeup with interrupt mask on event + input + 6 + 1 + + + IM5 + CPU wakeup with interrupt mask on event + input + 5 + 1 + + + IM4 + CPU wakeup with interrupt mask on event + input + 4 + 1 + + + IM3 + CPU wakeup with interrupt mask on event + input + 3 + 1 + + + IM2 + CPU wakeup with interrupt mask on event + input + 2 + 1 + + + IM1 + CPU wakeup with interrupt mask on event + input + 1 + 1 + + + IM0 + CPU wakeup with interrupt mask on event + input + 0 + 1 + + + + + EMR + EMR + EXTI CPU wakeup with event mask + register + 0x84 + 0x20 + read-write + 0x00000000 + + + EM29 + CPU wakeup with event mask on event + input + 29 + 1 + + + EM19 + CPU wakeup with event mask on event + input + 19 + 1 + + + EM18 + CPU wakeup with event mask on event + input + 18 + 1 + + + EM17 + CPU wakeup with event mask on event + input + 17 + 1 + + + EM16 + CPU wakeup with event mask on event + input + 16 + 1 + + + EM15 + CPU wakeup with event mask on event + input + 15 + 1 + + + EM14 + CPU wakeup with event mask on event + input + 14 + 1 + + + EM13 + CPU wakeup with event mask on event + input + 13 + 1 + + + EM12 + CPU wakeup with event mask on event + input + 12 + 1 + + + EM11 + CPU wakeup with event mask on event + input + 11 + 1 + + + EM10 + CPU wakeup with event mask on event + input + 10 + 1 + + + EM9 + CPU wakeup with event mask on event + input + 9 + 1 + + + EM8 + CPU wakeup with event mask on event + input + 8 + 1 + + + EM7 + CPU wakeup with event mask on event + input + 7 + 1 + + + EM6 + CPU wakeup with event mask on event + input + 6 + 1 + + + EM5 + CPU wakeup with event mask on event + input + 5 + 1 + + + EM4 + CPU wakeup with event mask on event + input + 4 + 1 + + + EM3 + CPU wakeup with event mask on event + input + 3 + 1 + + + EM2 + CPU wakeup with event mask on event + input + 2 + 1 + + + EM1 + CPU wakeup with event mask on event + input + 1 + 1 + + + EM0 + CPU wakeup with event mask on event + input + 0 + 1 + + + + + + + LPTIM + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + ARRM + Autoreload match + 1 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + PRELOAD + Registers update mode + 22 + 1 + + + PRESC + Clock prescaler + 9 + 3 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + Reset after read enable + 4 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global Interrupt + 27 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C0 + + + ABRRQ + Automate baudrate detection requeset + 12 + 1 + write-only + + + ABRE + Automate baudrate detection error flag + 11 + 1 + read-only + + + ABRF + Automate baudrate detection flag + 10 + 1 + read-only + + + CTS + CTS flag + 9 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NE + Noise error flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + 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bits + 12 + 2 + + + CLKEN + Clock enable + 11 + 1 + + + CPOL + Clock polarity + 10 + 1 + + + CPHA + Clock phase + 9 + 1 + + + LBCL + Last bit clock pulse + 8 + 1 + + + ADD + Address of the USART node + 0 + 4 + + + + + CR3 + CR3 + Control register 3 + 0x14 + 0x20 + read-write + 0x0000 + + + ABRMOD + Auto baudrate mode + 13 + 2 + + + ABREN + Auto baudrate enable + 12 + 1 + + + OVER8 + Oversampling mode + 11 + 1 + + + CTSIE + CTS interrupt enable + 10 + 1 + + + CTSE + CTS enable + 9 + 1 + + + RTSE + RTS enable + 8 + 1 + + + DMAT + DMA enable transmitter + 7 + 1 + + + DMAR + DMA enable receiver + 6 + 1 + + + HDSEL + Half-duplex selection + 3 + 1 + + + IRLP + IrDA low-power + 2 + 1 + + + IREN + IrDA mode enable + 1 + 1 + + + EIE + Error interrupt enable + 0 + 1 + + + + + + + USART2 + 0x40004400 + + USART2 + USART2 global Interrupt + 28 + + + + RTC + Real time clock + RTC + 0x40002800 + + 0x0 + 0x400 + registers + + + RTC + RTC Interrupt through EXTI Lines 19 + 2 + + + + CRH + CRH + RTC Control Register High + 0x0 + 0x20 + read-write + 0x00000000 + + + OWIE + Overflow interrupt Enable + 2 + 1 + + + ALRIE + Alarm interrupt Enable + 1 + 1 + + + SECIE + Second interrupt Enable + 0 + 1 + + + + + CRL + CRL + RTC Control Register Low + 0x4 + 0x20 + 0x00000020 + + + RTOFF + RTC operation OFF + 5 + 1 + read-only + + + CNF + Configuration Flag + 4 + 1 + read-write + + + RSF + Registers Synchronized + Flag + 3 + 1 + read-write + + + OWF + Overflow Flag + 2 + 1 + read-write + + + ALRF + Alarm Flag + 1 + 1 + read-write + + + SECF + Second Flag + 0 + 1 + read-write + + + + + PRLH + PRLH + RTC Prescaler Load Register + High + 0x8 + 0x20 + write-only + 0x00000000 + + + PRLH + RTC Prescaler Load Register + High + 0 + 4 + + + + + PRLL + PRLL + RTC Prescaler Load Register + Low + 0xC + 0x20 + write-only + 0x8000 + + + PRLL + RTC Prescaler Divider Register + Low + 0 + 16 + + + + + DIVH + DIVH + RTC Prescaler Divider Register + High + 0x10 + 0x20 + read-only + 0x00000000 + + + DIVH + RTC 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+ + + + + + + IWDG + Independent watchdog + IWDG + 0x40003000 + + 0x0 + 0x400 + registers + + + + KR + KR + Key register (IWDG_KR) + 0x0 + 0x20 + write-only + 0x00000000 + + + KEY + Key value + 0 + 16 + + + + + PR + PR + Prescaler register (IWDG_PR) + 0x4 + 0x20 + read-write + 0x00000000 + + + PR + Prescaler divider + 0 + 3 + + + + + RLR + RLR + Reload register (IWDG_RLR) + 0x8 + 0x20 + read-write + 0x00000FFF + + + RL + Watchdog counter reload + value + 0 + 12 + + + + + SR + SR + Status register (IWDG_SR) + 0xC + 0x20 + read-only + 0x00000000 + + + WVU + Watchdog counter window value update + 2 + 1 + + + RVU + Watchdog counter reload value + update + 1 + 1 + + + PVU + Watchdog prescaler value + update + 0 + 1 + + + + + WINR + WINR + Window register (IWDG_SR) + 0x10 + 0x20 + read-only + 0x00000000 + + + WIN + window counter + 0 + 12 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window WatchDog Interrupt + 0 + + + + CR + CR + Control register (WWDG_CR) + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + Configuration register + (WWDG_CFR) + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early Wakeup Interrupt + 9 + 1 + + + WDGTB + Timer Base + 7 + 2 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register (WWDG_SR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early Wakeup Interrupt flag + 0 + 1 + + + + + + + TIM1 + Advanced timer + TIM + 0x40012C00 + + 0x0 + 0x400 + registers + + + TIM1_BRK_UP_TRG_COM + TIM1 Break, Update, Trigger and Commutation Interrupt + 13 + + + TIM1_CC + TIM1 Capture Compare Interrupt + 14 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Clock division + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + CMS + Center-aligned mode + selection + 5 + 2 + + + DIR + Direction + 4 + 1 + + + OPM + One-pulse mode + 3 + 1 + + + URS + Update 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read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 32 + + + + + + + TIM17 + 0x40014800 + + TIM17 + TIM17 global Interrupt + 22 + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x30 + registers + + + + CFGR1 + CFGR1 + SYSCFG configuration register + 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + I2C_PF1_ANF + Analog filter enable control driving capability + activation bits PF1 + 30 + 1 + + + I2C_PF0_ANF + Analog filter enable control driving capability + activation bits PF0 + 29 + 1 + + + I2C_PB8_ANF + Analog filter enable control driving capability + activation bits PB8 + 28 + 1 + + + I2C_PB7_ANF + Analog filter enable control driving capability + activation bits PB7 + 27 + 1 + + I2C_PB6_ANF + Analog filter enable control driving capability + activation bits PB6 + 26 + 1 + + + I2C_PA12_ANF + Analog filter enable control driving capability + activation bits PA12 + 25 + 1 + + + I2C_PA11_ANF + Analog filter enable control driving capability + activation bits PA11 + 24 + 1 + + + I2C_PA10_ANF + Analog filter enable control driving capability + activation bits PA10 + 23 + 1 + + + I2C_PA9_ANF + Analog filter enable control driving capability + activation bits PA9 + 22 + 1 + + + I2C_PA8_ANF + Analog filter enable control driving capability + activation bits PA8 + 21 + 1 + + + I2C_PA7_ANF + Analog filter enable control driving capability + activation bits PA7 + 20 + 1 + + + I2C_PA3_ANF + Analog filter enable control driving capability + activation bits PA3 + 19 + 1 + + + I2C_PA2_ANF + Analog filter enable control driving capability + activation bits PA2 + 18 + 1 + + + MEM_MODE + Memory mapping selection + bits + 0 + 2 + + + + + CFGR2 + CFGR2 + SYSCFG configuration register + 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + ETR_SRC_TIM1 + TIM1 ETR source selection + 9 + 2 + + + COMP2_BRK_TIM17 + COMP2 is enable to input of TIM17 break + 8 + 1 + + + COMP1_BRK_TIM17 + COMP1 is enable to input of TIM17 break + 7 + 1 + + + COMP2_BRK_TIM16 + COMP2 is enable to input of TIM16 break + 6 + 1 + + + COMP1_BRK_TIM16 + COMP1 is enable to input of TIM16 break + 5 + 1 + + + COMP2_BRK_TIM1 + COMP2 is enable to input of TIM1 break + 4 + 1 + + + COMP1_BRK_TIM1 + COMP1 is enable to input of TIM1 break + 3 + 1 + + + PVD_LOCK + PVD lock enable bit + 2 + 1 + + + LOCKUP_LOCK + Cortex-M0+ LOCKUP bit enable + bit + 0 + 1 + + + + + CFGR3 + CFGR3 + SYSCFG configuration register + 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + DMA3_MAP + DMA channel3 requeset selection + 16 + 5 + + + DMA2_MAP + DMA channel2 requeset selection + 8 + 5 + + + DMA1_MAP + DMA channel1 requeset selection + 0 + 5 + + + + + + + DMA + Direct memory access + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA_Channel1 + DMA Channel 1 Interrupt + 9 + + + DMA_Channel2_3 + DMA Channel 2 and Channel 3 Interrupt + 10 + + + + ISR + ISR + DMA interrupt status register + (DMA_ISR) + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + (DMA_IFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + + + CCR1 + CCR1 + DMA channel configuration register + (DMA_CCR) + 0x8 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel 1 number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + DMA channel configuration register + (DMA_CCR) + 0x1C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + DMA channel configuration register + (DMA_CCR) + 0x30 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH global Interrupt + 3 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 1 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEY + Flash key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + read-write + 0x00000000 + + + BSY + Busy + 16 + 1 + + + OPTVERR + Option and Engineering bits loading + validity error + 15 + 1 + + + WRPERR + Write protected error + 4 + 1 + + + EOP + End of operation + 0 + 1 + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + OBL_LAUNCH + Force the option byte + loading + 27 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + EOPIE + End of operation interrupt + enable + 24 + 1 + + + PGTSTRT + Flash main memory program start + 19 + 1 + + + OPTSTRT + Option byte program start + 17 + 1 + + + SER + Sector erase + 11 + 1 + + + MER + Mass erase + 2 + 1 + + + PER + Page erase + 1 + 1 + + + PG + Programming + 0 + 1 + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0x4F55B0AA + + + nBOOT1 + Boot configuration + 15 + 1 + + + NRST_MODE + NRST_MODE + 14 + 1 + + + WWDG_SW + Window watchdog selection + 13 + 1 + + + IDWG_SW + Independent watchdog + selection + 12 + 1 + + + BORF_LEV + These bits contain the VDD supply level + threshold that activates the reset + 9 + 3 + + + BOREN + BOR reset Level + 8 + 1 + + + RDP + Read Protection + 0 + 8 + + + + + SDKR + SDKR + Flash SDK address + register + 0x24 + 0x20 + read-write + 0xFFE0001F + + + SDK_END + SDK area end address + 8 + 5 + + + SDK_STRT + SDK area start address + 0 + 5 + + + + + WRPR + WRPR + Flash WRP address + register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + WRP + WRP address + 0 + 16 + + + + + STCR + STCR + Flash sleep time config + register + 0x90 + 0x20 + read-write + 0x00006400 + + + SLEEP_TIME + FLash sleep time configuration(counter based on HSI_10M) + 8 + 8 + + + SLEEP_EN + FLash sleep enable + 0 + 1 + + + + + TS0 + TS0 + Flash TS0 + register + 0x100 + 0x20 + read-write + 0x000000B4 + + + TS0 + FLash TS0 register + 0 + 8 + + + + + TS1 + TS1 + Flash TS1 + register + 0x104 + 0x20 + read-write + 0x000001B0 + + + TS1 + FLash TS1 register + 0 + 9 + + + + + TS2P + TS2P + Flash TS2P + register + 0x108 + 0x20 + read-write + 0x000000B4 + + + TS2P + FLash TS2P register + 0 + 8 + + + + + TPS3 + TPS3 + Flash TPS3 + register + 0x10C + 0x20 + read-write + 0x000006C0 + + + TPS3 + FLash TPS3 register + 0 + 11 + + + + + TS3 + TS3 + Flash TS3 + register + 0x110 + 0x20 + read-write + 0x000000B4 + + + TS3 + FLash TS3 register + 0 + 8 + + + + + PERTPE + PERTPE + Flash PERTPE + register + 0x114 + 0x20 + read-write + 0x0000EA60 + + + PERTPE + FLash PERTPE register + 0 + 17 + + + + + SMERTPE + SMERTPE + Flash SMERTPE + register + 0x118 + 0x20 + read-write + 0x0000FD20 + + + SMERTPE + FLash SMERTPE register + 0 + 17 + + + + + PRGTPE + PRGTPE + Flash PRGTPE + register + 0x11C + 0x20 + read-write + 0x00008CA0 + + + PRGTPE + FLash PRGTPE register + 0 + 16 + + + + + PRETPE + PRETPE + Flash PRETPE + register + 0x120 + 0x20 + read-write + 0x000012C0 + + + PRETPE + FLash PRETPE register + 0 + 13 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global Interrupt + 25 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave selection + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + SLVFM + Slave fast mode enable + 15 + 1 + + + LDMA_TX + Last DAM Transmit(TX) + 14 + 1 + + + LDMA_RX + Last DAM Transmit(RX) + 13 + 1 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + DS + Data length + + 11 + 1 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + + + I2C + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 global Interrupt + 23 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + LAST + DMA last transfer + 12 + 1 + + + DMAEN + DMA requests enable + 11 + 1 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADD + Interface address + 1 + 7 + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DR + 8-bit data register + 0 + 8 + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + + + + CR + CR + Debug MCU Configuration + Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + + + APB_FZ1 + APB_FZ1 + APB Freeze Register1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER3_STOP + Debug Timer 3 stopped when Core is + halted + 1 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is + halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core + is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when + Core is halted + 12 + 1 + + + DBG_LPTIM_STOP + Debug LPTIM stopped when Core is + halted + 31 + 1 + + + + + APB_FZ2 + APB_FZ2 + APB Freeze Register2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIMER1_STOP + Debug Timer 1 stopped when Core is + halted + 11 + 1 + + + DBG_TIMER14_STOP + Debug Timer 14 stopped when Core is + halted + 15 + 1 + + + DBG_TIMER16_STOP + Debug Timer 16 stopped when Core is + halted + 17 + 1 + + + DBG_TIMER17_STOP + Debug Timer 17 stopped when Core is + halted + 18 + 1 + + + + + + + diff --git a/Misc/py32f030xx.svd b/Misc/SVD/py32f030xx.svd similarity index 96% rename from Misc/py32f030xx.svd rename to Misc/SVD/py32f030xx.svd index 3f41e8a..07f1dee 100644 --- a/Misc/py32f030xx.svd +++ b/Misc/SVD/py32f030xx.svd @@ -1,11582 +1,11582 @@ - - - - Puya - Puya - PY32F0xx_DFP - - PY32F0 - 1.0.0 - Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. - - - - CM0+ - r0p1 - little - false - false - 4 - false - - - - 8 - 32 - 32 - read-write - 0x00000000 - 0xFFFFFFFF - - - ADC - Analog to Digital Converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC_COMP - ADC and COMP Interrupt through EXTI Lines 17 and 18 - 12 - - - - ISR - ISR - ADC interrupt and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - AWD - ADC analog watchdog flag - 7 - 1 - - - OVR - ADC group regular overrun - flag - 4 - 1 - - - EOSEQ - ADC group regular end of sequence - conversions flag - 3 - 1 - - - EOC - ADC group regular end of unitary - conversion flag - 2 - 1 - - - EOSMP - ADC group regular end of sampling - flag - 1 - 1 - - - - - IER - IER - ADC interrupt enable register - 0x4 - 0x20 - read-write - 0x00000000 - - - AWDIE - ADC analog watchdog - interrupt - 7 - 1 - - - OVRIE - ADC group regular overrun - interrupt - 4 - 1 - - - EOSEQIE - ADC group regular end of sequence - conversions interrupt - 3 - 1 - - - EOCIE - ADC group regular end of unitary - conversion interrupt - 2 - 1 - - - EOSMPIE - ADC group regular end of sampling - interrupt - 1 - 1 - - - - - CR - CR - ADC control register - 0x8 - 0x20 - read-write - 0x00000000 - - - ADCAL - ADC group regular conversion - calibration - 31 - 1 - - - ADSTP - ADC group regular conversion - stop - 4 - 1 - - - ADSTART - ADC group regular conversion - start - 2 - 1 - - - ADEN - ADC enable - 0 - 1 - - - - - CFGR1 - CFGR1 - ADC configuration register 1 - 0xC - 0x20 - read-write - 0x00000000 - - - AWDCH - ADC analog watchdog monitored channel - selection - 26 - 4 - - - AWDEN - ADC analog watchdog enable on scope - ADC group regular - 23 - 1 - - - AWDSGL - ADC analog watchdog monitoring a - single channel or all channels - 22 - 1 - - - DISCEN - ADC group regular sequencer - discontinuous mode - 16 - 1 - - - WAIT - Wait conversion mode - 14 - 1 - - - CONT - ADC group regular continuous conversion - mode - 13 - 1 - - - OVRMOD - ADC group regular overrun - configuration - 12 - 1 - - - EXTEN - ADC group regular external trigger - polarity - 10 - 2 - - - EXTSEL - ADC group regular external trigger - source - 6 - 3 - - - ALIGN - ADC data alignement - 5 - 1 - - - RESSEL - ADC data resolution - 3 - 2 - - - SCANDIR - Scan sequence direction - 2 - 1 - - - DMACFG - ADC DMA transfer - configuration - 1 - 1 - - - DMAEN - ADC DMA transfer enable - 0 - 1 - - - - - CFGR2 - CFGR2 - ADC configuration register 2 - 0x10 - 0x20 - read-write - 0x00000000 - - - CKMODE - ADC clock mode - 28 - 4 - - - - - SMPR - SMPR - ADC sampling time register - 0x14 - 0x20 - read-write - 0x00000000 - - - SMP - Sampling time selection - 0 - 3 - - - - - TR - TR - ADC analog watchdog 1 threshold register - 0x20 - 0x20 - read-write - 0x0FFF0000 - - - HT - ADC analog watchdog threshold - high - 16 - 12 - - - LT - ADC analog watchdog threshold - low - 0 - 12 - - - - - CHSELR - CHSELR - ADC group regular sequencer register - 0x28 - 0x20 - read-write - 0x0FFF0000 - - - CHSEL12 - Channel-12 selection - 12 - 1 - - - CHSEL11 - Channel-11 selection - 11 - 1 - - - CHSEL9 - Channel-9 selection - 9 - 1 - - - CHSEL8 - Channel-8 selection - 8 - 1 - - - CHSEL7 - Channel-7 selection - 7 - 1 - - - CHSEL6 - Channel-6 selection - 6 - 1 - - - CHSEL5 - Channel-5 selection - 5 - 1 - - - CHSEL4 - Channel-4 selection - 4 - 1 - - - CHSEL3 - Channel-3 selection - 3 - 1 - - - CHSEL2 - Channel-2 selection - 2 - 1 - - - CHSEL1 - Channel-1 selection - 1 - 1 - - - CHSEL0 - Channel-0 selection - 0 - 1 - - - - - DR - DR - ADC group regular data register - 0x40 - 0x20 - read-only - 0x00000000 - - - DATA - ADC group regular conversion - data - 0 - 16 - - - - - CCSR - CCSR - ADC calibration configuration and status register - 0x44 - 0x20 - read-write - 0x00000000 - - - CALON - Calibration flag - 31 - 1 - read-only - - - CALFAIL - Calibration fail flag - 30 - 1 - - - CALSET - Calibration factor selection - 15 - 1 - - - CALSMP - Calibration sample time selection - 12 - 2 - - - CALSEL - Calibration contents selection - 11 - 1 - - - - - CALRR1 - CALRR1 - ADC calibration result register 1 - 0x48 - 0x20 - read-only - 0x00000000 - - - CALBOUT - offset result - 16 - 7 - - - CALC5OUT - C5 result - 8 - 8 - - - CALC4OUT - C4 result - 0 - 8 - - - - - CALRR2 - CALRR2 - ADC calibration result register 2 - 0x4C - 0x20 - read-only - 0x00000000 - - - CALC3OUT - C3 result - 24 - 8 - - - CALC2OUT - C2 result - 16 - 8 - - - CALC1OUT - C1 result - 8 - 8 - - - CALC0OUT - C0 result - 0 - 8 - - - - - CALFIR1 - CALFIR1 - ADC calibration factor input register 1 - 0x50 - 0x20 - read-write - 0x00000000 - - - CALBIO - Calibration offset factor input - 16 - 7 - - - CALC5IO - Calibration C5 factor input - 8 - 8 - - - CALC4IO - Calibration C4 factor input - 0 - 8 - - - - - CALFIR2 - CALFIR2 - ADC calibration factor input register 2 - 0x54 - 0x20 - read-write - 0x00000000 - - - CALC3IO - Calibration C3 factor input - 24 - 8 - - - CALC2IO - Calibration C2 factor input - 16 - 8 - - - CALC1IO - Calibration C1 factor input - 8 - 8 - - - CALC0IO - Calibration C0 factor input - 0 - 8 - - - - - CCR - CCR - ADC common configuration register - 0x308 - 0x20 - read-write - 0x00000000 - - - TSEN - Temperature sensor enable - 23 - 1 - - - VREFEN - VREFINT enable - 22 - 1 - - - - - - - COMP1 - Comparator - COMP - 0x40010200 - - 0x0 - 0x10 - registers - - - - CSR - CSR - COMP control and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - LOCK - CSR register lock - 31 - 1 - - - COMP_OUT - Comparator output status - 30 - 1 - - - PWRMODE - Comparator power mode - selector - 18 - 2 - - - HYST - Comparator hysteresis enable - selector - 16 - 1 - - - POLARITY - Comparator polarity - selector - 15 - 1 - - - WINMODE - Comparator non-inverting input - selector for window mode - 11 - 1 - - - INPSEL - Comparator signal selector for - non-inverting input - 8 - 2 - - - INMSEL - Comparator signal selector for - inverting input INM - 4 - 4 - - - SCALER_EN - SCALER enable bit - 1 - 1 - - - COMP_EN - COMP enable bit - 0 - 1 - - - - - FR - FR - Comparator Filter - register - 0x4 - 0x20 - read-write - 0x00000000 - - - FLTCNT - Comparator filter and counter - 16 - 16 - - - FLTEN - Filter enable bit - 0 - 1 - - - - - - - COMP2 - Comparator - COMP - 0x40010210 - - 0x0 - 0x10 - registers - - - - CSR - CSR - COMP control and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - LOCK - CSR register lock - 31 - 1 - - - COMP_OUT - Comparator output status - 30 - 1 - - - PWRMODE - Comparator power mode - selector - 18 - 2 - - - POLARITY - Comparator polarity - selector - 15 - 1 - - - WINMODE - Comparator non-inverting input - selector for window mode - 11 - 1 - - - INPSEL - Comparator signal selector for - non-inverting input - 8 - 2 - - - INMSEL - Comparator signal selector for - inverting input INM - 4 - 4 - - - COMP_EN - COMP enable bit - 0 - 1 - - - - - FR - FR - Comparator Filter - register - 0x4 - 0x20 - read-write - 0x00000000 - - - FLTCNT - Comparator filter and counter - 16 - 16 - - - FLTEN - Filter enable bit - 0 - 1 - - - - - - - RCC - Reset and clock control - RCC - 0x40021000 - - 0x0 - 0x400 - registers - - - RCC - RCC global Interrupt - 4 - - - - CR - CR - Clock control register - 0x0 - 0x20 - read-write - 0x00000100 - - - PLLRDY - PLL clock ready flag - 25 - 1 - - - PLLON - PLL enable - 24 - 1 - - - CSSON - Clock security system - enable - 19 - 1 - - - HSEBYP - HSE crystal oscillator - bypass - 18 - 1 - - - HSERDY - HSE clock ready flag - 17 - 1 - - - HSEON - HSE clock enable - 16 - 1 - - - HSIDIV - HSI16 clock division - factor - 11 - 3 - - - HSIRDY - HSI16 clock ready flag - 10 - 1 - - - HSIKERON - HSI16 always enable for peripheral - kernels - 9 - 1 - - - HSION - HSI16 clock enable - 8 - 1 - - - - - ICSCR - ICSCR - Internal clock sources calibration - register - 0x4 - 0x20 - 0x10000000 - - - LSI_STARTUP - LSI startup time - 26 - 2 - read-write - - - LSI_TRIM - LSI clock trimming - 16 - 9 - read-write - - - HSI_FS - HSI frequency selection - 13 - 3 - read-write - - - HSI_TRIM - HSI clock trimming - 0 - 13 - read-write - - - - - CFGR - CFGR - Clock configuration register - 0x8 - 0x20 - 0x00000000 - - - MCOPRE - Microcontroller clock output - prescaler - 28 - 3 - read-write - - - MCOSEL - Microcontroller clock - output - 24 - 3 - read-write - - - PPRE - APB prescaler - 12 - 3 - read-write - - - HPRE - AHB prescaler - 8 - 4 - read-write - - - SWS - System clock switch status - 3 - 3 - read-only - - - SW - System clock switch - 0 - 3 - read-write - - - - - PLLCFGR - PLLCFGR - PLL configuration register - 0xC - 0x20 - 0x00000000 - - - PLLSRC - PLL clock source selection - 0 - 1 - read-write - - - - - ECSCR - ECSCR - External clock source control register - 0x10 - 0x20 - 0x00000000 - - - LSE_DRIVER - LSE clock driver selection - 16 - 2 - read-write - - - HSE_FREQ - HSE clock freqency selection - 2 - 2 - read-write - - - - - CIER - CIER - Clock interrupt enable - register - 0x18 - 0x20 - read-write - 0x00000000 - - - PLLRDYIE - PLL ready interrupt enable - 5 - 1 - - - HSERDYIE - HSE ready interrupt enable - 4 - 1 - - - HSIRDYIE - HSI ready interrupt enable - 3 - 1 - - - LSERDYIE - LSE ready interrupt enable - 1 - 1 - - - LSIRDYIE - LSI ready interrupt enable - 0 - 1 - - - - - CIFR - CIFR - Clock interrupt flag register - 0x1C - 0x20 - read-only - 0x00000000 - - - LSECSSF - LSE clock secure system interrupt flag - 9 - 1 - - - CSSF - HSE clock secure system interrupt flag - 8 - 1 - - - PLLRDYF - PLL ready interrupt flag - 5 - 1 - - - HSERDYF - HSE ready interrupt flag - 4 - 1 - - - HSIRDYF - HSI ready interrupt flag - 3 - 1 - - - LSERDYF - LSE ready interrupt flag - 1 - 1 - - - LSIRDYF - LSI ready interrupt flag - 0 - 1 - - - - - CICR - CICR - Clock interrupt clear register - 0x20 - 0x20 - write-only - 0x00000000 - - - LSECSSC - LSE clock secure system interrupt flag clear - 9 - 1 - - - CSSC - clock secure system interrupt flag clear - 8 - 1 - - - PLLRDYC - PLL ready interrupt clear - 5 - 1 - - - HSERDYC - HSE ready interrupt clear - 4 - 1 - - - HSIRDYC - HSI ready interrupt clear - 3 - 1 - - - LSERDYC - LSE ready interrupt clear - 1 - 1 - - - LSIRDYC - LSI ready interrupt clear - 0 - 1 - - - - - IOPRSTR - IOPRSTR - GPIO reset register - 0x24 - 0x20 - read-write - 0x00000000 - - - GPIOFRST - I/O port F reset - 5 - 1 - - - GPIOBRST - I/O port B reset - 1 - 1 - - - GPIOARST - I/O port A reset - 0 - 1 - - - - - AHBRSTR - AHBRSTR - AHB peripheral reset register - 0x28 - 0x20 - read-write - 0x00000000 - - - CRCRST - CRC reset - 12 - 1 - - - DMARST - DMA reset - 0 - 1 - - - - - APBRSTR1 - APBRSTR1 - APB peripheral reset register - 1 - 0x2C - 0x20 - read-write - 0x00000000 - - - LPTIMRST - Low Power Timer reset - 31 - 1 - - - PWRRST - Power interface reset - 28 - 1 - - - DBGRST - Debug support reset - 27 - 1 - - - I2CRST - I2C reset - 21 - 1 - - - USART2RST - USART2 reset - 17 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - TIM3RST - TIM3 timer reset - 1 - 1 - - - - - APBRSTR2 - APBRSTR2 - APB peripheral reset register - 2 - 0x30 - 0x20 - read-write - 0x00000000 - - - LEDRST - LED reset - 23 - 1 - - - COMP2RST - COMP2 reset - 22 - 1 - - - COMP1RST - COMP1 reset - 21 - 1 - - - ADCRST - ADC reset - 20 - 1 - - - TIM17RST - TIM17 timer reset - 18 - 1 - - - TIM16RST - TIM16 timer reset - 17 - 1 - - - TIM14RST - TIM14 timer reset - 15 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - TIM1RST - TIM1 timer reset - 11 - 1 - - - SYSCFGRST - SYSCFG and COMP - reset - 0 - 1 - - - - - IOPENR - IOPENR - GPIO clock enable register - 0x34 - 0x20 - read-write - 0x00000000 - - - GPIOFEN - I/O port F clock enable - 5 - 1 - - - GPIOBEN - I/O port B clock enable - 1 - 1 - - - GPIOAEN - I/O port A clock enable - 0 - 1 - - - - - AHBENR - AHBENR - AHB peripheral clock enable - register - 0x38 - 0x20 - read-write - 0x00000000 - - - CRCEN - CRC clock enable - 12 - 1 - - - SRAMEN - SRAM memory interface clock - enable - 9 - 1 - - - FLASHEN - Flash memory interface clock - enable - 8 - 1 - - - DMAEN - DMA clock enable - 0 - 1 - - - - - APBENR1 - APBENR1 - APB peripheral clock enable register - 1 - 0x3C - 0x20 - read-write - 0x00000000 - - - LPTIMEN - LPTIM clock enable - 31 - 1 - - - PWREN - Power interface clock - enable - 28 - 1 - - - DBGEN - Debug support clock enable - 27 - 1 - - - I2CEN - I2C clock enable - 21 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - WWDGEN - WWDG clock enable - 11 - 1 - - - RTCAPBEN - RTC APB clock enable - 10 - 1 - - - TIM3EN - TIM3 timer clock enable - 1 - 1 - - - - - APBENR2 - APBENR2 - APB peripheral clock enable register - 2 - 0x40 - 0x20 - read-write - 0x00000000 - - - LEDEN - LED clock enable - 23 - 1 - - - COMP2EN - COMP2 clock enable - 22 - 1 - - - COMP1EN - COMP1 clock enable - 21 - 1 - - - ADCEN - ADC clock enable - 20 - 1 - - - TIM17EN - TIM16 timer clock enable - 18 - 1 - - - TIM16EN - TIM16 timer clock enable - 17 - 1 - - - TIM14EN - TIM14 timer clock enable - 15 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - TIM1EN - TIM1 timer clock enable - 11 - 1 - - - SYSCFGEN - SYSCFG, COMP and VREFBUF clock - enable - 0 - 1 - - - - - CCIPR - CCIPR - Peripherals independent clock configuration - register - 0x54 - 0x20 - read-write - 0x00000000 - - - LPTIM1SEL - LPTIM1 clock source - selection - 18 - 2 - - - COMP2SEL - COMP2 clock source - selection - 9 - 1 - - - COMP1SEL - COMP1 clock source - selection - 8 - 1 - - - PVDSEL - PVD detect clock source - selection - 7 - 1 - - - - - BDCR - BDCR - RTC domain control register - 0x5C - 0x20 - read-write - 0x00000000 - - - LSCOSEL - Low-speed clock output - selection - 25 - 1 - - - LSCOEN - Low-speed clock output (LSCO) - enable - 24 - 1 - - - BDRST - RTC domain software reset - 16 - 1 - - - RTCEN - RTC clock source enable - 15 - 1 - - - RTCSEL - RTC clock source selection - 8 - 2 - - - LSECSSD - LSE CSS detect - 6 - 1 - - - LSECSSON - LSE CSS enable - 5 - 1 - - - LSEBYP - LSE oscillator bypass - 2 - 1 - - - LSERDY - LSE oscillator ready - 1 - 1 - - - LSEON - LSE oscillator enable - 0 - 1 - - - - - CSR - CSR - Control/status register - 0x60 - 0x20 - read-write - 0x00000000 - - - WWDGRSTF - Window watchdog reset flag - 30 - 1 - - - IWDGRSTF - Independent window watchdog reset - flag - 29 - 1 - - - SFTRSTF - Software reset flag - 28 - 1 - - - PWRRSTF - BOR or POR/PDR flag - 27 - 1 - - - PINRSTF - Pin reset flag - 26 - 1 - - - OBLRSTF - Option byte loader reset - flag - 25 - 1 - - - RMVF - Remove reset flags - 23 - 1 - - - LSIRDY - LSI oscillator ready - 1 - 1 - - - LSION - LSI oscillator enable - 0 - 1 - - - - - - - PWR - Power control - PWR - 0x40007000 - - 0x0 - 0x400 - registers - - - - CR1 - CR1 - Power control register 1 - 0x0 - 0x20 - read-write - 0x00030000 - - - HSION_CTRL - HSI open time control - 19 - 1 - - - SRAM_RETV - SRAM retention voltage control - 16 - 3 - - - LPR - Low-power run - 14 - 1 - - - FLS_SLPTIME - Flash wait time after wakeup from the stop mode - 12 - 2 - - - MRRDY_TIME - Time selection wakeup from LP to VR - 10 - 2 - - - VOS - Voltage scaling range - selection - 9 - 1 - - - DBP - Disable backup domain write - protection - 8 - 1 - - - BIAS_CR_SEL - MR Bias current selection - 4 - 1 - - - BIAS_CR - MR Bias current - 0 - 4 - - - - - CR2 - CR2 - Power control register 2 - 0x4 - 0x20 - read-write - 0x00000500 - - - FLT_TIME - Digital filter time configuration - 9 - 3 - - - FLTEN - Digital filter enable - 8 - 1 - - - PVDT - Power voltage detector threshold - selection - 4 - 3 - - - SRCSEL - Power voltage detector volatage - selection - 2 - 1 - - - PVDE - Power voltage detector - enable - 0 - 1 - - - - - SR - SR - Power status register - 0x14 - 0x20 - read-only - 0x00000000 - - - PVDO - PVD output - 11 - 1 - - - - - - - GPIOA - General-purpose I/Os - GPIO - 0x50000000 - - 0x0 - 0x400 - registers - - - - MODER - MODER - GPIO port mode register - 0x0 - 0x20 - read-write - 0xEBFFFFFF - - - MODE15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - MODE14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - MODE13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - MODE12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - MODE11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - MODE10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - MODE9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - MODE8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - MODE7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - MODE6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - MODE5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - MODE4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - MODE3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - MODE2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - MODE1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - MODE0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - OTYPER - OTYPER - GPIO port output type register - 0x4 - 0x20 - read-write - 0x00000000 - - - OT15 - Port x configuration bits (y = - 0..15) - 15 - 1 - - - OT14 - Port x configuration bits (y = - 0..15) - 14 - 1 - - - OT13 - Port x configuration bits (y = - 0..15) - 13 - 1 - - - OT12 - Port x configuration bits (y = - 0..15) - 12 - 1 - - - OT11 - Port x configuration bits (y = - 0..15) - 11 - 1 - - - OT10 - Port x configuration bits (y = - 0..15) - 10 - 1 - - - OT9 - Port x configuration bits (y = - 0..15) - 9 - 1 - - - OT8 - Port x configuration bits (y = - 0..15) - 8 - 1 - - - OT7 - Port x configuration bits (y = - 0..15) - 7 - 1 - - - OT6 - Port x configuration bits (y = - 0..15) - 6 - 1 - - - OT5 - Port x configuration bits (y = - 0..15) - 5 - 1 - - - OT4 - Port x configuration bits (y = - 0..15) - 4 - 1 - - - OT3 - Port x configuration bits (y = - 0..15) - 3 - 1 - - - OT2 - Port x configuration bits (y = - 0..15) - 2 - 1 - - - OT1 - Port x configuration bits (y = - 0..15) - 1 - 1 - - - OT0 - Port x configuration bits (y = - 0..15) - 0 - 1 - - - - - OSPEEDR - OSPEEDR - GPIO port output speed - register - 0x8 - 0x20 - read-write - 0x0C000000 - - - OSPEED15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - OSPEED14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - OSPEED13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - OSPEED12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - OSPEED11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - OSPEED10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - OSPEED9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - OSPEED8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - OSPEED7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - OSPEED6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - OSPEED5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - OSPEED4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - OSPEED3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - OSPEED2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - OSPEED1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - OSPEED0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - PUPDR - PUPDR - GPIO port pull-up/pull-down - register - 0xC - 0x20 - read-write - 0x24000000 - - - PUPD15 - Port x configuration bits (y = - 0..15) - 30 - 2 - - - PUPD14 - Port x configuration bits (y = - 0..15) - 28 - 2 - - - PUPD13 - Port x configuration bits (y = - 0..15) - 26 - 2 - - - PUPD12 - Port x configuration bits (y = - 0..15) - 24 - 2 - - - PUPD11 - Port x configuration bits (y = - 0..15) - 22 - 2 - - - PUPD10 - Port x configuration bits (y = - 0..15) - 20 - 2 - - - PUPD9 - Port x configuration bits (y = - 0..15) - 18 - 2 - - - PUPD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - PUPD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - PUPD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - PUPD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - PUPD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - PUPD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - PUPD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - PUPD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - PUPD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - IDR - IDR - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ID15 - Port input data (y = - 0..15) - 15 - 1 - - - ID14 - Port input data (y = - 0..15) - 14 - 1 - - - ID13 - Port input data (y = - 0..15) - 13 - 1 - - - ID12 - Port input data (y = - 0..15) - 12 - 1 - - - ID11 - Port input data (y = - 0..15) - 11 - 1 - - - ID10 - Port input data (y = - 0..15) - 10 - 1 - - - ID9 - Port input data (y = - 0..15) - 9 - 1 - - - ID8 - Port input data (y = - 0..15) - 8 - 1 - - - ID7 - Port input data (y = - 0..15) - 7 - 1 - - - ID6 - Port input data (y = - 0..15) - 6 - 1 - - - ID5 - Port input data (y = - 0..15) - 5 - 1 - - - ID4 - Port input data (y = - 0..15) - 4 - 1 - - - ID3 - Port input data (y = - 0..15) - 3 - 1 - - - ID2 - Port input data (y = - 0..15) - 2 - 1 - - - ID1 - Port input data (y = - 0..15) - 1 - 1 - - - ID0 - Port input data (y = - 0..15) - 0 - 1 - - - - - ODR - ODR - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OD15 - Port output data (y = - 0..15) - 15 - 1 - - - OD14 - Port output data (y = - 0..15) - 14 - 1 - - - OD13 - Port output data (y = - 0..15) - 13 - 1 - - - OD12 - Port output data (y = - 0..15) - 12 - 1 - - - OD11 - Port output data (y = - 0..15) - 11 - 1 - - - OD10 - Port output data (y = - 0..15) - 10 - 1 - - - OD9 - Port output data (y = - 0..15) - 9 - 1 - - - OD8 - Port output data (y = - 0..15) - 8 - 1 - - - OD7 - Port output data (y = - 0..15) - 7 - 1 - - - OD6 - Port output data (y = - 0..15) - 6 - 1 - - - OD5 - Port output data (y = - 0..15) - 5 - 1 - - - OD4 - Port output data (y = - 0..15) - 4 - 1 - - - OD3 - Port output data (y = - 0..15) - 3 - 1 - - - OD2 - Port output data (y = - 0..15) - 2 - 1 - - - OD1 - Port output data (y = - 0..15) - 1 - 1 - - - OD0 - Port output data (y = - 0..15) - 0 - 1 - - - - - BSRR - BSRR - GPIO port bit set/reset - register - 0x18 - 0x20 - write-only - 0x00000000 - - - BR15 - Port x reset bit y (y = - 0..15) - 31 - 1 - - - BR14 - Port x reset bit y (y = - 0..15) - 30 - 1 - - - BR13 - Port x reset bit y (y = - 0..15) - 29 - 1 - - - BR12 - Port x reset bit y (y = - 0..15) - 28 - 1 - - - BR11 - Port x reset bit y (y = - 0..15) - 27 - 1 - - - BR10 - Port x reset bit y (y = - 0..15) - 26 - 1 - - - BR9 - Port x reset bit y (y = - 0..15) - 25 - 1 - - - BR8 - Port x reset bit y (y = - 0..15) - 24 - 1 - - - BR7 - Port x reset bit y (y = - 0..15) - 23 - 1 - - - BR6 - Port x reset bit y (y = - 0..15) - 22 - 1 - - - BR5 - Port x reset bit y (y = - 0..15) - 21 - 1 - - - BR4 - Port x reset bit y (y = - 0..15) - 20 - 1 - - - BR3 - Port x reset bit y (y = - 0..15) - 19 - 1 - - - BR2 - Port x reset bit y (y = - 0..15) - 18 - 1 - - - BR1 - Port x reset bit y (y = - 0..15) - 17 - 1 - - - BR0 - Port x set bit y (y= - 0..15) - 16 - 1 - - - BS15 - Port x set bit y (y= - 0..15) - 15 - 1 - - - BS14 - Port x set bit y (y= - 0..15) - 14 - 1 - - - BS13 - Port x set bit y (y= - 0..15) - 13 - 1 - - - BS12 - Port x set bit y (y= - 0..15) - 12 - 1 - - - BS11 - Port x set bit y (y= - 0..15) - 11 - 1 - - - BS10 - Port x set bit y (y= - 0..15) - 10 - 1 - - - BS9 - Port x set bit y (y= - 0..15) - 9 - 1 - - - BS8 - Port x set bit y (y= - 0..15) - 8 - 1 - - - BS7 - Port x set bit y (y= - 0..15) - 7 - 1 - - - BS6 - Port x set bit y (y= - 0..15) - 6 - 1 - - - BS5 - Port x set bit y (y= - 0..15) - 5 - 1 - - - BS4 - Port x set bit y (y= - 0..15) - 4 - 1 - - - BS3 - Port x set bit y (y= - 0..15) - 3 - 1 - - - BS2 - Port x set bit y (y= - 0..15) - 2 - 1 - - - BS1 - Port x set bit y (y= - 0..15) - 1 - 1 - - - BS0 - Port x set bit y (y= - 0..15) - 0 - 1 - - - - - LCKR - LCKR - GPIO port configuration lock - register - 0x1C - 0x20 - read-write - 0x00000000 - - - LCKK - Port x lock bit y (y= - 0..15) - 16 - 1 - - - LCK15 - Port x lock bit y (y= - 0..15) - 15 - 1 - - - LCK14 - Port x lock bit y (y= - 0..15) - 14 - 1 - - - LCK13 - Port x lock bit y (y= - 0..15) - 13 - 1 - - - LCK12 - Port x lock bit y (y= - 0..15) - 12 - 1 - - - LCK11 - Port x lock bit y (y= - 0..15) - 11 - 1 - - - LCK10 - Port x lock bit y (y= - 0..15) - 10 - 1 - - - LCK9 - Port x lock bit y (y= - 0..15) - 9 - 1 - - - LCK8 - Port x lock bit y (y= - 0..15) - 8 - 1 - - - LCK7 - Port x lock bit y (y= - 0..15) - 7 - 1 - - - LCK6 - Port x lock bit y (y= - 0..15) - 6 - 1 - - - LCK5 - Port x lock bit y (y= - 0..15) - 5 - 1 - - - LCK4 - Port x lock bit y (y= - 0..15) - 4 - 1 - - - LCK3 - Port x lock bit y (y= - 0..15) - 3 - 1 - - - LCK2 - Port x lock bit y (y= - 0..15) - 2 - 1 - - - LCK1 - Port x lock bit y (y= - 0..15) - 1 - 1 - - - LCK0 - Port x lock bit y (y= - 0..15) - 0 - 1 - - - - - AFRL - AFRL - GPIO alternate function low - register - 0x20 - 0x20 - read-write - 0x00000000 - - - AFSEL7 - Alternate function selection for port x - bit y (y = 0..7) - 28 - 4 - - - AFSEL6 - Alternate function selection for port x - bit y (y = 0..7) - 24 - 4 - - - AFSEL5 - Alternate function selection for port x - bit y (y = 0..7) - 20 - 4 - - - AFSEL4 - Alternate function selection for port x - bit y (y = 0..7) - 16 - 4 - - - AFSEL3 - Alternate function selection for port x - bit y (y = 0..7) - 12 - 4 - - - AFSEL2 - Alternate function selection for port x - bit y (y = 0..7) - 8 - 4 - - - AFSEL1 - Alternate function selection for port x - bit y (y = 0..7) - 4 - 4 - - - AFSEL0 - Alternate function selection for port x - bit y (y = 0..7) - 0 - 4 - - - - - AFRH - AFRH - GPIO alternate function high - register - 0x24 - 0x20 - read-write - 0x00000000 - - - AFSEL15 - Alternate function selection for port x - bit y (y = 8..15) - 28 - 4 - - - AFSEL14 - Alternate function selection for port x - bit y (y = 8..15) - 24 - 4 - - - AFSEL13 - Alternate function selection for port x - bit y (y = 8..15) - 20 - 4 - - - AFSEL12 - Alternate function selection for port x - bit y (y = 8..15) - 16 - 4 - - - AFSEL11 - Alternate function selection for port x - bit y (y = 8..15) - 12 - 4 - - - AFSEL10 - Alternate function selection for port x - bit y (y = 8..15) - 8 - 4 - - - AFSEL9 - Alternate function selection for port x - bit y (y = 8..15) - 4 - 4 - - - AFSEL8 - Alternate function selection for port x - bit y (y = 8..15) - 0 - 4 - - - - - BRR - BRR - port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - BR15 - Port Reset bit - 15 - 1 - - - BR14 - Port Reset bit - 14 - 1 - - - BR13 - Port Reset bit - 13 - 1 - - - BR12 - Port Reset bit - 12 - 1 - - - BR11 - Port Reset bit - 11 - 1 - - - BR10 - Port Reset bit - 10 - 1 - - - BR9 - Port Reset bit - 9 - 1 - - - BR8 - Port Reset bit - 8 - 1 - - - BR7 - Port Reset bit - 7 - 1 - - - BR6 - Port Reset bit - 6 - 1 - - - BR5 - Port Reset bit - 5 - 1 - - - BR4 - Port Reset bit - 4 - 1 - - - BR3 - Port Reset bit - 3 - 1 - - - BR2 - Port Reset bit - 2 - 1 - - - BR1 - Port Reset bit - 1 - 1 - - - BR0 - Port Reset bit - 0 - 1 - - - - - - - GPIOB - General-purpose I/Os - GPIO - 0x50000400 - - 0x0 - 0x400 - registers - - - - MODER - MODER - GPIO port mode register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - MODE8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - MODE7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - MODE6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - MODE5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - MODE4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - MODE3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - MODE2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - MODE1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - MODE0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - OTYPER - OTYPER - GPIO port output type register - 0x4 - 0x20 - read-write - 0x00000000 - - - OT8 - Port x configuration bits (y = - 0..15) - 8 - 1 - - - OT7 - Port x configuration bits (y = - 0..15) - 7 - 1 - - - OT6 - Port x configuration bits (y = - 0..15) - 6 - 1 - - - OT5 - Port x configuration bits (y = - 0..15) - 5 - 1 - - - OT4 - Port x configuration bits (y = - 0..15) - 4 - 1 - - - OT3 - Port x configuration bits (y = - 0..15) - 3 - 1 - - - OT2 - Port x configuration bits (y = - 0..15) - 2 - 1 - - - OT1 - Port x configuration bits (y = - 0..15) - 1 - 1 - - - OT0 - Port x configuration bits (y = - 0..15) - 0 - 1 - - - - - OSPEEDR - OSPEEDR - GPIO port output speed - register - 0x8 - 0x20 - read-write - 0x00000000 - - - OSPEED8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - OSPEED7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - OSPEED6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - OSPEED5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - OSPEED4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - OSPEED3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - OSPEED2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - OSPEED1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - OSPEED0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - PUPDR - PUPDR - GPIO port pull-up/pull-down - register - 0xC - 0x20 - read-write - 0x00000000 - - - PUPD8 - Port x configuration bits (y = - 0..15) - 16 - 2 - - - PUPD7 - Port x configuration bits (y = - 0..15) - 14 - 2 - - - PUPD6 - Port x configuration bits (y = - 0..15) - 12 - 2 - - - PUPD5 - Port x configuration bits (y = - 0..15) - 10 - 2 - - - PUPD4 - Port x configuration bits (y = - 0..15) - 8 - 2 - - - PUPD3 - Port x configuration bits (y = - 0..15) - 6 - 2 - - - PUPD2 - Port x configuration bits (y = - 0..15) - 4 - 2 - - - PUPD1 - Port x configuration bits (y = - 0..15) - 2 - 2 - - - PUPD0 - Port x configuration bits (y = - 0..15) - 0 - 2 - - - - - IDR - IDR - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ID8 - Port input data (y = - 0..15) - 8 - 1 - - - ID7 - Port input data (y = - 0..15) - 7 - 1 - - - ID6 - Port input data (y = - 0..15) - 6 - 1 - - - ID5 - Port input data (y = - 0..15) - 5 - 1 - - - ID4 - Port input data (y = - 0..15) - 4 - 1 - - - ID3 - Port input data (y = - 0..15) - 3 - 1 - - - ID2 - Port input data (y = - 0..15) - 2 - 1 - - - ID1 - Port input data (y = - 0..15) - 1 - 1 - - - ID0 - Port input data (y = - 0..15) - 0 - 1 - - - - - ODR - ODR - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OD8 - Port output data (y = - 0..15) - 8 - 1 - - - OD7 - Port output data (y = - 0..15) - 7 - 1 - - - OD6 - Port output data (y = - 0..15) - 6 - 1 - - - OD5 - Port output data (y = - 0..15) - 5 - 1 - - - OD4 - Port output data (y = - 0..15) - 4 - 1 - - - OD3 - Port output data (y = - 0..15) - 3 - 1 - - - OD2 - Port output data (y = - 0..15) - 2 - 1 - - - OD1 - Port output data (y = - 0..15) - 1 - 1 - - - OD0 - Port output data (y = - 0..15) - 0 - 1 - - - - - BSRR - BSRR - GPIO port bit set/reset - register - 0x18 - 0x20 - write-only - 0x00000000 - - - BR8 - Port x reset bit y (y = - 0..15) - 24 - 1 - - - BR7 - Port x reset bit y (y = - 0..15) - 23 - 1 - - - BR6 - Port x reset bit y (y = - 0..15) - 22 - 1 - - - BR5 - Port x reset bit y (y = - 0..15) - 21 - 1 - - - BR4 - Port x reset bit y (y = - 0..15) - 20 - 1 - - - BR3 - Port x reset bit y (y = - 0..15) - 19 - 1 - - - BR2 - Port x reset bit y (y = - 0..15) - 18 - 1 - - - BR1 - Port x reset bit y (y = - 0..15) - 17 - 1 - - - BR0 - Port x set bit y (y= - 0..15) - 16 - 1 - - - BS8 - Port x set bit y (y= - 0..15) - 8 - 1 - - - BS7 - Port x set bit y (y= - 0..15) - 7 - 1 - - - BS6 - Port x set bit y (y= - 0..15) - 6 - 1 - - - BS5 - Port x set bit y (y= - 0..15) - 5 - 1 - - - BS4 - Port x set bit y (y= - 0..15) - 4 - 1 - - - BS3 - Port x set bit y (y= - 0..15) - 3 - 1 - - - BS2 - Port x set bit y (y= - 0..15) - 2 - 1 - - - BS1 - Port x set bit y (y= - 0..15) - 1 - 1 - - - BS0 - Port x set bit y (y= - 0..15) - 0 - 1 - - - - - LCKR - LCKR - GPIO port configuration lock - register - 0x1C - 0x20 - read-write - 0x00000000 - - - LCKK - Port x lock bit y (y= - 0..15) - 16 - 1 - - - LCK8 - Port x lock bit y (y= - 0..15) - 8 - 1 - - - LCK7 - Port x lock bit y (y= - 0..15) - 7 - 1 - - - LCK6 - Port x lock bit y (y= - 0..15) - 6 - 1 - - - LCK5 - Port x lock bit y (y= - 0..15) - 5 - 1 - - - LCK4 - Port x lock bit y (y= - 0..15) - 4 - 1 - - - LCK3 - Port x lock bit y (y= - 0..15) - 3 - 1 - - - LCK2 - Port x lock bit y (y= - 0..15) - 2 - 1 - - - LCK1 - Port x lock bit y (y= - 0..15) - 1 - 1 - - - LCK0 - Port x lock bit y (y= - 0..15) - 0 - 1 - - - - - AFRL - AFRL - GPIO alternate function low - register - 0x20 - 0x20 - read-write - 0x00000000 - - - AFSEL7 - Alternate function selection for port x - bit y (y = 0..7) - 28 - 4 - - - AFSEL6 - Alternate function selection for port x - bit y (y = 0..7) - 24 - 4 - - - AFSEL5 - Alternate function selection for port x - bit y (y = 0..7) - 20 - 4 - - - AFSEL4 - Alternate function selection for port x - bit y (y = 0..7) - 16 - 4 - - - AFSEL3 - Alternate function selection for port x - bit y (y = 0..7) - 12 - 4 - - - AFSEL2 - Alternate function selection for port x - bit y (y = 0..7) - 8 - 4 - - - AFSEL1 - Alternate function selection for port x - bit y (y = 0..7) - 4 - 4 - - - AFSEL0 - Alternate function selection for port x - bit y (y = 0..7) - 0 - 4 - - - - - AFRH - AFRH - GPIO alternate function high - register - 0x24 - 0x20 - read-write - 0x00000000 - - - AFSEL15 - Alternate function selection for port x - bit y (y = 8..15) - 28 - 4 - - - AFSEL14 - Alternate function selection for port x - bit y (y = 8..15) - 24 - 4 - - - AFSEL13 - Alternate function selection for port x - bit y (y = 8..15) - 20 - 4 - - - AFSEL12 - Alternate function selection for port x - bit y (y = 8..15) - 16 - 4 - - - AFSEL11 - Alternate function selection for port x - bit y (y = 8..15) - 12 - 4 - - - AFSEL10 - Alternate function selection for port x - bit y (y = 8..15) - 8 - 4 - - - AFSEL9 - Alternate function selection for port x - bit y (y = 8..15) - 4 - 4 - - - AFSEL8 - Alternate function selection for port x - bit y (y = 8..15) - 0 - 4 - - - - - BRR - BRR - port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - BR8 - Port Reset bit - 8 - 1 - - - BR7 - Port Reset bit - 7 - 1 - - - BR6 - Port Reset bit - 6 - 1 - - - BR5 - Port Reset bit - 5 - 1 - - - BR4 - Port Reset bit - 4 - 1 - - - BR3 - Port Reset bit - 3 - 1 - - - BR2 - Port Reset bit - 2 - 1 - - - BR1 - Port Reset bit - 1 - 1 - - - BR0 - Port Reset bit - 0 - 1 - - - - - - - GPIOF - 0x50001400 - - - EXTI - External interrupt/event - controller - EXTI - 0x40021800 - - 0x0 - 0x400 - registers - - - PVD - PVD Interrupt through EXTI Lines 16 - 1 - - - EXTI0_1 - EXTI Line 0 and 1 Interrupt - 5 - - - EXTI2_3 - EXTI Line 2 and 3 Interrupt - 6 - - - EXTI4_15 - EXTI Line 4 to 15 Interrupt - 7 - - - - RTSR - RTSR - EXTI rising trigger selection - register - 0x0 - 0x20 - read-write - 0x00000000 - - - RT18 - Rising trigger event configuration bit - of Configurable Event input - 18 - 1 - - - RT17 - Rising trigger event configuration bit - of Configurable Event input - 17 - 1 - - - RT16 - Rising trigger event configuration bit - of Configurable Event input - 16 - 1 - - - RT15 - Rising trigger event configuration bit - of Configurable Event input - 15 - 1 - - - RT14 - Rising trigger event configuration bit - of Configurable Event input - 14 - 1 - - - RT13 - Rising trigger event configuration bit - of Configurable Event input - 13 - 1 - - - RT12 - Rising trigger event configuration bit - of Configurable Event input - 12 - 1 - - - RT11 - Rising trigger event configuration bit - of Configurable Event input - 11 - 1 - - - RT10 - Rising trigger event configuration bit - of Configurable Event input - 10 - 1 - - - RT9 - Rising trigger event configuration bit - of Configurable Event input - 9 - 1 - - - RT8 - Rising trigger event configuration bit - of Configurable Event input - 8 - 1 - - - RT7 - Rising trigger event configuration bit - of Configurable Event input - 7 - 1 - - - RT6 - Rising trigger event configuration bit - of Configurable Event input - 6 - 1 - - - RT5 - Rising trigger event configuration bit - of Configurable Event input - 5 - 1 - - - RT4 - Rising trigger event configuration bit - of Configurable Event input - 4 - 1 - - - RT3 - Rising trigger event configuration bit - of Configurable Event input - 3 - 1 - - - RT2 - Rising trigger event configuration bit - of Configurable Event input - 2 - 1 - - - RT1 - Rising trigger event configuration bit - of Configurable Event input - 1 - 1 - - - RT0 - Rising trigger event configuration bit - of Configurable Event input - 0 - 1 - - - - - FTSR - FTSR - EXTI falling trigger selection - register - 0x4 - 0x20 - read-write - 0x00000000 - - - FT18 - Falling trigger event configuration bit - of Configurable Event input - 18 - 1 - - - FT17 - Falling trigger event configuration bit - of Configurable Event input - 17 - 1 - - - FT16 - Falling trigger event configuration bit - of Configurable Event input - 16 - 1 - - - FT15 - Falling trigger event configuration bit - of Configurable Event input - 15 - 1 - - - FT14 - Falling trigger event configuration bit - of Configurable Event input - 14 - 1 - - - FT13 - Falling trigger event configuration bit - of Configurable Event input - 13 - 1 - - - FT12 - Falling trigger event configuration bit - of Configurable Event input - 12 - 1 - - - FT11 - Falling trigger event configuration bit - of Configurable Event input - 11 - 1 - - - FT10 - Falling trigger event configuration bit - of Configurable Event input - 10 - 1 - - - FT9 - Falling trigger event configuration bit - of Configurable Event input - 9 - 1 - - - FT8 - Falling trigger event configuration bit - of Configurable Event input - 8 - 1 - - - FT7 - Falling trigger event configuration bit - of Configurable Event input - 7 - 1 - - - FT6 - Falling trigger event configuration bit - of Configurable Event input - 6 - 1 - - - FT5 - Falling trigger event configuration bit - of Configurable Event input - 5 - 1 - - - FT4 - Falling trigger event configuration bit - of Configurable Event input - 4 - 1 - - - FT3 - Falling trigger event configuration bit - of Configurable Event input - 3 - 1 - - - FT2 - Falling trigger event configuration bit - of Configurable Event input - 2 - 1 - - - FT1 - Falling trigger event configuration bit - of Configurable Event input - 1 - 1 - - - FT0 - Falling trigger event configuration bit - of Configurable Event input - 0 - 1 - - - - - SWIER - SWIER - EXTI software interrupt event - register - 0x8 - 0x20 - read-write - 0x00000000 - - - SWI18 - Rising trigger event configuration bit - of Configurable Event input - 18 - 1 - - - SWI17 - Rising trigger event configuration bit - of Configurable Event input - 17 - 1 - - - SWI16 - Rising trigger event configuration bit - of Configurable Event input - 16 - 1 - - - SWI15 - Rising trigger event configuration bit - of Configurable Event input - 15 - 1 - - - SWI14 - Rising trigger event configuration bit - of Configurable Event input - 14 - 1 - - - SWI13 - Rising trigger event configuration bit - of Configurable Event input - 13 - 1 - - - SWI12 - Rising trigger event configuration bit - of Configurable Event input - 12 - 1 - - - SWI11 - Rising trigger event configuration bit - of Configurable Event input - 11 - 1 - - - SWI10 - Rising trigger event configuration bit - of Configurable Event input - 10 - 1 - - - SWI9 - Rising trigger event configuration bit - of Configurable Event input - 9 - 1 - - - SWI8 - Rising trigger event configuration bit - of Configurable Event input - 8 - 1 - - - SWI7 - Rising trigger event configuration bit - of Configurable Event input - 7 - 1 - - - SWI6 - Rising trigger event configuration bit - of Configurable Event input - 6 - 1 - - - SWI5 - Rising trigger event configuration bit - of Configurable Event input - 5 - 1 - - - SWI4 - Rising trigger event configuration bit - of Configurable Event input - 4 - 1 - - - SWI3 - Rising trigger event configuration bit - of Configurable Event input - 3 - 1 - - - SWI2 - Rising trigger event configuration bit - of Configurable Event input - 2 - 1 - - - SWI1 - Rising trigger event configuration bit - of Configurable Event input - 1 - 1 - - - SWI0 - Rising trigger event configuration bit - of Configurable Event input - 0 - 1 - - - - - PR - PR - EXTI pending - register - 0xC - 0x20 - read-write - 0x00000000 - - - PR18 - configurable event inputs x rising edge - Pending bit. - 18 - 1 - - - PR17 - configurable event inputs x rising edge - Pending bit. - 17 - 1 - - - PR16 - configurable event inputs x rising edge - Pending bit. - 16 - 1 - - - PR15 - configurable event inputs x rising edge - Pending bit. - 15 - 1 - - - PR14 - configurable event inputs x rising edge - Pending bit. - 14 - 1 - - - PR13 - configurable event inputs x rising edge - Pending bit - 13 - 1 - - - PR12 - configurable event inputs x rising edge - Pending bit. - 12 - 1 - - - PR11 - configurable event inputs x rising edge - Pending bit. - 11 - 1 - - - PR10 - configurable event inputs x rising edge - Pending bit. - 10 - 1 - - - PR9 - configurable event inputs x rising edge - Pending bit. - 9 - 1 - - - PR8 - configurable event inputs x rising edge - Pending bit. - 8 - 1 - - - PR7 - configurable event inputs x rising edge - Pending bit. - 7 - 1 - - - PR6 - configurable event inputs x rising edge - Pending bit. - 6 - 1 - - - PR5 - configurable event inputs x rising edge - Pending bit. - 5 - 1 - - - PR4 - configurable event inputs x rising edge - Pending bit. - 4 - 1 - - - PR3 - configurable event inputs x rising edge - Pending bit. - 3 - 1 - - - PR2 - configurable event inputs x rising edge - Pending bit. - 2 - 1 - - - PR1 - configurable event inputs x rising edge - Pending bit. - 1 - 1 - - - PR0 - configurable event inputs x rising edge - Pending bit. - 0 - 1 - - - - - EXTICR1 - EXTICR1 - EXTI external interrupt selection - register - 0x60 - 0x20 - read-write - 0x00000000 - - - EXTI3 - GPIO port selection - 24 - 2 - - - EXTI2 - GPIO port selection - 16 - 2 - - - EXTI1 - GPIO port selection - 8 - 2 - - - EXTI0 - GPIO port selection - 0 - 2 - - - - - EXTICR2 - EXTICR2 - EXTI external interrupt selection - register - 0x64 - 0x20 - read-write - 0x00000000 - - - EXTI7 - GPIO port selection - 24 - 1 - - - EXTI6 - GPIO port selection - 16 - 1 - - - EXTI5 - GPIO port selection - 8 - 1 - - - EXTI4 - GPIO port selection - 0 - 2 - - - - - EXTICR3 - EXTICR3 - EXTI external interrupt selection - register - 0x68 - 0x20 - read-write - 0x00000000 - - - EXTI8 - GPIO port selection - 0 - 1 - - - - - IMR - IMR - EXTI CPU wakeup with interrupt mask - register - 0x80 - 0x20 - read-write - 0xFFF80000 - - - IM29 - CPU wakeup with interrupt mask on event - input - 29 - 1 - - - IM19 - CPU wakeup with interrupt mask on event - input - 19 - 1 - - - IM18 - CPU wakeup with interrupt mask on event - input - 18 - 1 - - - IM17 - CPU wakeup with interrupt mask on event - input - 17 - 1 - - - IM16 - CPU wakeup with interrupt mask on event - input - 16 - 1 - - - IM15 - CPU wakeup with interrupt mask on event - input - 15 - 1 - - - IM14 - CPU wakeup with interrupt mask on event - input - 14 - 1 - - - IM13 - CPU wakeup with interrupt mask on event - input - 13 - 1 - - - IM12 - CPU wakeup with interrupt mask on event - input - 12 - 1 - - - IM11 - CPU wakeup with interrupt mask on event - input - 11 - 1 - - - IM10 - CPU wakeup with interrupt mask on event - input - 10 - 1 - - - IM9 - CPU wakeup with interrupt mask on event - input - 9 - 1 - - - IM8 - CPU wakeup with interrupt mask on event - input - 8 - 1 - - - IM7 - CPU wakeup with interrupt mask on event - input - 7 - 1 - - - IM6 - CPU wakeup with interrupt mask on event - input - 6 - 1 - - - IM5 - CPU wakeup with interrupt mask on event - input - 5 - 1 - - - IM4 - CPU wakeup with interrupt mask on event - input - 4 - 1 - - - IM3 - CPU wakeup with interrupt mask on event - input - 3 - 1 - - - IM2 - CPU wakeup with interrupt mask on event - input - 2 - 1 - - - IM1 - CPU wakeup with interrupt mask on event - input - 1 - 1 - - - IM0 - CPU wakeup with interrupt mask on event - input - 0 - 1 - - - - - EMR - EMR - EXTI CPU wakeup with event mask - register - 0x84 - 0x20 - read-write - 0x00000000 - - - EM29 - CPU wakeup with event mask on event - input - 29 - 1 - - - EM19 - CPU wakeup with event mask on event - input - 19 - 1 - - - EM18 - CPU wakeup with event mask on event - input - 18 - 1 - - - EM17 - CPU wakeup with event mask on event - input - 17 - 1 - - - EM16 - CPU wakeup with event mask on event - input - 16 - 1 - - - EM15 - CPU wakeup with event mask on event - input - 15 - 1 - - - EM14 - CPU wakeup with event mask on event - input - 14 - 1 - - - EM13 - CPU wakeup with event mask on event - input - 13 - 1 - - - EM12 - CPU wakeup with event mask on event - input - 12 - 1 - - - EM11 - CPU wakeup with event mask on event - input - 11 - 1 - - - EM10 - CPU wakeup with event mask on event - input - 10 - 1 - - - EM9 - CPU wakeup with event mask on event - input - 9 - 1 - - - EM8 - CPU wakeup with event mask on event - input - 8 - 1 - - - EM7 - CPU wakeup with event mask on event - input - 7 - 1 - - - EM6 - CPU wakeup with event mask on event - input - 6 - 1 - - - EM5 - CPU wakeup with event mask on event - input - 5 - 1 - - - EM4 - CPU wakeup with event mask on event - input - 4 - 1 - - - EM3 - CPU wakeup with event mask on event - input - 3 - 1 - - - EM2 - CPU wakeup with event mask on event - input - 2 - 1 - - - EM1 - CPU wakeup with event mask on event - input - 1 - 1 - - - EM0 - CPU wakeup with event mask on event - input - 0 - 1 - - - - - - - LPTIM - Low power timer - LPTIM - 0x40007C00 - - 0x0 - 0x400 - registers - - - - ISR - ISR - Interrupt and Status Register - 0x0 - 0x20 - read-only - 0x00000000 - - - ARRM - Autoreload match - 1 - 1 - - - - - ICR - ICR - Interrupt Clear Register - 0x4 - 0x20 - write-only - 0x00000000 - - - ARRMCF - Autoreload match Clear - Flag - 1 - 1 - - - - - IER - IER - Interrupt Enable Register - 0x8 - 0x20 - read-write - 0x00000000 - - - ARRMIE - Autoreload match Interrupt - Enable - 1 - 1 - - - - - CFGR - CFGR - Configuration Register - 0xC - 0x20 - read-write - 0x00000000 - - - PRELOAD - Registers update mode - 22 - 1 - - - PRESC - Clock prescaler - 9 - 3 - - - - - CR - CR - Control Register - 0x10 - 0x20 - read-write - 0x00000000 - - - RSTARE - Reset after read enable - 4 - 1 - - - SNGSTRT - LPTIM start in single mode - 1 - 1 - - - ENABLE - LPTIM Enable - 0 - 1 - - - - - ARR - ARR - Autoreload Register - 0x18 - 0x20 - read-write - 0x00000001 - - - ARR - Auto reload value - 0 - 16 - - - - - CNT - CNT - Counter Register - 0x1C - 0x20 - read-only - 0x00000000 - - - CNT - Counter value - 0 - 16 - - - - - - - USART1 - Universal synchronous asynchronous receiver - transmitter - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global Interrupt - 27 - - - - SR - SR - Status register - 0x0 - 0x20 - 0x00C0 - - - ABRRQ - Automate baudrate detection requeset - 12 - 1 - write-only - - - ABRE - Automate baudrate detection error flag - 11 - 1 - read-only - - - ABRF - Automate baudrate detection flag - 10 - 1 - read-only - - - CTS - CTS flag - 9 - 1 - read-write - - - TXE - Transmit data register - empty - 7 - 1 - read-only - - - TC - Transmission complete - 6 - 1 - read-write - - - RXNE - Read data register not - empty - 5 - 1 - read-write - - - IDLE - IDLE line detected - 4 - 1 - read-only - - - ORE - Overrun error - 3 - 1 - read-only - - - NE - Noise error flag - 2 - 1 - read-only - - - FE - Framing error - 1 - 1 - read-only - - - PE - Parity error - 0 - 1 - read-only - - - - - DR - DR - Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - DR - Data value - 0 - 9 - - - - - BRR - BRR - Baud rate register - 0x8 - 0x20 - read-write - 0x0000 - - - DIV_Mantissa - mantissa of USARTDIV - 4 - 12 - - - DIV_Fraction - fraction of USARTDIV - 0 - 4 - - - - - CR1 - CR1 - Control register 1 - 0xC - 0x20 - read-write - 0x0000 - - - UE - USART enable - 13 - 1 - - - M - Word length - 12 - 1 - - - WAKE - Wakeup method - 11 - 1 - - - PCE - Parity control enable - 10 - 1 - - - PS - Parity selection - 9 - 1 - - - PEIE - PE interrupt enable - 8 - 1 - - - TXEIE - TXE interrupt enable - 7 - 1 - - - TCIE - Transmission complete interrupt - enable - 6 - 1 - - - RXNEIE - RXNE interrupt enable - 5 - 1 - - - IDLEIE - IDLE interrupt enable - 4 - 1 - - - TE - Transmitter enable - 3 - 1 - - - RE - Receiver enable - 2 - 1 - - - RWU - Receiver wakeup - 1 - 1 - - - SBK - Send break - 0 - 1 - - - - - CR2 - CR2 - Control register 2 - 0x10 - 0x20 - read-write - 0x0000 - - - STOP - STOP bits - 12 - 2 - - - CLKEN - Clock enable - 11 - 1 - - - CPOL - Clock polarity - 10 - 1 - - - CPHA - Clock phase - 9 - 1 - - - LBCL - Last bit clock pulse - 8 - 1 - - - ADD - Address of the USART node - 0 - 4 - - - - - CR3 - CR3 - Control register 3 - 0x14 - 0x20 - read-write - 0x0000 - - - ABRMOD - Auto baudrate mode - 13 - 2 - - - ABREN - Auto baudrate enable - 12 - 1 - - - OVER8 - Oversampling mode - 11 - 1 - - - CTSIE - CTS interrupt enable - 10 - 1 - - - CTSE - CTS enable - 9 - 1 - - - RTSE - RTS enable - 8 - 1 - - - DMAT - DMA enable transmitter - 7 - 1 - - - DMAR - DMA enable receiver - 6 - 1 - - - HDSEL - Half-duplex selection - 3 - 1 - - - IRLP - IrDA low-power - 2 - 1 - - - IREN - IrDA mode enable - 1 - 1 - - - EIE - Error interrupt enable - 0 - 1 - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global Interrupt - 28 - - - - RTC - Real time clock - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC - RTC Interrupt through EXTI Lines 19 - 2 - - - - CRH - CRH - RTC Control Register High - 0x0 - 0x20 - read-write - 0x00000000 - - - OWIE - Overflow interrupt Enable - 2 - 1 - - - ALRIE - Alarm interrupt Enable - 1 - 1 - - - SECIE - Second interrupt Enable - 0 - 1 - - - - - CRL - CRL - RTC Control Register Low - 0x4 - 0x20 - 0x00000020 - - - RTOFF - RTC operation OFF - 5 - 1 - read-only - - - CNF - Configuration Flag - 4 - 1 - read-write - - - RSF - Registers Synchronized - Flag - 3 - 1 - read-write - - - OWF - Overflow Flag - 2 - 1 - read-write - - - ALRF - Alarm Flag - 1 - 1 - read-write - - - SECF - Second Flag - 0 - 1 - read-write - - - - - PRLH - PRLH - RTC Prescaler Load Register - High - 0x8 - 0x20 - write-only - 0x00000000 - - - PRLH - RTC Prescaler Load Register - High - 0 - 4 - - - - - PRLL - PRLL - RTC Prescaler Load Register - Low - 0xC - 0x20 - write-only - 0x8000 - - - PRLL - RTC Prescaler Divider Register - Low - 0 - 16 - - - - - DIVH - DIVH - RTC Prescaler Divider Register - High - 0x10 - 0x20 - read-only - 0x00000000 - - - DIVH - RTC prescaler divider register - high - 0 - 4 - - - - - DIVL - DIVL - RTC Prescaler Divider Register - Low - 0x14 - 0x20 - read-only - 0x8000 - - - DIVL - RTC prescaler divider register - Low - 0 - 16 - - - - - CNTH - CNTH - RTC Counter Register High - 0x18 - 0x20 - read-write - 0x00000000 - - - CNTH - RTC counter register high - 0 - 16 - - - - - CNTL - CNTL - RTC Counter Register Low - 0x1C - 0x20 - read-write - 0x00000000 - - - CNTL - RTC counter register Low - 0 - 16 - - - - - ALRH - ALRH - RTC Alarm Register High - 0x20 - 0x20 - write-only - 0xFFFF - - - ALRH - RTC alarm register high - 0 - 16 - - - - - ALRL - ALRL - RTC Alarm Register Low - 0x24 - 0x20 - write-only - 0xFFFF - - - ALRL - RTC alarm register low - 0 - 16 - - - - - RTCCR - RTCCR - RTC clock calibration - 0x2C - 0x20 - read-write - 0x0000 - - - ASOS - Alarm or second output selection - 9 - 1 - - - ASOE - Alarm or second output enable - 8 - 1 - - - CCO - Calibration clock output - 7 - 1 - - - CAL - Calibration value - 0 - 7 - - - - - - - IWDG - Independent watchdog - IWDG - 0x40003000 - - 0x0 - 0x400 - registers - - - - KR - KR - Key register (IWDG_KR) - 0x0 - 0x20 - write-only - 0x00000000 - - - KEY - Key value - 0 - 16 - - - - - PR - PR - Prescaler register (IWDG_PR) - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Prescaler divider - 0 - 3 - - - - - RLR - RLR - Reload register (IWDG_RLR) - 0x8 - 0x20 - read-write - 0x00000FFF - - - RL - Watchdog counter reload - value - 0 - 12 - - - - - SR - SR - Status register (IWDG_SR) - 0xC - 0x20 - read-only - 0x00000000 - - - WVU - Watchdog counter window value update - 2 - 1 - - - RVU - Watchdog counter reload value - update - 1 - 1 - - - PVU - Watchdog prescaler value - update - 0 - 1 - - - - - WINR - WINR - Window register (IWDG_SR) - 0x10 - 0x20 - read-only - 0x00000000 - - - WIN - window counter - 0 - 12 - - - - - - - WWDG - Window watchdog - WWDG - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDG - Window WatchDog Interrupt - 0 - - - - CR - CR - Control register (WWDG_CR) - 0x0 - 0x20 - read-write - 0x0000007F - - - WDGA - Activation bit - 7 - 1 - - - T - 7-bit counter (MSB to LSB) - 0 - 7 - - - - - CFR - CFR - Configuration register - (WWDG_CFR) - 0x4 - 0x20 - read-write - 0x0000007F - - - EWI - Early Wakeup Interrupt - 9 - 1 - - - WDGTB - Timer Base - 7 - 2 - - - W - 7-bit window value - 0 - 7 - - - - - SR - SR - Status register (WWDG_SR) - 0x8 - 0x20 - read-write - 0x00000000 - - - EWIF - Early Wakeup Interrupt flag - 0 - 1 - - - - - - - TIM1 - Advanced timer - TIM - 0x40012C00 - - 0x0 - 0x400 - registers - - - TIM1_BRK_UP_TRG_COM - TIM1 Break, Update, Trigger and Commutation Interrupt - 13 - - - TIM1_CC - TIM1 Capture Compare Interrupt - 14 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - CMS - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - OIS4 - Output Idle state 4 - 14 - 1 - - - OIS3N - Output Idle state 3 - 13 - 1 - - - OIS3 - Output Idle state 3 - 12 - 1 - - - OIS2N - Output Idle state 2 - 11 - 1 - - - OIS2 - Output Idle state 2 - 10 - 1 - - - OIS1N - Output Idle state 1 - 9 - 1 - - - OIS1 - Output Idle state 1 - 8 - 1 - - - TI1S - TI1 selection - 7 - 1 - - - MMS - Master mode selection - 4 - 3 - - - CCDS - Capture/compare DMA - selection - 3 - 1 - - - CCUS - Capture/compare control update - selection - 2 - 1 - - - CCPC - Capture/compare preloaded - control - 0 - 1 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - ETP - External trigger polarity - 15 - 1 - - - ECE - External clock enable - 14 - 1 - - - ETPS - External trigger prescaler - 12 - 2 - - - ETF - External trigger filter - 8 - 4 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - OCCS - OCREF clear selection bit - 3 - 1 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDE - Trigger DMA request enable - 14 - 1 - - - COMDE - COM DMA request enable - 13 - 1 - - - CC4DE - Capture/Compare 4 DMA request - enable - 12 - 1 - - - CC3DE - Capture/Compare 3 DMA request - enable - 11 - 1 - - - CC2DE - Capture/Compare 2 DMA request - enable - 10 - 1 - - - CC1DE - Capture/Compare 1 DMA request - enable - 9 - 1 - - - UDE - Update DMA request enable - 8 - 1 - - - BIE - Break interrupt enable - 7 - 1 - - - TIE - Trigger interrupt enable - 6 - 1 - - - COMIE - COM interrupt enable - 5 - 1 - - - CC4IE - Capture/Compare 4 interrupt - enable - 4 - 1 - - - CC3IE - Capture/Compare 3 interrupt - enable - 3 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC4OF - Capture/Compare 4 overcapture - flag - 12 - 1 - - - CC3OF - Capture/Compare 3 overcapture - flag - 11 - 1 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - BIF - Break interrupt flag - 7 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - COMIF - COM interrupt flag - 5 - 1 - - - CC4IF - Capture/Compare 4 interrupt - flag - 4 - 1 - - - CC3IF - Capture/Compare 3 interrupt - flag - 3 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - BG - Break generation - 7 - 1 - - - TG - Trigger generation - 6 - 1 - - - COMG - Capture/Compare control update - generation - 5 - 1 - - - CC4G - Capture/compare 4 - generation - 4 - 1 - - - CC3G - Capture/compare 3 - generation - 3 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - Output Compare 2 clear - enable - 15 - 1 - - - OC2M - Output Compare 2 mode - 12 - 3 - - - OC2PE - Output Compare 2 preload - enable - 11 - 1 - - - OC2FE - Output Compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1CE - Output Compare 1 clear - enable - 7 - 1 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - ICPSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register (output - mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - Output compare 4 clear - enable - 15 - 1 - - - OC4M - Output compare 4 mode - 12 - 3 - - - OC4PE - Output compare 4 preload - enable - 11 - 1 - - - OC4FE - Output compare 4 fast - enable - 10 - 1 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - OC3CE - Output compare 3 clear - enable - 7 - 1 - - - OC3M - Output compare 3 mode - 4 - 3 - - - OC3PE - Output compare 3 preload - enable - 3 - 1 - - - OC3FE - Output compare 3 fast - enable - 2 - 1 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input - mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - IC3F - Input capture 3 filter - 4 - 4 - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - CC3S - Capture/compare 3 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC4P - Capture/Compare 3 output - Polarity - 13 - 1 - - - CC4E - Capture/Compare 4 output - enable - 12 - 1 - - - CC3NP - Capture/Compare 3 output - Polarity - 11 - 1 - - - CC3NE - Capture/Compare 3 complementary output - enable - 10 - 1 - - - CC3P - Capture/Compare 3 output - Polarity - 9 - 1 - - - CC3E - Capture/Compare 3 output - enable - 8 - 1 - - - CC2NP - Capture/Compare 2 output - Polarity - 7 - 1 - - - CC2NE - Capture/Compare 2 complementary output - enable - 6 - 1 - - - CC2P - Capture/Compare 2 output - Polarity - 5 - 1 - - - CC2E - Capture/Compare 2 output - enable - 4 - 1 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1NE - Capture/Compare 1 complementary output - enable - 2 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - RCR - RCR - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - REP - Repetition counter value - 0 - 8 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - CCR3 - CCR3 - capture/compare register 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - CCR3 - Capture/Compare value - 0 - 16 - - - - - CCR4 - CCR4 - capture/compare register 4 - 0x40 - 0x20 - read-write - 0x00000000 - - - CCR4 - Capture/Compare value - 0 - 16 - - - - - BDTR - BDTR - break and dead-time register - 0x44 - 0x20 - read-write - 0x0000 - - - MOE - Main output enable - 15 - 1 - - - AOE - Automatic output enable - 14 - 1 - - - BKP - Break polarity - 13 - 1 - - - BKE - Break enable - 12 - 1 - - - OSSR - Off-state selection for Run - mode - 11 - 1 - - - OSSI - Off-state selection for Idle - mode - 10 - 1 - - - LOCK - Lock configuration - 8 - 2 - - - DTG - Dead-time generator setup - 0 - 8 - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DBL - DMA burst length - 8 - 5 - - - DBA - DMA base address - 0 - 5 - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMAB - DMA register for burst - accesses - 0 - 16 - - - - - - - TIM3 - General purpose timer - TIM - 0x40000400 - - 0x00 - 0x400 - registers - - - TIM3 - TIM3 global Interrupt - 16 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Clock division - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - CMS - Center-aligned mode - selection - 5 - 2 - - - DIR - Direction - 4 - 1 - - - OPM - One-pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - TI1S - TI1 selection - 7 - 1 - - - MMS - Master mode selection - 4 - 3 - - - CCDS - Capture/compare DMA - selection - 3 - 1 - - - - - SMCR - SMCR - slave mode control register - 0x8 - 0x20 - read-write - 0x0000 - - - MSM - Master/Slave mode - 7 - 1 - - - TS - Trigger selection - 4 - 3 - - - OCCS - OCREF Clear Selection - 3 - 1 - - - SMS - Slave mode selection - 0 - 3 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - TDE - Trigger DMA request enable - 14 - 1 - - - CC4DE - Capture/Compare 4 DMA request - enable - 12 - 1 - - - CC3DE - Capture/Compare 3 DMA request - enable - 11 - 1 - - - CC2DE - Capture/Compare 2 DMA request - enable - 10 - 1 - - - CC1DE - Capture/Compare 1 DMA request - enable - 9 - 1 - - - UDE - Update DMA request enable - 8 - 1 - - - TIE - Trigger interrupt enable - 6 - 1 - - - CC4IE - Capture/Compare 4 interrupt - enable - 4 - 1 - - - CC3IE - Capture/Compare 3 interrupt - enable - 3 - 1 - - - CC2IE - Capture/Compare 2 interrupt - enable - 2 - 1 - - - CC1IE - Capture/Compare 1 interrupt - enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC4OF - Capture/Compare 4 overcapture - flag - 12 - 1 - - - CC3OF - Capture/Compare 3 overcapture - flag - 11 - 1 - - - CC2OF - Capture/compare 2 overcapture - flag - 10 - 1 - - - CC1OF - Capture/Compare 1 overcapture - flag - 9 - 1 - - - TIF - Trigger interrupt flag - 6 - 1 - - - CC4IF - Capture/Compare 4 interrupt - flag - 4 - 1 - - - CC3IF - Capture/Compare 3 interrupt - flag - 3 - 1 - - - CC2IF - Capture/Compare 2 interrupt - flag - 2 - 1 - - - CC1IF - Capture/compare 1 interrupt - flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - TG - Trigger generation - 6 - 1 - - - CC4G - Capture/compare 4 - generation - 4 - 1 - - - CC3G - Capture/compare 3 - generation - 3 - 1 - - - CC2G - Capture/compare 2 - generation - 2 - 1 - - - CC1G - Capture/compare 1 - generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register 1 (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC2CE - Output compare 2 clear - enable - 15 - 1 - - - OC2M - Output compare 2 mode - 12 - 3 - - - OC2PE - Output compare 2 preload - enable - 11 - 1 - - - OC2FE - Output compare 2 fast - enable - 10 - 1 - - - CC2S - Capture/Compare 2 - selection - 8 - 2 - - - OC1CE - Output compare 1 clear - enable - 7 - 1 - - - OC1M - Output compare 1 mode - 4 - 3 - - - OC1PE - Output compare 1 preload - enable - 3 - 1 - - - OC1FE - Output compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC2F - Input capture 2 filter - 12 - 4 - - - IC2PSC - Input capture 2 prescaler - 10 - 2 - - - CC2S - Capture/compare 2 - selection - 8 - 2 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR2_Output - CCMR2_Output - capture/compare mode register 2 (output - mode) - 0x1C - 0x20 - read-write - 0x00000000 - - - OC4CE - Output compare 4 clear - enable - 15 - 1 - - - OC4M - Output compare 4 mode - 12 - 3 - - - OC4PE - Output compare 4 preload - enable - 11 - 1 - - - OC4FE - Output compare 4 fast - enable - 10 - 1 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - OC3CE - Output compare 3 clear - enable - 7 - 1 - - - OC3M - Output compare 3 mode - 4 - 3 - - - OC3PE - Output compare 3 preload - enable - 3 - 1 - - - OC3FE - Output compare 3 fast - enable - 2 - 1 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCMR2_Input - CCMR2_Input - capture/compare mode register 2 (input - mode) - CCMR2_Output - 0x1C - 0x20 - read-write - 0x00000000 - - - IC4F - Input capture 4 filter - 12 - 4 - - - IC4PSC - Input capture 4 prescaler - 10 - 2 - - - CC4S - Capture/Compare 4 - selection - 8 - 2 - - - IC3F - Input capture 3 filter - 4 - 4 - - - IC3PSC - Input capture 3 prescaler - 2 - 2 - - - CC3S - Capture/Compare 3 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC4NP - - Capture/Compare 4 output - Polarity - - 15 - 1 - - - CC4P - - Capture/Compare 4 output - Polarity - - 13 - 1 - - - CC4E - - Capture/Compare 4 output - enable - - 12 - 1 - - - CC3NP - - Capture/Compare 3 output - Polarity - - 11 - 1 - - - CC3P - - Capture/Compare 3 output - Polarity - - 9 - 1 - - - CC3E - - Capture/Compare 3 output - enable - - 8 - 1 - - - CC2NP - - Capture/Compare 2 output - Polarity - - 7 - 1 - - - CC2P - - Capture/Compare 2 output - Polarity - - 5 - 1 - - - CC2E - - Capture/Compare 2 output - enable - - 4 - 1 - - - CC1NP - - Capture/Compare 1 output - Polarity - - 3 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - CCR2 - CCR2 - capture/compare register 2 - 0x38 - 0x20 - read-write - 0x00000000 - - - CCR2 - Capture/Compare 2 value - 0 - 16 - - - - - CCR3 - CCR3 - capture/compare register 3 - 0x3C - 0x20 - read-write - 0x00000000 - - - CCR3 - Capture/Compare value - 0 - 16 - - - - - CCR4 - CCR4 - capture/compare register 4 - 0x40 - 0x20 - read-write - 0x00000000 - - - CCR4 - Capture/Compare value - 0 - 16 - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DBL - DMA burst length - 8 - 5 - - - DBA - DMA base address - 0 - 5 - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMAB - DMA register for burst - accesses - 0 - 32 - - - - - - - TIM14 - General purpose timer - TIM - 0x40002000 - - 0x00 - 0x400 - registers - - - TIM14 - TIM14 global Interrupt - 19 - - - - CR1 - CR1 - TIM14 control register1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Prescaler factor - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - CC1IE - Compare/ - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC1OF - Compare/capture 1 flag - 9 - 1 - - - CC1IF - Compare/capture 1 interrupt flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - CC1G - Compare/capture1 event - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - OR - OR - Option register - 0x50 - 0x20 - read-write - 0x00000000 - - - TI1_RMP - TIM14 channel1 input remap - 0 - 2 - - - - - - - TIM16 - General purpose timer - TIM - 0x40014400 - - 0x00 - 0x400 - registers - - - TIM16 - TIM16 global Interrupt - 21 - - - - CR1 - CR1 - TIM16 control register1 - 0x0 - 0x20 - read-write - 0x0000 - - - CKD - Prescaler factor - 8 - 2 - - - ARPE - Auto-reload preload enable - 7 - 1 - - - OPM - One pulse mode - 3 - 1 - - - URS - Update request source - 2 - 1 - - - UDIS - Update disable - 1 - 1 - - - CEN - Counter enable - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - OIS1N - Output Idle state 1 - 9 - 1 - - - OIS1 - Output Idle state 1 - 8 - 1 - - - CCDS - Capture/compare DMA - selection - 3 - 1 - - - CCPC - Capture/compare preloaded - control - 0 - 1 - - - - - DIER - DIER - DMA/Interrupt enable register - 0xC - 0x20 - read-write - 0x0000 - - - CC1DE - Compare/capture DMA requeset enable - 9 - 1 - - - UDE - Update DMA request enable - 8 - 1 - - - BIE - Break interrupt enable - 7 - 1 - - - COMIE - Com interrupt enable - 5 - 1 - - - CC1IE - Capture/Compare 1 interrupt enable - 1 - 1 - - - UIE - Update interrupt enable - 0 - 1 - - - - - SR - SR - status register - 0x10 - 0x20 - read-write - 0x0000 - - - CC1OF - Update interrupt flag - 9 - 1 - - - BIF - Break interrupt flag - 7 - 1 - - - COMIF - Com interrupt flag - 5 - 1 - - - CC1IF - Capture/Compare 1 interrupt flag - 1 - 1 - - - UIF - Update interrupt flag - 0 - 1 - - - - - EGR - EGR - event generation register - 0x14 - 0x20 - write-only - 0x0000 - - - BG - Break event generation - 7 - 1 - - - COMG - COM evnet generation - 5 - 1 - - - CC1G - Capture/Compare 1 generation - 1 - 1 - - - UG - Update generation - 0 - 1 - - - - - CCMR1_Output - CCMR1_Output - capture/compare mode register (output - mode) - 0x18 - 0x20 - read-write - 0x00000000 - - - OC1M - Output Compare 1 mode - 4 - 3 - - - OC1PE - Output Compare 1 preload - enable - 3 - 1 - - - OC1FE - Output Compare 1 fast - enable - 2 - 1 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCMR1_Input - CCMR1_Input - capture/compare mode register 1 (input - mode) - CCMR1_Output - 0x18 - 0x20 - read-write - 0x00000000 - - - IC1F - Input capture 1 filter - 4 - 4 - - - IC1PSC - Input capture 1 prescaler - 2 - 2 - - - CC1S - Capture/Compare 1 - selection - 0 - 2 - - - - - CCER - CCER - capture/compare enable - register - 0x20 - 0x20 - read-write - 0x0000 - - - CC1NP - Capture/Compare 1 output - Polarity - 3 - 1 - - - CC1NE - Capture/Compare 1 complementary output - enable - 2 - 1 - - - CC1P - Capture/Compare 1 output - Polarity - 1 - 1 - - - CC1E - Capture/Compare 1 output - enable - 0 - 1 - - - - - CNT - CNT - counter - 0x24 - 0x20 - read-write - 0x00000000 - - - CNT - counter value - 0 - 16 - - - - - PSC - PSC - prescaler - 0x28 - 0x20 - read-write - 0x0000 - - - PSC - Prescaler value - 0 - 16 - - - - - ARR - ARR - auto-reload register - 0x2C - 0x20 - read-write - 0x00000000 - - - ARR - Auto-reload value - 0 - 16 - - - - - RCR - RCR - repetition counter register - 0x30 - 0x20 - read-write - 0x0000 - - - REP - Repetition counter value - 0 - 8 - - - - - CCR1 - CCR1 - capture/compare register 1 - 0x34 - 0x20 - read-write - 0x00000000 - - - CCR1 - Capture/Compare 1 value - 0 - 16 - - - - - BDTR - BDTR - break and dead-time register - 0x44 - 0x20 - read-write - 0x0000 - - - MOE - Main output enable - 15 - 1 - - - AOE - Automatic output enable - 14 - 1 - - - BKP - Break polarity - 13 - 1 - - - BKE - Break enable - 12 - 1 - - - OSSR - Off-state selection for Run - mode - 11 - 1 - - - OSSI - Off-state selection for Idle - mode - 10 - 1 - - - LOCK - Lock configuration - 8 - 2 - - - DTG - Dead-time generator setup - 0 - 8 - - - - - DCR - DCR - DMA control register - 0x48 - 0x20 - read-write - 0x0000 - - - DBL - DMA burst length - 8 - 5 - - - DBA - DMA base address - 0 - 5 - - - - - DMAR - DMAR - DMA address for full transfer - 0x4C - 0x20 - read-write - 0x0000 - - - DMAB - DMA register for burst - accesses - 0 - 32 - - - - - - - TIM17 - 0x40014800 - - TIM17 - TIM17 global Interrupt - 22 - - - - SYSCFG - System configuration controller - SYSCFG - 0x40010000 - - 0x0 - 0x30 - registers - - - - CFGR1 - CFGR1 - SYSCFG configuration register - 1 - 0x0 - 0x20 - read-write - 0x00000000 - - - I2C_PF1_ANF - Analog filter enable control driving capability - activation bits PF1 - 30 - 1 - - - I2C_PF0_ANF - Analog filter enable control driving capability - activation bits PF0 - 29 - 1 - - - I2C_PB8_ANF - Analog filter enable control driving capability - activation bits PB8 - 28 - 1 - - - I2C_PB7_ANF - Analog filter enable control driving capability - activation bits PB7 - 27 - 1 - - I2C_PB6_ANF - Analog filter enable control driving capability - activation bits PB6 - 26 - 1 - - - I2C_PA12_ANF - Analog filter enable control driving capability - activation bits PA12 - 25 - 1 - - - I2C_PA11_ANF - Analog filter enable control driving capability - activation bits PA11 - 24 - 1 - - - I2C_PA10_ANF - Analog filter enable control driving capability - activation bits PA10 - 23 - 1 - - - I2C_PA9_ANF - Analog filter enable control driving capability - activation bits PA9 - 22 - 1 - - - I2C_PA8_ANF - Analog filter enable control driving capability - activation bits PA8 - 21 - 1 - - - I2C_PA7_ANF - Analog filter enable control driving capability - activation bits PA7 - 20 - 1 - - - I2C_PA3_ANF - Analog filter enable control driving capability - activation bits PA3 - 19 - 1 - - - I2C_PA2_ANF - Analog filter enable control driving capability - activation bits PA2 - 18 - 1 - - - MEM_MODE - Memory mapping selection - bits - 0 - 2 - - - - - CFGR2 - CFGR2 - SYSCFG configuration register - 2 - 0x18 - 0x20 - read-write - 0x00000000 - - - ETR_SRC_TIM1 - TIM1 ETR source selection - 9 - 2 - - - COMP2_BRK_TIM17 - COMP2 is enable to input of TIM17 break - 8 - 1 - - - COMP1_BRK_TIM17 - COMP1 is enable to input of TIM17 break - 7 - 1 - - - COMP2_BRK_TIM16 - COMP2 is enable to input of TIM16 break - 6 - 1 - - - COMP1_BRK_TIM16 - COMP1 is enable to input of TIM16 break - 5 - 1 - - - COMP2_BRK_TIM1 - COMP2 is enable to input of TIM1 break - 4 - 1 - - - COMP1_BRK_TIM1 - COMP1 is enable to input of TIM1 break - 3 - 1 - - - PVD_LOCK - PVD lock enable bit - 2 - 1 - - - LOCKUP_LOCK - Cortex-M0+ LOCKUP bit enable - bit - 0 - 1 - - - - - CFGR3 - CFGR3 - SYSCFG configuration register - 3 - 0x1C - 0x20 - read-write - 0x00000000 - - - DMA3_MAP - DMA channel3 requeset selection - 16 - 5 - - - DMA2_MAP - DMA channel2 requeset selection - 8 - 5 - - - DMA1_MAP - DMA channel1 requeset selection - 0 - 5 - - - - - - - DMA - Direct memory access - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA_Channel1 - DMA Channel 1 Interrupt - 9 - - - DMA_Channel2_3 - DMA Channel 2 and Channel 3 Interrupt - 10 - - - - ISR - ISR - DMA interrupt status register - (DMA_ISR) - 0x0 - 0x20 - read-only - 0x00000000 - - - TEIF3 - Channel 3 Transfer Error - flag - 11 - 1 - - - HTIF3 - Channel 3 Half Transfer Complete - flag - 10 - 1 - - - TCIF3 - Channel 3 Transfer Complete - flag - 9 - 1 - - - GIF3 - Channel 3 Global interrupt - flag - 8 - 1 - - - TEIF2 - Channel 2 Transfer Error - flag - 7 - 1 - - - HTIF2 - Channel 2 Half Transfer Complete - flag - 6 - 1 - - - TCIF2 - Channel 2 Transfer Complete - flag - 5 - 1 - - - GIF2 - Channel 2 Global interrupt - flag - 4 - 1 - - - TEIF1 - Channel 1 Transfer Error - flag - 3 - 1 - - - HTIF1 - Channel 1 Half Transfer Complete - flag - 2 - 1 - - - TCIF1 - Channel 1 Transfer Complete - flag - 1 - 1 - - - GIF1 - Channel 1 Global interrupt - flag - 0 - 1 - - - - - IFCR - IFCR - DMA interrupt flag clear register - (DMA_IFCR) - 0x4 - 0x20 - write-only - 0x00000000 - - - CTEIF3 - Channel 3 Transfer Error - clear - 11 - 1 - - - CHTIF3 - Channel 3 Half Transfer - clear - 10 - 1 - - - CTCIF3 - Channel 3 Transfer Complete - clear - 9 - 1 - - - CGIF3 - Channel 3 Global interrupt - clear - 8 - 1 - - - CTEIF2 - Channel 2 Transfer Error - clear - 7 - 1 - - - CHTIF2 - Channel 2 Half Transfer - clear - 6 - 1 - - - CTCIF2 - Channel 2 Transfer Complete - clear - 5 - 1 - - - CGIF2 - Channel 2 Global interrupt - clear - 4 - 1 - - - CTEIF1 - Channel 1 Transfer Error - clear - 3 - 1 - - - CHTIF1 - Channel 1 Half Transfer - clear - 2 - 1 - - - CTCIF1 - Channel 1 Transfer Complete - clear - 1 - 1 - - - CGIF1 - Channel 1 Global interrupt - clear - 0 - 1 - - - - - CCR1 - CCR1 - DMA channel configuration register - (DMA_CCR) - 0x8 - 0x20 - read-write - 0x00000000 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - PL - Channel Priority level - 12 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PSIZE - Peripheral size - 8 - 2 - - - MINC - Memory increment mode - 7 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - CIRC - Circular mode - 5 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - EN - Channel enable - 0 - 1 - - - - - CNDTR1 - CNDTR1 - DMA channel 1 number of data - register - 0xC - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR1 - CPAR1 - DMA channel 1 peripheral address - register - 0x10 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR1 - CMAR1 - DMA channel 1 memory address - register - 0x14 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR2 - CCR2 - DMA channel configuration register - (DMA_CCR) - 0x1C - 0x20 - read-write - 0x00000000 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - PL - Channel Priority level - 12 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PSIZE - Peripheral size - 8 - 2 - - - MINC - Memory increment mode - 7 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - CIRC - Circular mode - 5 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - EN - Channel enable - 0 - 1 - - - - - CNDTR2 - CNDTR2 - DMA channel 2 number of data - register - 0x20 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR2 - CPAR2 - DMA channel 2 peripheral address - register - 0x24 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR2 - CMAR2 - DMA channel 2 memory address - register - 0x28 - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - CCR3 - CCR3 - DMA channel configuration register - (DMA_CCR) - 0x30 - 0x20 - read-write - 0x00000000 - - - MEM2MEM - Memory to memory mode - 14 - 1 - - - PL - Channel Priority level - 12 - 2 - - - MSIZE - Memory size - 10 - 2 - - - PSIZE - Peripheral size - 8 - 2 - - - MINC - Memory increment mode - 7 - 1 - - - PINC - Peripheral increment mode - 6 - 1 - - - CIRC - Circular mode - 5 - 1 - - - DIR - Data transfer direction - 4 - 1 - - - TEIE - Transfer error interrupt - enable - 3 - 1 - - - HTIE - Half Transfer interrupt - enable - 2 - 1 - - - TCIE - Transfer complete interrupt - enable - 1 - 1 - - - EN - Channel enable - 0 - 1 - - - - - CNDTR3 - CNDTR3 - DMA channel 3 number of data - register - 0x34 - 0x20 - read-write - 0x00000000 - - - NDT - Number of data to transfer - 0 - 16 - - - - - CPAR3 - CPAR3 - DMA channel 3 peripheral address - register - 0x38 - 0x20 - read-write - 0x00000000 - - - PA - Peripheral address - 0 - 32 - - - - - CMAR3 - CMAR3 - DMA channel 3 memory address - register - 0x3C - 0x20 - read-write - 0x00000000 - - - MA - Memory address - 0 - 32 - - - - - - - FLASH - Flash - Flash - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - FLASH global Interrupt - 3 - - - - ACR - ACR - Access control register - 0x0 - 0x20 - read-write - 0x00000600 - - - LATENCY - Latency - 0 - 1 - - - - - KEYR - KEYR - Flash key register - 0x8 - 0x20 - write-only - 0x00000000 - - - KEY - Flash key - 0 - 32 - - - - - OPTKEYR - OPTKEYR - Option byte key register - 0xC - 0x20 - write-only - 0x00000000 - - - OPTKEY - Option byte key - 0 - 32 - - - - - SR - SR - Status register - 0x10 - 0x20 - read-write - 0x00000000 - - - BSY - Busy - 16 - 1 - - - OPTVERR - Option and Engineering bits loading - validity error - 15 - 1 - - - WRPERR - Write protected error - 4 - 1 - - - EOP - End of operation - 0 - 1 - - - - - CR - CR - Flash control register - 0x14 - 0x20 - read-write - 0xC0000000 - - - LOCK - FLASH_CR Lock - 31 - 1 - - - OPTLOCK - Options Lock - 30 - 1 - - - OBL_LAUNCH - Force the option byte - loading - 27 - 1 - - - ERRIE - Error interrupt enable - 25 - 1 - - - EOPIE - End of operation interrupt - enable - 24 - 1 - - - PGTSTRT - Flash main memory program start - 19 - 1 - - - OPTSTRT - Option byte program start - 17 - 1 - - - SER - Sector erase - 11 - 1 - - - MER - Mass erase - 2 - 1 - - - PER - Page erase - 1 - 1 - - - PG - Programming - 0 - 1 - - - - - OPTR - OPTR - Flash option register - 0x20 - 0x20 - read-write - 0x4F55B0AA - - - nBOOT1 - Boot configuration - 15 - 1 - - - NRST_MODE - NRST_MODE - 14 - 1 - - - WWDG_SW - Window watchdog selection - 13 - 1 - - - IDWG_SW - Independent watchdog - selection - 12 - 1 - - - BORF_LEV - These bits contain the VDD supply level - threshold that activates the reset - 9 - 3 - - - BOREN - BOR reset Level - 8 - 1 - - - RDP - Read Protection - 0 - 8 - - - - - SDKR - SDKR - Flash SDK address - register - 0x24 - 0x20 - read-write - 0xFFE0001F - - - SDK_END - SDK area end address - 8 - 5 - - - SDK_STRT - SDK area start address - 0 - 5 - - - - - WRPR - WRPR - Flash WRP address - register - 0x2C - 0x20 - read-write - 0x0000FFFF - - - WRP - WRP address - 0 - 16 - - - - - STCR - STCR - Flash sleep time config - register - 0x90 - 0x20 - read-write - 0x00006400 - - - SLEEP_TIME - FLash sleep time configuration(counter based on HSI_10M) - 8 - 8 - - - SLEEP_EN - FLash sleep enable - 0 - 1 - - - - - TS0 - TS0 - Flash TS0 - register - 0x100 - 0x20 - read-write - 0x000000B4 - - - TS0 - FLash TS0 register - 0 - 8 - - - - - TS1 - TS1 - Flash TS1 - register - 0x104 - 0x20 - read-write - 0x000001B0 - - - TS1 - FLash TS1 register - 0 - 9 - - - - - TS2P - TS2P - Flash TS2P - register - 0x108 - 0x20 - read-write - 0x000000B4 - - - TS2P - FLash TS2P register - 0 - 8 - - - - - TPS3 - TPS3 - Flash TPS3 - register - 0x10C - 0x20 - read-write - 0x000006C0 - - - TPS3 - FLash TPS3 register - 0 - 11 - - - - - TS3 - TS3 - Flash TS3 - register - 0x110 - 0x20 - read-write - 0x000000B4 - - - TS3 - FLash TS3 register - 0 - 8 - - - - - PERTPE - PERTPE - Flash PERTPE - register - 0x114 - 0x20 - read-write - 0x0000EA60 - - - PERTPE - FLash PERTPE register - 0 - 17 - - - - - SMERTPE - SMERTPE - Flash SMERTPE - register - 0x118 - 0x20 - read-write - 0x0000FD20 - - - SMERTPE - FLash SMERTPE register - 0 - 17 - - - - - PRGTPE - PRGTPE - Flash PRGTPE - register - 0x11C - 0x20 - read-write - 0x00008CA0 - - - PRGTPE - FLash PRGTPE register - 0 - 16 - - - - - PRETPE - PRETPE - Flash PRETPE - register - 0x120 - 0x20 - read-write - 0x000012C0 - - - PRETPE - FLash PRETPE register - 0 - 13 - - - - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DR - DR - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DR - Data Register - 0 - 32 - - - - - IDR - IDR - Independent Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - IDR - Independent Data register - 0 - 8 - - - - - CR - CR - Control register - 0x8 - 0x20 - write-only - 0x00000000 - - - RESET - Reset bit - 0 - 1 - - - - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global Interrupt - 25 - - - - CR1 - CR1 - control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - BIDIMODE - Bidirectional data mode - enable - 15 - 1 - - - BIDIOE - Output enable in bidirectional - mode - 14 - 1 - - - RXONLY - Receive only - 10 - 1 - - - SSM - Software slave management - 9 - 1 - - - SSI - Internal slave selection - 8 - 1 - - - LSBFIRST - Frame format - 7 - 1 - - - SPE - SPI enable - 6 - 1 - - - BR - Baud rate control - 3 - 3 - - - MSTR - Master selection - 2 - 1 - - - CPOL - Clock polarity - 1 - 1 - - - CPHA - Clock phase - 0 - 1 - - - - - CR2 - CR2 - control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - SLVFM - Slave fast mode enable - 15 - 1 - - - LDMA_TX - Last DAM Transmit(TX) - 14 - 1 - - - LDMA_RX - Last DAM Transmit(RX) - 13 - 1 - - - FRXTH - FIFO reception threshold - 12 - 1 - - - DS - Data length - - 11 - 1 - - - TXEIE - Tx buffer empty interrupt - enable - 7 - 1 - - - RXNEIE - RX buffer not empty interrupt - enable - 6 - 1 - - - ERRIE - Error interrupt enable - 5 - 1 - - - SSOE - SS output enable - 2 - 1 - - - TXDMAEN - Tx buffer DMA enable - 1 - 1 - - - RXDMAEN - Rx buffer DMA enable - 0 - 1 - - - - - SR - SR - status register - 0x8 - 0x20 - 0x0002 - - - FTLVL - FIFO transmission level - 11 - 2 - read-only - - - FRLVL - FIFO reception level - 9 - 2 - read-only - - - BSY - Busy flag - 7 - 1 - read-only - - - OVR - Overrun flag - 6 - 1 - read-only - - - MODF - Mode fault - 5 - 1 - read-only - - - TXE - Transmit buffer empty - 1 - 1 - read-only - - - RXNE - Receive buffer not empty - 0 - 1 - read-only - - - - - DR - DR - data register - 0xC - 0x20 - read-write - 0x0000 - - - DR - Data register - 0 - 16 - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global Interrupt - 26 - - - - I2C - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1 - I2C1 global Interrupt - 23 - - - - CR1 - CR1 - Control register 1 - 0x0 - 0x20 - read-write - 0x0000 - - - SWRST - Software reset - 15 - 1 - - - PEC - Packet error checking - 12 - 1 - - - POS - Acknowledge/PEC Position (for data - reception) - 11 - 1 - - - ACK - Acknowledge enable - 10 - 1 - - - STOP - Stop generation - 9 - 1 - - - START - Start generation - 8 - 1 - - - NOSTRETCH - Clock stretching disable (Slave - mode) - 7 - 1 - - - ENGC - General call enable - 6 - 1 - - - ENPEC - PEC enable - 5 - 1 - - - PE - Peripheral enable - 0 - 1 - - - - - CR2 - CR2 - Control register 2 - 0x4 - 0x20 - read-write - 0x0000 - - - LAST - DMA last transfer - 12 - 1 - - - DMAEN - DMA requests enable - 11 - 1 - - - ITBUFEN - Buffer interrupt enable - 10 - 1 - - - ITEVTEN - Event interrupt enable - 9 - 1 - - - ITERREN - Error interrupt enable - 8 - 1 - - - FREQ - Peripheral clock frequency - 0 - 6 - - - - - OAR1 - OAR1 - Own address register 1 - 0x8 - 0x20 - read-write - 0x0000 - - - ADD - Interface address - 1 - 7 - - - - - DR - DR - Data register - 0x10 - 0x20 - read-write - 0x0000 - - - DR - 8-bit data register - 0 - 8 - - - - - SR1 - SR1 - Status register 1 - 0x14 - 0x20 - 0x0000 - - - PECERR - PEC Error in reception - 12 - 1 - read-write - - - OVR - Overrun/Underrun - 11 - 1 - read-write - - - AF - Acknowledge failure - 10 - 1 - read-write - - - ARLO - Arbitration lost (master - mode) - 9 - 1 - read-write - - - BERR - Bus error - 8 - 1 - read-write - - - TxE - Data register empty - (transmitters) - 7 - 1 - read-only - - - RxNE - Data register not empty - (receivers) - 6 - 1 - read-only - - - STOPF - Stop detection (slave - mode) - 4 - 1 - read-only - - - BTF - Byte transfer finished - 2 - 1 - read-only - - - ADDR - Address sent (master mode)/matched - (slave mode) - 1 - 1 - read-only - - - SB - Start bit (Master mode) - 0 - 1 - read-only - - - - - SR2 - SR2 - Status register 2 - 0x18 - 0x20 - read-only - 0x0000 - - - PEC - acket error checking - register - 8 - 8 - - - DUALF - Dual flag (Slave mode) - 7 - 1 - - - GENCALL - General call address (Slave - mode) - 4 - 1 - - - TRA - Transmitter/receiver - 2 - 1 - - - BUSY - Bus busy - 1 - 1 - - - MSL - Master/slave - 0 - 1 - - - - - CCR - CCR - Clock control register - 0x1C - 0x20 - read-write - 0x0000 - - - F_S - I2C master mode selection - 15 - 1 - - - DUTY - Fast mode duty cycle - 14 - 1 - - - CCR - Clock control register in Fast/Standard - mode (Master mode) - 0 - 12 - - - - - TRISE - TRISE - TRISE register - 0x20 - 0x20 - read-write - 0x0002 - - - TRISE - Maximum rise time in Fast/Standard mode - (Master mode) - 0 - 6 - - - - - - - LED - LED CONTROLLER - LED - 0x40002400 - - 0x0 - 0x400 - registers - - - LED - LED global Interrupt - 30 - - - - CR - LED_CR - Control register - 0x0 - 0x20 - read-write - 0x0000 - - - EHS - Light control - 12 - 2 - - - IE - LED interrupt enable - 3 - 1 - - - LED_COM_SEL - LED COM Selection - 1 - 2 - - - LEDON - LED enable - 0 - 1 - - - - - PR - LED_PR - Prescaler register - 0x4 - 0x20 - read-write - 0x0000 - - - PR - Prescaler control - 0 - 8 - - - - - TR - LED_TR - Time register - 0x8 - 0x20 - read-write - 0x0000 - - - T2 - Switch time - 8 - 8 - - - T1 - Light on time - 0 - 8 - - - - - DR0 - LED_DR0 - Data0 register - 0x0C - 0x20 - read-write - 0x0000 - - - DATA0_DP - 8-bit data register - 7 - 1 - - - DATA0_G - 8-bit data register - 6 - 1 - - - DATA0_F - 8-bit data register - 5 - 1 - - - DATA0_E - 8-bit data register - 4 - 1 - - - DATA0_D - 8-bit data register - 3 - 1 - - - DATA0_C - 8-bit data register - 2 - 1 - - - DATA0_B - 8-bit data register - 1 - 1 - - - DATA0_A - 8-bit data register - 0 - 1 - - - - - DR1 - LED_DR1 - Data1 register - 0x10 - 0x20 - read-write - 0x0000 - - - DATA1_DP - 8-bit data register - 7 - 1 - - - DATA1_G - 8-bit data register - 6 - 1 - - - DATA1_F - 8-bit data register - 5 - 1 - - - DATA1_E - 8-bit data register - 4 - 1 - - - DATA1_D - 8-bit data register - 3 - 1 - - - DATA1_C - 8-bit data register - 2 - 1 - - - DATA1_B - 8-bit data register - 1 - 1 - - - DATA1_A - 8-bit data register - 0 - 1 - - - - - DR2 - LED_DR2 - Data2 register - 0x14 - 0x20 - read-write - 0x0000 - - - DATA2_DP - 8-bit data register - 7 - 1 - - - DATA2_G - 8-bit data register - 6 - 1 - - - DATA2_F - 8-bit data register - 5 - 1 - - - DATA2_E - 8-bit data register - 4 - 1 - - - DATA2_D - 8-bit data register - 3 - 1 - - - DATA2_C - 8-bit data register - 2 - 1 - - - DATA2_B - 8-bit data register - 1 - 1 - - - DATA2_A - 8-bit data register - 0 - 1 - - - - - DR3 - LED_DR3 - Data3 register - 0x18 - 0x20 - read-write - 0x0000 - - - DATA3_DP - 8-bit data register - 7 - 1 - - - DATA3_G - 8-bit data register - 6 - 1 - - - DATA3_F - 8-bit data register - 5 - 1 - - - DATA3_E - 8-bit data register - 4 - 1 - - - DATA3_D - 8-bit data register - 3 - 1 - - - DATA3_C - 8-bit data register - 2 - 1 - - - DATA3_B - 8-bit data register - 1 - 1 - - - DATA3_A - 8-bit data register - 0 - 1 - - - - - IR - LED_IR - Interrupt register 1 - 0x1C - 0x20 - 0x0000 - - - FLAG - interrupt flag - 0 - 1 - read-write - - - - - - - DBGMCU - Debug support - DBGMCU - 0x40015800 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - MCU Device ID Code Register - 0x0 - 0x20 - read-only - 0x0 - - - - - - CR - CR - Debug MCU Configuration - Register - 0x4 - 0x20 - read-write - 0x0 - - - DBG_STOP - Debug Stop Mode - 1 - 1 - - - - - APB_FZ1 - APB_FZ1 - APB Freeze Register1 - 0x8 - 0x20 - read-write - 0x0 - - - DBG_TIMER3_STOP - Debug Timer 3 stopped when Core is - halted - 1 - 1 - - - DBG_RTC_STOP - Debug RTC stopped when Core is - halted - 10 - 1 - - - DBG_WWDG_STOP - Debug Window Wachdog stopped when Core - is halted - 11 - 1 - - - DBG_IWDG_STOP - Debug Independent Wachdog stopped when - Core is halted - 12 - 1 - - - DBG_LPTIM_STOP - Debug LPTIM stopped when Core is - halted - 31 - 1 - - - - - APB_FZ2 - APB_FZ2 - APB Freeze Register2 - 0xC - 0x20 - read-write - 0x0 - - - DBG_TIMER1_STOP - Debug Timer 1 stopped when Core is - halted - 11 - 1 - - - DBG_TIMER14_STOP - Debug Timer 14 stopped when Core is - halted - 15 - 1 - - - DBG_TIMER16_STOP - Debug Timer 16 stopped when Core is - halted - 17 - 1 - - - DBG_TIMER17_STOP - Debug Timer 17 stopped when Core is - halted - 18 - 1 - - - - - - - + + + + Puya + Puya + PY32F0xx_DFP + + PY32F0 + 1.0.0 + Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. + + + + CM0+ + r0p1 + little + false + false + 4 + false + + + + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + ADC + Analog to Digital Converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + ISR + ISR + ADC interrupt and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + AWD + ADC analog watchdog flag + 7 + 1 + + + OVR + ADC group regular overrun + flag + 4 + 1 + + + EOSEQ + ADC group regular end of sequence + conversions flag + 3 + 1 + + + EOC + ADC group regular end of unitary + conversion flag + 2 + 1 + + + EOSMP + ADC group regular end of sampling + flag + 1 + 1 + + + + + IER + IER + ADC interrupt enable register + 0x4 + 0x20 + read-write + 0x00000000 + + + AWDIE + ADC analog watchdog + interrupt + 7 + 1 + + + OVRIE + ADC group regular overrun + interrupt + 4 + 1 + + + EOSEQIE + ADC group regular end of sequence + conversions interrupt + 3 + 1 + + + EOCIE + ADC group regular end of unitary + conversion interrupt + 2 + 1 + + + EOSMPIE + ADC group regular end of sampling + interrupt + 1 + 1 + + + + + CR + CR + ADC control register + 0x8 + 0x20 + read-write + 0x00000000 + + + ADCAL + ADC group regular conversion + calibration + 31 + 1 + + + ADSTP + ADC group regular conversion + stop + 4 + 1 + + + ADSTART + ADC group regular conversion + start + 2 + 1 + + + ADEN + ADC enable + 0 + 1 + + + + + CFGR1 + CFGR1 + ADC configuration register 1 + 0xC + 0x20 + read-write + 0x00000000 + + + AWDCH + ADC analog watchdog monitored channel + selection + 26 + 4 + + + AWDEN + ADC analog watchdog enable on scope + ADC group regular + 23 + 1 + + + AWDSGL + ADC analog watchdog monitoring a + single channel or all channels + 22 + 1 + + + DISCEN + ADC group regular sequencer + discontinuous mode + 16 + 1 + + + WAIT + Wait conversion mode + 14 + 1 + + + CONT + ADC group regular continuous conversion + mode + 13 + 1 + + + OVRMOD + ADC group regular overrun + configuration + 12 + 1 + + + EXTEN + ADC group regular external trigger + polarity + 10 + 2 + + + EXTSEL + ADC group regular external trigger + source + 6 + 3 + + + ALIGN + ADC data alignement + 5 + 1 + + + RESSEL + ADC data resolution + 3 + 2 + + + SCANDIR + Scan sequence direction + 2 + 1 + + + DMACFG + ADC DMA transfer + configuration + 1 + 1 + + + DMAEN + ADC DMA transfer enable + 0 + 1 + + + + + CFGR2 + CFGR2 + ADC configuration register 2 + 0x10 + 0x20 + read-write + 0x00000000 + + + CKMODE + ADC clock mode + 28 + 4 + + + + + SMPR + SMPR + ADC sampling time register + 0x14 + 0x20 + read-write + 0x00000000 + + + SMP + Sampling time selection + 0 + 3 + + + + + TR + TR + ADC analog watchdog 1 threshold register + 0x20 + 0x20 + read-write + 0x0FFF0000 + + + HT + ADC analog watchdog threshold + high + 16 + 12 + + + LT + ADC analog watchdog threshold + low + 0 + 12 + + + + + CHSELR + CHSELR + ADC group regular sequencer register + 0x28 + 0x20 + read-write + 0x0FFF0000 + + + CHSEL12 + Channel-12 selection + 12 + 1 + + + CHSEL11 + Channel-11 selection + 11 + 1 + + + CHSEL9 + Channel-9 selection + 9 + 1 + + + CHSEL8 + Channel-8 selection + 8 + 1 + + + CHSEL7 + Channel-7 selection + 7 + 1 + + + CHSEL6 + Channel-6 selection + 6 + 1 + + + CHSEL5 + Channel-5 selection + 5 + 1 + + + CHSEL4 + Channel-4 selection + 4 + 1 + + + CHSEL3 + Channel-3 selection + 3 + 1 + + + CHSEL2 + Channel-2 selection + 2 + 1 + + + CHSEL1 + Channel-1 selection + 1 + 1 + + + CHSEL0 + Channel-0 selection + 0 + 1 + + + + + DR + DR + ADC group regular data register + 0x40 + 0x20 + read-only + 0x00000000 + + + DATA + ADC group regular conversion + data + 0 + 16 + + + + + CCSR + CCSR + ADC calibration configuration and status register + 0x44 + 0x20 + read-write + 0x00000000 + + + CALON + Calibration flag + 31 + 1 + read-only + + + CALFAIL + Calibration fail flag + 30 + 1 + + + CALSET + Calibration factor selection + 15 + 1 + + + CALSMP + Calibration sample time selection + 12 + 2 + + + CALSEL + Calibration contents selection + 11 + 1 + + + + + CALRR1 + CALRR1 + ADC calibration result register 1 + 0x48 + 0x20 + read-only + 0x00000000 + + + CALBOUT + offset result + 16 + 7 + + + CALC5OUT + C5 result + 8 + 8 + + + CALC4OUT + C4 result + 0 + 8 + + + + + CALRR2 + CALRR2 + ADC calibration result register 2 + 0x4C + 0x20 + read-only + 0x00000000 + + + CALC3OUT + C3 result + 24 + 8 + + + CALC2OUT + C2 result + 16 + 8 + + + CALC1OUT + C1 result + 8 + 8 + + + CALC0OUT + C0 result + 0 + 8 + + + + + CALFIR1 + CALFIR1 + ADC calibration factor input register 1 + 0x50 + 0x20 + read-write + 0x00000000 + + + CALBIO + Calibration offset factor input + 16 + 7 + + + CALC5IO + Calibration C5 factor input + 8 + 8 + + + CALC4IO + Calibration C4 factor input + 0 + 8 + + + + + CALFIR2 + CALFIR2 + ADC calibration factor input register 2 + 0x54 + 0x20 + read-write + 0x00000000 + + + CALC3IO + Calibration C3 factor input + 24 + 8 + + + CALC2IO + Calibration C2 factor input + 16 + 8 + + + CALC1IO + Calibration C1 factor input + 8 + 8 + + + CALC0IO + Calibration C0 factor input + 0 + 8 + + + + + CCR + CCR + ADC common configuration register + 0x308 + 0x20 + read-write + 0x00000000 + + + TSEN + Temperature sensor enable + 23 + 1 + + + VREFEN + VREFINT enable + 22 + 1 + + + + + + + COMP1 + Comparator + COMP + 0x40010200 + + 0x0 + 0x10 + registers + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + LOCK + CSR register lock + 31 + 1 + + + COMP_OUT + Comparator output status + 30 + 1 + + + PWRMODE + Comparator power mode + selector + 18 + 2 + + + HYST + Comparator hysteresis enable + selector + 16 + 1 + + + POLARITY + Comparator polarity + selector + 15 + 1 + + + WINMODE + Comparator non-inverting input + selector for window mode + 11 + 1 + + + INPSEL + Comparator signal selector for + non-inverting input + 8 + 2 + + + INMSEL + Comparator signal selector for + inverting input INM + 4 + 4 + + + SCALER_EN + SCALER enable bit + 1 + 1 + + + COMP_EN + COMP enable bit + 0 + 1 + + + + + FR + FR + Comparator Filter + register + 0x4 + 0x20 + read-write + 0x00000000 + + + FLTCNT + Comparator filter and counter + 16 + 16 + + + FLTEN + Filter enable bit + 0 + 1 + + + + + + + COMP2 + Comparator + COMP + 0x40010210 + + 0x0 + 0x10 + registers + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + LOCK + CSR register lock + 31 + 1 + + + COMP_OUT + Comparator output status + 30 + 1 + + + PWRMODE + Comparator power mode + selector + 18 + 2 + + + POLARITY + Comparator polarity + selector + 15 + 1 + + + WINMODE + Comparator non-inverting input + selector for window mode + 11 + 1 + + + INPSEL + Comparator signal selector for + non-inverting input + 8 + 2 + + + INMSEL + Comparator signal selector for + inverting input INM + 4 + 4 + + + COMP_EN + COMP enable bit + 0 + 1 + + + + + FR + FR + Comparator Filter + register + 0x4 + 0x20 + read-write + 0x00000000 + + + FLTCNT + Comparator filter and counter + 16 + 16 + + + FLTEN + Filter enable bit + 0 + 1 + + + + + + + RCC + Reset and clock control + RCC + 0x40021000 + + 0x0 + 0x400 + registers + + + RCC + RCC global Interrupt + 4 + + + + CR + CR + Clock control register + 0x0 + 0x20 + read-write + 0x00000100 + + + PLLRDY + PLL clock ready flag + 25 + 1 + + + PLLON + PLL enable + 24 + 1 + + + CSSON + Clock security system + enable + 19 + 1 + + + HSEBYP + HSE crystal oscillator + bypass + 18 + 1 + + + HSERDY + HSE clock ready flag + 17 + 1 + + + HSEON + HSE clock enable + 16 + 1 + + + HSIDIV + HSI16 clock division + factor + 11 + 3 + + + HSIRDY + HSI16 clock ready flag + 10 + 1 + + + HSIKERON + HSI16 always enable for peripheral + kernels + 9 + 1 + + + HSION + HSI16 clock enable + 8 + 1 + + + + + ICSCR + ICSCR + Internal clock sources calibration + register + 0x4 + 0x20 + 0x10000000 + + + LSI_STARTUP + LSI startup time + 26 + 2 + read-write + + + LSI_TRIM + LSI clock trimming + 16 + 9 + read-write + + + HSI_FS + HSI frequency selection + 13 + 3 + read-write + + + HSI_TRIM + HSI clock trimming + 0 + 13 + read-write + + + + + CFGR + CFGR + Clock configuration register + 0x8 + 0x20 + 0x00000000 + + + MCOPRE + Microcontroller clock output + prescaler + 28 + 3 + read-write + + + MCOSEL + Microcontroller clock + output + 24 + 3 + read-write + + + PPRE + APB prescaler + 12 + 3 + read-write + + + HPRE + AHB prescaler + 8 + 4 + read-write + + + SWS + System clock switch status + 3 + 3 + read-only + + + SW + System clock switch + 0 + 3 + read-write + + + + + PLLCFGR + PLLCFGR + PLL configuration register + 0xC + 0x20 + 0x00000000 + + + PLLSRC + PLL clock source selection + 0 + 1 + read-write + + + + + ECSCR + ECSCR + External clock source control register + 0x10 + 0x20 + 0x00000000 + + + LSE_DRIVER + LSE clock driver selection + 16 + 2 + read-write + + + HSE_FREQ + HSE clock freqency selection + 2 + 2 + read-write + + + + + CIER + CIER + Clock interrupt enable + register + 0x18 + 0x20 + read-write + 0x00000000 + + + PLLRDYIE + PLL ready interrupt enable + 5 + 1 + + + HSERDYIE + HSE ready interrupt enable + 4 + 1 + + + HSIRDYIE + HSI ready interrupt enable + 3 + 1 + + + LSERDYIE + LSE ready interrupt enable + 1 + 1 + + + LSIRDYIE + LSI ready interrupt enable + 0 + 1 + + + + + CIFR + CIFR + Clock interrupt flag register + 0x1C + 0x20 + read-only + 0x00000000 + + + LSECSSF + LSE clock secure system interrupt flag + 9 + 1 + + + CSSF + HSE clock secure system interrupt flag + 8 + 1 + + + PLLRDYF + PLL ready interrupt flag + 5 + 1 + + + HSERDYF + HSE ready interrupt flag + 4 + 1 + + + HSIRDYF + HSI ready interrupt flag + 3 + 1 + + + LSERDYF + LSE ready interrupt flag + 1 + 1 + + + LSIRDYF + LSI ready interrupt flag + 0 + 1 + + + + + CICR + CICR + Clock interrupt clear register + 0x20 + 0x20 + write-only + 0x00000000 + + + LSECSSC + LSE clock secure system interrupt flag clear + 9 + 1 + + + CSSC + clock secure system interrupt flag clear + 8 + 1 + + + PLLRDYC + PLL ready interrupt clear + 5 + 1 + + + HSERDYC + HSE ready interrupt clear + 4 + 1 + + + HSIRDYC + HSI ready interrupt clear + 3 + 1 + + + LSERDYC + LSE ready interrupt clear + 1 + 1 + + + LSIRDYC + LSI ready interrupt clear + 0 + 1 + + + + + IOPRSTR + IOPRSTR + GPIO reset register + 0x24 + 0x20 + read-write + 0x00000000 + + + GPIOFRST + I/O port F reset + 5 + 1 + + + GPIOBRST + I/O port B reset + 1 + 1 + + + GPIOARST + I/O port A reset + 0 + 1 + + + + + AHBRSTR + AHBRSTR + AHB peripheral reset register + 0x28 + 0x20 + read-write + 0x00000000 + + + CRCRST + CRC reset + 12 + 1 + + + DMARST + DMA reset + 0 + 1 + + + + + APBRSTR1 + APBRSTR1 + APB peripheral reset register + 1 + 0x2C + 0x20 + read-write + 0x00000000 + + + LPTIMRST + Low Power Timer reset + 31 + 1 + + + PWRRST + Power interface reset + 28 + 1 + + + DBGRST + Debug support reset + 27 + 1 + + + I2CRST + I2C reset + 21 + 1 + + + USART2RST + USART2 reset + 17 + 1 + + + SPI2RST + SPI2 reset + 14 + 1 + + + TIM3RST + TIM3 timer reset + 1 + 1 + + + + + APBRSTR2 + APBRSTR2 + APB peripheral reset register + 2 + 0x30 + 0x20 + read-write + 0x00000000 + + + LEDRST + LED reset + 23 + 1 + + + COMP2RST + COMP2 reset + 22 + 1 + + + COMP1RST + COMP1 reset + 21 + 1 + + + ADCRST + ADC reset + 20 + 1 + + + TIM17RST + TIM17 timer reset + 18 + 1 + + + TIM16RST + TIM16 timer reset + 17 + 1 + + + TIM14RST + TIM14 timer reset + 15 + 1 + + + USART1RST + USART1 reset + 14 + 1 + + + SPI1RST + SPI1 reset + 12 + 1 + + + TIM1RST + TIM1 timer reset + 11 + 1 + + + SYSCFGRST + SYSCFG and COMP + reset + 0 + 1 + + + + + IOPENR + IOPENR + GPIO clock enable register + 0x34 + 0x20 + read-write + 0x00000000 + + + GPIOFEN + I/O port F clock enable + 5 + 1 + + + GPIOBEN + I/O port B clock enable + 1 + 1 + + + GPIOAEN + I/O port A clock enable + 0 + 1 + + + + + AHBENR + AHBENR + AHB peripheral clock enable + register + 0x38 + 0x20 + read-write + 0x00000000 + + + CRCEN + CRC clock enable + 12 + 1 + + + SRAMEN + SRAM memory interface clock + enable + 9 + 1 + + + FLASHEN + Flash memory interface clock + enable + 8 + 1 + + + DMAEN + DMA clock enable + 0 + 1 + + + + + APBENR1 + APBENR1 + APB peripheral clock enable register + 1 + 0x3C + 0x20 + read-write + 0x00000000 + + + LPTIMEN + LPTIM clock enable + 31 + 1 + + + PWREN + Power interface clock + enable + 28 + 1 + + + DBGEN + Debug support clock enable + 27 + 1 + + + I2CEN + I2C clock enable + 21 + 1 + + + USART2EN + USART2 clock enable + 17 + 1 + + + SPI2EN + SPI2 clock enable + 14 + 1 + + + WWDGEN + WWDG clock enable + 11 + 1 + + + RTCAPBEN + RTC APB clock enable + 10 + 1 + + + TIM3EN + TIM3 timer clock enable + 1 + 1 + + + + + APBENR2 + APBENR2 + APB peripheral clock enable register + 2 + 0x40 + 0x20 + read-write + 0x00000000 + + + LEDEN + LED clock enable + 23 + 1 + + + COMP2EN + COMP2 clock enable + 22 + 1 + + + COMP1EN + COMP1 clock enable + 21 + 1 + + + ADCEN + ADC clock enable + 20 + 1 + + + TIM17EN + TIM16 timer clock enable + 18 + 1 + + + TIM16EN + TIM16 timer clock enable + 17 + 1 + + + TIM14EN + TIM14 timer clock enable + 15 + 1 + + + USART1EN + USART1 clock enable + 14 + 1 + + + SPI1EN + SPI1 clock enable + 12 + 1 + + + TIM1EN + TIM1 timer clock enable + 11 + 1 + + + SYSCFGEN + SYSCFG, COMP and VREFBUF clock + enable + 0 + 1 + + + + + CCIPR + CCIPR + Peripherals independent clock configuration + register + 0x54 + 0x20 + read-write + 0x00000000 + + + LPTIM1SEL + LPTIM1 clock source + selection + 18 + 2 + + + COMP2SEL + COMP2 clock source + selection + 9 + 1 + + + COMP1SEL + COMP1 clock source + selection + 8 + 1 + + + PVDSEL + PVD detect clock source + selection + 7 + 1 + + + + + BDCR + BDCR + RTC domain control register + 0x5C + 0x20 + read-write + 0x00000000 + + + LSCOSEL + Low-speed clock output + selection + 25 + 1 + + + LSCOEN + Low-speed clock output (LSCO) + enable + 24 + 1 + + + BDRST + RTC domain software reset + 16 + 1 + + + RTCEN + RTC clock source enable + 15 + 1 + + + RTCSEL + RTC clock source selection + 8 + 2 + + + LSECSSD + LSE CSS detect + 6 + 1 + + + LSECSSON + LSE CSS enable + 5 + 1 + + + LSEBYP + LSE oscillator bypass + 2 + 1 + + + LSERDY + LSE oscillator ready + 1 + 1 + + + LSEON + LSE oscillator enable + 0 + 1 + + + + + CSR + CSR + Control/status register + 0x60 + 0x20 + read-write + 0x00000000 + + + WWDGRSTF + Window watchdog reset flag + 30 + 1 + + + IWDGRSTF + Independent window watchdog reset + flag + 29 + 1 + + + SFTRSTF + Software reset flag + 28 + 1 + + + PWRRSTF + BOR or POR/PDR flag + 27 + 1 + + + PINRSTF + Pin reset flag + 26 + 1 + + + OBLRSTF + Option byte loader reset + flag + 25 + 1 + + + RMVF + Remove reset flags + 23 + 1 + + + LSIRDY + LSI oscillator ready + 1 + 1 + + + LSION + LSI oscillator enable + 0 + 1 + + + + + + + PWR + Power control + PWR + 0x40007000 + + 0x0 + 0x400 + registers + + + + CR1 + CR1 + Power control register 1 + 0x0 + 0x20 + read-write + 0x00030000 + + + HSION_CTRL + HSI open time control + 19 + 1 + + + SRAM_RETV + SRAM retention voltage control + 16 + 3 + + + LPR + Low-power run + 14 + 1 + + + FLS_SLPTIME + Flash wait time after wakeup from the stop mode + 12 + 2 + + + MRRDY_TIME + Time selection wakeup from LP to VR + 10 + 2 + + + VOS + Voltage scaling range + selection + 9 + 1 + + + DBP + Disable backup domain write + protection + 8 + 1 + + + BIAS_CR_SEL + MR Bias current selection + 4 + 1 + + + BIAS_CR + MR Bias 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trigger event configuration bit + of Configurable Event input + 15 + 1 + + + RT14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + RT13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + RT12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + RT11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + RT10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + RT9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + RT8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + RT7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + RT6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + RT5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + RT4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + RT3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + RT2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + RT1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + RT0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + + + FTSR + FTSR + EXTI falling trigger selection + register + 0x4 + 0x20 + read-write + 0x00000000 + + + FT18 + Falling trigger event configuration bit + of Configurable Event input + 18 + 1 + + + FT17 + Falling trigger event configuration bit + of Configurable Event input + 17 + 1 + + + FT16 + Falling trigger event configuration bit + of Configurable Event input + 16 + 1 + + + FT15 + Falling trigger event configuration bit + of Configurable Event input + 15 + 1 + + + FT14 + Falling trigger event configuration bit + of Configurable Event input + 14 + 1 + + + FT13 + Falling trigger event configuration bit + of Configurable Event input + 13 + 1 + + + FT12 + Falling trigger event configuration bit + of Configurable Event input + 12 + 1 + + + FT11 + Falling trigger event configuration bit + of Configurable Event input + 11 + 1 + + + FT10 + Falling trigger event configuration bit + of Configurable Event input + 10 + 1 + + + FT9 + Falling trigger event configuration bit + of Configurable Event input + 9 + 1 + + + FT8 + Falling trigger event configuration bit + of Configurable Event input + 8 + 1 + + + FT7 + Falling trigger event configuration bit + of Configurable Event input + 7 + 1 + + + FT6 + Falling trigger event configuration bit + of Configurable Event input + 6 + 1 + + + FT5 + Falling trigger event configuration bit + of Configurable Event input + 5 + 1 + + + FT4 + Falling trigger event configuration bit + of Configurable Event input + 4 + 1 + + + FT3 + Falling trigger event configuration bit + of Configurable Event input + 3 + 1 + + + FT2 + Falling trigger event configuration bit + of Configurable Event input + 2 + 1 + + + FT1 + Falling trigger event configuration bit + of Configurable Event input + 1 + 1 + + + FT0 + Falling trigger event configuration bit + of Configurable Event input + 0 + 1 + + + + + SWIER + SWIER + EXTI software interrupt event + register + 0x8 + 0x20 + read-write + 0x00000000 + + + SWI18 + Rising trigger event configuration bit + of Configurable Event input + 18 + 1 + + + SWI17 + Rising trigger event configuration bit + of Configurable Event input + 17 + 1 + + + SWI16 + Rising trigger event configuration bit + of Configurable Event input + 16 + 1 + + + SWI15 + Rising trigger event configuration bit + of Configurable Event input + 15 + 1 + + + SWI14 + Rising trigger event configuration bit + of Configurable Event input + 14 + 1 + + + SWI13 + Rising trigger event configuration bit + of Configurable Event input + 13 + 1 + + + SWI12 + Rising trigger event configuration bit + of Configurable Event input + 12 + 1 + + + SWI11 + Rising trigger event configuration bit + of Configurable Event input + 11 + 1 + + + SWI10 + Rising trigger event configuration bit + of Configurable Event input + 10 + 1 + + + SWI9 + Rising trigger event configuration bit + of Configurable Event input + 9 + 1 + + + SWI8 + Rising trigger event configuration bit + of Configurable Event input + 8 + 1 + + + SWI7 + Rising trigger event configuration bit + of Configurable Event input + 7 + 1 + + + SWI6 + Rising trigger event configuration bit + of Configurable Event input + 6 + 1 + + + SWI5 + Rising trigger event configuration bit + of Configurable Event input + 5 + 1 + + + SWI4 + Rising trigger event configuration bit + of Configurable Event input + 4 + 1 + + + SWI3 + Rising trigger event configuration bit + of Configurable Event input + 3 + 1 + + + SWI2 + Rising trigger event configuration bit + of Configurable Event input + 2 + 1 + + + SWI1 + Rising trigger event configuration bit + of Configurable Event input + 1 + 1 + + + SWI0 + Rising trigger event configuration bit + of Configurable Event input + 0 + 1 + + + + + PR + PR + EXTI pending + register + 0xC + 0x20 + read-write + 0x00000000 + + + PR18 + configurable event inputs x rising edge + Pending bit. + 18 + 1 + + + PR17 + configurable event inputs x rising edge + Pending bit. + 17 + 1 + + + PR16 + configurable event inputs x rising edge + Pending bit. + 16 + 1 + + + PR15 + configurable event inputs x rising edge + Pending bit. + 15 + 1 + + + PR14 + configurable event inputs x rising edge + Pending bit. + 14 + 1 + + + PR13 + configurable event inputs x rising edge + Pending bit + 13 + 1 + + + PR12 + configurable event inputs x rising edge + Pending bit. + 12 + 1 + + + PR11 + configurable event inputs x rising edge + Pending bit. + 11 + 1 + + + PR10 + configurable event inputs x rising edge + Pending bit. + 10 + 1 + + + PR9 + configurable event inputs x rising edge + Pending bit. + 9 + 1 + + + PR8 + configurable event inputs x rising edge + Pending bit. + 8 + 1 + + + PR7 + configurable event inputs x rising edge + Pending bit. + 7 + 1 + + + PR6 + configurable event inputs x rising edge + Pending bit. + 6 + 1 + + + PR5 + configurable event inputs x rising edge + Pending bit. + 5 + 1 + + + PR4 + configurable event inputs x rising edge + Pending bit. + 4 + 1 + + + PR3 + configurable event inputs x rising edge + Pending bit. + 3 + 1 + + + PR2 + configurable event inputs x rising edge + Pending bit. + 2 + 1 + + + PR1 + configurable event inputs x rising edge + Pending bit. + 1 + 1 + + + PR0 + configurable event inputs x rising edge + Pending bit. + 0 + 1 + + + + + EXTICR1 + EXTICR1 + EXTI external interrupt selection + register + 0x60 + 0x20 + read-write + 0x00000000 + + + EXTI3 + GPIO port selection + 24 + 2 + + + EXTI2 + GPIO port selection + 16 + 2 + + + EXTI1 + GPIO port selection + 8 + 2 + + + EXTI0 + GPIO port selection + 0 + 2 + + + + + EXTICR2 + EXTICR2 + EXTI external interrupt selection + register + 0x64 + 0x20 + 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6 + 1 + + + EM5 + CPU wakeup with event mask on event + input + 5 + 1 + + + EM4 + CPU wakeup with event mask on event + input + 4 + 1 + + + EM3 + CPU wakeup with event mask on event + input + 3 + 1 + + + EM2 + CPU wakeup with event mask on event + input + 2 + 1 + + + EM1 + CPU wakeup with event mask on event + input + 1 + 1 + + + EM0 + CPU wakeup with event mask on event + input + 0 + 1 + + + + + + + LPTIM + Low power timer + LPTIM + 0x40007C00 + + 0x0 + 0x400 + registers + + + + ISR + ISR + Interrupt and Status Register + 0x0 + 0x20 + read-only + 0x00000000 + + + ARRM + Autoreload match + 1 + 1 + + + + + ICR + ICR + Interrupt Clear Register + 0x4 + 0x20 + write-only + 0x00000000 + + + ARRMCF + Autoreload match Clear + Flag + 1 + 1 + + + + + IER + IER + Interrupt Enable Register + 0x8 + 0x20 + read-write + 0x00000000 + + + ARRMIE + Autoreload match Interrupt + Enable + 1 + 1 + + + + + CFGR + CFGR + Configuration Register + 0xC + 0x20 + read-write + 0x00000000 + + + PRELOAD + Registers update mode + 22 + 1 + + + PRESC + Clock prescaler + 9 + 3 + + + + + CR + CR + Control Register + 0x10 + 0x20 + read-write + 0x00000000 + + + RSTARE + Reset after read enable + 4 + 1 + + + SNGSTRT + LPTIM start in single mode + 1 + 1 + + + ENABLE + LPTIM Enable + 0 + 1 + + + + + ARR + ARR + Autoreload Register + 0x18 + 0x20 + read-write + 0x00000001 + + + ARR + Auto reload value + 0 + 16 + + + + + CNT + CNT + Counter Register + 0x1C + 0x20 + read-only + 0x00000000 + + + CNT + Counter value + 0 + 16 + + + + + + + USART1 + Universal synchronous asynchronous receiver + transmitter + USART + 0x40013800 + + 0x0 + 0x400 + registers + + + USART1 + USART1 global Interrupt + 27 + + + + SR + SR + Status register + 0x0 + 0x20 + 0x00C0 + + + ABRRQ + Automate baudrate detection requeset + 12 + 1 + write-only + + + ABRE + Automate baudrate detection error flag + 11 + 1 + read-only + + + ABRF + Automate baudrate detection flag + 10 + 1 + read-only + + + CTS + CTS flag + 9 + 1 + read-write + + + TXE + Transmit data register + empty + 7 + 1 + read-only + + + TC + Transmission complete + 6 + 1 + read-write + + + RXNE + Read data register not + empty + 5 + 1 + read-write + + + IDLE + IDLE line detected + 4 + 1 + read-only + + + ORE + Overrun error + 3 + 1 + read-only + + + NE + Noise error flag + 2 + 1 + read-only + + + FE + Framing error + 1 + 1 + read-only + + + PE + Parity error + 0 + 1 + read-only + + + + + DR + DR + Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + DR + Data value + 0 + 9 + + + + + BRR + BRR + Baud rate register + 0x8 + 0x20 + read-write + 0x0000 + + + DIV_Mantissa + mantissa of USARTDIV + 4 + 12 + + + DIV_Fraction + fraction of USARTDIV + 0 + 4 + + + + + CR1 + CR1 + Control register 1 + 0xC + 0x20 + read-write + 0x0000 + + + UE + USART enable + 13 + 1 + + + M + Word length + 12 + 1 + + + WAKE + Wakeup method + 11 + 1 + + + PCE + Parity control enable + 10 + 1 + + + PS + Parity selection + 9 + 1 + + + PEIE + PE interrupt enable + 8 + 1 + + + TXEIE + TXE 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Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 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Capture/compare 3 + generation + 3 + 1 + + + CC2G + Capture/compare 2 + generation + 2 + 1 + + + CC1G + Capture/compare 1 + generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register 1 (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC2CE + Output compare 2 clear + enable + 15 + 1 + + + OC2M + Output compare 2 mode + 12 + 3 + + + OC2PE + Output compare 2 preload + enable + 11 + 1 + + + OC2FE + Output compare 2 fast + enable + 10 + 1 + + + CC2S + Capture/Compare 2 + selection + 8 + 2 + + + OC1CE + Output compare 1 clear + enable + 7 + 1 + + + OC1M + Output compare 1 mode + 4 + 3 + + + OC1PE + Output compare 1 preload + enable + 3 + 1 + + + OC1FE + Output compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC2F + Input capture 2 filter + 12 + 4 + + + IC2PSC + Input capture 2 prescaler + 10 + 2 + + + CC2S + Capture/compare 2 + selection + 8 + 2 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR2_Output + CCMR2_Output + capture/compare mode register 2 (output + mode) + 0x1C + 0x20 + read-write + 0x00000000 + + + OC4CE + Output compare 4 clear + enable + 15 + 1 + + + OC4M + Output compare 4 mode + 12 + 3 + + + OC4PE + Output compare 4 preload + enable + 11 + 1 + + + OC4FE + Output compare 4 fast + enable + 10 + 1 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + OC3CE + Output compare 3 clear + enable + 7 + 1 + + + OC3M + Output compare 3 mode + 4 + 3 + + + OC3PE + Output compare 3 preload + enable + 3 + 1 + + + OC3FE + Output compare 3 fast + enable + 2 + 1 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCMR2_Input + CCMR2_Input + capture/compare mode register 2 (input + mode) + CCMR2_Output + 0x1C + 0x20 + read-write + 0x00000000 + + + IC4F + Input capture 4 filter + 12 + 4 + + + IC4PSC + Input capture 4 prescaler + 10 + 2 + + + CC4S + Capture/Compare 4 + selection + 8 + 2 + + + IC3F + Input capture 3 filter + 4 + 4 + + + IC3PSC + Input capture 3 prescaler + 2 + 2 + + + CC3S + Capture/Compare 3 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC4NP + + Capture/Compare 4 output + Polarity + + 15 + 1 + + + CC4P + + Capture/Compare 4 output + Polarity + + 13 + 1 + + + CC4E + + Capture/Compare 4 output + enable + + 12 + 1 + + + CC3NP + + Capture/Compare 3 output + Polarity + + 11 + 1 + + + CC3P + + Capture/Compare 3 output + Polarity + + 9 + 1 + + + CC3E + + Capture/Compare 3 output + enable + + 8 + 1 + + + CC2NP + + Capture/Compare 2 output + Polarity + + 7 + 1 + + + CC2P + + Capture/Compare 2 output + Polarity + + 5 + 1 + + + CC2E + + Capture/Compare 2 output + enable + + 4 + 1 + + + CC1NP + + Capture/Compare 1 output + Polarity + + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + CCR2 + CCR2 + capture/compare register 2 + 0x38 + 0x20 + read-write + 0x00000000 + + + CCR2 + Capture/Compare 2 value + 0 + 16 + + + + + CCR3 + CCR3 + capture/compare register 3 + 0x3C + 0x20 + read-write + 0x00000000 + + + CCR3 + Capture/Compare value + 0 + 16 + + + + + CCR4 + CCR4 + capture/compare register 4 + 0x40 + 0x20 + read-write + 0x00000000 + + + CCR4 + Capture/Compare value + 0 + 16 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 32 + + + + + + + TIM14 + General purpose timer + TIM + 0x40002000 + + 0x00 + 0x400 + registers + + + TIM14 + TIM14 global Interrupt + 19 + + + + CR1 + CR1 + TIM14 control register1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Prescaler factor + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1IE + Compare/ + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Compare/capture 1 flag + 9 + 1 + + + CC1IF + Compare/capture 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + CC1G + Compare/capture1 event + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + OR + OR + Option register + 0x50 + 0x20 + read-write + 0x00000000 + + + TI1_RMP + TIM14 channel1 input remap + 0 + 2 + + + + + + + TIM16 + General purpose timer + TIM + 0x40014400 + + 0x00 + 0x400 + registers + + + TIM16 + TIM16 global Interrupt + 21 + + + + CR1 + CR1 + TIM16 control register1 + 0x0 + 0x20 + read-write + 0x0000 + + + CKD + Prescaler factor + 8 + 2 + + + ARPE + Auto-reload preload enable + 7 + 1 + + + OPM + One pulse mode + 3 + 1 + + + URS + Update request source + 2 + 1 + + + UDIS + Update disable + 1 + 1 + + + CEN + Counter enable + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + OIS1N + Output Idle state 1 + 9 + 1 + + + OIS1 + Output Idle state 1 + 8 + 1 + + + CCDS + Capture/compare DMA + selection + 3 + 1 + + + CCPC + Capture/compare preloaded + control + 0 + 1 + + + + + DIER + DIER + DMA/Interrupt enable register + 0xC + 0x20 + read-write + 0x0000 + + + CC1DE + Compare/capture DMA requeset enable + 9 + 1 + + + UDE + Update DMA request enable + 8 + 1 + + + BIE + Break interrupt enable + 7 + 1 + + + COMIE + Com interrupt enable + 5 + 1 + + + CC1IE + Capture/Compare 1 interrupt enable + 1 + 1 + + + UIE + Update interrupt enable + 0 + 1 + + + + + SR + SR + status register + 0x10 + 0x20 + read-write + 0x0000 + + + CC1OF + Update interrupt flag + 9 + 1 + + + BIF + Break interrupt flag + 7 + 1 + + + COMIF + Com interrupt flag + 5 + 1 + + + CC1IF + Capture/Compare 1 interrupt flag + 1 + 1 + + + UIF + Update interrupt flag + 0 + 1 + + + + + EGR + EGR + event generation register + 0x14 + 0x20 + write-only + 0x0000 + + + BG + Break event generation + 7 + 1 + + + COMG + COM evnet generation + 5 + 1 + + + CC1G + Capture/Compare 1 generation + 1 + 1 + + + UG + Update generation + 0 + 1 + + + + + CCMR1_Output + CCMR1_Output + capture/compare mode register (output + mode) + 0x18 + 0x20 + read-write + 0x00000000 + + + OC1M + Output Compare 1 mode + 4 + 3 + + + OC1PE + Output Compare 1 preload + enable + 3 + 1 + + + OC1FE + Output Compare 1 fast + enable + 2 + 1 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCMR1_Input + CCMR1_Input + capture/compare mode register 1 (input + mode) + CCMR1_Output + 0x18 + 0x20 + read-write + 0x00000000 + + + IC1F + Input capture 1 filter + 4 + 4 + + + IC1PSC + Input capture 1 prescaler + 2 + 2 + + + CC1S + Capture/Compare 1 + selection + 0 + 2 + + + + + CCER + CCER + capture/compare enable + register + 0x20 + 0x20 + read-write + 0x0000 + + + CC1NP + Capture/Compare 1 output + Polarity + 3 + 1 + + + CC1NE + Capture/Compare 1 complementary output + enable + 2 + 1 + + + CC1P + Capture/Compare 1 output + Polarity + 1 + 1 + + + CC1E + Capture/Compare 1 output + enable + 0 + 1 + + + + + CNT + CNT + counter + 0x24 + 0x20 + read-write + 0x00000000 + + + CNT + counter value + 0 + 16 + + + + + PSC + PSC + prescaler + 0x28 + 0x20 + read-write + 0x0000 + + + PSC + Prescaler value + 0 + 16 + + + + + ARR + ARR + auto-reload register + 0x2C + 0x20 + read-write + 0x00000000 + + + ARR + Auto-reload value + 0 + 16 + + + + + RCR + RCR + repetition counter register + 0x30 + 0x20 + read-write + 0x0000 + + + REP + Repetition counter value + 0 + 8 + + + + + CCR1 + CCR1 + capture/compare register 1 + 0x34 + 0x20 + read-write + 0x00000000 + + + CCR1 + Capture/Compare 1 value + 0 + 16 + + + + + BDTR + BDTR + break and dead-time register + 0x44 + 0x20 + read-write + 0x0000 + + + MOE + Main output enable + 15 + 1 + + + AOE + Automatic output enable + 14 + 1 + + + BKP + Break polarity + 13 + 1 + + + BKE + Break enable + 12 + 1 + + + OSSR + Off-state selection for Run + mode + 11 + 1 + + + OSSI + Off-state selection for Idle + mode + 10 + 1 + + + LOCK + Lock configuration + 8 + 2 + + + DTG + Dead-time generator setup + 0 + 8 + + + + + DCR + DCR + DMA control register + 0x48 + 0x20 + read-write + 0x0000 + + + DBL + DMA burst length + 8 + 5 + + + DBA + DMA base address + 0 + 5 + + + + + DMAR + DMAR + DMA address for full transfer + 0x4C + 0x20 + read-write + 0x0000 + + + DMAB + DMA register for burst + accesses + 0 + 32 + + + + + + + TIM17 + 0x40014800 + + TIM17 + TIM17 global Interrupt + 22 + + + + SYSCFG + System configuration controller + SYSCFG + 0x40010000 + + 0x0 + 0x30 + registers + + + + CFGR1 + CFGR1 + SYSCFG configuration register + 1 + 0x0 + 0x20 + read-write + 0x00000000 + + + I2C_PF1_ANF + Analog filter enable control driving capability + activation bits PF1 + 30 + 1 + + + I2C_PF0_ANF + Analog filter enable control driving capability + activation bits PF0 + 29 + 1 + + + I2C_PB8_ANF + Analog filter enable control driving capability + activation bits PB8 + 28 + 1 + + + I2C_PB7_ANF + Analog filter enable control driving capability + activation bits PB7 + 27 + 1 + + I2C_PB6_ANF + Analog filter enable control driving capability + activation bits PB6 + 26 + 1 + + + I2C_PA12_ANF + Analog filter enable control driving capability + activation bits PA12 + 25 + 1 + + + I2C_PA11_ANF + Analog filter enable control driving capability + activation bits PA11 + 24 + 1 + + + I2C_PA10_ANF + Analog filter enable control driving capability + activation bits PA10 + 23 + 1 + + + I2C_PA9_ANF + Analog filter enable control driving capability + activation bits PA9 + 22 + 1 + + + I2C_PA8_ANF + Analog filter enable control driving capability + activation bits PA8 + 21 + 1 + + + I2C_PA7_ANF + Analog filter enable control driving capability + activation bits PA7 + 20 + 1 + + + I2C_PA3_ANF + Analog filter enable control driving capability + activation bits PA3 + 19 + 1 + + + I2C_PA2_ANF + Analog filter enable control driving capability + activation bits PA2 + 18 + 1 + + + MEM_MODE + Memory mapping selection + bits + 0 + 2 + + + + + CFGR2 + CFGR2 + SYSCFG configuration register + 2 + 0x18 + 0x20 + read-write + 0x00000000 + + + ETR_SRC_TIM1 + TIM1 ETR source selection + 9 + 2 + + + COMP2_BRK_TIM17 + COMP2 is enable to input of TIM17 break + 8 + 1 + + + COMP1_BRK_TIM17 + COMP1 is enable to input of TIM17 break + 7 + 1 + + + COMP2_BRK_TIM16 + COMP2 is enable to input of TIM16 break + 6 + 1 + + + COMP1_BRK_TIM16 + COMP1 is enable to input of TIM16 break + 5 + 1 + + + COMP2_BRK_TIM1 + COMP2 is enable to input of TIM1 break + 4 + 1 + + + COMP1_BRK_TIM1 + COMP1 is enable to input of TIM1 break + 3 + 1 + + + PVD_LOCK + PVD lock enable bit + 2 + 1 + + + LOCKUP_LOCK + Cortex-M0+ LOCKUP bit enable + bit + 0 + 1 + + + + + CFGR3 + CFGR3 + SYSCFG configuration register + 3 + 0x1C + 0x20 + read-write + 0x00000000 + + + DMA3_MAP + DMA channel3 requeset selection + 16 + 5 + + + DMA2_MAP + DMA channel2 requeset selection + 8 + 5 + + + DMA1_MAP + DMA channel1 requeset selection + 0 + 5 + + + + + + + DMA + Direct memory access + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA_Channel1 + DMA Channel 1 Interrupt + 9 + + + DMA_Channel2_3 + DMA Channel 2 and Channel 3 Interrupt + 10 + + + + ISR + ISR + DMA interrupt status register + (DMA_ISR) + 0x0 + 0x20 + read-only + 0x00000000 + + + TEIF3 + Channel 3 Transfer Error + flag + 11 + 1 + + + HTIF3 + Channel 3 Half Transfer Complete + flag + 10 + 1 + + + TCIF3 + Channel 3 Transfer Complete + flag + 9 + 1 + + + GIF3 + Channel 3 Global interrupt + flag + 8 + 1 + + + TEIF2 + Channel 2 Transfer Error + flag + 7 + 1 + + + HTIF2 + Channel 2 Half Transfer Complete + flag + 6 + 1 + + + TCIF2 + Channel 2 Transfer Complete + flag + 5 + 1 + + + GIF2 + Channel 2 Global interrupt + flag + 4 + 1 + + + TEIF1 + Channel 1 Transfer Error + flag + 3 + 1 + + + HTIF1 + Channel 1 Half Transfer Complete + flag + 2 + 1 + + + TCIF1 + Channel 1 Transfer Complete + flag + 1 + 1 + + + GIF1 + Channel 1 Global interrupt + flag + 0 + 1 + + + + + IFCR + IFCR + DMA interrupt flag clear register + (DMA_IFCR) + 0x4 + 0x20 + write-only + 0x00000000 + + + CTEIF3 + Channel 3 Transfer Error + clear + 11 + 1 + + + CHTIF3 + Channel 3 Half Transfer + clear + 10 + 1 + + + CTCIF3 + Channel 3 Transfer Complete + clear + 9 + 1 + + + CGIF3 + Channel 3 Global interrupt + clear + 8 + 1 + + + CTEIF2 + Channel 2 Transfer Error + clear + 7 + 1 + + + CHTIF2 + Channel 2 Half Transfer + clear + 6 + 1 + + + CTCIF2 + Channel 2 Transfer Complete + clear + 5 + 1 + + + CGIF2 + Channel 2 Global interrupt + clear + 4 + 1 + + + CTEIF1 + Channel 1 Transfer Error + clear + 3 + 1 + + + CHTIF1 + Channel 1 Half Transfer + clear + 2 + 1 + + + CTCIF1 + Channel 1 Transfer Complete + clear + 1 + 1 + + + CGIF1 + Channel 1 Global interrupt + clear + 0 + 1 + + + + + CCR1 + CCR1 + DMA channel configuration register + (DMA_CCR) + 0x8 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR1 + CNDTR1 + DMA channel 1 number of data + register + 0xC + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR1 + CPAR1 + DMA channel 1 peripheral address + register + 0x10 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR1 + CMAR1 + DMA channel 1 memory address + register + 0x14 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR2 + CCR2 + DMA channel configuration register + (DMA_CCR) + 0x1C + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR2 + CNDTR2 + DMA channel 2 number of data + register + 0x20 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR2 + CPAR2 + DMA channel 2 peripheral address + register + 0x24 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR2 + CMAR2 + DMA channel 2 memory address + register + 0x28 + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + CCR3 + CCR3 + DMA channel configuration register + (DMA_CCR) + 0x30 + 0x20 + read-write + 0x00000000 + + + MEM2MEM + Memory to memory mode + 14 + 1 + + + PL + Channel Priority level + 12 + 2 + + + MSIZE + Memory size + 10 + 2 + + + PSIZE + Peripheral size + 8 + 2 + + + MINC + Memory increment mode + 7 + 1 + + + PINC + Peripheral increment mode + 6 + 1 + + + CIRC + Circular mode + 5 + 1 + + + DIR + Data transfer direction + 4 + 1 + + + TEIE + Transfer error interrupt + enable + 3 + 1 + + + HTIE + Half Transfer interrupt + enable + 2 + 1 + + + TCIE + Transfer complete interrupt + enable + 1 + 1 + + + EN + Channel enable + 0 + 1 + + + + + CNDTR3 + CNDTR3 + DMA channel 3 number of data + register + 0x34 + 0x20 + read-write + 0x00000000 + + + NDT + Number of data to transfer + 0 + 16 + + + + + CPAR3 + CPAR3 + DMA channel 3 peripheral address + register + 0x38 + 0x20 + read-write + 0x00000000 + + + PA + Peripheral address + 0 + 32 + + + + + CMAR3 + CMAR3 + DMA channel 3 memory address + register + 0x3C + 0x20 + read-write + 0x00000000 + + + MA + Memory address + 0 + 32 + + + + + + + FLASH + Flash + Flash + 0x40022000 + + 0x0 + 0x400 + registers + + + FLASH + FLASH global Interrupt + 3 + + + + ACR + ACR + Access control register + 0x0 + 0x20 + read-write + 0x00000600 + + + LATENCY + Latency + 0 + 1 + + + + + KEYR + KEYR + Flash key register + 0x8 + 0x20 + write-only + 0x00000000 + + + KEY + Flash key + 0 + 32 + + + + + OPTKEYR + OPTKEYR + Option byte key register + 0xC + 0x20 + write-only + 0x00000000 + + + OPTKEY + Option byte key + 0 + 32 + + + + + SR + SR + Status register + 0x10 + 0x20 + read-write + 0x00000000 + + + BSY + Busy + 16 + 1 + + + OPTVERR + Option and Engineering bits loading + validity error + 15 + 1 + + + WRPERR + Write protected error + 4 + 1 + + + EOP + End of operation + 0 + 1 + + + + + CR + CR + Flash control register + 0x14 + 0x20 + read-write + 0xC0000000 + + + LOCK + FLASH_CR Lock + 31 + 1 + + + OPTLOCK + Options Lock + 30 + 1 + + + OBL_LAUNCH + Force the option byte + loading + 27 + 1 + + + ERRIE + Error interrupt enable + 25 + 1 + + + EOPIE + End of operation interrupt + enable + 24 + 1 + + + PGTSTRT + Flash main memory program start + 19 + 1 + + + OPTSTRT + Option byte program start + 17 + 1 + + + SER + Sector erase + 11 + 1 + + + MER + Mass erase + 2 + 1 + + + PER + Page erase + 1 + 1 + + + PG + Programming + 0 + 1 + + + + + OPTR + OPTR + Flash option register + 0x20 + 0x20 + read-write + 0x4F55B0AA + + + nBOOT1 + Boot configuration + 15 + 1 + + + NRST_MODE + NRST_MODE + 14 + 1 + + + WWDG_SW + Window watchdog selection + 13 + 1 + + + IDWG_SW + Independent watchdog + selection + 12 + 1 + + + BORF_LEV + These bits contain the VDD supply level + threshold that activates the reset + 9 + 3 + + + BOREN + BOR reset Level + 8 + 1 + + + RDP + Read Protection + 0 + 8 + + + + + SDKR + SDKR + Flash SDK address + register + 0x24 + 0x20 + read-write + 0xFFE0001F + + + SDK_END + SDK area end address + 8 + 5 + + + SDK_STRT + SDK area start address + 0 + 5 + + + + + WRPR + WRPR + Flash WRP address + register + 0x2C + 0x20 + read-write + 0x0000FFFF + + + WRP + WRP address + 0 + 16 + + + + + STCR + STCR + Flash sleep time config + register + 0x90 + 0x20 + read-write + 0x00006400 + + + SLEEP_TIME + FLash sleep time configuration(counter based on HSI_10M) + 8 + 8 + + + SLEEP_EN + FLash sleep enable + 0 + 1 + + + + + TS0 + TS0 + Flash TS0 + register + 0x100 + 0x20 + read-write + 0x000000B4 + + + TS0 + FLash TS0 register + 0 + 8 + + + + + TS1 + TS1 + Flash TS1 + register + 0x104 + 0x20 + read-write + 0x000001B0 + + + TS1 + FLash TS1 register + 0 + 9 + + + + + TS2P + TS2P + Flash TS2P + register + 0x108 + 0x20 + read-write + 0x000000B4 + + + TS2P + FLash TS2P register + 0 + 8 + + + + + TPS3 + TPS3 + Flash TPS3 + register + 0x10C + 0x20 + read-write + 0x000006C0 + + + TPS3 + FLash TPS3 register + 0 + 11 + + + + + TS3 + TS3 + Flash TS3 + register + 0x110 + 0x20 + read-write + 0x000000B4 + + + TS3 + FLash TS3 register + 0 + 8 + + + + + PERTPE + PERTPE + Flash PERTPE + register + 0x114 + 0x20 + read-write + 0x0000EA60 + + + PERTPE + FLash PERTPE register + 0 + 17 + + + + + SMERTPE + SMERTPE + Flash SMERTPE + register + 0x118 + 0x20 + read-write + 0x0000FD20 + + + SMERTPE + FLash SMERTPE register + 0 + 17 + + + + + PRGTPE + PRGTPE + Flash PRGTPE + register + 0x11C + 0x20 + read-write + 0x00008CA0 + + + PRGTPE + FLash PRGTPE register + 0 + 16 + + + + + PRETPE + PRETPE + Flash PRETPE + register + 0x120 + 0x20 + read-write + 0x000012C0 + + + PRETPE + FLash PRETPE register + 0 + 13 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global Interrupt + 25 + + + + CR1 + CR1 + control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + BIDIMODE + Bidirectional data mode + enable + 15 + 1 + + + BIDIOE + Output enable in bidirectional + mode + 14 + 1 + + + RXONLY + Receive only + 10 + 1 + + + SSM + Software slave management + 9 + 1 + + + SSI + Internal slave selection + 8 + 1 + + + LSBFIRST + Frame format + 7 + 1 + + + SPE + SPI enable + 6 + 1 + + + BR + Baud rate control + 3 + 3 + + + MSTR + Master selection + 2 + 1 + + + CPOL + Clock polarity + 1 + 1 + + + CPHA + Clock phase + 0 + 1 + + + + + CR2 + CR2 + control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + SLVFM + Slave fast mode enable + 15 + 1 + + + LDMA_TX + Last DAM Transmit(TX) + 14 + 1 + + + LDMA_RX + Last DAM Transmit(RX) + 13 + 1 + + + FRXTH + FIFO reception threshold + 12 + 1 + + + DS + Data length + + 11 + 1 + + + TXEIE + Tx buffer empty interrupt + enable + 7 + 1 + + + RXNEIE + RX buffer not empty interrupt + enable + 6 + 1 + + + ERRIE + Error interrupt enable + 5 + 1 + + + SSOE + SS output enable + 2 + 1 + + + TXDMAEN + Tx buffer DMA enable + 1 + 1 + + + RXDMAEN + Rx buffer DMA enable + 0 + 1 + + + + + SR + SR + status register + 0x8 + 0x20 + 0x0002 + + + FTLVL + FIFO transmission level + 11 + 2 + read-only + + + FRLVL + FIFO reception level + 9 + 2 + read-only + + + BSY + Busy flag + 7 + 1 + read-only + + + OVR + Overrun flag + 6 + 1 + read-only + + + MODF + Mode fault + 5 + 1 + read-only + + + TXE + Transmit buffer empty + 1 + 1 + read-only + + + RXNE + Receive buffer not empty + 0 + 1 + read-only + + + + + DR + DR + data register + 0xC + 0x20 + read-write + 0x0000 + + + DR + Data register + 0 + 16 + + + + + + + SPI2 + 0x40003800 + + SPI2 + SPI2 global Interrupt + 26 + + + + I2C + Inter integrated circuit + I2C + 0x40005400 + + 0x0 + 0x400 + registers + + + I2C1 + I2C1 global Interrupt + 23 + + + + CR1 + CR1 + Control register 1 + 0x0 + 0x20 + read-write + 0x0000 + + + SWRST + Software reset + 15 + 1 + + + PEC + Packet error checking + 12 + 1 + + + POS + Acknowledge/PEC Position (for data + reception) + 11 + 1 + + + ACK + Acknowledge enable + 10 + 1 + + + STOP + Stop generation + 9 + 1 + + + START + Start generation + 8 + 1 + + + NOSTRETCH + Clock stretching disable (Slave + mode) + 7 + 1 + + + ENGC + General call enable + 6 + 1 + + + ENPEC + PEC enable + 5 + 1 + + + PE + Peripheral enable + 0 + 1 + + + + + CR2 + CR2 + Control register 2 + 0x4 + 0x20 + read-write + 0x0000 + + + LAST + DMA last transfer + 12 + 1 + + + DMAEN + DMA requests enable + 11 + 1 + + + ITBUFEN + Buffer interrupt enable + 10 + 1 + + + ITEVTEN + Event interrupt enable + 9 + 1 + + + ITERREN + Error interrupt enable + 8 + 1 + + + FREQ + Peripheral clock frequency + 0 + 6 + + + + + OAR1 + OAR1 + Own address register 1 + 0x8 + 0x20 + read-write + 0x0000 + + + ADD + Interface address + 1 + 7 + + + + + DR + DR + Data register + 0x10 + 0x20 + read-write + 0x0000 + + + DR + 8-bit data register + 0 + 8 + + + + + SR1 + SR1 + Status register 1 + 0x14 + 0x20 + 0x0000 + + + PECERR + PEC Error in reception + 12 + 1 + read-write + + + OVR + Overrun/Underrun + 11 + 1 + read-write + + + AF + Acknowledge failure + 10 + 1 + read-write + + + ARLO + Arbitration lost (master + mode) + 9 + 1 + read-write + + + BERR + Bus error + 8 + 1 + read-write + + + TxE + Data register empty + (transmitters) + 7 + 1 + read-only + + + RxNE + Data register not empty + (receivers) + 6 + 1 + read-only + + + STOPF + Stop detection (slave + mode) + 4 + 1 + read-only + + + BTF + Byte transfer finished + 2 + 1 + read-only + + + ADDR + Address sent (master mode)/matched + (slave mode) + 1 + 1 + read-only + + + SB + Start bit (Master mode) + 0 + 1 + read-only + + + + + SR2 + SR2 + Status register 2 + 0x18 + 0x20 + read-only + 0x0000 + + + PEC + acket error checking + register + 8 + 8 + + + DUALF + Dual flag (Slave mode) + 7 + 1 + + + GENCALL + General call address (Slave + mode) + 4 + 1 + + + TRA + Transmitter/receiver + 2 + 1 + + + BUSY + Bus busy + 1 + 1 + + + MSL + Master/slave + 0 + 1 + + + + + CCR + CCR + Clock control register + 0x1C + 0x20 + read-write + 0x0000 + + + F_S + I2C master mode selection + 15 + 1 + + + DUTY + Fast mode duty cycle + 14 + 1 + + + CCR + Clock control register in Fast/Standard + mode (Master mode) + 0 + 12 + + + + + TRISE + TRISE + TRISE register + 0x20 + 0x20 + read-write + 0x0002 + + + TRISE + Maximum rise time in Fast/Standard mode + (Master mode) + 0 + 6 + + + + + + + LED + LED CONTROLLER + LED + 0x40002400 + + 0x0 + 0x400 + registers + + + LED + LED global Interrupt + 30 + + + + CR + LED_CR + Control register + 0x0 + 0x20 + read-write + 0x0000 + + + EHS + Light control + 12 + 2 + + + IE + LED interrupt enable + 3 + 1 + + + LED_COM_SEL + LED COM Selection + 1 + 2 + + + LEDON + LED enable + 0 + 1 + + + + + PR + LED_PR + Prescaler register + 0x4 + 0x20 + read-write + 0x0000 + + + PR + Prescaler control + 0 + 8 + + + + + TR + LED_TR + Time register + 0x8 + 0x20 + read-write + 0x0000 + + + T2 + Switch time + 8 + 8 + + + T1 + Light on time + 0 + 8 + + + + + DR0 + LED_DR0 + Data0 register + 0x0C + 0x20 + read-write + 0x0000 + + + DATA0_DP + 8-bit data register + 7 + 1 + + + DATA0_G + 8-bit data register + 6 + 1 + + + DATA0_F + 8-bit data register + 5 + 1 + + + DATA0_E + 8-bit data register + 4 + 1 + + + DATA0_D + 8-bit data register + 3 + 1 + + + DATA0_C + 8-bit data register + 2 + 1 + + + DATA0_B + 8-bit data register + 1 + 1 + + + DATA0_A + 8-bit data register + 0 + 1 + + + + + DR1 + LED_DR1 + Data1 register + 0x10 + 0x20 + read-write + 0x0000 + + + DATA1_DP + 8-bit data register + 7 + 1 + + + DATA1_G + 8-bit data register + 6 + 1 + + + DATA1_F + 8-bit data register + 5 + 1 + + + DATA1_E + 8-bit data register + 4 + 1 + + + DATA1_D + 8-bit data register + 3 + 1 + + + DATA1_C + 8-bit data register + 2 + 1 + + + DATA1_B + 8-bit data register + 1 + 1 + + + DATA1_A + 8-bit data register + 0 + 1 + + + + + DR2 + LED_DR2 + Data2 register + 0x14 + 0x20 + read-write + 0x0000 + + + DATA2_DP + 8-bit data register + 7 + 1 + + + DATA2_G + 8-bit data register + 6 + 1 + + + DATA2_F + 8-bit data register + 5 + 1 + + + DATA2_E + 8-bit data register + 4 + 1 + + + DATA2_D + 8-bit data register + 3 + 1 + + + DATA2_C + 8-bit data register + 2 + 1 + + + DATA2_B + 8-bit data register + 1 + 1 + + + DATA2_A + 8-bit data register + 0 + 1 + + + + + DR3 + LED_DR3 + Data3 register + 0x18 + 0x20 + read-write + 0x0000 + + + DATA3_DP + 8-bit data register + 7 + 1 + + + DATA3_G + 8-bit data register + 6 + 1 + + + DATA3_F + 8-bit data register + 5 + 1 + + + DATA3_E + 8-bit data register + 4 + 1 + + + DATA3_D + 8-bit data register + 3 + 1 + + + DATA3_C + 8-bit data register + 2 + 1 + + + DATA3_B + 8-bit data register + 1 + 1 + + + DATA3_A + 8-bit data register + 0 + 1 + + + + + IR + LED_IR + Interrupt register 1 + 0x1C + 0x20 + 0x0000 + + + FLAG + interrupt flag + 0 + 1 + read-write + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + + + + CR + CR + Debug MCU Configuration + Register + 0x4 + 0x20 + read-write + 0x0 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + + + APB_FZ1 + APB_FZ1 + APB Freeze Register1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER3_STOP + Debug Timer 3 stopped when Core is + halted + 1 + 1 + + + DBG_RTC_STOP + Debug RTC stopped when Core is + halted + 10 + 1 + + + DBG_WWDG_STOP + Debug Window Wachdog stopped when Core + is halted + 11 + 1 + + + DBG_IWDG_STOP + Debug Independent Wachdog stopped when + Core is halted + 12 + 1 + + + DBG_LPTIM_STOP + Debug LPTIM stopped when Core is + halted + 31 + 1 + + + + + APB_FZ2 + APB_FZ2 + APB Freeze Register2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIMER1_STOP + Debug Timer 1 stopped when Core is + halted + 11 + 1 + + + DBG_TIMER14_STOP + Debug Timer 14 stopped when Core is + halted + 15 + 1 + + + DBG_TIMER16_STOP + Debug Timer 16 stopped when Core is + halted + 17 + 1 + + + DBG_TIMER17_STOP + Debug Timer 17 stopped when Core is + halted + 18 + 1 + + + + + + + diff --git a/Misc/py32f072xx.svd b/Misc/SVD/py32f072xx.svd similarity index 96% rename from Misc/py32f072xx.svd rename to Misc/SVD/py32f072xx.svd index f2becf6..46b4ae0 100644 --- a/Misc/py32f072xx.svd +++ b/Misc/SVD/py32f072xx.svd @@ -1,20252 +1,20250 @@ - - - - Puya - Puya - PY32F0xx_DFP - - PY32F0 - 1.0.0 - Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. - - - - CM0+ - r0p1 - little - false - false - 4 - false - - - - 8 - - 32 - - - 32 - - read-write - - 0x00000000 - - 0xFFFFFFFF - - - - ADC - Analog to Digital Converter - ADC - 0x40012400 - - 0x0 - 0x400 - registers - - - ADC_COMP - ADC and COMP Interrupt through EXTI Lines 17 and 18 - 12 - - - - SR - desc SR - 0x0 - 32 - read-write - 0x0 - - - AWD - desc AWD - 0 - 0 - read-write - - - EOC - desc EOC - 1 - 1 - read-write - - - JEOC - desc JEOC - 2 - 2 - read-write - - - JSTRT - desc JSTRT - 3 - 3 - read-write - - - STRT - desc STRT - 4 - 4 - read-write - - - OVER - desc OVER - 5 - 5 - read-write - - - - - CR1 - desc CR1 - 0x4 - 32 - read-write - 0x0 - - - AWDCH - desc AWDCH - 4 - 0 - read-write - - - EOCIE - desc EOCIE - 5 - 5 - read-write - - - AWDIE - desc AWDIE - 6 - 6 - read-write - - - JEOCIE - desc JEOCIE - 7 - 7 - read-write - - - SCAN - desc SCAN - 8 - 8 - read-write - - - AWDSGL - desc AWDSGL - 9 - 9 - read-write - - - JAUTO - desc JAUTO - 10 - 10 - read-write - - - DISCEN - desc DISCEN - 11 - 11 - read-write - - - JDISCEN - desc JDISCEN - 12 - 12 - read-write - - - DISCNUM - desc DISCNUM - 15 - 13 - read-write - - - JAWDEN - desc JAWDEN - 22 - 22 - read-write - - - AWDEN - desc AWDEN - 23 - 23 - read-write - - - RESSEL - desc RESSEL - 25 - 24 - read-write - - - ADSTP - desc ADSTP - 27 - 27 - read-write - - - MSBSEL - desc MSBSEL - 28 - 28 - read-write - - - OVETIE - desc OVETIE - 29 - 29 - read-write - - - - - CR2 - desc CR2 - 0x8 - 32 - read-write - 0x0 - - - ADON - desc ADON - 0 - 0 - read-write - - - CONT - desc CONT - 1 - 1 - read-write - - - CAL - desc CAL - 2 - 2 - read-write - - - RSTCAL - desc RSTCAL - 3 - 3 - read-write - - - DMA - desc DMA - 8 - 8 - read-write - - - ALIGN - desc ALIGN - 11 - 11 - read-write - - - JEXTSEL - desc JEXTSEL - 14 - 12 - read-write - - - JEXTTRIG - desc JEXTTRIG - 15 - 15 - read-write - - - EXTSEL - desc EXTSEL - 19 - 17 - read-write - - - EXTTRIG - desc EXTTRIG - 20 - 20 - read-write - - - JSWSTART - desc JSWSTART - 21 - 21 - read-write - - - SWSTART - desc SWSTART - 22 - 22 - read-write - - - TSVREFE - desc TSVREFE - 23 - 23 - read-write - - - VERFBUFFEREN - desc VERFBUFFEREN - 25 - 25 - read-write - - - VERFBUFFERSEL - desc VERFBUFFERSEL - 27 - 26 - read-write - - - - - SMPR1 - desc SMPR1 - 0xC - 32 - read-write - 0x0 - - - SMP20 - desc SMP20 - 2 - 0 - read-write - - - SMP21 - desc SMP21 - 5 - 3 - read-write - - - SMP22 - desc SMP22 - 8 - 6 - read-write - - - SMP23 - desc SMP23 - 11 - 9 - read-write - - - - - SMPR2 - desc SMPR2 - 0x10 - 32 - read-write - 0x0 - - - SMP10 - desc SMP10 - 2 - 0 - read-write - - - SMP11 - desc SMP11 - 5 - 3 - read-write - - - SMP12 - desc SMP12 - 8 - 6 - read-write - - - SMP13 - desc SMP13 - 11 - 9 - read-write - - - SMP14 - desc SMP14 - 14 - 12 - read-write - - - SMP15 - desc SMP15 - 17 - 15 - read-write - - - SMP16 - desc SMP16 - 20 - 18 - read-write - - - SMP17 - desc SMP17 - 23 - 21 - read-write - - - SMP18 - desc SMP18 - 26 - 24 - read-write - - - SMP19 - desc SMP19 - 29 - 27 - read-write - - - - - SMPR3 - desc SMPR2 - 0x14 - 32 - read-write - 0x0 - - - SMP0 - desc SMP0 - 2 - 0 - read-write - - - SMP1 - desc SMP1 - 5 - 3 - read-write - - - SMP2 - desc SMP2 - 8 - 6 - read-write - - - SMP3 - desc SMP3 - 11 - 9 - read-write - - - SMP4 - desc SMP4 - 14 - 12 - read-write - - - SMP5 - desc SMP5 - 17 - 15 - read-write - - - SMP6 - desc SMP6 - 20 - 18 - read-write - - - SMP7 - desc SMP7 - 23 - 21 - read-write - - - SMP8 - desc SMP8 - 26 - 24 - read-write - - - SMP9 - desc SMP9 - 29 - 27 - read-write - - - - - JOFR1 - desc JOFR1 - 0x18 - 32 - read-write - 0x0 - - - JOFFSET1 - desc JOFFSET1 - 11 - 0 - read-write - - - - - JOFR2 - desc JOFR2 - 0x1C - 32 - read-write - 0x0 - - - JOFFSET2 - desc JOFFSET2 - 11 - 0 - read-write - - - - - JOFR3 - desc JOFR3 - 0x20 - 32 - read-write - 0x0 - - - JOFFSET3 - desc JOFFSET3 - 11 - 0 - read-write - - - - - JOFR4 - desc JOFR4 - 0x24 - 32 - read-write - 0x0 - - - JOFFSET4 - desc JOFFSET4 - 11 - 0 - read-write - - - - - HTR - desc HTR - 0x28 - 32 - read-write - 0x0 - - - HT - desc HT - 11 - 0 - read-write - - - - - LTR - desc LTR - 0x2C - 32 - read-write - 0x0 - - - LT - desc LT - 11 - 0 - read-write - - - - - SQR1 - desc SQR1 - 0x30 - 32 - read-write - 0x0 - - - SQ13 - desc SQ13 - 4 - 0 - read-write - - - SQ14 - desc SQ14 - 9 - 5 - read-write - - - SQ15 - desc SQ15 - 14 - 10 - read-write - - - SQ16 - desc SQ16 - 19 - 15 - read-write - - - L - desc L - 23 - 20 - read-write - - - - - SQR2 - desc SQR2 - 0x34 - 32 - read-write - 0x0 - - - SQ7 - desc SQ7 - 4 - 0 - read-write - - - SQ8 - desc SQ8 - 9 - 5 - read-write - - - SQ9 - desc SQ9 - 14 - 10 - read-write - - - SQ10 - desc SQ10 - 19 - 15 - read-write - - - SQ11 - desc SQ11 - 24 - 20 - read-write - - - SQ12 - desc SQ12 - 29 - 25 - read-write - - - - - SQR3 - desc SQR3 - 0x38 - 32 - read-write - 0x0 - - - SQ1 - desc SQ1 - 4 - 0 - read-write - - - SQ2 - desc SQ2 - 9 - 5 - read-write - - - SQ3 - desc SQ3 - 14 - 10 - read-write - - - SQ4 - desc SQ4 - 19 - 15 - read-write - - - SQ5 - desc SQ5 - 24 - 20 - read-write - - - SQ6 - desc SQ6 - 29 - 25 - read-write - - - - - JSQR - desc JSQR - 0x3C - 32 - read-write - 0x0 - - - JSQ1 - desc JSQ1 - 4 - 0 - read-write - - - JSQ2 - desc JSQ2 - 9 - 5 - read-write - - - JSQ3 - desc JSQ3 - 14 - 10 - read-write - - - JSQ4 - desc JSQ4 - 19 - 15 - read-write - - - JL - desc JL - 21 - 20 - read-write - - - - - JDR1 - desc JDR1 - 0x40 - 32 - read-only - 0x0 - - - JDR1 - desc JDR1 - 15 - 0 - read-only - - - - - JDR2 - desc JDR2 - 0x44 - 32 - read-only - 0x0 - - - JDR2 - desc JDR2 - 15 - 0 - read-only - - - - - JDR3 - desc JDR3 - 0x48 - 32 - read-only - 0x0 - - - JDR3 - desc JDR3 - 15 - 0 - read-only - - - - - JDR4 - desc JDR4 - 0x4C - 32 - read-only - 0x0 - - - JDR4 - desc JDR4 - 15 - 0 - read-only - - - - - DR - desc DR - 0x50 - 32 - read-only - 0x0 - - - DATA - desc DATA - 15 - 0 - read-only - - - - - CCSR - desc CCSR - 0x54 - 32 - read-write - 0x0 - - - CALSEL - desc CALSEL - 11 - 11 - read-write - - - CALSMP - desc CALSMP - 13 - 12 - read-write - - - CALBYP - desc CALBYP - 14 - 14 - read-write - - - CALSET - desc CALSET - 15 - 15 - read-write - - - CALFAIL - desc CALFAIL - 30 - 30 - read-write - - - CALON - desc CALON - 31 - 31 - read-only - - - - - CALRR1 - desc CALRR1 - 0x58 - 32 - read-only - 0x0 - - - CALC10OUT - desc CALC10OUT - 7 - 0 - read-only - - - CALC11OUT - desc CALC11OUT - 15 - 8 - read-only - - - CALBOUT - desc CALBOUT - 23 - 16 - read-only - - - - - CALRR2 - desc CALRR2 - 0x5C - 32 - read-only - 0x0 - - - CALC6OUT - desc CALC6OUT - 7 - 0 - read-only - - - CALC7OUT - desc CALC7OUT - 15 - 8 - read-only - - - CALC8OUT - desc CALC8OUT - 23 - 16 - read-only - - - CALC9OUT - desc CALC9OUT - 31 - 24 - read-only - - - - - CALFIR1 - desc CALFIR1 - 0x60 - 32 - read-write - 0x0 - - - CALC10IO - desc CALC10IO - 7 - 0 - read-write - - - CALC11IO - desc CALC11IO - 15 - 8 - read-write - - - CALBIO - desc CALBIO - 23 - 16 - read-write - - - - - CALFIR2 - desc CALFIR2 - 0x64 - 32 - read-write - 0x0 - - - CALC6IO - desc CALC6IO - 7 - 0 - read-write - - - CALC7IO - desc CALC7IO - 15 - 8 - read-write - - - CALC8IO - desc CALC8IO - 23 - 16 - read-write - - - CALC9IO - desc CALC9IO - 31 - 24 - read-write - - - - - - - CAN - desc CAN - CAN - 0x40006400 - - 0x0 - 0x400 - registers - - - CAN - CAN global Interrupt - 30 - - - - TSNCR - desc TSNCR - 0x0 - 32 - read-write - 0x2010801 - - - VERSION - desc VERSION - 15 - 0 - read-only - - - CES - desc CES - 16 - 16 - read-write - - - ROP - desc ROP - 17 - 17 - read-write - - - TMSE - desc TMSE - 18 - 18 - read-write - - - TSEN - desc TSEN - 24 - 24 - read-write - - - TSPOS - desc TSPOS - 25 - 25 - read-write - - - - - ACBTR - desc ACBTR - 0x4 - 32 - read-write - 0x5050008 - - - AC_SEG_1 - desc AC_SEG_1 - 8 - 0 - read-write - - - AC_SEG_2 - desc AC_SEG_2 - 22 - 16 - read-write - - - AC_SJW - desc AC_SJW - 30 - 24 - read-write - - - - - FDBTR - desc FDBTR - 0x8 - 32 - read-write - 0x2020003 - - - FD_SEG_1 - desc FD_SEG_1 - 7 - 0 - read-write - - - FD_SEG_2 - desc FD_SEG_2 - 22 - 16 - read-write - - - FD_SJW - desc FD_SJW - 30 - 24 - read-write - - - - - XLBTR - desc XLBTR - 0xC - 32 - read-write - 0x2020003 - - - XL_SEG_1 - desc XL_SEG_1 - 7 - 0 - read-write - - - XL_SEG_2 - desc XL_SEG_2 - 22 - 16 - read-write - - - XL_SJW - desc XL_SJW - 30 - 24 - read-write - - - - - RLSSP - desc RLSSP - 0x10 - 32 - read-write - 0x77000000 - - - PRESC - desc PRESC - 4 - 0 - read-write - - - FD_SSPOFF - desc FD_SSPOFF - 15 - 8 - read-write - - - XL_SSPOFF - desc XL_SSPOFF - 23 - 16 - read-write - - - REALIM - desc REALIM - 26 - 24 - read-write - - - RETLIM - desc RETLIM - 30 - 28 - read-write - - - - - IFR - desc IFR - 0x14 - 32 - read-write - 0x0 - - - AIF - desc AIF - 0 - 0 - read-write - - - EIF - desc EIF - 1 - 1 - read-write - - - TSIF - desc TSIF - 2 - 2 - read-write - - - TPIF - desc TPIF - 3 - 3 - read-write - - - RAFIF - desc RAFIF - 4 - 4 - read-write - - - RFIF - desc RFIF - 5 - 5 - read-write - - - ROIF - desc ROIF - 6 - 6 - read-write - - - RIF - desc RIF - 7 - 7 - read-write - - - BEIF - desc BEIF - 8 - 8 - read-write - - - ALIF - desc ALIF - 9 - 9 - read-write - - - EPIF - desc EPIF - 10 - 10 - read-write - - - TTIF - desc TTIF - 11 - 11 - read-write - - - TEIF - desc TEIF - 12 - 12 - read-write - - - WTIF - desc WTIF - 13 - 13 - read-write - - - MDWIF - desc MDWIF - 14 - 14 - read-write - - - MDEIF - desc MDEIF - 15 - 15 - read-write - - - MAEIF - desc MAEIF - 16 - 16 - read-write - - - SEIF - desc SEIF - 17 - 17 - read-write - - - SWIF - desc SWIF - 18 - 18 - read-write - - - EPASS - desc EPASS - 30 - 30 - read-only - - - EWARN - desc EWARN - 31 - 31 - read-only - - - - - IER - desc IER - 0x18 - 32 - read-write - 0x468FE - - - EIE - desc EIE - 1 - 1 - read-write - - - TSIE - desc TSIE - 2 - 2 - read-write - - - TPIE - desc TPIE - 3 - 3 - read-write - - - RAFIE - desc RAFIE - 4 - 4 - read-write - - - RFIE - desc RFIE - 5 - 5 - read-write - - - ROIE - desc ROIE - 6 - 6 - read-write - - - RIE - desc RIE - 7 - 7 - read-write - - - BEIE - desc BEIE - 8 - 8 - read-write - - - ALIE - desc ALIE - 9 - 9 - read-write - - - EPIE - desc EPIE - 10 - 10 - read-write - - - TTIE - desc TTIE - 11 - 11 - read-write - - - WTIE - desc WTIE - 13 - 13 - read-write - - - MDWIE - desc MDWIE - 14 - 14 - read-write - - - SWIE - desc SWIE - 18 - 18 - read-write - - - - - TSR - desc TSR - 0x1C - 32 - read-only - 0x0 - - - HANDLE_L - desc HANDLE_L - 7 - 0 - read-only - - - TSTAT_L - desc TSTAT_L - 10 - 8 - read-only - - - HANDLE_H - desc HANDLE_H - 23 - 16 - read-only - - - TSTAT_H - desc TSTAT_H - 26 - 24 - read-only - - - - - TTSL - desc TTSL - 0x20 - 32 - read-only - 0x2000000 - - - TTS - desc TTS - 31 - 0 - read-only - - - - - TTSH - desc TTSH - 0x24 - 32 - read-only - 0x2000000 - - - TTS - desc TTS - 31 - 0 - read-only - - - - - MCR - desc MCR - 0x28 - 32 - read-write - 0x900080 - - - BUSOFF - desc BUSOFF - 0 - 0 - read-write - - - LBMI - desc LBMI - 5 - 5 - read-write - - - LBME - desc LBME - 6 - 6 - read-write - - - RESET - desc RESET - 7 - 7 - read-write - - - TSA - desc TSA - 8 - 8 - read-write - - - TSALL - desc TSALL - 9 - 9 - read-write - - - TSONE - desc TSONE - 10 - 10 - read-write - - - TPA - desc TPA - 11 - 11 - read-write - - - TPE - desc TPE - 12 - 12 - read-write - - - STBY - desc STBY - 13 - 13 - read-write - - - LOM - desc LOM - 14 - 14 - read-write - - - TBSEL - desc TBSEL - 15 - 15 - read-write - - - TSSTAT - desc TSSTAT - 17 - 16 - read-only - - - TSFF - desc TSFF - 18 - 18 - read-only - - - TTTBM - desc TTTBM - 20 - 20 - read-write - - - TSMODE - desc TSMODE - 21 - 21 - read-write - - - TSNEXT - desc TSNEXT - 22 - 22 - read-write - - - FD_ISO - desc FD_ISO - 23 - 23 - read-write - - - RSTAT - desc RSTAT - 25 - 24 - read-only - - - RBALL - desc RBALL - 27 - 27 - read-write - - - RREL - desc RREL - 28 - 28 - read-write - - - ROV - desc ROV - 29 - 29 - read-only - - - ROM - desc ROM - 30 - 30 - read-write - - - SACK - desc SACK - 31 - 31 - read-write - - - - - WECR - desc WECR - 0x2C - 32 - read-write - 0x1B - - - EWL - desc EWL - 3 - 0 - read-write - - - AFWL - desc AFWL - 7 - 4 - read-write - - - ALC - desc ALC - 12 - 8 - read-only - - - KOER - desc KOER - 15 - 13 - read-only - - - RECNT - desc RECNT - 23 - 16 - read-only - - - TECNT - desc TECNT - 31 - 24 - read-only - - - - - REFMSG - desc REFMSG - 0x30 - 32 - read-write - 0x0 - - - REF_ID - desc REF_ID - 28 - 0 - read-write - - - REF_IDE - desc REF_IDE - 31 - 31 - read-write - - - - - TTCR - desc TTCR - 0x34 - 32 - read-write - 0x0 - - - TTPTR - desc TTPTR - 5 - 0 - read-write - - - TTYPE - desc TTYPE - 10 - 8 - read-write - - - TEW - desc TEW - 15 - 12 - read-write - - - TBPTR - desc TBPTR - 21 - 16 - read-write - - - TBF - desc TBF - 22 - 22 - read-write - - - TBE - desc TBE - 23 - 23 - read-write - - - TTEN - desc TTEN - 24 - 24 - read-write - - - T_PRESC - desc T_PRESC - 26 - 25 - read-write - - - - - TTTR - desc TTTR - 0x38 - 32 - read-write - 0xFFFF0000 - - - TT_TRIG - desc TT_TRIG - 15 - 0 - read-write - - - TT_WTRIG - desc TT_WTRIG - 31 - 16 - read-write - - - - - SCMS - desc SCMS - 0x3C - 32 - read-write - 0x0 - - - XMREN - desc XMREN - 0 - 0 - read-write - - - FSTIM - desc FSTIM - 3 - 1 - read-write - - - ACFA - desc ACFA - 24 - 24 - read-write - - - TXS - desc TXS - 25 - 25 - read-only - - - TXB - desc TXB - 26 - 26 - read-only - - - HELOC - desc HELOC - 28 - 27 - read-only - - - MPEN - desc MPEN - 31 - 31 - read-write - - - - - MESR - desc MESR - 0x40 - 32 - read-write - 0x0 - - - MEBP1 - desc MEBP1 - 5 - 0 - read-write - - - ME1EE - desc ME1EE - 6 - 6 - read-write - - - MEAEE - desc MEAEE - 7 - 7 - read-write - - - MEBP2 - desc MEBP2 - 13 - 8 - read-write - - - ME2EE - desc ME2EE - 14 - 14 - read-write - - - MEEEC - desc MEEEC - 19 - 16 - read-write - - - MENEC - desc MENEC - 23 - 20 - read-write - - - MEL - desc MEL - 25 - 24 - read-write - - - MES - desc MES - 26 - 26 - read-write - - - - - ACFCR - desc ACFCR - 0x44 - 32 - read-write - 0x10000 - - - ACFADR - desc ACFADR - 3 - 0 - read-write - - - AE_0 - desc AE_0 - 16 - 16 - read-write - - - AE_1 - desc AE_1 - 17 - 17 - read-write - - - AE_2 - desc AE_2 - 18 - 18 - read-write - - - AE_3 - desc AE_3 - 19 - 19 - read-write - - - AE_4 - desc AE_4 - 20 - 20 - read-write - - - AE_5 - desc AE_5 - 21 - 21 - read-write - - - AE_6 - desc AE_6 - 22 - 22 - read-write - - - AE_7 - desc AE_7 - 23 - 23 - read-write - - - AE_8 - desc AE_8 - 24 - 24 - read-write - - - AE_9 - desc AE_9 - 25 - 25 - read-write - - - AE_10 - desc AE_10 - 26 - 26 - read-write - - - AE_11 - desc AE_11 - 27 - 27 - read-write - - - AE_12 - desc AE_12 - 28 - 28 - read-write - - - AE_13 - desc AE_13 - 29 - 29 - read-write - - - AE_14 - desc AE_14 - 30 - 30 - read-write - - - AE_15 - desc AE_15 - 31 - 31 - read-write - - - - - PWMCR - desc PWMCR - 0xB8 - 32 - read-write - 0x2080400 - - - PWMO - desc PWMO - 5 - 0 - read-write - - - PWMS - desc PWMS - 13 - 8 - read-write - - - PWML - desc PWML - 21 - 16 - read-write - - - - - - - COMP1 - Comparator 1 - COMP - 0x40010200 - - 0x0 - 0x10 - registers - - - ADC_COMP - ADC and COMP Interrupt through EXTI Lines 17 and 18 - 12 - - - - CSR - CSR - COMP control and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - COMP_OUT - Comparator output status - 30 - 1 - - - VCSEL - VCSEL - 27 - 1 - - - VCDIV_EN - VCDIV_EN - 26 - 1 - - - VCDIV - VCDIV - 20 - 6 - - - PWRMODE - - Comparator power mode - selector - - 18 - 2 - - - HYST - - Comparator hysteresis enable - selector - - 16 - 1 - - - POLARITY - - Comparator polarity - selector - - 15 - 1 - - - WINMODE - - Comparator non-inverting input - selector for window mode - - 11 - 1 - - - INPSEL - - Comparator signal selector for - non-inverting input - - 6 - 4 - - - INMSEL - - Comparator signal selector for - inverting input INM - - 2 - 4 - - - EN - COMP enable bit - 0 - 1 - - - - - FR - FR - - Comparator Filter - register - - 0x4 - 0x20 - read-write - 0x00000000 - - - FLTCNT1 - Comparator filter and counter - 16 - 16 - - - FLTEN1 - Filter enable bit - 0 - 1 - - - - - - - COMP2 - Comparator2 - COMP - 0x40010210 - - 0x0 - 0x10 - registers - - - ADC_COMP - ADC and COMP Interrupt through EXTI Lines 17 and 18 - 12 - - - - CSR - CSR - COMP control and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - COMP_OUT - Comparator output status - 30 - 1 - - - PWRMODE - - Comparator power mode - selector - - 18 - 2 - - - POLARITY - - Comparator polarity - selector - - 15 - 1 - - - WINMODE - - Comparator non-inverting input - selector for window mode - - 11 - 1 - - - INPSEL - - Comparator signal selector for - non-inverting input - - 6 - 4 - - - INMSEL - - Comparator signal selector for - inverting input INM - - 2 - 4 - - - HYST - - Comparator hysteresis enable - selector - - 1 - 1 - - - EN - COMP enable bit - 0 - 1 - - - - - FR - FR - - Comparator Filter - register - - 0x4 - 0x20 - read-write - 0x00000000 - - - FLTCNT2 - Comparator filter and counter - 16 - 16 - - - FLTEN2 - Filter enable bit - 0 - 1 - - - - - - - COMP3 - Comparator3 - COMP - 0x40010220 - - 0x0 - 0x10 - registers - - - ADC_COMP - ADC and COMP Interrupt through EXTI Lines 17 and 18 - 12 - - - - CSR - CSR - COMP control and status register - 0x0 - 0x20 - read-write - 0x00000000 - - - COMP_OUT - Comparator output status - 30 - 1 - - - PWRMODE - - Comparator power mode - selector - - 18 - 2 - - - POLARITY - - Comparator polarity - selector - - 15 - 1 - - - INPSEL - - Comparator signal selector for - non-inverting input - - 6 - 4 - - - INMSEL - - Comparator signal selector for - inverting input INM - - 2 - 4 - - - HYST - - Comparator hysteresis enable - selector - - 1 - 1 - - - EN - COMP enable bit - 0 - 1 - - - - - FR - FR - - Comparator Filter - register - - 0x4 - 0x20 - read-write - 0x00000000 - - - FLTCNT3 - Comparator filter and counter - 16 - 16 - - - FLTEN3 - Filter enable bit - 0 - 1 - - - - - - - CRC - CRC calculation unit - CRC - 0x40023000 - - 0x0 - 0x400 - registers - - - - DR - DR - Data register - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - DR - Data Register - 0 - 32 - - - - - IDR - IDR - Independent Data register - 0x4 - 0x20 - read-write - 0x00000000 - - - IDR - Independent Data register - 0 - 8 - - - - - CR - CR - Control register - 0x8 - 0x20 - write-only - 0x00000000 - - - RESET - Reset bit - 0 - 1 - - - - - - - CTC - desc CTC - CTC - 0x40006C00 - - 0x0 - 0x400 - registers - - - RCC_CTC - RCC and CTC global Interrupts - 4 - - - - CTL0 - desc CTL0 - 0x0 - 32 - read-write - 0x2000 - - - CKOKIE - desc CKOKIE - 0 - 0 - read-write - - - CKWARNIE - desc CKWARNIE - 1 - 1 - read-write - - - ERRIE - desc ERRIE - 2 - 2 - read-write - - - EREFIE - desc EREFIE - 3 - 3 - read-write - - - CNTEN - desc CNTEN - 5 - 5 - read-write - - - AUTOTRIM - desc AUTOTRIM - 6 - 6 - read-write - - - SWREFPUL - desc SWREFPUL - 7 - 7 - write-only - - - TRIMVALUE - desc TRIMVALUE - 13 - 8 - read-write - - - - - CTL1 - desc CTL1 - 0x4 - 32 - read-write - 0x2022BB7F - - - RLVALUE - desc RLVALUE - 15 - 0 - read-write - - - CKLIM - desc CKLIM - 23 - 16 - read-write - - - REFPSC - desc REFPSC - 26 - 24 - read-write - - - REFSEL - desc REFSEL - 29 - 28 - read-write - - - REFPOL - desc REFPOL - 31 - 31 - read-write - - - - - SR - desc SR - 0x8 - 32 - read-only - 0x0 - - - CKOKIF - desc CKOKIF - 0 - 0 - read-only - - - CKWARNIF - desc CKWARNIF - 1 - 1 - read-only - - - ERRIF - desc ERRIF - 2 - 2 - read-only - - - EREFIF - desc EREFIF - 3 - 3 - read-only - - - CKERR - desc CKERR - 8 - 8 - read-only - - - REFMISS - desc REFMISS - 9 - 9 - read-only - - - TRIMERR - desc TRIMERR - 10 - 10 - read-only - - - REFDIR - desc REFDIR - 15 - 15 - read-only - - - REFCAP - desc REFCAP - 31 - 16 - read-only - - - - - INTC - desc INTC - 0xC - 32 - write-only - 0x0 - - - CKOKIC - desc CKOKIC - 0 - 0 - write-only - - - CKWARNIC - desc CKWARNIC - 1 - 1 - write-only - - - ERRIC - desc ERRIC - 2 - 2 - write-only - - - EREFIC - desc EREFIC - 3 - 3 - write-only - - - - - - - DAC - desc DAC - DAC - 0x40007400 - - 0x0 - 0x400 - registers - - - TIM6_LPTIM1_DAC - TIM6, LPTIM1, DAC global Interrupts - 17 - - - - CR - desc CR - 0x0 - 32 - read-write - 0x0 - - - EN1 - desc EN1 - 0 - 0 - read-write - - - BOFF1 - desc BOFF1 - 1 - 1 - read-write - - - TEN1 - desc TEN1 - 2 - 2 - read-write - - - TSEL1 - desc TSEL1 - 5 - 3 - read-write - - - WAVE1 - desc WAVE1 - 7 - 6 - read-write - - - MAMP1 - desc MAMP1 - 11 - 8 - read-write - - - DMAEN1 - desc DMAEN1 - 12 - 12 - read-write - - - DMAUDRIE1 - desc DMAUDRIE1 - 13 - 13 - read-write - - - DAC1CEN - desc DAC1CEN - 14 - 14 - read-write - - - EN2 - desc EN2 - 16 - 16 - read-write - - - BOFF2 - desc BOFF2 - 17 - 17 - read-write - - - TEN2 - desc TEN2 - 18 - 18 - read-write - - - TSEL2 - desc TSEL2 - 21 - 19 - read-write - - - WAVE2 - desc WAVE2 - 23 - 22 - read-write - - - MAMP2 - desc MAMP2 - 27 - 24 - read-write - - - DMAEN2 - desc DMAEN2 - 28 - 28 - read-write - - - DMAUDRIE2 - desc DMAUDRIE2 - 29 - 29 - read-write - - - DAC2CEN - desc DAC2CEN - 30 - 30 - read-write - - - - - SWTRIGR - desc SWTRIGR - 0x4 - 32 - write-only - 0x0 - - - SWTRIG1 - desc SWTRIG1 - 0 - 0 - write-only - - - SWTRIG2 - desc SWTRIG2 - 1 - 1 - write-only - - - - - DHR12R1 - desc DHR12R1 - 0x8 - 32 - read-write - 0x0 - - - DACC1DHR - desc DACC1DHR - 11 - 0 - read-write - - - - - DHR12L1 - desc DHR12L1 - 0xC - 32 - read-write - 0x0 - - - DACC1DHR - desc DACC1DHR - 14 - 3 - read-write - - - - - DHR8R1 - desc DHR8R1 - 0x10 - 32 - read-write - 0x0 - - - DACC1DHR - desc DACC1DHR - 7 - 0 - read-write - - - - - DHR12R2 - desc DHR12R2 - 0x14 - 32 - read-write - 0x0 - - - DACC2DHR - desc DACC2DHR - 11 - 0 - read-write - - - - - DHR12L2 - desc DHR12L2 - 0x18 - 32 - read-write - 0x0 - - - DACC2DHR - desc DACC2DHR - 15 - 4 - read-write - - - - - DHR8R2 - desc DHR8R2 - 0x1C - 32 - read-write - 0x0 - - - DACC2DHR - desc DACC2DHR - 7 - 0 - read-write - - - - - DHR12RD - desc DHR12RD - 0x20 - 32 - read-write - 0x0 - - - DACC1DHR - desc DACC1DHR - 11 - 0 - read-write - - - DACC2DHR - desc DACC2DHR - 27 - 16 - read-write - - - - - DHR12LD - desc DHR12LD - 0x24 - 32 - read-write - 0x0 - - - DACC1DHR - desc DACC1DHR - 15 - 4 - read-write - - - DACC2DHR - desc DACC2DHR - 31 - 20 - read-write - - - - - DHR8RD - desc DHR8RD - 0x28 - 32 - read-write - 0x0 - - - DACC1DHR - desc DACC1DHR - 7 - 0 - read-write - - - DACC2DHR - desc DACC2DHR - 15 - 8 - read-write - - - - - DOR1 - desc DOR1 - 0x2C - 32 - read-only - 0x0 - - - DACC1DOR - desc DACC1DOR - 11 - 0 - read-only - - - - - DOR2 - desc DOR2 - 0x30 - 32 - read-only - 0x0 - - - DACC2DOR - desc DACC2DOR - 11 - 0 - read-only - - - - - SR - desc SR - 0x34 - 32 - read-only - 0x0 - - - DMAUDR1 - desc DMAUDR1 - 13 - 13 - read-only - - - DMAUDR2 - desc DMAUDR2 - 29 - 29 - read-only - - - - - - - DBGMCU - Debug support - DBGMCU - 0x40015800 - - 0x0 - 0x400 - registers - - - - IDCODE - IDCODE - MCU Device ID Code Register - 0x0 - 0x20 - read-only - 0x0 - - - DBG_ID - DBG_ID - 0 - 16 - - - - - CR - CR - - Debug MCU Configuration - Register - - 0x4 - 0x20 - read-write - 0x0 - - - DBG_SLEEP - Debug Sleep Mode - 0 - 1 - - - DBG_STOP - Debug Stop Mode - 1 - 1 - - - - - APB_FZ1 - APB_FZ1 - APB Freeze Register1 - 0x8 - 0x20 - read-write - 0x0 - - - DBG_TIMER2_STOP - - Debug Timer 2 stopped when Core is - halted - - 0 - 1 - - - DBG_TIMER3_STOP - - Debug Timer 3 stopped when Core is - halted - - 1 - 1 - - - DBG_TIMER6_STOP - - Debug Timer 6 stopped when Core is - halted - - 4 - 1 - - - DBG_TIMER7_STOP - - Debug Timer 7 stopped when Core is - halted - - 5 - 1 - - - DBG_RTC_STOP - - Debug RTC stopped when Core is - halted - - 10 - 1 - - - DBG_WWDG_STOP - - Debug Window Wachdog stopped when Core - is halted - - 11 - 1 - - - DBG_IWDG_STOP - - Debug Independent Wachdog stopped when - Core is halted - - 12 - 1 - - - DBG_CAN_STOP - DBG_CAN_STOP - 19 - 1 - - - DBG_I2C1_SMBUS_TIMEOUT - DBG_I2C1_SMBUS_TIMEOUT - 21 - 1 - - - DBG_I2C2_SMBUS_TIMEOUT - DBG_I2C2_SMBUS_TIMEOUT - 22 - 1 - read-only - - - DBG_LPTIM_STOP - - Debug LPTIM stopped when Core is - halted - - 31 - 1 - - - - - APB_FZ2 - APB_FZ2 - APB Freeze Register2 - 0xC - 0x20 - read-write - 0x0 - - - DBG_TIMER1_STOP - - Debug Timer 1 stopped when Core is - halted - - 11 - 1 - - - DBG_TIMER14_STOP - - Debug Timer 14 stopped when Core is - halted - - 15 - 1 - - - DBG_TIMER15_STOP - - Debug Timer 15 stopped when Core is - halted - - 16 - 1 - - - DBG_TIMER16_STOP - - Debug Timer 16 stopped when Core is - halted - - 17 - 1 - - - DBG_TIMER17_STOP - - Debug Timer 17 stopped when Core is - halted - - 18 - 1 - - - - - - - DV - Divider - DV - 0x40023800 - - 0x0 - 0x400 - registers - - - - DEND - DEND - Dividend - 0x0 - 0x20 - read-write - 0x0 - - - DEND - Dividend - 0 - 32 - - - - - SOR - SOR - Divisor - 0x4 - 0x20 - read-write - 0x0 - - - SOR - Divisor - 0 - 32 - - - - - QUOT - QUOT - Quotient - 0x8 - 0x20 - read-only - 0x0 - - - QUOT - Quotient - 0 - 32 - - - - - REMA - REMA - Remainder - 0xC - 0x20 - read-only - 0x0 - - - REMA - Remainder - 0 - 32 - read-only - - - - - SIGN - SIGN - des SIGN - 0x10 - 0x20 - read-write - 0x0 - - - DIV_SIGN - des DIV_SIGN - 0 - 1 - - - - - STAT - STAT - des SIGN - 0x14 - 0x20 - read-write - 0x0 - - - DIV_END - des DIV_END - 0 - 1 - - - DIV_ZERO - des DIV_ZERO - 1 - 1 - - - - - - - DMA - Direct memory access - DMA - 0x40020000 - - 0x0 - 0x400 - registers - - - DMA1_Channel1 - DMA1 Channel 1 Interrupt - 9 - - - DMA1_Channel2_3 - DMA1 Channel 2 and Channel 3 Interrupt - 10 - - - DMA1_Channel4_5_6_7 - DMA1 Channel 4, 5, 6, 7 Interrupts - 11 - - - - ISR - desc ISR - 0x0 - 32 - read-only - 0x0 - - - GIF1 - desc GIF1 - 0 - 0 - read-only - - - TCIF1 - desc TCIF1 - 1 - 1 - read-only - - - HTIF1 - desc HTIF1 - 2 - 2 - read-only - - - TEIF1 - desc TEIF1 - 3 - 3 - read-only - - - GIF2 - desc GIF2 - 4 - 4 - read-only - - - TCIF2 - desc TCIF2 - 5 - 5 - read-only - - - HTIF2 - desc HTIF2 - 6 - 6 - read-only - - - TEIF2 - desc TEIF2 - 7 - 7 - read-only - - - GIF3 - desc GIF3 - 8 - 8 - read-only - - - TCIF3 - desc TCIF3 - 9 - 9 - read-only - - - HTIF3 - desc HTIF3 - 10 - 10 - read-only - - - TEIF3 - desc TEIF3 - 11 - 11 - read-only - - - GIF4 - desc GIF4 - 12 - 12 - read-only - - - TCIF4 - desc TCIF4 - 13 - 13 - read-only - - - HTIF4 - desc HTIF4 - 14 - 14 - read-only - - - TEIF4 - desc TEIF4 - 15 - 15 - read-only - - - GIF5 - desc GIF5 - 16 - 16 - read-only - - - TCIF5 - desc TCIF5 - 17 - 17 - read-only - - - HTIF5 - desc HTIF5 - 18 - 18 - read-only - - - TEIF5 - desc TEIF5 - 19 - 19 - read-only - - - GIF6 - desc GIF6 - 20 - 20 - read-only - - - TCIF6 - desc TCIF6 - 21 - 21 - read-only - - - HTIF6 - desc HTIF6 - 22 - 22 - read-only - - - TEIF6 - desc TEIF6 - 23 - 23 - read-only - - - GIF7 - desc GIF7 - 24 - 24 - read-only - - - TCIF7 - desc TCIF7 - 25 - 25 - read-only - - - HTIF7 - desc HTIF7 - 26 - 26 - read-only - - - TEIF7 - desc TEIF7 - 27 - 27 - read-only - - - - - IFCR - desc IFCR - 0x4 - 32 - write-only - 0x0 - - - CGIF1 - desc CGIF1 - 0 - 0 - write-only - - - CTCIF1 - desc CTCIF1 - 1 - 1 - write-only - - - CHTIF1 - desc CHTIF1 - 2 - 2 - write-only - - - CTEIF1 - desc CTEIF1 - 3 - 3 - write-only - - - CGIF2 - desc CGIF2 - 4 - 4 - write-only - - - CTCIF2 - desc CTCIF2 - 5 - 5 - write-only - - - CHTIF2 - desc CHTIF2 - 6 - 6 - write-only - - - CTEIF2 - desc CTEIF2 - 7 - 7 - write-only - - - CGIF3 - desc CGIF3 - 8 - 8 - write-only - - - CTCIF3 - desc CTCIF3 - 9 - 9 - write-only - - - CHTIF3 - desc CHTIF3 - 10 - 10 - write-only - - - CTEIF3 - desc CTEIF3 - 11 - 11 - write-only - - - CGIF4 - desc CGIF4 - 12 - 12 - write-only - - - CTCIF4 - desc CTCIF4 - 13 - 13 - write-only - - - CHTIF4 - desc CHTIF4 - 14 - 14 - write-only - - - CTEIF4 - desc CTEIF4 - 15 - 15 - write-only - - - CGIF5 - desc CGIF5 - 16 - 16 - write-only - - - CTCIF5 - desc CTCIF5 - 17 - 17 - write-only - - - CHTIF5 - desc CHTIF5 - 18 - 18 - write-only - - - CTEIF5 - desc CTEIF5 - 19 - 19 - write-only - - - CGIF6 - desc CGIF6 - 20 - 20 - write-only - - - CTCIF6 - desc CTCIF6 - 21 - 21 - write-only - - - CHTIF6 - desc CHTIF6 - 22 - 22 - write-only - - - CTEIF6 - desc CTEIF6 - 23 - 23 - write-only - - - CGIF7 - desc CGIF7 - 24 - 24 - write-only - - - CTCIF7 - desc CTCIF7 - 25 - 25 - write-only - - - CHTIF7 - desc CHTIF7 - 26 - 26 - write-only - - - CTEIF7 - desc CTEIF7 - 27 - 27 - write-only - - - - - CCR1 - desc CCR1 - 0x8 - 32 - read-write - 0x0 - - - EN - desc EN - 0 - 0 - read-write - - - TCIE - desc TCIE - 1 - 1 - read-write - - - HTIE - desc HTIE - 2 - 2 - read-write - - - TEIE - desc TEIE - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CIRC - desc CIRC - 5 - 5 - read-write - - - PINC - desc PINC - 6 - 6 - read-write - - - MINC - desc MINC - 7 - 7 - read-write - - - PSIZE - desc PSIZE - 9 - 8 - read-write - - - MSIZE - desc MSIZE - 11 - 10 - read-write - - - PL - desc PL - 13 - 12 - read-write - - - MEM2MEM - desc MEM2MEM - 14 - 14 - read-write - - - - - CNDTR1 - desc CNDTR1 - 0xC - 32 - read-write - 0x0 - - - NDT - desc NDT - 15 - 0 - read-write - - - - - CPAR1 - desc CPAR1 - 0x10 - 32 - read-write - 0x0 - - - PA - desc PA - 31 - 0 - read-write - - - - - CMAR1 - desc CMAR1 - 0x14 - 32 - read-write - 0x0 - - - MA - desc MA - 31 - 0 - read-write - - - - - CCR2 - desc CCR2 - 0x1C - 32 - read-write - 0x0 - - - EN - desc EN - 0 - 0 - read-write - - - TCIE - desc TCIE - 1 - 1 - read-write - - - HTIE - desc HTIE - 2 - 2 - read-write - - - TEIE - desc TEIE - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CIRC - desc CIRC - 5 - 5 - read-write - - - PINC - desc PINC - 6 - 6 - read-write - - - MINC - desc MINC - 7 - 7 - read-write - - - PSIZE - desc PSIZE - 9 - 8 - read-write - - - MSIZE - desc MSIZE - 11 - 10 - read-write - - - PL - desc PL - 13 - 12 - read-write - - - MEM2MEM - desc MEM2MEM - 14 - 14 - read-write - - - - - CNDTR2 - desc CNDTR2 - 0x20 - 32 - read-write - 0x0 - - - NDT - desc NDT - 15 - 0 - read-write - - - - - CPAR2 - desc CPAR2 - 0x24 - 32 - read-write - 0x0 - - - PA - desc PA - 31 - 0 - read-write - - - - - CMAR2 - desc CMAR2 - 0x28 - 32 - read-write - 0x0 - - - MA - desc MA - 31 - 0 - read-write - - - - - CCR3 - desc CCR3 - 0x30 - 32 - read-write - 0x0 - - - EN - desc EN - 0 - 0 - read-write - - - TCIE - desc TCIE - 1 - 1 - read-write - - - HTIE - desc HTIE - 2 - 2 - read-write - - - TEIE - desc TEIE - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CIRC - desc CIRC - 5 - 5 - read-write - - - PINC - desc PINC - 6 - 6 - read-write - - - MINC - desc MINC - 7 - 7 - read-write - - - PSIZE - desc PSIZE - 9 - 8 - read-write - - - MSIZE - desc MSIZE - 11 - 10 - read-write - - - PL - desc PL - 13 - 12 - read-write - - - MEM2MEM - desc MEM2MEM - 14 - 14 - read-write - - - - - CNDTR3 - desc CNDTR3 - 0x34 - 32 - read-write - 0x0 - - - NDT - desc NDT - 15 - 0 - read-write - - - - - CPAR3 - desc CPAR3 - 0x38 - 32 - read-write - 0x0 - - - PA - desc PA - 31 - 0 - read-write - - - - - CMAR3 - desc CMAR3 - 0x3C - 32 - read-write - 0x0 - - - MA - desc MA - 31 - 0 - read-write - - - - - CCR4 - desc CCR4 - 0x44 - 32 - read-write - 0x0 - - - EN - desc EN - 0 - 0 - read-write - - - TCIE - desc TCIE - 1 - 1 - read-write - - - HTIE - desc HTIE - 2 - 2 - read-write - - - TEIE - desc TEIE - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CIRC - desc CIRC - 5 - 5 - read-write - - - PINC - desc PINC - 6 - 6 - read-write - - - MINC - desc MINC - 7 - 7 - read-write - - - PSIZE - desc PSIZE - 9 - 8 - read-write - - - MSIZE - desc MSIZE - 11 - 10 - read-write - - - PL - desc PL - 13 - 12 - read-write - - - MEM2MEM - desc MEM2MEM - 14 - 14 - read-write - - - - - CNDTR4 - desc CNDTR4 - 0x48 - 32 - read-write - 0x0 - - - NDT - desc NDT - 15 - 0 - read-write - - - - - CPAR4 - desc CPAR4 - 0x4C - 32 - read-write - 0x0 - - - PA - desc PA - 31 - 0 - read-write - - - - - CMAR4 - desc CMAR4 - 0x50 - 32 - read-write - 0x0 - - - MA - desc MA - 31 - 0 - read-write - - - - - CCR5 - desc CCR5 - 0x58 - 32 - read-write - 0x0 - - - EN - desc EN - 0 - 0 - read-write - - - TCIE - desc TCIE - 1 - 1 - read-write - - - HTIE - desc HTIE - 2 - 2 - read-write - - - TEIE - desc TEIE - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CIRC - desc CIRC - 5 - 5 - read-write - - - PINC - desc PINC - 6 - 6 - read-write - - - MINC - desc MINC - 7 - 7 - read-write - - - PSIZE - desc PSIZE - 9 - 8 - read-write - - - MSIZE - desc MSIZE - 11 - 10 - read-write - - - PL - desc PL - 13 - 12 - read-write - - - MEM2MEM - desc MEM2MEM - 14 - 14 - read-write - - - - - CNDTR5 - desc CNDTR5 - 0x5C - 32 - read-write - 0x0 - - - NDT - desc NDT - 15 - 0 - read-write - - - - - CPAR5 - desc CPAR5 - 0x60 - 32 - read-write - 0x0 - - - PA - desc PA - 31 - 0 - read-write - - - - - CMAR5 - desc CMAR5 - 0x64 - 32 - read-write - 0x0 - - - MA - desc MA - 31 - 0 - read-write - - - - - CCR6 - desc CCR6 - 0x6C - 32 - read-write - 0x0 - - - EN - desc EN - 0 - 0 - read-write - - - TCIE - desc TCIE - 1 - 1 - read-write - - - HTIE - desc HTIE - 2 - 2 - read-write - - - TEIE - desc TEIE - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CIRC - desc CIRC - 5 - 5 - read-write - - - PINC - desc PINC - 6 - 6 - read-write - - - MINC - desc MINC - 7 - 7 - read-write - - - PSIZE - desc PSIZE - 9 - 8 - read-write - - - MSIZE - desc MSIZE - 11 - 10 - read-write - - - PL - desc PL - 13 - 12 - read-write - - - MEM2MEM - desc MEM2MEM - 14 - 14 - read-write - - - - - CNDTR6 - desc CNDTR6 - 0x70 - 32 - read-write - 0x0 - - - NDT - desc NDT - 15 - 0 - read-write - - - - - CPAR6 - desc CPAR6 - 0x74 - 32 - read-write - 0x0 - - - PA - desc PA - 31 - 0 - read-write - - - - - CMAR6 - desc CMAR6 - 0x78 - 32 - read-write - 0x0 - - - MA - desc MA - 31 - 0 - read-write - - - - - CCR7 - desc CCR7 - 0x80 - 32 - read-write - 0x0 - - - EN - desc EN - 0 - 0 - read-write - - - TCIE - desc TCIE - 1 - 1 - read-write - - - HTIE - desc HTIE - 2 - 2 - read-write - - - TEIE - desc TEIE - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CIRC - desc CIRC - 5 - 5 - read-write - - - PINC - desc PINC - 6 - 6 - read-write - - - MINC - desc MINC - 7 - 7 - read-write - - - PSIZE - desc PSIZE - 9 - 8 - read-write - - - MSIZE - desc MSIZE - 11 - 10 - read-write - - - PL - desc PL - 13 - 12 - read-write - - - MEM2MEM - desc MEM2MEM - 14 - 14 - read-write - - - - - CNDTR7 - desc CNDTR7 - 0x84 - 32 - read-write - 0x0 - - - NDT - desc NDT - 15 - 0 - read-write - - - - - CPAR7 - desc CPAR7 - 0x88 - 32 - read-write - 0x0 - - - PA - desc PA - 31 - 0 - read-write - - - - - CMAR7 - desc CMAR7 - 0x8C - 32 - read-write - 0x0 - - - MA - desc MA - 31 - 0 - read-write - - - - - - - EXTI - - External interrupt/event - controller - - EXTI - 0x40021800 - - 0x0 - 0x400 - registers - - - PVD - PVD Interrupt through EXTI Lines 16 - 1 - - - EXTI0_1 - EXTI Line 0 and 1 Interrupt - 5 - - - EXTI2_3 - EXTI Line 2 and 3 Interrupt - 6 - - - EXTI4_15 - EXTI Line 4 to 15 Interrupt - 7 - - - - RTSR - RTSR - - EXTI rising trigger selection - register - - 0x0 - 0x20 - read-write - 0x00000000 - - - RT20 - - Rising trigger event configuration bit - of Configurable Event input - - 20 - 1 - - - RT19 - - Rising trigger event configuration bit - of Configurable Event input - - 19 - 1 - - - RT18 - - Rising trigger event configuration bit - of Configurable Event input - - 18 - 1 - - - RT17 - - Rising trigger event configuration bit - of Configurable Event input - - 17 - 1 - - - RT16 - - Rising trigger event configuration bit - of Configurable Event input - - 16 - 1 - - - RT15 - - Rising trigger event configuration bit - of Configurable Event input - - 15 - 1 - - - RT14 - - Rising trigger event configuration bit - of Configurable Event input - - 14 - 1 - - - RT13 - - Rising trigger event configuration bit - of Configurable Event input - - 13 - 1 - - - RT12 - - Rising trigger event configuration bit - of Configurable Event input - - 12 - 1 - - - RT11 - - Rising trigger event configuration bit - of Configurable Event input - - 11 - 1 - - - RT10 - - Rising trigger event configuration bit - of Configurable Event input - - 10 - 1 - - - RT9 - - Rising trigger event configuration bit - of Configurable Event input - - 9 - 1 - - - RT8 - - Rising trigger event configuration bit - of Configurable Event input - - 8 - 1 - - - RT7 - - Rising trigger event configuration bit - of Configurable Event input - - 7 - 1 - - - RT6 - - Rising trigger event configuration bit - of Configurable Event input - - 6 - 1 - - - RT5 - - Rising trigger event configuration bit - of Configurable Event input - - 5 - 1 - - - RT4 - - Rising trigger event configuration bit - of Configurable Event input - - 4 - 1 - - - RT3 - - Rising trigger event configuration bit - of Configurable Event input - - 3 - 1 - - - RT2 - - Rising trigger event configuration bit - of Configurable Event input - - 2 - 1 - - - RT1 - - Rising trigger event configuration bit - of Configurable Event input - - 1 - 1 - - - RT0 - - Rising trigger event configuration bit - of Configurable Event input - - 0 - 1 - - - - - FTSR - FTSR - - EXTI falling trigger selection - register - - 0x4 - 0x20 - read-write - 0x00000000 - - - FT20 - - Falling trigger event configuration bit - of Configurable Event input - - 20 - 1 - - - FT19 - - Falling trigger event configuration bit - of Configurable Event input - - 19 - 1 - - - FT18 - - Falling trigger event configuration bit - of Configurable Event input - - 18 - 1 - - - FT17 - - Falling trigger event configuration bit - of Configurable Event input - - 17 - 1 - - - FT16 - - Falling trigger event configuration bit - of Configurable Event input - - 16 - 1 - - - FT15 - - Falling trigger event configuration bit - of Configurable Event input - - 15 - 1 - - - FT14 - - Falling trigger event configuration bit - of Configurable Event input - - 14 - 1 - - - FT13 - - Falling trigger event configuration bit - of Configurable Event input - - 13 - 1 - - - FT12 - - Falling trigger event configuration bit - of Configurable Event input - - 12 - 1 - - - FT11 - - Falling trigger event configuration bit - of Configurable Event input - - 11 - 1 - - - FT10 - - Falling trigger event configuration bit - of Configurable Event input - - 10 - 1 - - - FT9 - - Falling trigger event configuration bit - of Configurable Event input - - 9 - 1 - - - FT8 - - Falling trigger event configuration bit - of Configurable Event input - - 8 - 1 - - - FT7 - - Falling trigger event configuration bit - of Configurable Event input - - 7 - 1 - - - FT6 - - Falling trigger event configuration bit - of Configurable Event input - - 6 - 1 - - - FT5 - - Falling trigger event configuration bit - of Configurable Event input - - 5 - 1 - - - FT4 - - Falling trigger event configuration bit - of Configurable Event input - - 4 - 1 - - - FT3 - - Falling trigger event configuration bit - of Configurable Event input - - 3 - 1 - - - FT2 - - Falling trigger event configuration bit - of Configurable Event input - - 2 - 1 - - - FT1 - - Falling trigger event configuration bit - of Configurable Event input - - 1 - 1 - - - FT0 - - Falling trigger event configuration bit - of Configurable Event input - - 0 - 1 - - - - - SWIER - SWIER - - EXTI software interrupt event - register - - 0x8 - 0x20 - read-write - 0x00000000 - - - SWI20 - - Rising trigger event configuration bit - of Configurable Event input - - 20 - 1 - - - SWI19 - - Rising trigger event configuration bit - of Configurable Event input - - 19 - 1 - - - SWI18 - - Rising trigger event configuration bit - of Configurable Event input - - 18 - 1 - - - SWI17 - - Rising trigger event configuration bit - of Configurable Event input - - 17 - 1 - - - SWI16 - - Rising trigger event configuration bit - of Configurable Event input - - 16 - 1 - - - SWI15 - - Rising trigger event configuration bit - of Configurable Event input - - 15 - 1 - - - SWI14 - - Rising trigger event configuration bit - of Configurable Event input - - 14 - 1 - - - SWI13 - - Rising trigger event configuration bit - of Configurable Event input - - 13 - 1 - - - SWI12 - - Rising trigger event configuration bit - of Configurable Event input - - 12 - 1 - - - SWI11 - - Rising trigger event configuration bit - of Configurable Event input - - 11 - 1 - - - SWI10 - - Rising trigger event configuration bit - of Configurable Event input - - 10 - 1 - - - SWI9 - - Rising trigger event configuration bit - of Configurable Event input - - 9 - 1 - - - SWI8 - - Rising trigger event configuration bit - of Configurable Event input - - 8 - 1 - - - SWI7 - - Rising trigger event configuration bit - of Configurable Event input - - 7 - 1 - - - SWI6 - - Rising trigger event configuration bit - of Configurable Event input - - 6 - 1 - - - SWI5 - - Rising trigger event configuration bit - of Configurable Event input - - 5 - 1 - - - SWI4 - - Rising trigger event configuration bit - of Configurable Event input - - 4 - 1 - - - SWI3 - - Rising trigger event configuration bit - of Configurable Event input - - 3 - 1 - - - SWI2 - - Rising trigger event configuration bit - of Configurable Event input - - 2 - 1 - - - SWI1 - - Rising trigger event configuration bit - of Configurable Event input - - 1 - 1 - - - SWI0 - - Rising trigger event configuration bit - of Configurable Event input - - 0 - 1 - - - - - PR - PR - - EXTI pending - register - - 0xC - 0x20 - read-write - 0x00000000 - - - PR20 - - configurable event inputs x rising edge - Pending bit. - - 20 - 1 - - - PR19 - - configurable event inputs x rising edge - Pending bit. - - 19 - 1 - - - PR18 - - configurable event inputs x rising edge - Pending bit. - - 18 - 1 - - - PR17 - - configurable event inputs x rising edge - Pending bit. - - 17 - 1 - - - PR16 - - configurable event inputs x rising edge - Pending bit. - - 16 - 1 - - - PR15 - - configurable event inputs x rising edge - Pending bit. - - 15 - 1 - - - PR14 - - configurable event inputs x rising edge - Pending bit. - - 14 - 1 - - - PR13 - - configurable event inputs x rising edge - Pending bit - - 13 - 1 - - - PR12 - - configurable event inputs x rising edge - Pending bit. - - 12 - 1 - - - PR11 - - configurable event inputs x rising edge - Pending bit. - - 11 - 1 - - - PR10 - - configurable event inputs x rising edge - Pending bit. - - 10 - 1 - - - PR9 - - configurable event inputs x rising edge - Pending bit. - - 9 - 1 - - - PR8 - - configurable event inputs x rising edge - Pending bit. - - 8 - 1 - - - PR7 - - configurable event inputs x rising edge - Pending bit. - - 7 - 1 - - - PR6 - - configurable event inputs x rising edge - Pending bit. - - 6 - 1 - - - PR5 - - configurable event inputs x rising edge - Pending bit. - - 5 - 1 - - - PR4 - - configurable event inputs x rising edge - Pending bit. - - 4 - 1 - - - PR3 - - configurable event inputs x rising edge - Pending bit. - - 3 - 1 - - - PR2 - - configurable event inputs x rising edge - Pending bit. - - 2 - 1 - - - PR1 - - configurable event inputs x rising edge - Pending bit. - - 1 - 1 - - - PR0 - - configurable event inputs x rising edge - Pending bit. - - 0 - 1 - - - - - EXTICR1 - EXTICR1 - - EXTI external interrupt selection - register - - 0x60 - 0x20 - read-write - 0x00000000 - - - EXTI3 - GPIO port selection - 24 - 2 - - - EXTI2 - GPIO port selection - 16 - 2 - - - EXTI1 - GPIO port selection - 8 - 2 - - - EXTI0 - GPIO port selection - 0 - 2 - - - - - EXTICR2 - EXTICR2 - - EXTI external interrupt selection - register - - 0x64 - 0x20 - read-write - 0x00000000 - - - EXTI7 - GPIO port selection - 24 - 2 - - - EXTI6 - GPIO port selection - 16 - 2 - - - EXTI5 - GPIO port selection - 8 - 2 - - - EXTI4 - GPIO port selection - 0 - 2 - - - - - EXTICR3 - EXTICR3 - - EXTI external interrupt selection - register - - 0x68 - 0x20 - read-write - 0x00000000 - - - EXTI11 - GPIO port selection - 24 - 2 - - - EXTI10 - GPIO port selection - 16 - 2 - - - EXTI9 - GPIO port selection - 8 - 2 - - - EXTI8 - GPIO port selection - 0 - 2 - - - - - EXTICR4 - EXTICR4 - - EXTI external interrupt selection - register - - 0x6C - 0x20 - read-write - 0x00000000 - - - EXTI15 - GPIO port selection - 24 - 2 - - - EXTI14 - GPIO port selection - 16 - 2 - - - EXTI13 - GPIO port selection - 8 - 2 - - - EXTI12 - GPIO port selection - 0 - 2 - - - - - IMR - IMR - - EXTI CPU wakeup with interrupt mask - register - - 0x80 - 0x20 - read-write - 0xFFF80000 - - - IM29 - - CPU wakeup with interrupt mask on event - input - - 29 - 1 - - - IM20 - - CPU wakeup with interrupt mask on event - input - - 20 - 1 - - - IM19 - - CPU wakeup with interrupt mask on event - input - - 19 - 1 - - - IM18 - - CPU wakeup with interrupt mask on event - input - - 18 - 1 - - - IM17 - - CPU wakeup with interrupt mask on event - input - - 17 - 1 - - - IM16 - - CPU wakeup with interrupt mask on event - input - - 16 - 1 - - - IM15 - - CPU wakeup with interrupt mask on event - input - - 15 - 1 - - - IM14 - - CPU wakeup with interrupt mask on event - input - - 14 - 1 - - - IM13 - - CPU wakeup with interrupt mask on event - input - - 13 - 1 - - - IM12 - - CPU wakeup with interrupt mask on event - input - - 12 - 1 - - - IM11 - - CPU wakeup with interrupt mask on event - input - - 11 - 1 - - - IM10 - - CPU wakeup with interrupt mask on event - input - - 10 - 1 - - - IM9 - - CPU wakeup with interrupt mask on event - input - - 9 - 1 - - - IM8 - - CPU wakeup with interrupt mask on event - input - - 8 - 1 - - - IM7 - - CPU wakeup with interrupt mask on event - input - - 7 - 1 - - - IM6 - - CPU wakeup with interrupt mask on event - input - - 6 - 1 - - - IM5 - - CPU wakeup with interrupt mask on event - input - - 5 - 1 - - - IM4 - - CPU wakeup with interrupt mask on event - input - - 4 - 1 - - - IM3 - - CPU wakeup with interrupt mask on event - input - - 3 - 1 - - - IM2 - - CPU wakeup with interrupt mask on event - input - - 2 - 1 - - - IM1 - - CPU wakeup with interrupt mask on event - input - - 1 - 1 - - - IM0 - - CPU wakeup with interrupt mask on event - input - - 0 - 1 - - - - - EMR - EMR - - EXTI CPU wakeup with event mask - register - - 0x84 - 0x20 - read-write - 0x00000000 - - - EM29 - - CPU wakeup with event mask on event - input - - 29 - 1 - - - EM20 - - CPU wakeup with event mask on event - input - - 20 - 1 - - - EM19 - - CPU wakeup with event mask on event - input - - 19 - 1 - - - EM18 - - CPU wakeup with event mask on event - input - - 18 - 1 - - - EM17 - - CPU wakeup with event mask on event - input - - 17 - 1 - - - EM16 - - CPU wakeup with event mask on event - input - - 16 - 1 - - - EM15 - - CPU wakeup with event mask on event - input - - 15 - 1 - - - EM14 - - CPU wakeup with event mask on event - input - - 14 - 1 - - - EM13 - - CPU wakeup with event mask on event - input - - 13 - 1 - - - EM12 - - CPU wakeup with event mask on event - input - - 12 - 1 - - - EM11 - - CPU wakeup with event mask on event - input - - 11 - 1 - - - EM10 - - CPU wakeup with event mask on event - input - - 10 - 1 - - - EM9 - - CPU wakeup with event mask on event - input - - 9 - 1 - - - EM8 - - CPU wakeup with event mask on event - input - - 8 - 1 - - - EM7 - - CPU wakeup with event mask on event - input - - 7 - 1 - - - EM6 - - CPU wakeup with event mask on event - input - - 6 - 1 - - - EM5 - - CPU wakeup with event mask on event - input - - 5 - 1 - - - EM4 - - CPU wakeup with event mask on event - input - - 4 - 1 - - - EM3 - - CPU wakeup with event mask on event - input - - 3 - 1 - - - EM2 - - CPU wakeup with event mask on event - input - - 2 - 1 - - - EM1 - - CPU wakeup with event mask on event - input - - 1 - 1 - - - EM0 - - CPU wakeup with event mask on event - input - - 0 - 1 - - - - - - - FLASH - desc FLASH - FLASH - 0x40022000 - - 0x0 - 0x400 - registers - - - FLASH - FLASH global Interrupt - 3 - - - - ACR - desc ACR - 0x0 - 32 - read-write - 0x500 - - - LATENCY - desc LATENCY - 1 - 0 - read-write - - - PRFTEN - desc PRFTEN - 8 - 8 - read-write - - - ICEN - desc ICEN - 9 - 9 - read-write - - - DCEN - desc DCEN - 10 - 10 - read-write - - - - - KEYR - desc KEYR - 0x8 - 32 - write-only - 0x0 - - - KEY - desc KEY - 31 - 0 - write-only - - - - - OPTKEYR - desc OPTKEYR - 0xC - 32 - write-only - 0x0 - - - OPTKEY - desc OPTKEY - 31 - 0 - write-only - - - - - SR - desc SR - 0x10 - 32 - read-write - 0x0 - - - EOP - desc EOP - 0 - 0 - read-write - - - WRPERR - desc WRPERR - 4 - 4 - read-write - - - OPTVERR - desc OPTVERR - 15 - 15 - read-write - - - BSY - desc BSY - 16 - 16 - read-only - - - - - CR - desc CR - 0x14 - 32 - read-write - 0x0 - - - PG - desc PG - 0 - 0 - read-write - - - PER - desc PER - 1 - 1 - read-write - - - MER - desc MER - 2 - 2 - read-write - - - SER - desc SER - 11 - 11 - read-write - - - OPTSTRT - desc OPTSTRT - 17 - 17 - read-write - - - PGSTRT - desc PGSTRT - 19 - 19 - read-write - - - EOPIE - desc EOPIE - 24 - 24 - read-write - - - ERRIE - desc ERRIE - 25 - 25 - read-write - - - OBL_LAUNCH - desc OBL_LAUNCH - 27 - 27 - read-write - - - OPTLOCK - desc OPTLOCK - 30 - 30 - read-write - - - LOCK - desc LOCK - 31 - 31 - read-write - - - - - OPTR - desc OPTR - 0x20 - 32 - read-only - 0x0 - - - RDP - desc RDP - 7 - 0 - read-only - - - IWDG_SW - desc IWDG_SW - 11 - 11 - read-only - - - WWDG_SW - desc WWDG_SW - 12 - 12 - read-only - - - NRST_MODE - desc NRST_MODE - 13 - 13 - read-only - - - NBOOT1 - desc nBOOT1 - 14 - 14 - read-only - - - IWDG_STOP - desc IWDG_STOP - 15 - 15 - read-only - - - - - SDKR - desc SDKR - 0x24 - 32 - read-only - 0x0 - - - SDK_STRT - desc SDK_STRT - 4 - 0 - read-only - - - BOR_EN - desc BOR_EN - 5 - 5 - read-only - - - SDK_END - desc SDK_END - 12 - 8 - read-only - - - BOR_LEV - desc BOR_LEV - 15 - 13 - read-only - - - - - PCK_EN - desc PCK_EN - 0x28 - 32 - read-only - 0x0 - - - USB_CLK_EN - desc USB_CLK_EN - 0 - 0 - read-only - - - CAN_CLK_EN - desc CAN_CLK_EN - 1 - 1 - read-only - - - TIM2_CLK_EN - desc TIM2_CLK_EN - 2 - 2 - read-only - - - TIM3_CLK_EN - desc TIM3_CLK_EN - 3 - 3 - read-only - - - TIM7_CLK_EN - desc TIM7_CLK_EN - 4 - 4 - read-only - - - I2C2_CLK_EN - desc I2C2_CLK_EN - 5 - 5 - read-only - - - USART3_CLK_EN - desc USART3_CLK_EN - 6 - 6 - read-only - - - USART4_CLK_EN - desc USART4_CLK_EN - 7 - 7 - read-only - - - LCD_CLK_EN - desc LCD_CLK_EN - 8 - 8 - read-only - - - TIM14_CLK_EN - desc TIM14_CLK_EN - 9 - 9 - read-only - - - TIM15_CLK_EN - desc TIM15_CLK_EN - 10 - 10 - read-only - - - TIM17_CLK_EN - desc TIM17_CLK_EN - 11 - 11 - read-only - - - - - WRPR - desc WRPR - 0x2C - 32 - read-write - 0x0 - - - WRP - desc WRP - 15 - 0 - read-write - - - - - STCR - desc STCR - 0x90 - 32 - read-write - 0x00006400 - - - SLEEP_EN - desc SLEEP_EN - 0 - 0 - read-write - - - SLEEP_TIME - desc SLEEP_TIME - 15 - 8 - read-write - - - - - TS0 - desc TS0 - 0x100 - 32 - read-write - 0xB4 - - - TS0 - desc TS0 - 7 - 0 - read-write - - - - - TS1 - desc TS1 - 0x104 - 32 - read-write - 0x1B0 - - - TS1 - desc TS1 - 8 - 0 - read-write - - - - - TS2P - desc TS2P - 0x108 - 32 - read-write - 0xB4 - - - TS2P - desc TS2P - 7 - 0 - read-write - - - - - TPS3 - desc TPS3 - 0x10C - 32 - read-write - 0x6C0 - - - TPS3 - desc TPS3 - 10 - 0 - read-write - - - - - TS3 - desc TS3 - 0x110 - 32 - read-write - 0xB4 - - - TS3 - desc TS3 - 7 - 0 - read-write - - - - - PERTPE - desc PERTPE - 0x114 - 32 - read-write - 0xEA60 - - - PERTPE - desc PERTPE - 16 - 0 - read-write - - - - - SMERTPE - desc SMERTPE - 0x118 - 32 - read-write - 0xFD20 - - - SMERTPE - desc SMERTPE - 16 - 0 - read-write - - - - - PRGTPE - desc PRGTPE - 0x11C - 32 - read-write - 0x8CA0 - - - PRGTPE - desc PRGTPE - 15 - 0 - read-write - - - - - PRETPE - desc PRETPE - 0x120 - 32 - read-write - 0x12C0 - - - PRETPE - desc PRETPE - 13 - 0 - read-write - - - - - TRMLSR - desc TRMLSR - 0x290 - 32 - read-only - 0x0 - - - PMU_TRIM0_ERR - desc PMU_TRIM0_ERR - 0 - 0 - read-only - - - PMU_TRIM1_ERR - desc PMU_TRIM1_ERR - 1 - 1 - read-only - - - HSI_TRIM_ERR - desc HSI_TRIM_ERR - 2 - 2 - read-only - - - LSI_TRIM_ERR - desc LSI_TRIM_ERR - 3 - 3 - read-only - - - FLASH_TRIM0_ERR - desc FLASH_TRIM0_ERR - 4 - 4 - read-only - - - FLASH_TRIM1_ERR - desc FLASH_TRIM1_ERR - 5 - 5 - read-only - - - FLASH_TRIM2_ERR - desc FLASH_TRIM2_ERR - 6 - 6 - read-only - - - FLASH_TRIM3_ERR - desc FLASH_TRIM3_ERR - 7 - 7 - read-only - - - FLASH_TRIM4_ERR - desc FLASH_TRIM4_ERR - 8 - 8 - read-only - - - FLASH_TRIM5_ERR - desc FLASH_TRIM5_ERR - 9 - 9 - read-only - - - TS_TRIM_ERR - desc TS_TRIM_ERR - 10 - 10 - read-only - - - CHIP_CFG_ERR - desc CHIP_CFG_ERR - 11 - 11 - read-only - - - CHKRD0_PASS - desc CHKRD0_PASS - 16 - 16 - read-only - - - CHKRD1_PASS - desc CHKRD1_PASS - 17 - 17 - read-only - - - CHKRD2_PASS - desc CHKRD2_PASS - 18 - 18 - read-only - - - CHKRD3_PASS - desc CHKRD3_PASS - 19 - 19 - read-only - - - - - TRMDR0 - desc TRMDR0 - 0x294 - 32 - read-only - 0x0 - - - BIAS_CR - desc BIAS_CR - 3 - 0 - read-only - - - TRIM_MR - desc TRIM_MR - 8 - 4 - read-only - - - TRIM_VREF - desc TRIM_VREF - 13 - 9 - read-only - - - TRIM_POR - desc TRIM_POR - 19 - 16 - read-only - - - TRIM_BG - desc TRIM_BG - 27 - 20 - read-only - - - - - TRMDR1 - desc TRMDR1 - 0x298 - 32 - read-only - 0x0 - - - LSI_TRIM - desc LSI_TRIM - 8 - 0 - read-only - - - HSI_TRIM - desc HSI_TRIM - 28 - 16 - read-only - - - HSI_FS - desc HSI_FS - 31 - 29 - read-only - - - - - TRMDR2 - desc TRMDR2 - 0x29C - 32 - read-only - 0x0 - - - FLASH_OP - desc FLASH_OP - 31 - 0 - read-only - - - - - TRMDR3 - desc TRMDR3 - 0x2A0 - 32 - read-only - 0x0 - - - FLASH_OP - desc FLASH_OP - 31 - 0 - read-only - - - - - TRMDR4 - desc TRMDR4 - 0x2A4 - 32 - read-only - 0x0 - - - FLASH_ERASE_VPOS - desc FLASH_ERASE_VPOS - 4 - 0 - read-only - - - FLASH_ERASE_VNEG - desc FLASH_ERASE_VNEG - 9 - 5 - read-only - - - FLASH_PROG_VPOS - desc FLASH_PROG_VPOS - 20 - 16 - read-only - - - FLASH_PROG_VNEG - desc FLASH_PROG_VNEG - 25 - 21 - read-only - - - - - TRMDR5 - desc TRMDR5 - 0x2A8 - 32 - read-only - 0x0 - - - FLASH_SIZE - desc FLASH_SIZE - 2 - 0 - read-only - - - SRAM_SIZE - desc SRAM_SIZE - 6 - 4 - read-only - - - TS_TRIM - desc TS_TRIM - 11 - 8 - read-only - - - - - TRMDR6 - desc TRMDR6 - 0x2AC - 32 - read-only - 0x0 - - - OPA0_TRIM - desc OPA0_TRIM - 3 - 0 - read-only - - - OPA1_TRIM - desc OPA1_TRIM - 7 - 4 - read-only - - - OPA2_TRIM - desc OPA2_TRIM - 11 - 8 - read-only - - - OPA3_TRIM - desc OPA3_TRIM - 15 - 12 - read-only - - - OPA4_TRIM - desc OPA4_TRIM - 19 - 16 - read-only - - - LCD_TRIM - desc LCD_TRIM - 27 - 20 - read-only - - - - - TRMDR7 - desc TRMDR7 - 0x2B0 - 32 - read-only - 0x0 - - - TS_DATA_0_TRIM - desc TS_DATA_0_TRIM - 11 - 0 - read-only - - - TS_DATA_1_TRIM - desc TS_DATA_1_TRIM - 23 - 12 - read-only - - - - - TRMDR8 - desc TRMDR8 - 0x2B4 - 32 - read-only - 0x0 - - - DAC_0_TRIM - desc DAC_0_TRIM - 11 - 0 - read-only - - - DAC_1_TRIM - desc DAC_1_TRIM - 23 - 12 - read-only - - - VREF_BUF_TRIM - desc VREF_BUF_TRIM - 28 - 24 - read-only - - - - - - - GPIOA - General-purpose I/Os - GPIO - 0x50000000 - - 0x0 - 0x400 - registers - - - - MODER - MODER - GPIO port mode register - 0x0 - 0x20 - read-write - 0xEBFFFFFF - - - MODE15 - - Port x configuration bits (y=0-15) - - 30 - 2 - - - MODE14 - - Port x configuration bits (y=0-15) - - 28 - 2 - - - MODE13 - - Port x configuration bits (y=0-15) - - 26 - 2 - - - MODE12 - - Port x configuration bits (y=0-15) - - 24 - 2 - - - MODE11 - - Port x configuration bits (y=0-15) - - 22 - 2 - - - MODE10 - - Port x configuration bits (y=0-15) - - 20 - 2 - - - MODE9 - - Port x configuration bits (y=0-15) - - 18 - 2 - - - MODE8 - - Port x configuration bits (y=0-15) - - 16 - 2 - - - MODE7 - - Port x configuration bits (y=0-15) - - 14 - 2 - - - MODE6 - - Port x configuration bits (y=0-15) - - 12 - 2 - - - MODE5 - - Port x configuration bits (y=0-15) - - 10 - 2 - - - MODE4 - - Port x configuration bits (y=0-15) - - 8 - 2 - - - MODE3 - - Port x configuration bits (y=0-15) - - 6 - 2 - - - MODE2 - - Port x configuration bits (y=0-15) - - 4 - 2 - - - MODE1 - - Port x configuration bits (y=0-15) - - 2 - 2 - - - MODE0 - - Port x configuration bits (y=0-15) - - 0 - 2 - - - - - OTYPER - OTYPER - GPIO port output type register - 0x4 - 0x20 - read-write - 0x00000000 - - - OT15 - - Port x configuration bits (y=0-15) - - 15 - 1 - - - OT14 - - Port x configuration bits (y=0-15) - - 14 - 1 - - - OT13 - - Port x configuration bits (y=0-15) - - 13 - 1 - - - OT12 - - Port x configuration bits (y=0-15) - - 12 - 1 - - - OT11 - - Port x configuration bits (y=0-15) - - 11 - 1 - - - OT10 - - Port x configuration bits (y=0-15) - - 10 - 1 - - - OT9 - - Port x configuration bits (y=0-15) - - 9 - 1 - - - OT8 - - Port x configuration bits (y=0-15) - - 8 - 1 - - - OT7 - - Port x configuration bits (y=0-15) - - 7 - 1 - - - OT6 - - Port x configuration bits (y=0-15) - - 6 - 1 - - - OT5 - - Port x configuration bits (y=0-15) - - 5 - 1 - - - OT4 - - Port x configuration bits (y=0-15) - - 4 - 1 - - - OT3 - - Port x configuration bits (y=0-15) - - 3 - 1 - - - OT2 - - Port x configuration bits (y=0-15) - - 2 - 1 - - - OT1 - - Port x configuration bits (y=0-15) - - 1 - 1 - - - OT0 - - Port x configuration bits (y=0-15) - - 0 - 1 - - - - - OSPEEDR - OSPEEDR - - GPIO port output speed - register - - 0x8 - 0x20 - read-write - 0x0C000000 - - - OSPEED15 - - Port x configuration bits (y=0-15) - - 30 - 2 - - - OSPEED14 - - Port x configuration bits (y=0-15) - - 28 - 2 - - - OSPEED13 - - Port x configuration bits (y=0-15) - - 26 - 2 - - - OSPEED12 - - Port x configuration bits (y=0-15) - - 24 - 2 - - - OSPEED11 - - Port x configuration bits (y=0-15) - - 22 - 2 - - - OSPEED10 - - Port x configuration bits (y=0-15) - - 20 - 2 - - - OSPEED9 - - Port x configuration bits (y=0-15) - - 18 - 2 - - - OSPEED8 - - Port x configuration bits (y=0-15) - - 16 - 2 - - - OSPEED7 - - Port x configuration bits (y=0-15) - - 14 - 2 - - - OSPEED6 - - Port x configuration bits (y=0-15) - - 12 - 2 - - - OSPEED5 - - Port x configuration bits (y=0-15) - - 10 - 2 - - - OSPEED4 - - Port x configuration bits (y=0-15) - - 8 - 2 - - - OSPEED3 - - Port x configuration bits (y=0-15) - - 6 - 2 - - - OSPEED2 - - Port x configuration bits (y=0-15) - - 4 - 2 - - - OSPEED1 - - Port x configuration bits (y=0-15) - - 2 - 2 - - - OSPEED0 - - Port x configuration bits (y=0-15) - - 0 - 2 - - - - - PUPDR - PUPDR - - GPIO port pull-up/pull-down - register - - 0xC - 0x20 - read-write - 0x24000000 - - - PUPD15 - - Port x configuration bits (y=0-15) - - 30 - 2 - - - PUPD14 - - Port x configuration bits (y=0-15) - - 28 - 2 - - - PUPD13 - - Port x configuration bits (y=0-15) - - 26 - 2 - - - PUPD12 - - Port x configuration bits (y=0-15) - - 24 - 2 - - - PUPD11 - - Port x configuration bits (y=0-15) - - 22 - 2 - - - PUPD10 - - Port x configuration bits (y=0-15) - - 20 - 2 - - - PUPD9 - - Port x configuration bits (y=0-15) - - 18 - 2 - - - PUPD8 - - Port x configuration bits (y=0-15) - - 16 - 2 - - - PUPD7 - - Port x configuration bits (y=0-15) - - 14 - 2 - - - PUPD6 - - Port x configuration bits (y=0-15) - - 12 - 2 - - - PUPD5 - - Port x configuration bits (y=0-15) - - 10 - 2 - - - PUPD4 - - Port x configuration bits (y=0-15) - - 8 - 2 - - - PUPD3 - - Port x configuration bits (y=0-15) - - 6 - 2 - - - PUPD2 - - Port x configuration bits (y=0-15) - - 4 - 2 - - - PUPD1 - - Port x configuration bits (y=0-15) - - 2 - 2 - - - PUPD0 - - Port x configuration bits (y=0-15) - - 0 - 2 - - - - - IDR - IDR - GPIO port input data register - 0x10 - 0x20 - read-only - 0x00000000 - - - ID15 - - Port input data (y=0-15) - - 15 - 1 - - - ID14 - - Port input data (y=0-15) - - 14 - 1 - - - ID13 - - Port input data (y=0-15) - - 13 - 1 - - - ID12 - - Port input data (y=0-15) - - 12 - 1 - - - ID11 - - Port input data (y=0-15) - - 11 - 1 - - - ID10 - - Port input data (y=0-15) - - 10 - 1 - - - ID9 - - Port input data (y=0-15) - - 9 - 1 - - - ID8 - - Port input data (y=0-15) - - 8 - 1 - - - ID7 - - Port input data (y=0-15) - - 7 - 1 - - - ID6 - - Port input data (y=0-15) - - 6 - 1 - - - ID5 - - Port input data (y=0-15) - - 5 - 1 - - - ID4 - - Port input data (y=0-15) - - 4 - 1 - - - ID3 - - Port input data (y=0-15) - - 3 - 1 - - - ID2 - - Port input data (y=0-15) - - 2 - 1 - - - ID1 - - Port input data (y=0-15) - - 1 - 1 - - - ID0 - - Port input data (y=0-15) - - 0 - 1 - - - - - ODR - ODR - GPIO port output data register - 0x14 - 0x20 - read-write - 0x00000000 - - - OD15 - - Port output data (y=0-15) - - 15 - 1 - - - OD14 - - Port output data (y=0-15) - - 14 - 1 - - - OD13 - - Port output data (y=0-15) - - 13 - 1 - - - OD12 - - Port output data (y=0-15) - - 12 - 1 - - - OD11 - - Port output data (y=0-15) - - 11 - 1 - - - OD10 - - Port output data (y=0-15) - - 10 - 1 - - - OD9 - - Port output data (y=0-15) - - 9 - 1 - - - OD8 - - Port output data (y=0-15) - - 8 - 1 - - - OD7 - - Port output data (y=0-15) - - 7 - 1 - - - OD6 - - Port output data (y=0-15) - - 6 - 1 - - - OD5 - - Port output data (y=0-15) - - 5 - 1 - - - OD4 - - Port output data (y=0-15) - - 4 - 1 - - - OD3 - - Port output data (y=0-15) - - 3 - 1 - - - OD2 - - Port output data (y=0-15) - - 2 - 1 - - - OD1 - - Port output data (y=0-15) - - 1 - 1 - - - OD0 - - Port output data (y=0-15) - - 0 - 1 - - - - - BSRR - BSRR - - GPIO port bit set/reset - register - - 0x18 - 0x20 - write-only - 0x00000000 - - - BR15 - - Port x reset bit y (y=0-15) - - 31 - 1 - - - BR14 - - Port x reset bit y (y=0-15) - - 30 - 1 - - - BR13 - - Port x reset bit y (y=0-15) - - 29 - 1 - - - BR12 - - Port x reset bit y (y=0-15) - - 28 - 1 - - - BR11 - - Port x reset bit y (y=0-15) - - 27 - 1 - - - BR10 - - Port x reset bit y (y=0-15) - - 26 - 1 - - - BR9 - - Port x reset bit y (y=0-15) - - 25 - 1 - - - BR8 - - Port x reset bit y (y=0-15) - - 24 - 1 - - - BR7 - - Port x reset bit y (y=0-15) - - 23 - 1 - - - BR6 - - Port x reset bit y (y=0-15) - - 22 - 1 - - - BR5 - - Port x reset bit y (y=0-15) - - 21 - 1 - - - BR4 - - Port x reset bit y (y=0-15) - - 20 - 1 - - - BR3 - - Port x reset bit y (y=0-15) - - 19 - 1 - - - BR2 - - Port x reset bit y (y=0-15) - - 18 - 1 - - - BR1 - - Port x reset bit y (y=0-15) - - 17 - 1 - - - BR0 - - Port x set bit y (y=0-15) - - 16 - 1 - - - BS15 - - Port x set bit y (y=0-15) - - 15 - 1 - - - BS14 - - Port x set bit y (y=0-15) - - 14 - 1 - - - BS13 - - Port x set bit y (y=0-15) - - 13 - 1 - - - BS12 - - Port x set bit y (y=0-15) - - 12 - 1 - - - BS11 - - Port x set bit y (y=0-15) - - 11 - 1 - - - BS10 - - Port x set bit y (y=0-15) - - 10 - 1 - - - BS9 - - Port x set bit y (y=0-15) - - 9 - 1 - - - BS8 - - Port x set bit y (y=0-15) - - 8 - 1 - - - BS7 - - Port x set bit y (y=0-15) - - 7 - 1 - - - BS6 - - Port x set bit y (y=0-15) - - 6 - 1 - - - BS5 - - Port x set bit y (y=0-15) - - 5 - 1 - - - BS4 - - Port x set bit y (y=0-15) - - 4 - 1 - - - BS3 - - Port x set bit y (y=0-15) - - 3 - 1 - - - BS2 - - Port x set bit y (y=0-15) - - 2 - 1 - - - BS1 - - Port x set bit y (y=0-15) - - 1 - 1 - - - BS0 - - Port x set bit y (y=0-15) - - 0 - 1 - - - - - LCKR - LCKR - - GPIO port configuration lock - register - - 0x1C - 0x20 - read-write - 0x00000000 - - - LCKK - - Port x lock (LCKK) - - 16 - 1 - - - LCK15 - - Port x lock bit y (y=0-15) - - 15 - 1 - - - LCK14 - - Port x lock bit y (y=0-15) - - 14 - 1 - - - LCK13 - - Port x lock bit y (y=0-15) - - 13 - 1 - - - LCK12 - - Port x lock bit y (y=0-15) - - 12 - 1 - - - LCK11 - - Port x lock bit y (y=0-15) - - 11 - 1 - - - LCK10 - - Port x lock bit y (y=0-15) - - 10 - 1 - - - LCK9 - - Port x lock bit y (y=0-15) - - 9 - 1 - - - LCK8 - - Port x lock bit y (y=0-15) - - 8 - 1 - - - LCK7 - - Port x lock bit y (y=0-15) - - 7 - 1 - - - LCK6 - - Port x lock bit y (y=0-15) - - 6 - 1 - - - LCK5 - - Port x lock bit y (y=0-15) - - 5 - 1 - - - LCK4 - - Port x lock bit y (y=0-15) - - 4 - 1 - - - LCK3 - - Port x lock bit y (y=0-15) - - 3 - 1 - - - LCK2 - - Port x lock bit y (y=0-15) - - 2 - 1 - - - LCK1 - - Port x lock bit y (y=0-15) - - 1 - 1 - - - LCK0 - - Port x lock bit y (y=0-15) - - 0 - 1 - - - - - AFRL - AFRL - - GPIO alternate function low - register - - 0x20 - 0x20 - read-write - 0x00000000 - - - AFSEL7 - - Alternate function selection for port x bit y (y=0-7) - - 28 - 4 - - - AFSEL6 - - Alternate function selection for port x bit y (y=0-7) - - 24 - 4 - - - AFSEL5 - - Alternate function selection for port x bit y (y=0-7) - - 20 - 4 - - - AFSEL4 - - Alternate function selection for port x bit y (y=0-7) - - 16 - 4 - - - AFSEL3 - - Alternate function selection for port x bit y (y=0-7) - - 12 - 4 - - - AFSEL2 - - Alternate function selection for port x bit y (y=0-7) - - 8 - 4 - - - AFSEL1 - - Alternate function selection for port x bit y (y=0-7) - - 4 - 4 - - - AFSEL0 - - Alternate function selection for port x bit y (y=0-7) - - 0 - 4 - - - - - AFRH - AFRH - - GPIO alternate function high - register - - 0x24 - 0x20 - read-write - 0x00000000 - - - AFSEL15 - - Alternate function selection for port x bit y (y=8-15) - - 28 - 4 - - - AFSEL14 - - Alternate function selection for port x bit y (y=8-15) - - 24 - 4 - - - AFSEL13 - - Alternate function selection for port x bit y (y=8-15) - - 20 - 4 - - - AFSEL12 - - Alternate function selection for port x bit y (y=8-15) - - 16 - 4 - - - AFSEL11 - - Alternate function selection for port x bit y (y=8-15) - - 12 - 4 - - - AFSEL10 - - Alternate function selection for port x bit y (y=8-15) - - 8 - 4 - - - AFSEL9 - - Alternate function selection for port x bit y (y=8-15) - - 4 - 4 - - - AFSEL8 - - Alternate function selection for port x bit y (y=8-15) - - 0 - 4 - - - - - BRR - BRR - port bit reset register - 0x28 - 0x20 - write-only - 0x00000000 - - - BR15 - Port Reset bit - 15 - 1 - - - BR14 - Port Reset bit - 14 - 1 - - - BR13 - Port Reset bit - 13 - 1 - - - BR12 - Port Reset bit - 12 - 1 - - - BR11 - Port Reset bit - 11 - 1 - - - BR10 - Port Reset bit - 10 - 1 - - - BR9 - Port Reset bit - 9 - 1 - - - BR8 - Port Reset bit - 8 - 1 - - - BR7 - Port Reset bit - 7 - 1 - - - BR6 - Port Reset bit - 6 - 1 - - - BR5 - Port Reset bit - 5 - 1 - - - BR4 - Port Reset bit - 4 - 1 - - - BR3 - Port Reset bit - 3 - 1 - - - BR2 - Port Reset bit - 2 - 1 - - - BR1 - Port Reset bit - 1 - 1 - - - BR0 - Port Reset bit - 0 - 1 - - - - - - - GPIOB - General-purpose I/Os - GPIO - 0x50000400 - - 0x0 - 0x400 - registers - - - - GPIOC - General-purpose I/Os - GPIO - 0x50000800 - - 0x0 - 0x400 - registers - - - - GPIOF - General-purpose I/Os - GPIO - 0x50001400 - - 0x0 - 0x400 - registers - - - - I2C1 - Inter integrated circuit - I2C - 0x40005400 - - 0x0 - 0x400 - registers - - - I2C1 - I2C1 global Interrupt - 23 - - - - CR1 - desc CR1 - 0x0 - 32 - read-write - 0x0 - - - PE - desc PE - 0 - 0 - read-write - - - SMBUS - desc SMBUS - 1 - 1 - read-write - - - SMBTYPE - desc SMBTYPE - 3 - 3 - read-write - - - ENARP - desc ENARP - 4 - 4 - read-write - - - ENPEC - desc ENPEC - 5 - 5 - read-write - - - ENGC - desc ENGC - 6 - 6 - read-write - - - NOSTRETCH - desc NOSTRETCH - 7 - 7 - read-write - - - START - desc START - 8 - 8 - read-write - - - STOP - desc STOP - 9 - 9 - read-write - - - ACK - desc ACK - 10 - 10 - read-write - - - POS - desc POS - 11 - 11 - read-write - - - PEC - desc PEC - 12 - 12 - read-write - - - ALERT - desc ALERT - 13 - 13 - read-write - - - SWRST - desc SWRST - 15 - 15 - read-write - - - - - CR2 - desc CR2 - 0x4 - 32 - read-write - 0x0 - - - FREQ - desc FREQ - 5 - 0 - read-write - - - ITERREN - desc ITERREN - 8 - 8 - read-write - - - ITEVTEN - desc ITEVTEN - 9 - 9 - read-write - - - ITBUFEN - desc ITBUFEN - 10 - 10 - read-write - - - DMAEN - desc DMAEN - 11 - 11 - read-write - - - LAST - desc LAST - 12 - 12 - read-write - - - - - OAR1 - desc OAR1 - 0x8 - 32 - read-write - 0x0 - - - ADD0 - desc ADD0 - 0 - 0 - read-write - - - ADD1_7 - desc ADD1_7 - 7 - 1 - read-write - - - ADD8_9 - desc ADD8_9 - 9 - 8 - read-write - - - ADDMODE - desc ADDMODE - 15 - 15 - read-write - - - - - OAR2 - desc OAR2 - 0xC - 32 - read-write - 0x0 - - - ENDUAL - desc ENDUAL - 0 - 0 - read-write - - - ADD2 - desc ADD2 - 7 - 1 - read-write - - - - - DR - desc DR - 0x10 - 32 - read-write - 0x0 - - - DR - desc DR - 7 - 0 - read-write - - - - - SR1 - desc SR1 - 0x14 - 32 - read-write - 0x0 - - - SB - desc SB - 0 - 0 - read-only - - - ADDR - desc ADDR - 1 - 1 - read-only - - - BTF - desc BTF - 2 - 2 - read-only - - - ADD10 - desc ADD10 - 3 - 3 - read-only - - - STOPF - desc STOPF - 4 - 4 - read-only - - - RXNE - desc RXNE - 6 - 6 - read-only - - - TXE - desc TXE - 7 - 7 - read-only - - - BERR - desc BERR - 8 - 8 - read-write - - - ARLO - desc ARLO - 9 - 9 - read-write - - - AF - desc AF - 10 - 10 - read-write - - - OVR - desc OVR - 11 - 11 - read-write - - - PECERR - desc PECERR - 12 - 12 - read-write - - - TIMEOUT - desc TIMEOUT - 14 - 14 - read-write - - - SMBALERT - desc SMBALERT - 15 - 15 - read-write - - - - - SR2 - desc SR2 - 0x18 - 32 - read-only - 0x0 - - - MSL - desc MSL - 0 - 0 - read-only - - - BUSY - desc BUSY - 1 - 1 - read-only - - - TRA - desc TRA - 2 - 2 - read-only - - - GENCALL - desc GENCALL - 4 - 4 - read-only - - - SMBDEFAULT - desc SMBDEFAULT - 5 - 5 - read-only - - - SMBHOST - desc SMBHOST - 6 - 6 - read-only - - - DUALF - desc DUALF - 7 - 7 - read-only - - - PEC - desc PEC - 15 - 8 - read-only - - - - - CCR - desc CCR - 0x1C - 32 - read-write - 0x0 - - - CCR - desc CCR - 11 - 0 - read-write - - - DUTY - desc DUTY - 14 - 14 - read-write - - - FS - desc FS - 15 - 15 - read-write - - - - - TRISE - desc TRISE - 0x20 - 32 - read-write - 0x2 - - - - TRISE - desc TRISE - 5 - 0 - read-write - - - - - - - I2C2 - desc I2C - I2C - 0x40005800 - - 0x0 - 0x400 - registers - - - I2C2 - I2C2 Event Interrupt - 24 - - - - IWDG - Independent watchdog - IWDG - 0x40003000 - - 0x0 - 0x400 - registers - - - - KR - KR - Key register (IWDG_KR) - 0x0 - 0x20 - write-only - 0x00000000 - - - KEY - Key value - 0 - 16 - - - - - PR - PR - Prescaler register (IWDG_PR) - 0x4 - 0x20 - read-write - 0x00000000 - - - PR - Prescaler divider - 0 - 3 - - - - - RLR - RLR - Reload register (IWDG_RLR) - 0x8 - 0x20 - read-write - 0x00000FFF - - - RL - - Watchdog counter reload - value - - 0 - 12 - - - - - SR - SR - Status register (IWDG_SR) - 0xC - 0x20 - read-only - 0x00000000 - - - RVU - - Watchdog counter reload value - update - - 1 - 1 - - - PVU - - Watchdog prescaler value - update - - 0 - 1 - - - - - - - LCD - LCD CONTROLLER - LCD - 0x40002400 - - 0x0 - 0x400 - registers - - - LCD - LCD global Interrupt - 8 - - - - CR0 - CR0 - Control register - 0x0 - 0x20 - read-write - 0x0000 - - - EN - EN - 0 - 1 - - - LCDCLK - LCDCLK - 1 - 2 - - - BIAS - BIAS - 6 - 1 - - - DUTY - DUTY - 7 - 3 - - - BSEL - BSEL - 10 - 3 - - - CONTRAST - CONTRAST - 13 - 4 - - - - - CR1 - CR1 - CR1 - 0x4 - 0x20 - read-write - 0x0000 - - - BLINKCNT - BLINKCNT - 0 - 6 - - - BLINKEN - BLINKEN - 6 - 1 - - - MODE - MODE - 8 - 1 - - - IE - IE - 10 - 1 - - - INTF - INTF - 11 - 1 - - - - - INTCLR - INTCLR - INTCLR - 0x8 - 0x20 - read-write - 0x0000 - - - INTF_CLR - INTF_CLR - 10 - 1 - - - - - POEN0 - POEN0 - POEN0 - 0x0C - 0x20 - read-write - 0x0000 - - - S0 - S0 - 0 - 1 - - - S1 - S1 - 1 - 1 - - - S2 - S2 - 2 - 1 - - - S3 - S3 - 3 - 1 - - - S4 - S4 - 4 - 1 - - - S5 - S5 - 5 - 1 - - - S6 - S6 - 6 - 1 - - - S7 - S7 - 7 - 1 - - - S8 - S8 - 8 - 1 - - - S9 - S9 - 9 - 1 - - - S10 - S10 - 10 - 1 - - - S11 - S11 - 11 - 1 - - - S12 - S12 - 12 - 1 - - - S13 - S13 - 13 - 1 - - - S14 - S14 - 14 - 1 - - - S15 - S15 - 15 - 1 - - - S16 - S16 - 16 - 1 - - - S17 - S17 - 17 - 1 - - - S18 - S18 - 18 - 1 - - - S19 - S19 - 19 - 1 - - - S20 - S20 - 20 - 1 - - - S21 - S21 - 21 - 1 - - - S22 - S22 - 22 - 1 - - - S23 - S23 - 23 - 1 - - - S24 - S24 - 24 - 1 - - - S25 - S25 - 25 - 1 - - - S26 - S26 - 26 - 1 - - - S27 - S27 - 27 - 1 - - - S28 - S28 - 28 - 1 - - - S29 - S29 - 29 - 1 - - - S30 - S30 - 30 - 1 - - - S31 - S31 - 31 - 1 - - - - - POEN1 - POEN1 - POEN1 - 0x10 - 0x20 - read-write - 0x0000 - - - S32 - S32 - 0 - 1 - - - S33 - S33 - 1 - 1 - - - S34 - S34 - 2 - 1 - - - S35 - S35 - 3 - 1 - - - S36 - S36 - 4 - 1 - - - S37 - S37 - 5 - 1 - - - S38 - S38 - 6 - 1 - - - S39 - S39 - 7 - 1 - - - C0 - C0 - 8 - 1 - - - C1 - C1 - 9 - 1 - - - C2 - C2 - 10 - 1 - - - C3 - C3 - 11 - 1 - - - MUX - MUX - 12 - 1 - - - - - RAM0 - RAM0 - des RAM0 - 0x14 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 32 - - - - - RAM1 - RAM1 - des RAM1 - 0x18 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 32 - - - - - RAM2 - RAM2 - des RAM2 - 0x1C - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 32 - - - - - RAM3 - RAM3 - des RAM3 - 0x20 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 32 - - - - - RAM4 - RAM4 - des RAM4 - 0x24 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 32 - - - - - RAM5 - RAM5 - des RAM5 - 0x28 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 32 - - - - - RAM6 - RAM6 - des RAM6 - 0x2C - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 32 - - - - - RAM7 - RAM7 - des RAM7 - 0x30 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 32 - - - - - RAM8 - RAM8 - des RAM8 - 0x34 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 8 - - - - - RAM9 - RAM9 - des RAM9 - 0x38 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 8 - - - - - RAM10 - RAM10 - des RAM10 - 0x3C - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 8 - - - - - RAM11 - RAM11 - des RAM11 - 0x40 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 8 - - - - - RAM12 - RAM12 - des RAM12 - 0x44 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 8 - - - - - RAM13 - RAM13 - des RAM13 - 0x48 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 8 - - - - - RAM14 - RAM14 - des RAM14 - 0x4C - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 8 - - - - - RAM15 - RAM15 - des RAM15 - 0x50 - 0x20 - read-write - 0x0000 - - - D - des D - 0 - 8 - - - - - - - LPTIM1 - Low power timer - LPTIM1 - 0x40007C00 - - 0x0 - 0x400 - registers - - - TIM6_LPTIM1_DAC - TIM6, LPTIM1, DAC global Interrupts - 17 - - - - ISR - ISR - Interrupt and Status Register - 0x0 - 0x20 - read-only - 0x00000000 - - - ARRM - Autoreload match - 1 - 1 - - - ARROK - Autoreload match update OK - 4 - 1 - - - - - ICR - ICR - Interrupt Clear Register - 0x4 - 0x20 - write-only - 0x00000000 - - - ARRMCF - - Autoreload match Clear - Flag - - 1 - 1 - - - ARROKCF - - Autoreload match update OK - Clear Flag - - 4 - 1 - - - - - IER - IER - Interrupt Enable Register - 0x8 - 0x20 - read-write - 0x00000000 - - - ARRMIE - - Autoreload matchInterrupt - Enable - - 1 - 1 - - - ARROKIE - - Autoreload match update - OK Interrupt Enable - - 4 - 1 - - - - - CFGR - CFGR - Configuration Register - 0xC - 0x20 - read-write - 0x00000000 - - - PRELOAD - Registers update mode - 22 - 1 - - - PRESC - Clock prescaler - 9 - 3 - - - - - CR - CR - Control Register - 0x10 - 0x20 - read-write - 0x00000000 - - - RSTARE - Reset after read enable - 4 - 1 - - - CNTSTRT - CNTSTRT - 2 - 1 - - - SNGSTRT - LPTIM start in single mode - 1 - 1 - - - ENABLE - LPTIM Enable - 0 - 1 - - - - - ARR - ARR - Autoreload Register - 0x18 - 0x20 - read-write - 0x00000001 - - - ARR - Auto reload value - 0 - 16 - - - - - CNT - CNT - Counter Register - 0x1C - 0x20 - read-only - 0x00000000 - - - CNT - Counter value - 0 - 16 - - - - - - - OPA - des OPA - OPA - 0x40010300 - - 0x0 - 0x400 - registers - - - - CR0 - CR0 - CR0 register - 0x30 - 0x20 - read-write - 0xFFFFFFFF - - - OP1OEN1 - OP1OEN1 - 1 - 1 - - - OP2OEN1 - OP2OEN1 - 6 - 1 - - - OP3OEN1 - OP3OEN1 - 11 - 1 - - - - - CR1 - CR1 - CR1 register - 0x34 - 0x20 - read-write - 0x00000000 - - - EN1 - EN1 - 5 - 1 - - - EN2 - EN2 - 6 - 1 - - - EN3 - EN3 - 7 - 1 - - - - - - - PWR - Power control - PWR - 0x40007000 - - 0x0 - 0x400 - registers - - - - CR1 - CR1 - Power control register 1 - 0x0 - 0x20 - read-write - 0x00030000 - - - HSION_CTRL - HSI open time control - 19 - 1 - - - SRAM_RETV - SRAM retention voltage control - 16 - 3 - - - LPR - Low-power run - 14 - 1 - - - FLS_SLPTIME - Flash wait time after wakeup from the stop mode - 12 - 2 - - - VOS - - Voltage scaling range - selection - - 9 - 2 - - - DBP - - Disable backup domain write - protection - - 8 - 1 - - - BIAS_CR_SEL - MR Bias current selection - 4 - 1 - - - BIAS_CR - MR Bias current - 0 - 3 - - - - - CR2 - CR2 - Power control register 2 - 0x4 - 0x20 - read-write - 0x00000500 - - - FLT_TIME - Digital filter time configuration - 9 - 3 - - - FLTEN - Digital filter enable - 8 - 1 - - - PVDT - - Power voltage detector threshold - selection - - 4 - 3 - - - SRCSEL - - Power voltage detector volatage - selection - - 2 - 1 - - - PVDE - - Power voltage detector - enable - - 0 - 1 - - - - - SR - SR - Power status register - 0x14 - 0x20 - read-only - 0x00000000 - - - PVDO - PVD output - 11 - 1 - - - - - - - RCC - Reset and clock control - RCC - 0x40021000 - - 0x0 - 0x400 - registers - - - RCC_CTC - RCC and CTC global Interrupts - 4 - - - - CR - CR - Clock control register - 0x0 - 0x20 - read-write - 0x00000100 - - - PLLRDY - PLL clock ready flag - 25 - 1 - - - PLLON - PLL enable - 24 - 1 - - - ADC_DIV - ADC Frequency Division - 21 - 2 - - - CSSON - - Clock security system - enable - - 19 - 1 - - - HSEBYP - - HSE crystal oscillator - bypass - - 18 - 1 - - - HSERDY - HSE clock ready flag - 17 - 1 - - - HSEON - HSE clock enable - 16 - 1 - - - HSIDIV - - HSI16 clock division - factor - - 11 - 3 - - - HSIRDY - HSI16 clock ready flag - 10 - 1 - - - HSION - HSI16 clock enable - 8 - 1 - - - - - ICSCR - ICSCR - - Internal clock sources calibration - register - - 0x4 - 0x20 - 0x10000000 - - - LSI_TRIM - LSI clock trimming - 16 - 9 - read-write - - - HSI_FS - HSI frequency selection - 13 - 3 - read-write - - - HSI_TRIM - HSI clock trimming - 0 - 13 - read-write - - - - - CFGR - CFGR - Clock configuration register - 0x8 - 0x20 - 0x00000000 - - - MCOPRE - - Microcontroller clock output - prescaler - - 28 - 3 - read-write - - - MCOSEL - - Microcontroller clock - output - - 24 - 3 - read-write - - - PPRE - APB prescaler - 12 - 3 - read-write - - - HPRE - AHB prescaler - 8 - 4 - read-write - - - SWS - System clock switch status - 3 - 3 - read-only - - - SW - System clock switch - 0 - 3 - read-write - - - - - PLLCFGR - PLLCFGR - PLL configuration register - 0xC - 0x20 - 0x00000000 - - - PLLSRC - PLL clock source selection - 0 - 2 - read-write - - - PLLMUL - PLLMUL - 2 - 2 - read-write - - - - - ECSCR - ECSCR - External clock source control register - 0x10 - 0x20 - 0x00000000 - - - HSE_DRV - HSE_DRV - 0 - 2 - read-write - - - HSE_STARTUP - HSE_STARTUP - 3 - 2 - read-write - - - LSE_DRIVER - LSE clock driver selection - 16 - 2 - read-write - - - LSE_STARTUP - LSE_STARTUP - 20 - 2 - read-write - - - - - CIER - CIER - - Clock interrupt enable - register - - 0x18 - 0x20 - read-write - 0x00000000 - - - PLLRDYIE - PLL ready interrupt enable - 5 - 1 - - - HSERDYIE - HSE ready interrupt enable - 4 - 1 - - - HSIRDYIE - HSI ready interrupt enable - 3 - 1 - - - LSERDYIE - LSE ready interrupt enable - 1 - 1 - - - LSIRDYIE - LSI ready interrupt enable - 0 - 1 - - - - - CIFR - CIFR - Clock interrupt flag register - 0x1C - 0x20 - read-only - 0x00000000 - - - LSECSSF - LSE clock secure system interrupt flag - 9 - 1 - - - CSSF - HSE clock secure system interrupt flag - 8 - 1 - - - PLLRDYF - PLL ready interrupt flag - 5 - 1 - - - HSERDYF - HSE ready interrupt flag - 4 - 1 - - - HSIRDYF - HSI ready interrupt flag - 3 - 1 - - - LSERDYF - LSE ready interrupt flag - 1 - 1 - - - LSIRDYF - LSI ready interrupt flag - 0 - 1 - - - - - CICR - CICR - Clock interrupt clear register - 0x20 - 0x20 - write-only - 0x00000000 - - - LSECSSC - LSE clock secure system interrupt flag clear - 9 - 1 - - - CSSC - clock secure system interrupt flag clear - 8 - 1 - - - PLLRDYC - PLL ready interrupt clear - 5 - 1 - - - HSERDYC - HSE ready interrupt clear - 4 - 1 - - - HSIRDYC - HSI ready interrupt clear - 3 - 1 - - - LSERDYC - LSE ready interrupt clear - 1 - 1 - - - LSIRDYC - LSI ready interrupt clear - 0 - 1 - - - - - IOPRSTR - IOPRSTR - GPIO reset register - 0x24 - 0x20 - read-write - 0x00000000 - - - GPIOFRST - I/O port F reset - 5 - 1 - - - GPIOCRST - I/O port F reset - 2 - 1 - - - GPIOBRST - I/O port B reset - 1 - 1 - - - GPIOARST - I/O port A reset - 0 - 1 - - - - - AHBRSTR - AHBRSTR - AHB peripheral reset register - 0x28 - 0x20 - read-write - 0x00000000 - - - DIVRST - DIV reset - 24 - 1 - - - CRCRST - CRC reset - 12 - 1 - - - DMARST - DMA reset - 0 - 1 - - - - - APBRSTR1 - APBRSTR1 - - APB peripheral reset register - 1 - - 0x2C - 0x20 - read-write - 0x00000000 - - - LPTIMRST - Low Power Timer reset - 31 - 1 - - - OPARST - OPARST - 30 - 1 - - - DACRST - DACRST - 29 - 1 - - - PWRRST - Power interface reset - 28 - 1 - - - CTCRST - CTCRST - 27 - 1 - - - CANRST - CANRST - 25 - 1 - - - USBRST - USB reset - 23 - 1 - - - I2C2RST - I2C2 reset - 22 - 1 - - - I2C1RST - I2C1 reset - 21 - 1 - - - USART4RST - USART4 reset - 19 - 1 - - - USART3RST - USART3 reset - 18 - 1 - - - USART2RST - USART2 reset - 17 - 1 - - - SPI2RST - SPI2 reset - 14 - 1 - - - WWDGRST - WWDG reset - 11 - 1 - - - RTCAPBRST - RTCAPB reset - 10 - 1 - - - TIM7RST - TIM7 timer reset - 5 - 1 - - - TIM6RST - TIM6 timer reset - 4 - 1 - - - TIM3RST - TIM3 timer reset - 1 - 1 - - - TIM2RST - TIM2 timer reset - 0 - 1 - - - - - APBRSTR2 - APBRSTR2 - - APB peripheral reset register - 2 - - 0x30 - 0x20 - read-write - 0x00000000 - - - SYSCFGRST - SYSCFG reset - 0 - 1 - - - ADCRST - ADC reset - 9 - 1 - - - DBGRST - DBG reset - 10 - 1 - - - TIM1RST - TIM1 reset - 11 - 1 - - - SPI1RST - SPI1 reset - 12 - 1 - - - USART1RST - USART1 reset - 14 - 1 - - - TIM14RST - TIM14 reset - 15 - 1 - - - TIM15RST - TIM15 reset - 16 - 1 - - - TIM16RST - TIM16 reset - 17 - 1 - - - TIM17RST - TIM17 reset - 18 - 1 - - - COMP1RST - COMP1 reset - 20 - 1 - - - COMP2RST - COMP2 reset - 21 - 1 - - - COMP3RST - COMP3 reset - 22 - 1 - - - LCDRST - LCD reset - 23 - 1 - - - - - IOPENR - IOPENR - GPIO clock enable register - 0x34 - 0x20 - read-write - 0x00000000 - - - GPIOFEN - I/O port F clock enable - 5 - 1 - - - GPIOCEN - I/O port C clock enable - 2 - 1 - - - GPIOBEN - I/O port B clock enable - 1 - 1 - - - GPIOAEN - I/O port A clock enable - 0 - 1 - - - - - AHBENR - AHBENR - - AHB peripheral clock enable - register - - 0x38 - 0x20 - read-write - 0x00000000 - - - DIVEN - DIVEN - 24 - 1 - - - CRCEN - CRC clock enable - 12 - 1 - - - SRAMEN - - SRAM memory interface clock - enable - - 9 - 1 - - - FLASHEN - - Flash memory interface clock - enable - - 8 - 1 - - - DMAEN - DMA clock enable - 0 - 1 - - - - - APBENR1 - APBENR1 - - APB peripheral clock enable register - 1 - - 0x3C - 0x20 - read-write - 0x00000000 - - - LPTIMEN - LPTIM clock enable - 31 - 1 - - - - OPAEN - OPA clock enable - 30 - 1 - - - DACEN - DAC clock enable - 29 - 1 - - - PWREN - - Power interface clock - enable - - 28 - 1 - - - CTCEN - CTC clock enable - 27 - 1 - - - CANEN - CAN clock enable - 25 - 1 - - - USBEN - USB clock enable - 23 - 1 - - - I2C2EN - I2C2 clock enable - 22 - 1 - - - I2C1EN - I2C1 clock enable - 21 - 1 - - - USART4EN - USART4 clock enable - 19 - 1 - - - USART3EN - USART3 clock enable - 18 - 1 - - - USART2EN - USART2 clock enable - 17 - 1 - - - SPI2EN - SPI2 clock enable - 14 - 1 - - - WWDGEN - WWDG clock enable - 11 - 1 - - - RTCAPBEN - RTC APB clock enable - 10 - 1 - - - TIM7EN - TIM7 timer clock enable - 5 - 1 - - - TIM6EN - TIM6 timer clock enable - 4 - 1 - - - TIM3EN - TIM3 timer clock enable - 1 - 1 - - - TIM2EN - TIM2 timer clock enable - 0 - 1 - - - - - APBENR2 - APBENR2 - - APB peripheral clock enable register - 2 - - 0x40 - 0x20 - read-write - 0x00000000 - - - SYSCFGEN - - SYSCFG, COMP and VREFBUF clock - enable - - 0 - 1 - - - ADCEN - ADCEN clock enable - 9 - 1 - - - DBGEN - DBG clock enable - 10 - 1 - - - TIM1EN - TIM1 clock enable - 11 - 1 - - - SPI1EN - SPI1 clock enable - 12 - 1 - - - USART1EN - USART1 clock enable - 14 - 1 - - - TIM14EN - TIM14 clock enable - 15 - 1 - - - TIM15EN - TIM15 clock enable - 16 - 1 - - - TIM16EN - TIM16 clock enable - 17 - 1 - - - TIM17EN - TIM17 clock enable - 18 - 1 - - - COMP1EN - COMP1 clock enable - 20 - 1 - - - COMP2EN - COMP2 clock enable - 21 - 1 - - - COMP3EN - COMP3 clock enable - 22 - 1 - - - LCDEN - LCD clock enable - 23 - 1 - - - - - CCIPR - CCIPR - - Peripherals independent clock configuration - register - - 0x54 - 0x20 - read-write - 0x00000000 - - - LPTIM1SEL - - LPTIM1 clock source - selection - - 18 - 2 - - - COMP3SEL - - COMP3 clock source - selection - - 10 - 1 - - - COMP2SEL - - COMP2 clock source - selection - - 9 - 1 - - - COMP1SEL - - COMP1 clock source - selection - - 8 - 1 - - - PVDSEL - - PVD detect clock source - selection - - 7 - 1 - - - CANSEL - - CAN detect clock source - selection - - 6 - 1 - - - - - BDCR - BDCR - RTC domain control register - 0x5C - 0x20 - read-write - 0x00000000 - - - LSCOSEL - - Low-speed clock output - selection - - 25 - 1 - - - LSCOEN - - Low-speed clock output (LSCO) - enable - - 24 - 1 - - - BDRST - RTC domain software reset - 16 - 1 - - - RTCEN - RTC clock source enable - 15 - 1 - - - RTCSEL - RTC clock source selection - 8 - 2 - - - LSECSSD - LSE CSS detect - 6 - 1 - - - LSECSSON - LSE CSS enable - 5 - 1 - - - LSEBYP - LSE oscillator bypass - 2 - 1 - - - LSERDY - LSE oscillator ready - 1 - 1 - - - LSEON - LSE oscillator enable - 0 - 1 - - - - - CSR - CSR - Control/status register - 0x60 - 0x20 - read-write - 0x00000000 - - - WWDGRSTF - Window watchdog reset flag - 30 - 1 - - - IWDGRSTF - - Independent window watchdog reset - flag - - 29 - 1 - - - SFTRSTF - Software reset flag - 28 - 1 - - - PWRRSTF - BOR or POR/PDR flag - 27 - 1 - - - PINRSTF - Pin reset flag - 26 - 1 - - - OBLRSTF - - Option byte loader reset - flag - - 25 - 1 - - - RMVF - Remove reset flags - 23 - 1 - - - NRST_FLTDIS - NRST_FLTDIS oscillator ready - 8 - 1 - - - LSIRDY - LSI oscillator ready - 1 - 1 - - - LSION - LSI oscillator enable - 0 - 1 - - - - - - - RTC - desc RTC - RTC - 0x40002800 - - 0x0 - 0x400 - registers - - - RTC - RTC Interrupt through EXTI Lines 19 - 2 - - - - CRH - desc CRH - 0x0 - 32 - read-write - 0x0 - - - SECIE - desc SECIE - 0 - 0 - read-write - - - ALRIE - desc ALRIE - 1 - 1 - read-write - - - OWIE - desc OWIE - 2 - 2 - read-write - - - - - CRL - desc CRL - 0x4 - 32 - read-write - 0x20 - - - - SECF - desc SECF - 0 - 0 - read-write - - - ALRF - desc ALRF - 1 - 1 - read-write - - - OWF - desc OWF - 2 - 2 - read-write - - - RSF - desc RSF - 3 - 3 - read-write - - - CNF - desc CNF - 4 - 4 - read-write - - - RTOFF - desc RTOFF - 5 - 5 - read-only - - - - - PRLH - desc PRLH - 0x8 - 32 - write-only - 0x0 - - - PRL - desc PRL - 3 - 0 - write-only - - - - - PRLL - desc PRLL - 0xC - 32 - write-only - 0x8000 - - - PRL - desc PRL - 15 - 0 - write-only - - - - - DIVH - desc DIVH - 0x10 - 32 - read-only - 0x0 - - - DIV - desc DIV - 3 - 0 - read-only - - - - - DIVL - desc DIVL - 0x14 - 32 - read-only - 0x8000 - - - DIV - desc DIV - 15 - 0 - read-only - - - - - CNTH - desc CNTH - 0x18 - 32 - read-write - 0x0 - - - RTC_CNT - desc RTC_CNT - 15 - 0 - read-write - - - - - CNTL - desc CNTL - 0x1C - 32 - read-write - 0x0 - - - RTC_CNT - desc RTC_CNT - 15 - 0 - read-write - - - - - ALRH - desc ALRH - 0x20 - 32 - read-write - 0xFFFF - - - RTC_ALR - desc RTC_ALR - 15 - 0 - read-write - - - - - ALRL - desc ALRL - 0x24 - 32 - read-write - 0xFFFF - - - RTC_ALR - desc RTC_ALR - 15 - 0 - read-write - - - - - BKP_RTCCR - desc BKP_RTCCR - 0x2C - 32 - read-write - 0x0 - - - CAL - desc CAL - 6 - 0 - read-write - - - CCO - desc CCO - 7 - 7 - read-write - - - ASOE - desc ASOE - 8 - 8 - read-write - - - ASOS - desc ASOS - 9 - 9 - read-write - - - - - - - SPI1 - Serial peripheral interface - SPI - 0x40013000 - - 0x0 - 0x400 - registers - - - SPI1 - SPI1 global Interrupt - 25 - - - - CR1 - desc CR1 - 0x0 - 32 - read-write - 0x0 - - - CPHA - desc CPHA - 0 - 0 - read-write - - - CPOL - desc CPOL - 1 - 1 - read-write - - - MSTR - desc MSTR - 2 - 2 - read-write - - - BR - desc BR - 5 - 3 - read-write - - - SPE - desc SPE - 6 - 6 - read-write - - - LSBFIRST - desc LSBFIRST - 7 - 7 - read-write - - - SSI - desc SSI - 8 - 8 - read-write - - - SSM - desc SSM - 9 - 9 - read-write - - - RXONLY - desc RXONLY - 10 - 10 - read-write - - - DDF - desc DDF - 11 - 11 - read-write - - - CRCNEXT - desc CRCNEXT - 12 - 12 - read-write - - - CRCEN - desc CRCEN - 13 - 13 - read-write - - - BIDIOE - desc BIDIOE - 14 - 14 - read-write - - - BIDIMODE - desc BIDIMODE - 15 - 15 - read-write - - - - - CR2 - desc CR2 - 0x4 - 32 - read-write - 0x0 - - - RXDMAEN - desc RXDMAEN - 0 - 0 - read-write - - - TXDMAEN - desc TXDMAEN - 1 - 1 - read-write - - - SSOE - desc SSOE - 2 - 2 - read-write - - - CLRTXFIFO - desc CLRTXFIFO - 4 - 4 - read-write - - - ERRIE - desc ERRIE - 5 - 5 - read-write - - - RXNEIE - desc RXNEIE - 6 - 6 - read-write - - - TXEIE - desc TXEIE - 7 - 7 - read-write - - - FRXTH - desc FRXTH - 12 - 12 - read-write - - - LDMA_RX - desc LDMA_RX - 13 - 13 - read-write - - - LDMA_TX - desc LDMA_TX - 14 - 14 - read-write - - - - - SR - desc SR - 0x8 - 32 - read-write - 0x2 - - - RXNE - desc RXNE - 0 - 0 - read-only - - - TXE - desc TXE - 1 - 1 - read-only - - - CHSIDE - desc CHSIDE - 2 - 2 - read-only - - - UDR - desc UDR - 3 - 3 - read-only - - - CRCERR - desc CRCERR - 4 - 4 - read-write - - - MODF - desc MODF - 5 - 5 - read-only - - - OVR - desc OVR - 6 - 6 - read-only - - - BSY - desc BSY - 7 - 7 - read-only - - - FRLVL - desc FRLVL - 10 - 9 - read-only - - - FTLVL - desc FTLVL - 12 - 11 - read-only - - - - - DR - desc DR - 0xC - 32 - read-write - 0x0 - - - DR - desc DR - 15 - 0 - read-write - - - - - CRCPR - desc CRCPR - 0x10 - 32 - read-write - 0x7 - - - CRCPOLY - desc CRCPOLY - 15 - 0 - read-write - - - - - RXCRCR - desc RXCRCR - 0x14 - 32 - read-only - 0x0 - - - RXCRC - desc RXCRC - 15 - 0 - read-only - - - - - TXCRCR - desc TXCRCR - 0x18 - 32 - read-only - 0x0 - - - TXCRC - desc TXCRC - 15 - 0 - read-only - - - - - I2SCFGR - desc I2SCFGR - 0x1C - 32 - read-write - 0x0 - - - CHLEN - desc CHLEN - 0 - 0 - read-write - - - DATLEN - desc DATLEN - 2 - 1 - read-write - - - CKPOL - desc CKPOL - 3 - 3 - read-write - - - I2SSTD - desc I2SSTD - 5 - 4 - read-write - - - PCMSYNC - desc PCMSYNC - 7 - 7 - read-write - - - I2SCFG - desc I2SCFG - 9 - 8 - read-write - - - I2SE - desc I2SE - 10 - 10 - read-write - - - I2SMOD - desc I2SMOD - 11 - 11 - read-write - - - - - I2SPR - desc I2SPR - 0x20 - 32 - read-write - 0x2 - - - I2SDIV - desc I2SDIV - 7 - 0 - read-write - - - ODD - desc ODD - 8 - 8 - read-write - - - MCKOE - desc MCKOE - 9 - 9 - read-write - - - - - - - SPI2 - 0x40003800 - - SPI2 - SPI2 global Interrupt - 26 - - - - SYSCFG - desc SYSCFG - SYSCFG - 0x40010000 - - 0x0 - 0x200 - registers - - - - CFGR1 - desc CFGR1 - 0x0 - 32 - read-write - 0xFF0000 - - - MEM_MODE - desc MEM_MODE - 1 - 0 - read-write - - - TIM1_IC1_SRC - desc TIM1_IC1_SRC - 3 - 2 - read-write - - - TIM2_IC4_SRC - desc TIM2_IC4_SRC - 5 - 4 - read-write - - - TIM3_IC1_SRC - desc TIM3_IC1_SRC - 7 - 6 - read-write - - - ETR_SRC_TIM1 - desc ETR_SRC_TIM1 - 10 - 8 - read-write - - - ETR_SRC_TIM2 - desc ETR_SRC_TIM2 - 14 - 12 - read-write - - - ETR_SRC_TIM3 - desc ETR_SRC_TIM3 - 18 - 16 - read-write - - - GPIO_AHB_SEL - desc GPIO_AHB_SEL - 24 - 24 - read-write - - - - - CFGR2 - desc CFGR2 - 0x4 - 32 - read-write - 0x4 - - - LOCKUP_LOCK - desc LOCKUP_LOCK - 0 - 0 - read-write - - - PVD_LOCK - desc PVD_LOCK - 2 - 2 - read-write - - - COMP1_BRK_TIM1 - desc COMP1_BRK_TIM1 - 3 - 3 - read-write - - - COMP2_BRK_TIM1 - desc COMP2_BRK_TIM1 - 4 - 4 - read-write - - - COMP3_BRK_TIM1 - desc COMP3_BRK_TIM1 - 5 - 5 - read-write - - - COMP1_BRK_TIM15 - desc COMP1_BRK_TIM15 - 6 - 6 - read-write - - - COMP2_BRK_TIM15 - desc COMP2_BRK_TIM15 - 7 - 7 - read-write - - - COMP3_BRK_TIM15 - desc COMP3_BRK_TIM15 - 8 - 8 - read-write - - - COMP1_BRK_TIM16 - desc COMP1_BRK_TIM16 - 9 - 9 - read-write - - - COMP2_BRK_TIM16 - desc COMP2_BRK_TIM16 - 10 - 10 - read-write - - - COMP3_BRK_TIM16 - desc COMP3_BRK_TIM16 - 11 - 11 - read-write - - - COMP1_BRK_TIM17 - desc COMP1_BRK_TIM17 - 12 - 12 - read-write - - - COMP2_BRK_TIM17 - desc COMP2_BRK_TIM17 - 13 - 13 - read-write - - - COMP3_BRK_TIM17 - desc COMP3_BRK_TIM17 - 14 - 14 - read-write - - - COMP1_OCREF_CLR_TIM1 - desc COMP1_OCREF_CLR_TIM1 - 15 - 15 - read-write - - - COMP1_OCREF_CLR_TIM2 - desc COMP1_OCREF_CLR_TIM2 - 16 - 16 - read-write - - - COMP1_OCREF_CLR_TIM3 - desc COMP1_OCREF_CLR_TIM3 - 17 - 17 - read-write - - - COMP2_OCREF_CLR_TIM1 - desc COMP2_OCREF_CLR_TIM1 - 18 - 18 - read-write - - - COMP2_OCREF_CLR_TIM2 - desc COMP2_OCREF_CLR_TIM2 - 19 - 19 - read-write - - - COMP2_OCREF_CLR_TIM3 - desc COMP2_OCREF_CLR_TIM3 - 20 - 20 - read-write - - - COMP3_OCREF_CLR_TIM1 - desc COMP3_OCREF_CLR_TIM1 - 21 - 21 - read-write - - - COMP3_OCREF_CLR_TIM2 - desc COMP3_OCREF_CLR_TIM2 - 22 - 22 - read-write - - - COMP3_OCREF_CLR_TIM3 - desc COMP3_OCREF_CLR_TIM3 - 23 - 23 - read-write - - - - - CFGR3 - desc CFGR3 - 0x8 - 32 - read-write - 0x0 - - - DMA1_MAP - desc DMA1_MAP - 5 - 0 - read-write - - - DMA2_MAP - desc DMA2_MAP - 13 - 8 - read-write - - - DMA3_MAP - desc DMA3_MAP - 21 - 16 - read-write - - - DMA4_MAP - desc DMA4_MAP - 29 - 24 - read-write - - - - - CFGR4 - desc CFGR4 - 0xC - 32 - read-write - 0x0 - - - DMA5_MAP - desc DMA5_MAP - 5 - 0 - read-write - - - DMA6_MAP - desc DMA6_MAP - 13 - 8 - read-write - - - DMA7_MAP - desc DMA7_MAP - 21 - 16 - read-write - - - - - PAENS - desc PAENS - 0x10 - 32 - read-write - 0x0 - - - PA_ENS - desc PA_ENS - 15 - 0 - read-write - - - - - PBENS - desc PBENS - 0x14 - 32 - read-write - 0x0 - - - PB_ENS - desc PB_ENS - 15 - 0 - read-write - - - - - PCENS - desc PCENS - 0x18 - 32 - read-write - 0x0 - - - PC_ENS - desc PC_ENS - 15 - 0 - read-write - - - - - PFENS - desc PFENS - 0x1C - 32 - read-write - 0x0 - - - PF_ENS - desc PF_ENS - 15 - 0 - read-write - - - - - EIIC - desc EIIC - 0x20 - 32 - read-write - 0x0 - - - PA_EIIC - desc PA_EIIC - 1 - 0 - read-write - - - PB_EIIC - desc PB_EIIC - 16 - 8 - read-write - - - PF_EIIC - desc PF_EIIC - 25 - 24 - read-write - - - - - - - TIM1 - Advanced timer - TIM - 0x40012C00 - - 0x0 - 0x400 - registers - - - TIM1_BRK_UP_TRG_COM - TIM1 Break, Update, Trigger and Commutation Interrupt - 13 - - - TIM1_CC - TIM1 Capture Compare Interrupt - 14 - - - - CR1 - desc CR1 - 0x0 - 32 - read-write - 0x0 - 0x3FF - - - CEN - desc CEN - 0 - 0 - read-write - - - UDIS - desc UDIS - 1 - 1 - read-write - - - URS - desc URS - 2 - 2 - read-write - - - OPM - desc OPM - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CMS - desc CMS - 6 - 5 - read-write - - - ARPE - desc ARPE - 7 - 7 - read-write - - - CKD - desc CKD - 9 - 8 - read-write - - - - - CR2 - desc CR2 - 0x4 - 32 - read-write - 0x0 - 0xF8 - - - CCDS - desc CCDS - 3 - 3 - read-write - - - MMS - desc MMS - 6 - 4 - read-write - - - TI1S - desc TI1S - 7 - 7 - read-write - - - - - SMCR - desc SMCR - 0x8 - 32 - read-write - 0x0 - 0xFFF7 - - - SMS - desc SMS - 2 - 0 - read-write - - - TS - desc TS - 6 - 4 - read-write - - - MSM - desc MSM - 7 - 7 - read-write - - - ETF - desc ETF - 11 - 8 - read-write - - - ETPS - desc ETPS - 13 - 12 - read-write - - - ECE - desc ECE - 14 - 14 - read-write - - - ETP - desc ETP - 15 - 15 - read-write - - - - - DIER - desc DIER - 0xC - 32 - read-write - 0x0 - 0x5F5F - - - UIE - desc UIE - 0 - 0 - read-write - - - CC1IE - desc CC1IE - 1 - 1 - read-write - - - CC2IE - desc CC2IE - 2 - 2 - read-write - - - CC3IE - desc CC3IE - 3 - 3 - read-write - - - CC4IE - desc CC4IE - 4 - 4 - read-write - - - TIE - desc TIE - 6 - 6 - read-write - - - UDE - desc UDE - 8 - 8 - read-write - - - CC1DE - desc CC1DE - 9 - 9 - read-write - - - CC2DE - desc CC2DE - 10 - 10 - read-write - - - CC3DE - desc CC3DE - 11 - 11 - read-write - - - CC4DE - desc CC4DE - 12 - 12 - read-write - - - TDE - desc TDE - 14 - 14 - read-write - - - - - SR - desc SR - 0x10 - 32 - read-write - 0x0 - 0x1E5F - - - UIF - desc UIF - 0 - 0 - read-write - - - CC1IF - desc CC1IF - 1 - 1 - read-write - - - CC2IF - desc CC2IF - 2 - 2 - read-write - - - CC3IF - desc CC3IF - 3 - 3 - read-write - - - CC4IF - desc CC4IF - 4 - 4 - read-write - - - COMIF - desc COMIF - 5 - 5 - read-write - - - TIF - desc TIF - 6 - 6 - read-write - - - BIF - desc BIF - 7 - 7 - read-write - - - CC1OF - desc CC1OF - 9 - 9 - read-write - - - CC2OF - desc CC2OF - 10 - 10 - read-write - - - CC3OF - desc CC3OF - 11 - 11 - read-write - - - CC4OF - desc CC4OF - 12 - 12 - read-write - - - IC1IR - desc IC1IR - 16 - 16 - read-write - - - IC2IR - desc IC2IR - 17 - 17 - read-write - - - IC3IR - desc IC3IR - 18 - 18 - read-write - - - IC4IR - desc IC3IR - 19 - 19 - read-write - - - IC1IF - desc IC1IF - 20 - 20 - read-write - - - IC2IF - desc IC2IF - 21 - 21 - read-write - - - IC3IF - desc IC3IF - 22 - 22 - read-write - - - IC4IF - desc IC3IF - 23 - 23 - read-write - - - - - EGR - desc EGR - 0x14 - 32 - write-only - 0x0 - 0x5F - - - UG - desc UG - 0 - 0 - write-only - - - CC1G - Capture/Compare 1 Generation - 1 - 1 - write-only - - - CC2G - desc CC2G - 2 - 2 - write-only - - - CC3G - desc CC3G - 3 - 3 - write-only - - - CC4G - desc CC4G - 4 - 4 - write-only - - - TG - desc TG - 6 - 6 - write-only - - - - - CCMR1_OUTPUT - desc CCMR1:OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - OC1FE - desc OC1FE - 2 - 2 - read-write - - - OC1PE - desc OC1PE - 3 - 3 - read-write - - - OC1M - desc OC1M - 6 - 4 - read-write - - - OC1CE - desc OC1CE - 7 - 7 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - OC2FE - desc OC2FE - 10 - 10 - read-write - - - OC2PE - desc OC2PE - 11 - 11 - read-write - - - OC2M - desc OC2M - 14 - 12 - read-write - - - OC2CE - desc OC2CE - 15 - 15 - read-write - - - - - CCMR1_INPUT - desc CCMR1:INPUT - CCMR1_OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - IC1PSC - desc IC1PSC - 3 - 2 - read-write - - - IC1F - desc IC1F - 7 - 4 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - IC2PSC - desc IC2PSC - 11 - 10 - read-write - - - IC2F - desc IC2F - 15 - 12 - read-write - - - - - CCMR2_OUTPUT - desc CCMR2:OUTPUT - 0x1C - 32 - read-write - 0x0 - 0xFFFF - - - CC3S - desc CC3S - 1 - 0 - read-write - - - OC3FE - desc OC3FE - 2 - 2 - read-write - - - OC3PE - desc OC3PE - 3 - 3 - read-write - - - OC3M - desc OC3M - 6 - 4 - read-write - - - OC3CE - desc OC3CE - 7 - 7 - read-write - - - CC4S - desc CC4S - 9 - 8 - read-write - - - OC4FE - desc OC4FE - 10 - 10 - read-write - - - OC4PE - desc OC4PE - 11 - 11 - read-write - - - OC4M - desc OC4M - 14 - 12 - read-write - - - OC4CE - desc OC4CE - 15 - 15 - read-write - - - - - CCMR2_INPUT - desc CCMR2:INPUT - CCMR2_OUTPUT - 0x1C - 32 - read-write - 0x0 - 0xFFFF - - - CC3S - desc CC3S - 1 - 0 - read-write - - - IC3PSC - desc IC3PSC - 3 - 2 - read-write - - - IC3F - desc IC3F - 7 - 4 - read-write - - - CC4S - desc CC4S - 9 - 8 - read-write - - - IC4PSC - desc IC4PSC - 11 - 10 - read-write - - - IC4F - desc IC4F - 15 - 12 - read-write - - - - - CCER - desc CCER - 0x20 - 32 - read-write - 0x0 - 0x3333 - - - CC1E - desc CC1E - 0 - 0 - read-write - - - CC1P - desc CC1P - 1 - 1 - read-write - - - CC2E - desc CC2E - 4 - 4 - read-write - - - CC2P - desc CC2P - 5 - 5 - read-write - - - CC3E - desc CC3E - 8 - 8 - read-write - - - CC3P - desc CC3P - 9 - 9 - read-write - - - CC4E - desc CC4E - 12 - 12 - read-write - - - CC4P - desc CC4P - 13 - 13 - read-write - - - - - CNT - desc CNT - 0x24 - 32 - read-write - 0x0 - 0xFFFF - - - CNT - desc CNT - 15 - 0 - read-write - - - - - PSC - desc PSC - 0x28 - 32 - read-write - 0x0 - 0xFFFF - - - PSC - desc PSC - 15 - 0 - read-write - - - - - ARR - desc ARR - 0x2C - 32 - read-write - 0xFFFF - 0xFFFF - - - ARR - desc ARR - 15 - 0 - read-write - - - - - RCR - desc RCR - 0x30 - 32 - read-write - 0xFFFF - 0xFFFF - - - REP - desc REP - 7 - 0 - read-write - - - - - CCR1 - desc CCR1 - 0x34 - 32 - read-write - 0x0 - 0xFFFF - - - CCR1 - desc CCR1 - 15 - 0 - read-write - - - - - CCR2 - desc CCR2 - 0x38 - 32 - read-write - 0x0 - 0xFFFF - - - CCR2 - desc CCR2 - 15 - 0 - read-write - - - - - CCR3 - desc CCR3 - 0x3C - 32 - read-write - 0x0 - 0xFFFF - - - CCR3 - desc CCR3 - 15 - 0 - read-write - - - - - CCR4 - desc CCR4 - 0x40 - 32 - read-write - 0x0 - 0xFFFF - - - CCR4 - desc CCR4 - 15 - 0 - read-write - - - - - BDTR - desc BDTR - 0x44 - 32 - read-write - 0x0 - 0xFFFF - - - DTG - desc DTG - 7 - 0 - read-write - - - LOCK - desc LOCK - 9 - 8 - read-write - - - OSSI - desc OSSI - 10 - 10 - read-write - - - OSSR - desc OSSR - 11 - 11 - read-write - - - BKE - desc BKE - 12 - 12 - read-write - - - BKP - desc BKP - 13 - 13 - read-write - - - AOE - desc AOE - 14 - 14 - read-write - - - MOE - desc MOE - 15 - 15 - read-write - - - - - DCR - desc DCR - 0x48 - 32 - read-write - 0x0 - 0x1F1F - - - DBA - desc DBA - 4 - 0 - read-write - - - DBL - desc DBL - 12 - 8 - read-write - - - - - DMAR - desc DMAR - 0x4C - 32 - read-write - 0x0 - 0xFFFF - - - DMAB - desc DMAB - 15 - 0 - read-write - - - - - - - TIM2 - desc TIM - TIM - 0x40000000 - - 0x0 - 0x400 - registers - - - TIM2 - TIM2 global Interrupt - 15 - - - - CR1 - desc CR1 - 0x0 - 32 - read-write - 0x0 - 0x3FF - - - CEN - desc CEN - 0 - 0 - read-write - - - UDIS - desc UDIS - 1 - 1 - read-write - - - URS - desc URS - 2 - 2 - read-write - - - OPM - desc OPM - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CMS - desc CMS - 6 - 5 - read-write - - - ARPE - desc ARPE - 7 - 7 - read-write - - - CKD - desc CKD - 9 - 8 - read-write - - - - - CR2 - desc CR2 - 0x4 - 32 - read-write - 0x0 - 0xF8 - - - CCDS - desc CCDS - 3 - 3 - read-write - - - MMS - desc MMS - 6 - 4 - read-write - - - TI1S - desc TI1S - 7 - 7 - read-write - - - - - SMCR - desc SMCR - 0x8 - 32 - read-write - 0x0 - 0xFFF7 - - - SMS - desc SMS - 2 - 0 - read-write - - - TS - desc TS - 6 - 4 - read-write - - - MSM - desc MSM - 7 - 7 - read-write - - - ETF - desc ETF - 11 - 8 - read-write - - - ETPS - desc ETPS - 13 - 12 - read-write - - - ECE - desc ECE - 14 - 14 - read-write - - - ETP - desc ETP - 15 - 15 - read-write - - - - - DIER - desc DIER - 0xC - 32 - read-write - 0x0 - 0x5F5F - - - UIE - desc UIE - 0 - 0 - read-write - - - CC1IE - desc CC1IE - 1 - 1 - read-write - - - CC2IE - desc CC2IE - 2 - 2 - read-write - - - CC3IE - desc CC3IE - 3 - 3 - read-write - - - CC4IE - desc CC4IE - 4 - 4 - read-write - - - TIE - desc TIE - 6 - 6 - read-write - - - UDE - desc UDE - 8 - 8 - read-write - - - CC1DE - desc CC1DE - 9 - 9 - read-write - - - CC2DE - desc CC2DE - 10 - 10 - read-write - - - CC3DE - desc CC3DE - 11 - 11 - read-write - - - CC4DE - desc CC4DE - 12 - 12 - read-write - - - TDE - desc TDE - 14 - 14 - read-write - - - - - SR - desc SR - 0x10 - 32 - read-write - 0x0 - 0x1E5F - - - UIF - desc UIF - 0 - 0 - read-write - - - CC1IF - desc CC1IF - 1 - 1 - read-write - - - CC2IF - desc CC2IF - 2 - 2 - read-write - - - CC3IF - desc CC3IF - 3 - 3 - read-write - - - CC4IF - desc CC4IF - 4 - 4 - read-write - - - COMIF - desc COMIF - 5 - 5 - read-write - - - TIF - desc TIF - 6 - 6 - read-write - - - BIF - desc BIF - 7 - 7 - read-write - - - CC1OF - desc CC1OF - 9 - 9 - read-write - - - CC2OF - desc CC2OF - 10 - 10 - read-write - - - CC3OF - desc CC3OF - 11 - 11 - read-write - - - CC4OF - desc CC4OF - 12 - 12 - read-write - - - IC1IR - desc IC1IR - 16 - 16 - read-write - - - IC2IR - desc IC2IR - 17 - 17 - read-write - - - IC3IR - desc IC3IR - 18 - 18 - read-write - - - IC4IR - desc IC3IR - 19 - 19 - read-write - - - IC1IF - desc IC1IF - 20 - 20 - read-write - - - IC2IF - desc IC2IF - 21 - 21 - read-write - - - IC3IF - desc IC3IF - 22 - 22 - read-write - - - IC4IF - desc IC3IF - 23 - 23 - read-write - - - - - EGR - desc EGR - 0x14 - 32 - write-only - 0x0 - 0x5F - - - UG - desc UG - 0 - 0 - write-only - - - CC1G - Capture/Compare 1 Generation - 1 - 1 - write-only - - - CC2G - desc CC2G - 2 - 2 - write-only - - - CC3G - desc CC3G - 3 - 3 - write-only - - - CC4G - desc CC4G - 4 - 4 - write-only - - - TG - desc TG - 6 - 6 - write-only - - - - - CCMR1_OUTPUT - desc CCMR1:OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - OC1FE - desc OC1FE - 2 - 2 - read-write - - - OC1PE - desc OC1PE - 3 - 3 - read-write - - - OC1M - desc OC1M - 6 - 4 - read-write - - - OC1CE - desc OC1CE - 7 - 7 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - OC2FE - desc OC2FE - 10 - 10 - read-write - - - OC2PE - desc OC2PE - 11 - 11 - read-write - - - OC2M - desc OC2M - 14 - 12 - read-write - - - OC2CE - desc OC2CE - 15 - 15 - read-write - - - - - CCMR1_INPUT - desc CCMR1:INPUT - CCMR1_OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - IC1PSC - desc IC1PSC - 3 - 2 - read-write - - - IC1F - desc IC1F - 7 - 4 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - IC2PSC - desc IC2PSC - 11 - 10 - read-write - - - IC2F - desc IC2F - 15 - 12 - read-write - - - - - CCMR2_OUTPUT - desc CCMR2:OUTPUT - 0x1C - 32 - read-write - 0x0 - 0xFFFF - - - CC3S - desc CC3S - 1 - 0 - read-write - - - OC3FE - desc OC3FE - 2 - 2 - read-write - - - OC3PE - desc OC3PE - 3 - 3 - read-write - - - OC3M - desc OC3M - 6 - 4 - read-write - - - OC3CE - desc OC3CE - 7 - 7 - read-write - - - CC4S - desc CC4S - 9 - 8 - read-write - - - OC4FE - desc OC4FE - 10 - 10 - read-write - - - OC4PE - desc OC4PE - 11 - 11 - read-write - - - OC4M - desc OC4M - 14 - 12 - read-write - - - OC4CE - desc OC4CE - 15 - 15 - read-write - - - - - CCMR2_INPUT - desc CCMR2:INPUT - CCMR2_OUTPUT - 0x1C - 32 - read-write - 0x0 - 0xFFFF - - - CC3S - desc CC3S - 1 - 0 - read-write - - - IC3PSC - desc IC3PSC - 3 - 2 - read-write - - - IC3F - desc IC3F - 7 - 4 - read-write - - - CC4S - desc CC4S - 9 - 8 - read-write - - - IC4PSC - desc IC4PSC - 11 - 10 - read-write - - - IC4F - desc IC4F - 15 - 12 - read-write - - - - - CCER - desc CCER - 0x20 - 32 - read-write - 0x0 - 0x3333 - - - CC1E - desc CC1E - 0 - 0 - read-write - - - CC1P - desc CC1P - 1 - 1 - read-write - - - CC2E - desc CC2E - 4 - 4 - read-write - - - CC2P - desc CC2P - 5 - 5 - read-write - - - CC3E - desc CC3E - 8 - 8 - read-write - - - CC3P - desc CC3P - 9 - 9 - read-write - - - CC4E - desc CC4E - 12 - 12 - read-write - - - CC4P - desc CC4P - 13 - 13 - read-write - - - - - CNT - desc CNT - 0x24 - 32 - read-write - 0x0 - 0xFFFF - - - CNT - desc CNT - 15 - 0 - read-write - - - - - PSC - desc PSC - 0x28 - 32 - read-write - 0x0 - 0xFFFF - - - PSC - desc PSC - 15 - 0 - read-write - - - - - ARR - desc ARR - 0x2C - 32 - read-write - 0xFFFF - 0xFFFF - - - ARR - desc ARR - 15 - 0 - read-write - - - - - CCR1 - desc CCR1 - 0x34 - 32 - read-write - 0x0 - 0xFFFF - - - CCR1 - desc CCR1 - 15 - 0 - read-write - - - - - CCR2 - desc CCR2 - 0x38 - 32 - read-write - 0x0 - 0xFFFF - - - CCR2 - desc CCR2 - 15 - 0 - read-write - - - - - CCR3 - desc CCR3 - 0x3C - 32 - read-write - 0x0 - 0xFFFF - - - CCR3 - desc CCR3 - 15 - 0 - read-write - - - - - CCR4 - desc CCR4 - 0x40 - 32 - read-write - 0x0 - 0xFFFF - - - CCR4 - desc CCR4 - 15 - 0 - read-write - - - - - DCR - desc DCR - 0x48 - 32 - read-write - 0x0 - 0x1F1F - - - DBA - desc DBA - 4 - 0 - read-write - - - DBL - desc DBL - 12 - 8 - read-write - - - - - DMAR - desc DMAR - 0x4C - 32 - read-write - 0x0 - 0xFFFF - - - DMAB - desc DMAB - 15 - 0 - read-write - - - - - - - TIM3 - General purpose timer - TIM - 0x40000400 - - 0x00 - 0x400 - registers - - - TIM3 - TIM3 global Interrupt - 16 - - - - CR1 - desc CR1 - 0x0 - 32 - read-write - 0x0 - 0x3FF - - - CEN - desc CEN - 0 - 0 - read-write - - - UDIS - desc UDIS - 1 - 1 - read-write - - - URS - desc URS - 2 - 2 - read-write - - - OPM - desc OPM - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CMS - desc CMS - 6 - 5 - read-write - - - ARPE - desc ARPE - 7 - 7 - read-write - - - CKD - desc CKD - 9 - 8 - read-write - - - - - CR2 - desc CR2 - 0x4 - 32 - read-write - 0x0 - 0xF8 - - - CCDS - desc CCDS - 3 - 3 - read-write - - - MMS - desc MMS - 6 - 4 - read-write - - - TI1S - desc TI1S - 7 - 7 - read-write - - - - - SMCR - desc SMCR - 0x8 - 32 - read-write - 0x0 - 0xFFF7 - - - SMS - desc SMS - 2 - 0 - read-write - - - TS - desc TS - 6 - 4 - read-write - - - MSM - desc MSM - 7 - 7 - read-write - - - ETF - desc ETF - 11 - 8 - read-write - - - ETPS - desc ETPS - 13 - 12 - read-write - - - ECE - desc ECE - 14 - 14 - read-write - - - ETP - desc ETP - 15 - 15 - read-write - - - - - DIER - desc DIER - 0xC - 32 - read-write - 0x0 - 0x5F5F - - - UIE - desc UIE - 0 - 0 - read-write - - - CC1IE - desc CC1IE - 1 - 1 - read-write - - - CC2IE - desc CC2IE - 2 - 2 - read-write - - - CC3IE - desc CC3IE - 3 - 3 - read-write - - - CC4IE - desc CC4IE - 4 - 4 - read-write - - - TIE - desc TIE - 6 - 6 - read-write - - - UDE - desc UDE - 8 - 8 - read-write - - - CC1DE - desc CC1DE - 9 - 9 - read-write - - - CC2DE - desc CC2DE - 10 - 10 - read-write - - - CC3DE - desc CC3DE - 11 - 11 - read-write - - - CC4DE - desc CC4DE - 12 - 12 - read-write - - - TDE - desc TDE - 14 - 14 - read-write - - - - - SR - desc SR - 0x10 - 32 - read-write - 0x0 - 0x1E5F - - - UIF - desc UIF - 0 - 0 - read-write - - - CC1IF - desc CC1IF - 1 - 1 - read-write - - - CC2IF - desc CC2IF - 2 - 2 - read-write - - - CC3IF - desc CC3IF - 3 - 3 - read-write - - - CC4IF - desc CC4IF - 4 - 4 - read-write - - - COMIF - desc COMIF - 5 - 5 - read-write - - - TIF - desc TIF - 6 - 6 - read-write - - - BIF - desc BIF - 7 - 7 - read-write - - - CC1OF - desc CC1OF - 9 - 9 - read-write - - - CC2OF - desc CC2OF - 10 - 10 - read-write - - - CC3OF - desc CC3OF - 11 - 11 - read-write - - - CC4OF - desc CC4OF - 12 - 12 - read-write - - - IC1IR - desc IC1IR - 16 - 16 - read-write - - - IC2IR - desc IC2IR - 17 - 17 - read-write - - - IC3IR - desc IC3IR - 18 - 18 - read-write - - - IC4IR - desc IC3IR - 19 - 19 - read-write - - - IC1IF - desc IC1IF - 20 - 20 - read-write - - - IC2IF - desc IC2IF - 21 - 21 - read-write - - - IC3IF - desc IC3IF - 22 - 22 - read-write - - - IC4IF - desc IC3IF - 23 - 23 - read-write - - - - - EGR - desc EGR - 0x14 - 32 - write-only - 0x0 - 0x5F - - - UG - desc UG - 0 - 0 - write-only - - - CC1G - Capture/Compare 1 Generation - 1 - 1 - write-only - - - CC2G - desc CC2G - 2 - 2 - write-only - - - CC3G - desc CC3G - 3 - 3 - write-only - - - CC4G - desc CC4G - 4 - 4 - write-only - - - TG - desc TG - 6 - 6 - write-only - - - - - CCMR1_OUTPUT - desc CCMR1:OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - OC1FE - desc OC1FE - 2 - 2 - read-write - - - OC1PE - desc OC1PE - 3 - 3 - read-write - - - OC1M - desc OC1M - 6 - 4 - read-write - - - OC1CE - desc OC1CE - 7 - 7 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - OC2FE - desc OC2FE - 10 - 10 - read-write - - - OC2PE - desc OC2PE - 11 - 11 - read-write - - - OC2M - desc OC2M - 14 - 12 - read-write - - - OC2CE - desc OC2CE - 15 - 15 - read-write - - - - - CCMR1_INPUT - desc CCMR1:INPUT - CCMR1_OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - IC1PSC - desc IC1PSC - 3 - 2 - read-write - - - IC1F - desc IC1F - 7 - 4 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - IC2PSC - desc IC2PSC - 11 - 10 - read-write - - - IC2F - desc IC2F - 15 - 12 - read-write - - - - - CCMR2_OUTPUT - desc CCMR2:OUTPUT - 0x1C - 32 - read-write - 0x0 - 0xFFFF - - - CC3S - desc CC3S - 1 - 0 - read-write - - - OC3FE - desc OC3FE - 2 - 2 - read-write - - - OC3PE - desc OC3PE - 3 - 3 - read-write - - - OC3M - desc OC3M - 6 - 4 - read-write - - - OC3CE - desc OC3CE - 7 - 7 - read-write - - - CC4S - desc CC4S - 9 - 8 - read-write - - - OC4FE - desc OC4FE - 10 - 10 - read-write - - - OC4PE - desc OC4PE - 11 - 11 - read-write - - - OC4M - desc OC4M - 14 - 12 - read-write - - - OC4CE - desc OC4CE - 15 - 15 - read-write - - - - - CCMR2_INPUT - desc CCMR2:INPUT - CCMR2_OUTPUT - 0x1C - 32 - read-write - 0x0 - 0xFFFF - - - CC3S - desc CC3S - 1 - 0 - read-write - - - IC3PSC - desc IC3PSC - 3 - 2 - read-write - - - IC3F - desc IC3F - 7 - 4 - read-write - - - CC4S - desc CC4S - 9 - 8 - read-write - - - IC4PSC - desc IC4PSC - 11 - 10 - read-write - - - IC4F - desc IC4F - 15 - 12 - read-write - - - - - CCER - desc CCER - 0x20 - 32 - read-write - 0x0 - 0x3333 - - - CC1E - desc CC1E - 0 - 0 - read-write - - - CC1P - desc CC1P - 1 - 1 - read-write - - - CC2E - desc CC2E - 4 - 4 - read-write - - - CC2P - desc CC2P - 5 - 5 - read-write - - - CC3E - desc CC3E - 8 - 8 - read-write - - - CC3P - desc CC3P - 9 - 9 - read-write - - - CC4E - desc CC4E - 12 - 12 - read-write - - - CC4P - desc CC4P - 13 - 13 - read-write - - - - - CNT - desc CNT - 0x24 - 32 - read-write - 0x0 - 0xFFFF - - - CNT - desc CNT - 15 - 0 - read-write - - - - - PSC - desc PSC - 0x28 - 32 - read-write - 0x0 - 0xFFFF - - - PSC - desc PSC - 15 - 0 - read-write - - - - - ARR - desc ARR - 0x2C - 32 - read-write - 0xFFFF - 0xFFFF - - - ARR - desc ARR - 15 - 0 - read-write - - - - - CCR1 - desc CCR1 - 0x34 - 32 - read-write - 0x0 - 0xFFFF - - - CCR1 - desc CCR1 - 15 - 0 - read-write - - - - - CCR2 - desc CCR2 - 0x38 - 32 - read-write - 0x0 - 0xFFFF - - - CCR2 - desc CCR2 - 15 - 0 - read-write - - - - - CCR3 - desc CCR3 - 0x3C - 32 - read-write - 0x0 - 0xFFFF - - - CCR3 - desc CCR3 - 15 - 0 - read-write - - - - - CCR4 - desc CCR4 - 0x40 - 32 - read-write - 0x0 - 0xFFFF - - - CCR4 - desc CCR4 - 15 - 0 - read-write - - - - - DCR - desc DCR - 0x48 - 32 - read-write - 0x0 - 0x1F1F - - - DBA - desc DBA - 4 - 0 - read-write - - - DBL - desc DBL - 12 - 8 - read-write - - - - - DMAR - desc DMAR - 0x4C - 32 - read-write - 0x0 - 0xFFFF - - - DMAB - desc DMAB - 15 - 0 - read-write - - - - - - - TIM6 - desc TIM - TIM - 0x40001000 - - 0x0 - 0x400 - registers - - - TIM6_LPTIM1_DAC - TIM6, LPTIM1, DAC global Interrupts - 17 - - - - CR1 - desc CR1 - 0x0 - 32 - read-write - 0x0 - 0x3FF - - - CEN - desc CEN - 0 - 0 - read-write - - - UDIS - desc UDIS - 1 - 1 - read-write - - - URS - desc URS - 2 - 2 - read-write - - - OPM - desc OPM - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CMS - desc CMS - 6 - 5 - read-write - - - ARPE - desc ARPE - 7 - 7 - read-write - - - CKD - desc CKD - 9 - 8 - read-write - - - - - CR2 - desc CR2 - 0x4 - 32 - read-write - 0x0 - 0xF8 - - - CCDS - desc CCDS - 3 - 3 - read-write - - - MMS - desc MMS - 6 - 4 - read-write - - - TI1S - desc TI1S - 7 - 7 - read-write - - - - - DIER - desc DIER - 0xC - 32 - read-write - 0x0 - 0x5F5F - - - UIE - desc UIE - 0 - 0 - read-write - - - CC1IE - desc CC1IE - 1 - 1 - read-write - - - CC2IE - desc CC2IE - 2 - 2 - read-write - - - CC3IE - desc CC3IE - 3 - 3 - read-write - - - CC4IE - desc CC4IE - 4 - 4 - read-write - - - TIE - desc TIE - 6 - 6 - read-write - - - UDE - desc UDE - 8 - 8 - read-write - - - CC1DE - desc CC1DE - 9 - 9 - read-write - - - CC2DE - desc CC2DE - 10 - 10 - read-write - - - CC3DE - desc CC3DE - 11 - 11 - read-write - - - CC4DE - desc CC4DE - 12 - 12 - read-write - - - TDE - desc TDE - 14 - 14 - read-write - - - - - SR - desc SR - 0x10 - 32 - read-write - 0x0 - 0x1E5F - - - UIF - desc UIF - 0 - 0 - read-write - - - CC1IF - desc CC1IF - 1 - 1 - read-write - - - CC2IF - desc CC2IF - 2 - 2 - read-write - - - CC3IF - desc CC3IF - 3 - 3 - read-write - - - CC4IF - desc CC4IF - 4 - 4 - read-write - - - COMIF - desc COMIF - 5 - 5 - read-write - - - TIF - desc TIF - 6 - 6 - read-write - - - BIF - desc BIF - 7 - 7 - read-write - - - CC1OF - desc CC1OF - 9 - 9 - read-write - - - CC2OF - desc CC2OF - 10 - 10 - read-write - - - CC3OF - desc CC3OF - 11 - 11 - read-write - - - CC4OF - desc CC4OF - 12 - 12 - read-write - - - IC1IR - desc IC1IR - 16 - 16 - read-write - - - IC2IR - desc IC2IR - 17 - 17 - read-write - - - IC3IR - desc IC3IR - 18 - 18 - read-write - - - IC4IR - desc IC3IR - 19 - 19 - read-write - - - IC1IF - desc IC1IF - 20 - 20 - read-write - - - IC2IF - desc IC2IF - 21 - 21 - read-write - - - IC3IF - desc IC3IF - 22 - 22 - read-write - - - IC4IF - desc IC3IF - 23 - 23 - read-write - - - - - EGR - desc EGR - 0x14 - 32 - write-only - 0x0 - 0x5F - - - UG - desc UG - 0 - 0 - write-only - - - CC1G - Capture/Compare 1 Generation - 1 - 1 - write-only - - - CC2G - desc CC2G - 2 - 2 - write-only - - - CC3G - desc CC3G - 3 - 3 - write-only - - - CC4G - desc CC4G - 4 - 4 - write-only - - - TG - desc TG - 6 - 6 - write-only - - - - - CNT - desc CNT - 0x24 - 32 - read-write - 0x0 - 0xFFFF - - - CNT - desc CNT - 15 - 0 - read-write - - - - - PSC - desc PSC - 0x28 - 32 - read-write - 0x0 - 0xFFFF - - - PSC - desc PSC - 15 - 0 - read-write - - - - - ARR - desc ARR - 0x2C - 32 - read-write - 0xFFFF - 0xFFFF - - - ARR - desc ARR - 15 - 0 - read-write - - - - - - - TIM7 - desc TIM - TIM - 0x40001400 - - 0x0 - 0x400 - registers - - - TIM7 - TIM7 global Interrupt - 18 - - - - TIM14 - General purpose timer - TIM - 0x40002000 - - 0x00 - 0x400 - registers - - - TIM14 - TIM14 global Interrupt - 19 - - - - CR1 - desc CR1 - 0x0 - 32 - read-write - 0x0 - 0x3FF - - - CEN - desc CEN - 0 - 0 - read-write - - - UDIS - desc UDIS - 1 - 1 - read-write - - - URS - desc URS - 2 - 2 - read-write - - - OPM - desc OPM - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CMS - desc CMS - 6 - 5 - read-write - - - ARPE - desc ARPE - 7 - 7 - read-write - - - CKD - desc CKD - 9 - 8 - read-write - - - - - DIER - desc DIER - 0xC - 32 - read-write - 0x0 - 0x5F5F - - - UIE - desc UIE - 0 - 0 - read-write - - - CC1IE - desc CC1IE - 1 - 1 - read-write - - - CC2IE - desc CC2IE - 2 - 2 - read-write - - - CC3IE - desc CC3IE - 3 - 3 - read-write - - - CC4IE - desc CC4IE - 4 - 4 - read-write - - - TIE - desc TIE - 6 - 6 - read-write - - - UDE - desc UDE - 8 - 8 - read-write - - - CC1DE - desc CC1DE - 9 - 9 - read-write - - - CC2DE - desc CC2DE - 10 - 10 - read-write - - - CC3DE - desc CC3DE - 11 - 11 - read-write - - - CC4DE - desc CC4DE - 12 - 12 - read-write - - - TDE - desc TDE - 14 - 14 - read-write - - - - - SR - desc SR - 0x10 - 32 - read-write - 0x0 - 0x1E5F - - - UIF - desc UIF - 0 - 0 - read-write - - - CC1IF - desc CC1IF - 1 - 1 - read-write - - - CC2IF - desc CC2IF - 2 - 2 - read-write - - - CC3IF - desc CC3IF - 3 - 3 - read-write - - - CC4IF - desc CC4IF - 4 - 4 - read-write - - - TIF - desc TIF - 6 - 6 - read-write - - - CC1OF - desc CC1OF - 9 - 9 - read-write - - - CC2OF - desc CC2OF - 10 - 10 - read-write - - - CC3OF - desc CC3OF - 11 - 11 - read-write - - - CC4OF - desc CC4OF - 12 - 12 - read-write - - - - - EGR - desc EGR - 0x14 - 32 - write-only - 0x0 - 0x5F - - - UG - desc UG - 0 - 0 - write-only - - - CC1G - Capture/Compare 1 Generation - 1 - 1 - write-only - - - CC2G - desc CC2G - 2 - 2 - write-only - - - CC3G - desc CC3G - 3 - 3 - write-only - - - CC4G - desc CC4G - 4 - 4 - write-only - - - TG - desc TG - 6 - 6 - write-only - - - - - CCMR1_OUTPUT - desc CCMR1:OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - OC1FE - desc OC1FE - 2 - 2 - read-write - - - OC1PE - desc OC1PE - 3 - 3 - read-write - - - OC1M - desc OC1M - 6 - 4 - read-write - - - OC1CE - desc OC1CE - 7 - 7 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - OC2FE - desc OC2FE - 10 - 10 - read-write - - - OC2PE - desc OC2PE - 11 - 11 - read-write - - - OC2M - desc OC2M - 14 - 12 - read-write - - - OC2CE - desc OC2CE - 15 - 15 - read-write - - - - - CCMR1_INPUT - desc CCMR1:INPUT - CCMR1_OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - IC1PSC - desc IC1PSC - 3 - 2 - read-write - - - IC1F - desc IC1F - 7 - 4 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - IC2PSC - desc IC2PSC - 11 - 10 - read-write - - - IC2F - desc IC2F - 15 - 12 - read-write - - - - - CCER - desc CCER - 0x20 - 32 - read-write - 0x0 - 0x3333 - - - CC1E - desc CC1E - 0 - 0 - read-write - - - CC1P - desc CC1P - 1 - 1 - read-write - - - CC2E - desc CC2E - 4 - 4 - read-write - - - CC2P - desc CC2P - 5 - 5 - read-write - - - CC3E - desc CC3E - 8 - 8 - read-write - - - CC3P - desc CC3P - 9 - 9 - read-write - - - CC4E - desc CC4E - 12 - 12 - read-write - - - CC4P - desc CC4P - 13 - 13 - read-write - - - - - CNT - desc CNT - 0x24 - 32 - read-write - 0x0 - 0xFFFF - - - CNT - desc CNT - 15 - 0 - read-write - - - - - PSC - desc PSC - 0x28 - 32 - read-write - 0x0 - 0xFFFF - - - PSC - desc PSC - 15 - 0 - read-write - - - - - ARR - desc ARR - 0x2C - 32 - read-write - 0xFFFF - 0xFFFF - - - ARR - desc ARR - 15 - 0 - read-write - - - - - CCR1 - desc CCR1 - 0x34 - 32 - read-write - 0x0 - 0xFFFF - - - CCR1 - desc CCR1 - 15 - 0 - read-write - - - - - OR - desc OR - 0x50 - 32 - read-write - 0x0 - - - TI1_RMP - desc TI1_RMP - 1 - 0 - read-write - - - - - - - TIM15 - 0x40014000 - - 0x0 - 0x400 - registers - - - TIM15 - TIM15 global Interrupt - 20 - - - - CR1 - desc CR1 - 0x0 - 32 - read-write - 0x0 - 0x3FF - - - CEN - desc CEN - 0 - 0 - read-write - - - UDIS - desc UDIS - 1 - 1 - read-write - - - URS - desc URS - 2 - 2 - read-write - - - OPM - desc OPM - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CMS - desc CMS - 6 - 5 - read-write - - - ARPE - desc ARPE - 7 - 7 - read-write - - - CKD - desc CKD - 9 - 8 - read-write - - - - - CR2 - desc CR2 - 0x4 - 32 - read-write - 0x0 - 0xF8 - - - CCDS - desc CCDS - 3 - 3 - read-write - - - MMS - desc MMS - 6 - 4 - read-write - - - TI1S - desc TI1S - 7 - 7 - read-write - - - - - SMCR - desc SMCR - 0x8 - 32 - read-write - 0x0 - 0xFFF7 - - - SMS - desc SMS - 2 - 0 - read-write - - - TS - desc TS - 6 - 4 - read-write - - - MSM - desc MSM - 7 - 7 - read-write - - - ETF - desc ETF - 11 - 8 - read-write - - - ETPS - desc ETPS - 13 - 12 - read-write - - - ECE - desc ECE - 14 - 14 - read-write - - - ETP - desc ETP - 15 - 15 - read-write - - - - - DIER - desc DIER - 0xC - 32 - read-write - 0x0 - 0x5F5F - - - UIE - desc UIE - 0 - 0 - read-write - - - CC1IE - desc CC1IE - 1 - 1 - read-write - - - CC2IE - desc CC2IE - 2 - 2 - read-write - - - CC3IE - desc CC3IE - 3 - 3 - read-write - - - CC4IE - desc CC4IE - 4 - 4 - read-write - - - TIE - desc TIE - 6 - 6 - read-write - - - UDE - desc UDE - 8 - 8 - read-write - - - CC1DE - desc CC1DE - 9 - 9 - read-write - - - CC2DE - desc CC2DE - 10 - 10 - read-write - - - CC3DE - desc CC3DE - 11 - 11 - read-write - - - CC4DE - desc CC4DE - 12 - 12 - read-write - - - TDE - desc TDE - 14 - 14 - read-write - - - - - SR - desc SR - 0x10 - 32 - read-write - 0x0 - 0x1E5F - - - UIF - desc UIF - 0 - 0 - read-write - - - CC1IF - desc CC1IF - 1 - 1 - read-write - - - CC2IF - desc CC2IF - 2 - 2 - read-write - - - CC3IF - desc CC3IF - 3 - 3 - read-write - - - CC4IF - desc CC4IF - 4 - 4 - read-write - - - COMIF - desc COMIF - 5 - 5 - read-write - - - TIF - desc TIF - 6 - 6 - read-write - - - BIF - desc BIF - 7 - 7 - read-write - - - CC1OF - desc CC1OF - 9 - 9 - read-write - - - CC2OF - desc CC2OF - 10 - 10 - read-write - - - CC3OF - desc CC3OF - 11 - 11 - read-write - - - CC4OF - desc CC4OF - 12 - 12 - read-write - - - IC1IR - desc IC1IR - 16 - 16 - read-write - - - IC2IR - desc IC2IR - 17 - 17 - read-write - - - IC3IR - desc IC3IR - 18 - 18 - read-write - - - IC4IR - desc IC3IR - 19 - 19 - read-write - - - IC1IF - desc IC1IF - 20 - 20 - read-write - - - IC2IF - desc IC2IF - 21 - 21 - read-write - - - IC3IF - desc IC3IF - 22 - 22 - read-write - - - IC4IF - desc IC3IF - 23 - 23 - read-write - - - - - EGR - desc EGR - 0x14 - 32 - write-only - 0x0 - 0x5F - - - UG - desc UG - 0 - 0 - write-only - - - CC1G - Capture/Compare 1 Generation - 1 - 1 - write-only - - - CC2G - desc CC2G - 2 - 2 - write-only - - - CC3G - desc CC3G - 3 - 3 - write-only - - - CC4G - desc CC4G - 4 - 4 - write-only - - - TG - desc TG - 6 - 6 - write-only - - - - - CCMR1_OUTPUT - desc CCMR1:OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - OC1FE - desc OC1FE - 2 - 2 - read-write - - - OC1PE - desc OC1PE - 3 - 3 - read-write - - - OC1M - desc OC1M - 6 - 4 - read-write - - - OC1CE - desc OC1CE - 7 - 7 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - OC2FE - desc OC2FE - 10 - 10 - read-write - - - OC2PE - desc OC2PE - 11 - 11 - read-write - - - OC2M - desc OC2M - 14 - 12 - read-write - - - OC2CE - desc OC2CE - 15 - 15 - read-write - - - - - CCMR1_INPUT - desc CCMR1:INPUT - CCMR1_OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - IC1PSC - desc IC1PSC - 3 - 2 - read-write - - - IC1F - desc IC1F - 7 - 4 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - IC2PSC - desc IC2PSC - 11 - 10 - read-write - - - IC2F - desc IC2F - 15 - 12 - read-write - - - - - CCER - desc CCER - 0x20 - 32 - read-write - 0x0 - 0x3333 - - - CC1E - desc CC1E - 0 - 0 - read-write - - - CC1P - desc CC1P - 1 - 1 - read-write - - - CC2E - desc CC2E - 4 - 4 - read-write - - - CC2P - desc CC2P - 5 - 5 - read-write - - - CC3E - desc CC3E - 8 - 8 - read-write - - - CC3P - desc CC3P - 9 - 9 - read-write - - - CC4E - desc CC4E - 12 - 12 - read-write - - - CC4P - desc CC4P - 13 - 13 - read-write - - - - - CNT - desc CNT - 0x24 - 32 - read-write - 0x0 - 0xFFFF - - - CNT - desc CNT - 15 - 0 - read-write - - - - - PSC - desc PSC - 0x28 - 32 - read-write - 0x0 - 0xFFFF - - - PSC - desc PSC - 15 - 0 - read-write - - - - - ARR - desc ARR - 0x2C - 32 - read-write - 0xFFFF - 0xFFFF - - - ARR - desc ARR - 15 - 0 - read-write - - - - - RCR - desc RCR - 0x30 - 32 - read-write - 0xFFFF - 0xFFFF - - - REP - desc REP - 7 - 0 - read-write - - - - - CCR1 - desc CCR1 - 0x34 - 32 - read-write - 0x0 - 0xFFFF - - - CCR1 - desc CCR1 - 15 - 0 - read-write - - - - - CCR2 - desc CCR2 - 0x38 - 32 - read-write - 0x0 - 0xFFFF - - - CCR2 - desc CCR2 - 15 - 0 - read-write - - - - - BDTR - desc BDTR - 0x44 - 32 - read-write - 0x0 - 0xFFFF - - - DTG - desc DTG - 7 - 0 - read-write - - - LOCK - desc LOCK - 9 - 8 - read-write - - - OSSI - desc OSSI - 10 - 10 - read-write - - - OSSR - desc OSSR - 11 - 11 - read-write - - - BKE - desc BKE - 12 - 12 - read-write - - - BKP - desc BKP - 13 - 13 - read-write - - - AOE - desc AOE - 14 - 14 - read-write - - - MOE - desc MOE - 15 - 15 - read-write - - - - - DCR - desc DCR - 0x48 - 32 - read-write - 0x0 - 0x1F1F - - - DBA - desc DBA - 4 - 0 - read-write - - - DBL - desc DBL - 12 - 8 - read-write - - - - - DMAR - desc DMAR - 0x4C - 32 - read-write - 0x0 - 0xFFFF - - - DMAB - desc DMAB - 15 - 0 - read-write - - - - - - - TIM16 - General purpose timer - TIM - 0x40014400 - - 0x00 - 0x400 - registers - - - TIM16 - TIM16 global Interrupt - 21 - - - - CR1 - desc CR1 - 0x0 - 32 - read-write - 0x0 - 0x3FF - - - CEN - desc CEN - 0 - 0 - read-write - - - UDIS - desc UDIS - 1 - 1 - read-write - - - URS - desc URS - 2 - 2 - read-write - - - OPM - desc OPM - 3 - 3 - read-write - - - DIR - desc DIR - 4 - 4 - read-write - - - CMS - desc CMS - 6 - 5 - read-write - - - ARPE - desc ARPE - 7 - 7 - read-write - - - CKD - desc CKD - 9 - 8 - read-write - - - - - CR2 - desc CR2 - 0x4 - 32 - read-write - 0x0 - 0xF8 - - - CCDS - desc CCDS - 3 - 3 - read-write - - - MMS - desc MMS - 6 - 4 - read-write - - - TI1S - desc TI1S - 7 - 7 - read-write - - - - - DIER - desc DIER - 0xC - 32 - read-write - 0x0 - 0x5F5F - - - UIE - desc UIE - 0 - 0 - read-write - - - CC1IE - desc CC1IE - 1 - 1 - read-write - - - CC2IE - desc CC2IE - 2 - 2 - read-write - - - CC3IE - desc CC3IE - 3 - 3 - read-write - - - CC4IE - desc CC4IE - 4 - 4 - read-write - - - TIE - desc TIE - 6 - 6 - read-write - - - UDE - desc UDE - 8 - 8 - read-write - - - CC1DE - desc CC1DE - 9 - 9 - read-write - - - CC2DE - desc CC2DE - 10 - 10 - read-write - - - CC3DE - desc CC3DE - 11 - 11 - read-write - - - CC4DE - desc CC4DE - 12 - 12 - read-write - - - TDE - desc TDE - 14 - 14 - read-write - - - - - SR - desc SR - 0x10 - 32 - read-write - 0x0 - 0x1E5F - - - UIF - desc UIF - 0 - 0 - read-write - - - CC1IF - desc CC1IF - 1 - 1 - read-write - - - CC2IF - desc CC2IF - 2 - 2 - read-write - - - CC3IF - desc CC3IF - 3 - 3 - read-write - - - CC4IF - desc CC4IF - 4 - 4 - read-write - - - COMIF - desc COMIF - 5 - 5 - read-write - - - TIF - desc TIF - 6 - 6 - read-write - - - BIF - desc BIF - 7 - 7 - read-write - - - CC1OF - desc CC1OF - 9 - 9 - read-write - - - CC2OF - desc CC2OF - 10 - 10 - read-write - - - CC3OF - desc CC3OF - 11 - 11 - read-write - - - CC4OF - desc CC4OF - 12 - 12 - read-write - - - IC1IR - desc IC1IR - 16 - 16 - read-write - - - IC2IR - desc IC2IR - 17 - 17 - read-write - - - IC3IR - desc IC3IR - 18 - 18 - read-write - - - IC4IR - desc IC3IR - 19 - 19 - read-write - - - IC1IF - desc IC1IF - 20 - 20 - read-write - - - IC2IF - desc IC2IF - 21 - 21 - read-write - - - IC3IF - desc IC3IF - 22 - 22 - read-write - - - IC4IF - desc IC3IF - 23 - 23 - read-write - - - - - EGR - desc EGR - 0x14 - 32 - write-only - 0x0 - 0x5F - - - UG - desc UG - 0 - 0 - write-only - - - CC1G - Capture/Compare 1 Generation - 1 - 1 - write-only - - - CC2G - desc CC2G - 2 - 2 - write-only - - - CC3G - desc CC3G - 3 - 3 - write-only - - - CC4G - desc CC4G - 4 - 4 - write-only - - - TG - desc TG - 6 - 6 - write-only - - - - - CCMR1_OUTPUT - desc CCMR1:OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - OC1FE - desc OC1FE - 2 - 2 - read-write - - - OC1PE - desc OC1PE - 3 - 3 - read-write - - - OC1M - desc OC1M - 6 - 4 - read-write - - - OC1CE - desc OC1CE - 7 - 7 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - OC2FE - desc OC2FE - 10 - 10 - read-write - - - OC2PE - desc OC2PE - 11 - 11 - read-write - - - OC2M - desc OC2M - 14 - 12 - read-write - - - OC2CE - desc OC2CE - 15 - 15 - read-write - - - - - CCMR1_INPUT - desc CCMR1:INPUT - CCMR1_OUTPUT - 0x18 - 32 - read-write - 0x0 - 0xFFFF - - - CC1S - desc CC1S - 1 - 0 - read-write - - - IC1PSC - desc IC1PSC - 3 - 2 - read-write - - - IC1F - desc IC1F - 7 - 4 - read-write - - - CC2S - desc CC2S - 9 - 8 - read-write - - - IC2PSC - desc IC2PSC - 11 - 10 - read-write - - - IC2F - desc IC2F - 15 - 12 - read-write - - - - - CCER - desc CCER - 0x20 - 32 - read-write - 0x0 - 0x3333 - - - CC1E - desc CC1E - 0 - 0 - read-write - - - CC1P - desc CC1P - 1 - 1 - read-write - - - CC2E - desc CC2E - 4 - 4 - read-write - - - CC2P - desc CC2P - 5 - 5 - read-write - - - CC3E - desc CC3E - 8 - 8 - read-write - - - CC3P - desc CC3P - 9 - 9 - read-write - - - CC4E - desc CC4E - 12 - 12 - read-write - - - CC4P - desc CC4P - 13 - 13 - read-write - - - - - CNT - desc CNT - 0x24 - 32 - read-write - 0x0 - 0xFFFF - - - CNT - desc CNT - 15 - 0 - read-write - - - - - PSC - desc PSC - 0x28 - 32 - read-write - 0x0 - 0xFFFF - - - PSC - desc PSC - 15 - 0 - read-write - - - - - ARR - desc ARR - 0x2C - 32 - read-write - 0xFFFF - 0xFFFF - - - ARR - desc ARR - 15 - 0 - read-write - - - - - RCR - desc RCR - 0x30 - 32 - read-write - 0xFFFF - 0xFFFF - - - REP - desc REP - 7 - 0 - read-write - - - - - CCR1 - desc CCR1 - 0x34 - 32 - read-write - 0x0 - 0xFFFF - - - CCR1 - desc CCR1 - 15 - 0 - read-write - - - - - BDTR - desc BDTR - 0x44 - 32 - read-write - 0x0 - 0xFFFF - - - DTG - desc DTG - 7 - 0 - read-write - - - LOCK - desc LOCK - 9 - 8 - read-write - - - OSSI - desc OSSI - 10 - 10 - read-write - - - OSSR - desc OSSR - 11 - 11 - read-write - - - BKE - desc BKE - 12 - 12 - read-write - - - BKP - desc BKP - 13 - 13 - read-write - - - AOE - desc AOE - 14 - 14 - read-write - - - MOE - desc MOE - 15 - 15 - read-write - - - - - DCR - desc DCR - 0x48 - 32 - read-write - 0x0 - 0x1F1F - - - DBA - desc DBA - 4 - 0 - read-write - - - DBL - desc DBL - 12 - 8 - read-write - - - - - DMAR - desc DMAR - 0x4C - 32 - read-write - 0x0 - 0xFFFF - - - DMAB - desc DMAB - 15 - 0 - read-write - - - - - - - TIM17 - 0x40014800 - - TIM17 - TIM17 global Interrupt - 22 - - - - USART1 - - Universal synchronous asynchronous receiver - transmitter - - USART - 0x40013800 - - 0x0 - 0x400 - registers - - - USART1 - USART1 global Interrupt - 27 - - - - SR - desc SR - 0x0 - 32 - read-write - 0xC0 - - - PE - desc PE - 0 - 0 - read-only - - - FE - desc FE - 1 - 1 - read-only - - - NE - desc NE - 2 - 2 - read-only - - - ORE - desc ORE - 3 - 3 - read-only - - - IDLE - desc IDLE - 4 - 4 - read-only - - - RXNE - desc RXNE - 5 - 5 - read-write - - - TC - desc TC - 6 - 6 - read-write - - - TXE - desc TXE - 7 - 7 - read-only - - - LBD - desc LBD - 8 - 8 - read-write - - - CTS - desc CTS - 9 - 9 - read-write - - - ABRF - desc ABRF - 10 - 10 - read-only - - - ABRE - desc ABRE - 11 - 11 - read-only - - - ABRRQ - desc ABRRQ - 12 - 12 - write-only - - - - - DR - desc DR - 0x4 - 32 - read-write - 0x0 - - - DR - desc DR - 8 - 0 - read-write - - - - - BRR - desc BRR - 0x8 - 32 - read-write - 0x0 - - - DIV_FRACTION - desc DIV_Fraction - 3 - 0 - read-write - - - DIV_MANTISSA - desc DIV_Mantissa - 15 - 4 - read-write - - - - - CR1 - desc CR1 - 0xC - 32 - read-write - 0x0 - - - SBK - desc SBK - 0 - 0 - read-write - - - RWU - desc RWU - 1 - 1 - read-write - - - RE - desc RE - 2 - 2 - read-write - - - TE - desc TE - 3 - 3 - read-write - - - IDLEIE - desc IDLEIE - 4 - 4 - read-write - - - RXNEIE - desc RXNEIE - 5 - 5 - read-write - - - TCIE - desc TCIE - 6 - 6 - read-write - - - TXEIE - desc TXEIE - 7 - 7 - read-write - - - PEIE - desc PEIE - 8 - 8 - read-write - - - PS - desc PS - 9 - 9 - read-write - - - PCE - desc PCE - 10 - 10 - read-write - - - WAKE - desc WAKE - 11 - 11 - read-write - - - M - desc M - 12 - 12 - read-write - - - UE - desc UE - 13 - 13 - read-write - - - - - CR2 - desc CR2 - 0x10 - 32 - read-write - 0x0 - - - ADD - desc ADD - 3 - 0 - read-write - - - LBDL - desc LBDL - 5 - 5 - read-write - - - LBDIE - desc LBDIE - 6 - 6 - read-write - - - LBCL - desc LBCL - 8 - 8 - read-write - - - CPHA - desc CPHA - 9 - 9 - read-write - - - CPOL - desc CPOL - 10 - 10 - read-write - - - CLKEN - desc CLKEN - 11 - 11 - read-write - - - STOP - desc STOP - 13 - 12 - read-write - - - LINEN - desc LINEN - 14 - 14 - read-write - - - - - CR3 - desc CR3 - 0x14 - 32 - read-write - 0x0 - - - EIE - desc EIE - 0 - 0 - read-write - - - IREN - desc IREN - 1 - 1 - read-write - - - IRLP - desc IRLP - 2 - 2 - read-write - - - HDSEL - desc HDSEL - 3 - 3 - read-write - - - NACK - desc NACK - 4 - 4 - read-write - - - SCEN - desc SCEN - 5 - 5 - read-write - - - DMAR - desc DMAR - 6 - 6 - read-write - - - DMAT - desc DMAT - 7 - 7 - read-write - - - RTSE - desc RTSE - 8 - 8 - read-write - - - CTSE - desc CTSE - 9 - 9 - read-write - - - CTSIE - desc CTSIE - 10 - 10 - read-write - - - OVER8 - desc OVER8 - 11 - 11 - read-write - - - ABREN - desc ABREN - 12 - 12 - read-write - - - ABRMODE - desc ABRMODE - 14 - 13 - read-write - - - - - GTPR - desc GTPR - 0x18 - 32 - read-write - 0x0 - - - PSC - desc PSC - 7 - 0 - read-write - - - GT - desc GT - 15 - 8 - read-write - - - - - - - USART2 - 0x40004400 - - USART2 - USART2 global Interrupt - 28 - - - - USART3 - desc USART - USART - 0x40004800 - - 0x0 - 0x400 - registers - - - USART3_4 - USART3, 4 global Interrupts - 29 - - - - USART4 - desc USART - USART - 0x40004C00 - - 0x0 - 0x400 - registers - - - USART3_4 - USART3, 4 global Interrupts - 29 - - - - USB - USB - USB - 0x40005C00 - - 0x0 - 0x400 - registers - - - USB - USB global Interrupts - 31 - - - - CR - CR - CR - 0x0 - 0x20 - read-write - 0xFFFFFFFF - - - ADD - ADD - 0 - 7 - - - UPDATE - UPDATE - 7 - 1 - - - Enable_Suspend - Enable_Suspend - 8 - 1 - - - Suspend_Mode - Suspend_Mode - 9 - 1 - - - Resume - Resume - 10 - 1 - - - Reset - Reset - 11 - 1 - - - ISO_Update - ISO_Update - 15 - 1 - - - - - INTR - INTR - INTR - 0x4 - 0x20 - read-write - 0x00000000 - - - Suspend - Suspend - 0 - 1 - - - Resume - Resume - 1 - 1 - - - Reset - Reset - 2 - 1 - - - SOF - SOF - 3 - 1 - - - EP1OUT - EP1OUT - 9 - 1 - - - EP2OUT - EP2OUT - 10 - 1 - - - EP3OUT - EP3OUT - 11 - 1 - - - EP4OUT - EP4OUT - 12 - 1 - - - EP5OUT - EP5OUT - 13 - 1 - - - EP0 - EP0 - 16 - 1 - - - EP1IN - EP1IN - 17 - 1 - - - EP2IN - EP2IN - 18 - 1 - - - EP3IN - EP3IN - 19 - 1 - - - EP4IN - EP4IN - 20 - 1 - - - EP5IN - EP5IN - 21 - 1 - - - - - INTRE - INTRE - INTRE - 0x8 - 0x20 - read-write - 0x00000000 - - - EN_Suspend - EN_Suspend - 0 - 1 - - - EN_Resume - EN_Resume - 1 - 1 - - - EN_Reset - EN_Reset - 2 - 1 - - - EN_SOF - EN_SOF - 3 - 1 - - - EP1OUTE - EP1OUTE - 9 - 1 - - - EP2OUTE - EP2OUTE - 10 - 1 - - - EP3OUTE - EP3OUTE - 11 - 1 - - - EP4OUTE - EP4OUTE - 12 - 1 - - - EP5OUTE - EP5OUTE - 13 - 1 - - - EP0 - EP0 - 16 - 1 - - - EP1INE - EP1INE - 17 - 1 - - - EP2INE - EP2INE - 18 - 1 - - - EP3INE - EP3INE - 19 - 1 - - - EP4INE - EP4INE - 20 - 1 - - - EP5INE - EP5INE - 21 - 1 - - - - - FRAME - FRAME - FRAME - 0xC - 0x20 - write-only - 0x00000000 - - - FramNUM - FramNUM - 0 - 11 - - - INDEX - INDEX - 16 - 4 - - - - - EP0CSR - EP0CSR - EP0CSR - 0x10 - 0x20 - write-only - 0x00000000 - - - OutPktRdy - OutPktRdy - 0 - 1 - - - InPktRdy - InPktRdy - 1 - 1 - - - SentStall - SentStall - 2 - 1 - - - DataEnd - DataEnd - 3 - 1 - - - SetupEnd - SetupEnd - 4 - 1 - - - SendStall - OutPktRdy - 5 - 1 - - - ServicedOutPktRdy - ServicedOutPktRdy - 6 - 1 - - - ServicedSetupEnd - ServicedSetupEnd - 7 - 1 - - - COUNT0 - COUNT0 - 8 - 1 - - - - - INEPxCSR - INEPxCSR - INEPxCSR - 0x14 - 0x20 - write-only - 0x00000000 - - - FrcDataTog - FrcDataTog - 3 - 1 - - - DMAEnab - DMAEnab - 4 - 1 - - - Mode - Mode - 5 - 1 - - - ISO - ISO - 6 - 1 - - - AutoSet - AutoSet - 7 - 1 - - - InPktRdy - InPktRdy - 8 - 1 - - - FIFONotEmpty - FIFONotEmpty - 9 - 1 - - - UnderRun - UnderRun - 10 - 1 - - - FlushFIFO - FlushFIFO - 11 - 1 - - - SendStall - SendStall - 12 - 1 - - - SentStall - SentStall - 13 - 1 - - - ClrDataTog - ClrDataTog - 14 - 1 - - - INMAXP - INMAXP - 16 - 1 - - - - - OUTEPxCSR - OUTEPxCSR - OUTEPxCSR - 0x18 - 0x20 - write-only - 0x00000000 - - - DMAMode - DMAMode - 4 - 1 - - - DMAEnab - DMAEnab - 5 - 1 - - - ISO - ISO - 6 - 1 - - - AutoClear - AutoClear - 7 - 1 - - - OutPktRdy - OutPktRdy - 8 - 1 - - - FIFOFull - FIFOFull - 9 - 1 - - - OverRun - OverRun - 10 - 1 - - - DataError - DataError - 11 - 1 - - - FlushFIFO - FlushFIFO - 12 - 1 - - - SendStall - SendStall - 13 - 1 - - - SentStall - SentStall - 14 - 1 - - - ClrDataTog - ClrDataTog - 15 - 1 - - - INMAXP - INMAXP - 16 - 1 - - - - - OUTCOUNT - OUTCOUNT - OUTCOUNT - 0x1C - 0x20 - write-only - 0x00000000 - - - OUTCOUNT - OUTCOUNT - 0 - 10 - - - - - - - WWDG - Window watchdog - WWDG - 0x40002C00 - - 0x0 - 0x400 - registers - - - WWDG - Window WatchDog Interrupt - 0 - - - - CR - CR - Control register (WWDG_CR) - 0x0 - 0x20 - read-write - 0x0000007F - - - WDGA - Activation bit - 7 - 1 - - - T - 7-bit counter (MSB to LSB) - 0 - 7 - - - - - CFR - CFR - - Configuration register - (WWDG_CFR) - - 0x4 - 0x20 - read-write - 0x0000007F - - - EWI - Early Wakeup Interrupt - 9 - 1 - - - WDGTB - Timer Base - 7 - 2 - - - W - 7-bit window value - 0 - 7 - - - - - SR - SR - Status register (WWDG_SR) - 0x8 - 0x20 - read-write - 0x00000000 - - - EWIF - Early Wakeup Interrupt flag - 0 - 1 - - - - - - - + + + + Puya + Puya + PY32F0xx_DFP + + PY32F0 + 1.0.0 + Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. + + + + CM0+ + r0p1 + little + false + false + 4 + false + + + + 8 + + 32 + + + 32 + + read-write + + 0x00000000 + + 0xFFFFFFFF + + + + ADC + Analog to Digital Converter + ADC + 0x40012400 + + 0x0 + 0x400 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + SR + desc SR + 0x0 + 32 + read-write + 0x0 + + + AWD + desc AWD + 0 + 0 + read-write + + + EOC + desc EOC + 1 + 1 + read-write + + + JEOC + desc JEOC + 2 + 2 + read-write + + + JSTRT + desc JSTRT + 3 + 3 + read-write + + + STRT + desc STRT + 4 + 4 + read-write + + + OVER + desc OVER + 5 + 5 + read-write + + + + + CR1 + desc CR1 + 0x4 + 32 + read-write + 0x0 + + + AWDCH + desc AWDCH + 4 + 0 + read-write + + + EOCIE + desc EOCIE + 5 + 5 + read-write + + + AWDIE + desc AWDIE + 6 + 6 + read-write + + + JEOCIE + desc JEOCIE + 7 + 7 + read-write + + + SCAN + desc SCAN + 8 + 8 + read-write + + + AWDSGL + desc AWDSGL + 9 + 9 + read-write + + + JAUTO + desc JAUTO + 10 + 10 + read-write + + + DISCEN + desc DISCEN + 11 + 11 + read-write + + + JDISCEN + desc JDISCEN + 12 + 12 + read-write + + + DISCNUM + desc DISCNUM + 15 + 13 + read-write + + + JAWDEN + desc JAWDEN + 22 + 22 + read-write + + + AWDEN + desc AWDEN + 23 + 23 + read-write + + + RESSEL + desc RESSEL + 25 + 24 + read-write + + + ADSTP + desc ADSTP + 27 + 27 + read-write + + + MSBSEL + desc MSBSEL + 28 + 28 + read-write + + + OVETIE + desc OVETIE + 29 + 29 + read-write + + + + + CR2 + desc CR2 + 0x8 + 32 + read-write + 0x0 + + + ADON + desc ADON + 0 + 0 + read-write + + + CONT + desc CONT + 1 + 1 + read-write + + + CAL + desc CAL + 2 + 2 + read-write + + + RSTCAL + desc RSTCAL + 3 + 3 + read-write + + + DMA + desc DMA + 8 + 8 + read-write + + + ALIGN + desc ALIGN + 11 + 11 + read-write + + + JEXTSEL + desc JEXTSEL + 14 + 12 + read-write + + + JEXTTRIG + desc JEXTTRIG + 15 + 15 + read-write + + + EXTSEL + desc EXTSEL + 19 + 17 + read-write + + + EXTTRIG + desc EXTTRIG + 20 + 20 + read-write + + + JSWSTART + desc JSWSTART + 21 + 21 + read-write + + + SWSTART + desc SWSTART + 22 + 22 + read-write + + + TSVREFE + desc TSVREFE + 23 + 23 + read-write + + + VERFBUFFEREN + desc VERFBUFFEREN + 25 + 25 + read-write + + + VERFBUFFERSEL + desc VERFBUFFERSEL + 27 + 26 + read-write + + + + + SMPR1 + desc SMPR1 + 0xC + 32 + read-write + 0x0 + + + SMP20 + desc SMP20 + 2 + 0 + read-write + + + SMP21 + desc SMP21 + 5 + 3 + read-write + + + SMP22 + desc SMP22 + 8 + 6 + read-write + + + SMP23 + desc SMP23 + 11 + 9 + read-write + + + + + SMPR2 + desc SMPR2 + 0x10 + 32 + read-write + 0x0 + + + SMP10 + desc SMP10 + 2 + 0 + read-write + + + SMP11 + desc SMP11 + 5 + 3 + read-write + + + SMP12 + desc SMP12 + 8 + 6 + read-write + + + SMP13 + desc SMP13 + 11 + 9 + read-write + + + SMP14 + desc SMP14 + 14 + 12 + read-write + + + SMP15 + desc SMP15 + 17 + 15 + read-write + + + SMP16 + desc SMP16 + 20 + 18 + read-write + + + SMP17 + desc SMP17 + 23 + 21 + read-write + + + SMP18 + desc SMP18 + 26 + 24 + read-write + + + SMP19 + desc SMP19 + 29 + 27 + read-write + + + + + SMPR3 + desc SMPR2 + 0x14 + 32 + read-write + 0x0 + + + SMP0 + desc SMP0 + 2 + 0 + read-write + + + SMP1 + desc SMP1 + 5 + 3 + read-write + + + SMP2 + desc SMP2 + 8 + 6 + read-write + + + SMP3 + desc SMP3 + 11 + 9 + read-write + + + SMP4 + desc SMP4 + 14 + 12 + read-write + + + SMP5 + desc SMP5 + 17 + 15 + read-write + + + SMP6 + desc SMP6 + 20 + 18 + read-write + + + SMP7 + desc SMP7 + 23 + 21 + read-write + + + SMP8 + desc SMP8 + 26 + 24 + read-write + + + SMP9 + desc SMP9 + 29 + 27 + read-write + + + + + JOFR1 + desc JOFR1 + 0x18 + 32 + read-write + 0x0 + + + JOFFSET1 + desc JOFFSET1 + 11 + 0 + read-write + + + + + JOFR2 + desc JOFR2 + 0x1C + 32 + read-write + 0x0 + + + JOFFSET2 + desc JOFFSET2 + 11 + 0 + read-write + + + + + JOFR3 + desc JOFR3 + 0x20 + 32 + read-write + 0x0 + + + JOFFSET3 + desc JOFFSET3 + 11 + 0 + read-write + + + + + JOFR4 + desc JOFR4 + 0x24 + 32 + read-write + 0x0 + + + JOFFSET4 + desc JOFFSET4 + 11 + 0 + read-write + + + + + HTR + desc HTR + 0x28 + 32 + read-write + 0x0 + + + HT + desc HT + 11 + 0 + read-write + + + + + LTR + desc LTR + 0x2C + 32 + read-write + 0x0 + + + LT + desc LT + 11 + 0 + read-write + + + + + SQR1 + desc SQR1 + 0x30 + 32 + read-write + 0x0 + + + SQ13 + desc SQ13 + 4 + 0 + read-write + + + SQ14 + desc SQ14 + 9 + 5 + read-write + + + SQ15 + desc SQ15 + 14 + 10 + read-write + + + SQ16 + desc SQ16 + 19 + 15 + read-write + + + L + desc L + 23 + 20 + read-write + + + + + SQR2 + desc SQR2 + 0x34 + 32 + read-write + 0x0 + + + SQ7 + desc SQ7 + 4 + 0 + read-write + + + SQ8 + desc SQ8 + 9 + 5 + read-write + + + SQ9 + desc SQ9 + 14 + 10 + read-write + + + SQ10 + desc SQ10 + 19 + 15 + read-write + + + SQ11 + desc SQ11 + 24 + 20 + read-write + + + SQ12 + desc SQ12 + 29 + 25 + read-write + + + + + SQR3 + desc SQR3 + 0x38 + 32 + read-write + 0x0 + + + SQ1 + desc SQ1 + 4 + 0 + read-write + + + SQ2 + desc SQ2 + 9 + 5 + read-write + + + SQ3 + desc SQ3 + 14 + 10 + read-write + + + SQ4 + desc SQ4 + 19 + 15 + read-write + + + SQ5 + desc SQ5 + 24 + 20 + read-write + + + SQ6 + desc SQ6 + 29 + 25 + read-write + + + + + JSQR + desc JSQR + 0x3C + 32 + read-write + 0x0 + + + JSQ1 + desc JSQ1 + 4 + 0 + read-write + + + JSQ2 + desc JSQ2 + 9 + 5 + read-write + + + JSQ3 + desc JSQ3 + 14 + 10 + read-write + + + JSQ4 + desc JSQ4 + 19 + 15 + read-write + + + JL + desc JL + 21 + 20 + read-write + + + + + JDR1 + desc JDR1 + 0x40 + 32 + read-only + 0x0 + + + JDR1 + desc JDR1 + 15 + 0 + read-only + + + + + JDR2 + desc JDR2 + 0x44 + 32 + read-only + 0x0 + + + JDR2 + desc JDR2 + 15 + 0 + read-only + + + + + JDR3 + desc JDR3 + 0x48 + 32 + read-only + 0x0 + + + JDR3 + desc JDR3 + 15 + 0 + read-only + + + + + JDR4 + desc JDR4 + 0x4C + 32 + read-only + 0x0 + + + JDR4 + desc JDR4 + 15 + 0 + read-only + + + + + DR + desc DR + 0x50 + 32 + read-only + 0x0 + + + DATA + desc DATA + 15 + 0 + read-only + + + + + CCSR + desc CCSR + 0x54 + 32 + read-write + 0x0 + + + CALSEL + desc CALSEL + 11 + 11 + read-write + + + CALSMP + desc CALSMP + 13 + 12 + read-write + + + CALBYP + desc CALBYP + 14 + 14 + read-write + + + CALSET + desc CALSET + 15 + 15 + read-write + + + CALFAIL + desc CALFAIL + 30 + 30 + read-write + + + CALON + desc CALON + 31 + 31 + read-only + + + + + CALRR1 + desc CALRR1 + 0x58 + 32 + read-only + 0x0 + + + CALC10OUT + desc CALC10OUT + 7 + 0 + read-only + + + CALC11OUT + desc CALC11OUT + 15 + 8 + read-only + + + CALBOUT + desc CALBOUT + 23 + 16 + read-only + + + + + CALRR2 + desc CALRR2 + 0x5C + 32 + read-only + 0x0 + + + CALC6OUT + desc CALC6OUT + 7 + 0 + read-only + + + CALC7OUT + desc CALC7OUT + 15 + 8 + read-only + + + CALC8OUT + desc CALC8OUT + 23 + 16 + read-only + + + CALC9OUT + desc CALC9OUT + 31 + 24 + read-only + + + + + CALFIR1 + desc CALFIR1 + 0x60 + 32 + read-write + 0x0 + + + CALC10IO + desc CALC10IO + 7 + 0 + read-write + + + CALC11IO + desc CALC11IO + 15 + 8 + read-write + + + CALBIO + desc CALBIO + 23 + 16 + read-write + + + + + CALFIR2 + desc CALFIR2 + 0x64 + 32 + read-write + 0x0 + + + CALC6IO + desc CALC6IO + 7 + 0 + read-write + + + CALC7IO + desc CALC7IO + 15 + 8 + read-write + + + CALC8IO + desc CALC8IO + 23 + 16 + read-write + + + CALC9IO + desc CALC9IO + 31 + 24 + read-write + + + + + + + CAN + desc CAN + CAN + 0x40006400 + + 0x0 + 0x400 + registers + + + CAN + CAN global Interrupt + 30 + + + + TSNCR + desc TSNCR + 0x0 + 32 + read-write + 0x2010801 + + + VERSION + desc VERSION + 15 + 0 + read-only + + + CES + desc CES + 16 + 16 + read-write + + + ROP + desc ROP + 17 + 17 + read-write + + + TMSE + desc TMSE + 18 + 18 + read-write + + + TSEN + desc TSEN + 24 + 24 + read-write + + + TSPOS + desc TSPOS + 25 + 25 + read-write + + + + + ACBTR + desc ACBTR + 0x4 + 32 + read-write + 0x5050008 + + + AC_SEG_1 + desc AC_SEG_1 + 8 + 0 + read-write + + + AC_SEG_2 + desc AC_SEG_2 + 22 + 16 + read-write + + + AC_SJW + desc AC_SJW + 30 + 24 + read-write + + + + + FDBTR + desc FDBTR + 0x8 + 32 + read-write + 0x2020003 + + + FD_SEG_1 + desc FD_SEG_1 + 7 + 0 + read-write + + + FD_SEG_2 + desc FD_SEG_2 + 22 + 16 + read-write + + + FD_SJW + desc FD_SJW + 30 + 24 + read-write + + + + + XLBTR + desc XLBTR + 0xC + 32 + read-write + 0x2020003 + + + XL_SEG_1 + desc XL_SEG_1 + 7 + 0 + read-write + + + XL_SEG_2 + desc XL_SEG_2 + 22 + 16 + read-write + + + XL_SJW + desc XL_SJW + 30 + 24 + read-write + + + + + RLSSP + desc RLSSP + 0x10 + 32 + read-write + 0x77000000 + + + PRESC + desc PRESC + 4 + 0 + read-write + + + FD_SSPOFF + desc FD_SSPOFF + 15 + 8 + read-write + + + XL_SSPOFF + desc XL_SSPOFF + 23 + 16 + read-write + + + REALIM + desc REALIM + 26 + 24 + read-write + + + RETLIM + desc RETLIM + 30 + 28 + read-write + + + + + IFR + desc IFR + 0x14 + 32 + read-write + 0x0 + + + AIF + desc AIF + 0 + 0 + read-write + + + EIF + desc EIF + 1 + 1 + read-write + + + TSIF + desc TSIF + 2 + 2 + read-write + + + TPIF + desc TPIF + 3 + 3 + read-write + + + RAFIF + desc RAFIF + 4 + 4 + read-write + + + RFIF + desc RFIF + 5 + 5 + read-write + + + ROIF + desc ROIF + 6 + 6 + read-write + + + RIF + desc RIF + 7 + 7 + read-write + + + BEIF + desc BEIF + 8 + 8 + read-write + + + ALIF + desc ALIF + 9 + 9 + read-write + + + EPIF + desc EPIF + 10 + 10 + read-write + + + TTIF + desc TTIF + 11 + 11 + read-write + + + TEIF + desc TEIF + 12 + 12 + read-write + + + WTIF + desc WTIF + 13 + 13 + read-write + + + MDWIF + desc MDWIF + 14 + 14 + read-write + + + MDEIF + desc MDEIF + 15 + 15 + read-write + + + MAEIF + desc MAEIF + 16 + 16 + read-write + + + SEIF + desc SEIF + 17 + 17 + read-write + + + SWIF + desc SWIF + 18 + 18 + read-write + + + EPASS + desc EPASS + 30 + 30 + read-only + + + EWARN + desc EWARN + 31 + 31 + read-only + + + + + IER + desc IER + 0x18 + 32 + read-write + 0x468FE + + + EIE + desc EIE + 1 + 1 + read-write + + + TSIE + desc TSIE + 2 + 2 + read-write + + + TPIE + desc TPIE + 3 + 3 + read-write + + + RAFIE + desc RAFIE + 4 + 4 + read-write + + + RFIE + desc RFIE + 5 + 5 + read-write + + + ROIE + desc ROIE + 6 + 6 + read-write + + + RIE + desc RIE + 7 + 7 + read-write + + + BEIE + desc BEIE + 8 + 8 + read-write + + + ALIE + desc ALIE + 9 + 9 + read-write + + + EPIE + desc EPIE + 10 + 10 + read-write + + + TTIE + desc TTIE + 11 + 11 + read-write + + + WTIE + desc WTIE + 13 + 13 + read-write + + + MDWIE + desc MDWIE + 14 + 14 + read-write + + + SWIE + desc SWIE + 18 + 18 + read-write + + + + + TSR + desc TSR + 0x1C + 32 + read-only + 0x0 + + + HANDLE_L + desc HANDLE_L + 7 + 0 + read-only + + + TSTAT_L + desc TSTAT_L + 10 + 8 + read-only + + + HANDLE_H + desc HANDLE_H + 23 + 16 + read-only + + + TSTAT_H + desc TSTAT_H + 26 + 24 + read-only + + + + + TTSL + desc TTSL + 0x20 + 32 + read-only + 0x2000000 + + + TTS + desc TTS + 31 + 0 + read-only + + + + + TTSH + desc TTSH + 0x24 + 32 + read-only + 0x2000000 + + + TTS + desc TTS + 31 + 0 + read-only + + + + + MCR + desc MCR + 0x28 + 32 + read-write + 0x900080 + + + BUSOFF + desc BUSOFF + 0 + 0 + read-write + + + LBMI + desc LBMI + 5 + 5 + read-write + + + LBME + desc LBME + 6 + 6 + read-write + + + RESET + desc RESET + 7 + 7 + read-write + + + TSA + desc TSA + 8 + 8 + read-write + + + TSALL + desc TSALL + 9 + 9 + read-write + + + TSONE + desc TSONE + 10 + 10 + read-write + + + TPA + desc TPA + 11 + 11 + read-write + + + TPE + desc TPE + 12 + 12 + read-write + + + STBY + desc STBY + 13 + 13 + read-write + + + LOM + desc LOM + 14 + 14 + read-write + + + TBSEL + desc TBSEL + 15 + 15 + read-write + + + TSSTAT + desc TSSTAT + 17 + 16 + read-only + + + TSFF + desc TSFF + 18 + 18 + read-only + + + TTTBM + desc TTTBM + 20 + 20 + read-write + + + TSMODE + desc TSMODE + 21 + 21 + read-write + + + TSNEXT + desc TSNEXT + 22 + 22 + read-write + + + FD_ISO + desc FD_ISO + 23 + 23 + read-write + + + RSTAT + desc RSTAT + 25 + 24 + read-only + + + RBALL + desc RBALL + 27 + 27 + read-write + + + RREL + desc RREL + 28 + 28 + read-write + + + ROV + desc ROV + 29 + 29 + read-only + + + ROM + desc ROM + 30 + 30 + read-write + + + SACK + desc SACK + 31 + 31 + read-write + + + + + WECR + desc WECR + 0x2C + 32 + read-write + 0x1B + + + EWL + desc EWL + 3 + 0 + read-write + + + AFWL + desc AFWL + 7 + 4 + read-write + + + ALC + desc ALC + 12 + 8 + read-only + + + KOER + desc KOER + 15 + 13 + read-only + + + RECNT + desc RECNT + 23 + 16 + read-only + + + TECNT + desc TECNT + 31 + 24 + read-only + + + + + REFMSG + desc REFMSG + 0x30 + 32 + read-write + 0x0 + + + REF_ID + desc REF_ID + 28 + 0 + read-write + + + REF_IDE + desc REF_IDE + 31 + 31 + read-write + + + + + TTCR + desc TTCR + 0x34 + 32 + read-write + 0x0 + + + TTPTR + desc TTPTR + 5 + 0 + read-write + + + TTYPE + desc TTYPE + 10 + 8 + read-write + + + TEW + desc TEW + 15 + 12 + read-write + + + TBPTR + desc TBPTR + 21 + 16 + read-write + + + TBF + desc TBF + 22 + 22 + read-write + + + TBE + desc TBE + 23 + 23 + read-write + + + TTEN + desc TTEN + 24 + 24 + read-write + + + T_PRESC + desc T_PRESC + 26 + 25 + read-write + + + + + TTTR + desc TTTR + 0x38 + 32 + read-write + 0xFFFF0000 + + + TT_TRIG + desc TT_TRIG + 15 + 0 + read-write + + + TT_WTRIG + desc TT_WTRIG + 31 + 16 + read-write + + + + + SCMS + desc SCMS + 0x3C + 32 + read-write + 0x0 + + + XMREN + desc XMREN + 0 + 0 + read-write + + + FSTIM + desc FSTIM + 3 + 1 + read-write + + + ACFA + desc ACFA + 24 + 24 + read-write + + + TXS + desc TXS + 25 + 25 + read-only + + + TXB + desc TXB + 26 + 26 + read-only + + + HELOC + desc HELOC + 28 + 27 + read-only + + + MPEN + desc MPEN + 31 + 31 + read-write + + + + + MESR + desc MESR + 0x40 + 32 + read-write + 0x0 + + + MEBP1 + desc MEBP1 + 5 + 0 + read-write + + + ME1EE + desc ME1EE + 6 + 6 + read-write + + + MEAEE + desc MEAEE + 7 + 7 + read-write + + + MEBP2 + desc MEBP2 + 13 + 8 + read-write + + + ME2EE + desc ME2EE + 14 + 14 + read-write + + + MEEEC + desc MEEEC + 19 + 16 + read-write + + + MENEC + desc MENEC + 23 + 20 + read-write + + + MEL + desc MEL + 25 + 24 + read-write + + + MES + desc MES + 26 + 26 + read-write + + + + + ACFCR + desc ACFCR + 0x44 + 32 + read-write + 0x10000 + + + ACFADR + desc ACFADR + 3 + 0 + read-write + + + AE_0 + desc AE_0 + 16 + 16 + read-write + + + AE_1 + desc AE_1 + 17 + 17 + read-write + + + AE_2 + desc AE_2 + 18 + 18 + read-write + + + AE_3 + desc AE_3 + 19 + 19 + read-write + + + AE_4 + desc AE_4 + 20 + 20 + read-write + + + AE_5 + desc AE_5 + 21 + 21 + read-write + + + AE_6 + desc AE_6 + 22 + 22 + read-write + + + AE_7 + desc AE_7 + 23 + 23 + read-write + + + AE_8 + desc AE_8 + 24 + 24 + read-write + + + AE_9 + desc AE_9 + 25 + 25 + read-write + + + AE_10 + desc AE_10 + 26 + 26 + read-write + + + AE_11 + desc AE_11 + 27 + 27 + read-write + + + AE_12 + desc AE_12 + 28 + 28 + read-write + + + AE_13 + desc AE_13 + 29 + 29 + read-write + + + AE_14 + desc AE_14 + 30 + 30 + read-write + + + AE_15 + desc AE_15 + 31 + 31 + read-write + + + + + PWMCR + desc PWMCR + 0xB8 + 32 + read-write + 0x2080400 + + + PWMO + desc PWMO + 5 + 0 + read-write + + + PWMS + desc PWMS + 13 + 8 + read-write + + + PWML + desc PWML + 21 + 16 + read-write + + + + + + + COMP1 + Comparator 1 + COMP + 0x40010200 + + 0x0 + 0x10 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + COMP_OUT + Comparator output status + 30 + 1 + + + VCSEL + VCSEL + 27 + 1 + + + VCDIV_EN + VCDIV_EN + 26 + 1 + + + VCDIV + VCDIV + 20 + 6 + + + PWRMODE + + Comparator power mode + selector + + 18 + 2 + + + HYST + + Comparator hysteresis enable + selector + + 16 + 1 + + + POLARITY + + Comparator polarity + selector + + 15 + 1 + + + WINMODE + + Comparator non-inverting input + selector for window mode + + 11 + 1 + + + INPSEL + + Comparator signal selector for + non-inverting input + + 6 + 4 + + + INMSEL + + Comparator signal selector for + inverting input INM + + 2 + 4 + + + EN + COMP enable bit + 0 + 1 + + + + + FR + FR + + Comparator Filter + register + + 0x4 + 0x20 + read-write + 0x00000000 + + + FLTCNT1 + Comparator filter and counter + 16 + 16 + + + FLTEN1 + Filter enable bit + 0 + 1 + + + + + + + COMP2 + Comparator2 + COMP + 0x40010210 + + 0x0 + 0x10 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + COMP_OUT + Comparator output status + 30 + 1 + + + PWRMODE + + Comparator power mode + selector + + 18 + 2 + + + POLARITY + + Comparator polarity + selector + + 15 + 1 + + + WINMODE + + Comparator non-inverting input + selector for window mode + + 11 + 1 + + + INPSEL + + Comparator signal selector for + non-inverting input + + 6 + 4 + + + INMSEL + + Comparator signal selector for + inverting input INM + + 2 + 4 + + + HYST + + Comparator hysteresis enable + selector + + 1 + 1 + + + EN + COMP enable bit + 0 + 1 + + + + + FR + FR + + Comparator Filter + register + + 0x4 + 0x20 + read-write + 0x00000000 + + + FLTCNT2 + Comparator filter and counter + 16 + 16 + + + FLTEN2 + Filter enable bit + 0 + 1 + + + + + + + COMP3 + Comparator3 + COMP + 0x40010220 + + 0x0 + 0x10 + registers + + + ADC_COMP + ADC and COMP Interrupt through EXTI Lines 17 and 18 + 12 + + + + CSR + CSR + COMP control and status register + 0x0 + 0x20 + read-write + 0x00000000 + + + COMP_OUT + Comparator output status + 30 + 1 + + + PWRMODE + + Comparator power mode + selector + + 18 + 2 + + + POLARITY + + Comparator polarity + selector + + 15 + 1 + + + INPSEL + + Comparator signal selector for + non-inverting input + + 6 + 4 + + + INMSEL + + Comparator signal selector for + inverting input INM + + 2 + 4 + + + HYST + + Comparator hysteresis enable + selector + + 1 + 1 + + + EN + COMP enable bit + 0 + 1 + + + + + FR + FR + + Comparator Filter + register + + 0x4 + 0x20 + read-write + 0x00000000 + + + FLTCNT3 + Comparator filter and counter + 16 + 16 + + + FLTEN3 + Filter enable bit + 0 + 1 + + + + + + + CRC + CRC calculation unit + CRC + 0x40023000 + + 0x0 + 0x400 + registers + + + + DR + DR + Data register + 0x0 + 0x20 + read-write + 0xFFFFFFFF + + + DR + Data Register + 0 + 32 + + + + + IDR + IDR + Independent Data register + 0x4 + 0x20 + read-write + 0x00000000 + + + IDR + Independent Data register + 0 + 8 + + + + + CR + CR + Control register + 0x8 + 0x20 + write-only + 0x00000000 + + + RESET + Reset bit + 0 + 1 + + + + + + + CTC + desc CTC + CTC + 0x40006C00 + + 0x0 + 0x400 + registers + + + RCC_CTC + RCC and CTC global Interrupts + 4 + + + + CTL0 + desc CTL0 + 0x0 + 32 + read-write + 0x2000 + + + CKOKIE + desc CKOKIE + 0 + 0 + read-write + + + CKWARNIE + desc CKWARNIE + 1 + 1 + read-write + + + ERRIE + desc ERRIE + 2 + 2 + read-write + + + EREFIE + desc EREFIE + 3 + 3 + read-write + + + CNTEN + desc CNTEN + 5 + 5 + read-write + + + AUTOTRIM + desc AUTOTRIM + 6 + 6 + read-write + + + SWREFPUL + desc SWREFPUL + 7 + 7 + write-only + + + TRIMVALUE + desc TRIMVALUE + 13 + 8 + read-write + + + + + CTL1 + desc CTL1 + 0x4 + 32 + read-write + 0x2022BB7F + + + RLVALUE + desc RLVALUE + 15 + 0 + read-write + + + CKLIM + desc CKLIM + 23 + 16 + read-write + + + REFPSC + desc REFPSC + 26 + 24 + read-write + + + REFSEL + desc REFSEL + 29 + 28 + read-write + + + REFPOL + desc REFPOL + 31 + 31 + read-write + + + + + SR + desc SR + 0x8 + 32 + read-only + 0x0 + + + CKOKIF + desc CKOKIF + 0 + 0 + read-only + + + CKWARNIF + desc CKWARNIF + 1 + 1 + read-only + + + ERRIF + desc ERRIF + 2 + 2 + read-only + + + EREFIF + desc EREFIF + 3 + 3 + read-only + + + CKERR + desc CKERR + 8 + 8 + read-only + + + REFMISS + desc REFMISS + 9 + 9 + read-only + + + TRIMERR + desc TRIMERR + 10 + 10 + read-only + + + REFDIR + desc REFDIR + 15 + 15 + read-only + + + REFCAP + desc REFCAP + 31 + 16 + read-only + + + + + INTC + desc INTC + 0xC + 32 + write-only + 0x0 + + + CKOKIC + desc CKOKIC + 0 + 0 + write-only + + + CKWARNIC + desc CKWARNIC + 1 + 1 + write-only + + + ERRIC + desc ERRIC + 2 + 2 + write-only + + + EREFIC + desc EREFIC + 3 + 3 + write-only + + + + + + + DAC + desc DAC + DAC + 0x40007400 + + 0x0 + 0x400 + registers + + + TIM6_LPTIM1_DAC + TIM6, LPTIM1, DAC global Interrupts + 17 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x0 + + + EN1 + desc EN1 + 0 + 0 + read-write + + + BOFF1 + desc BOFF1 + 1 + 1 + read-write + + + TEN1 + desc TEN1 + 2 + 2 + read-write + + + TSEL1 + desc TSEL1 + 5 + 3 + read-write + + + WAVE1 + desc WAVE1 + 7 + 6 + read-write + + + MAMP1 + desc MAMP1 + 11 + 8 + read-write + + + DMAEN1 + desc DMAEN1 + 12 + 12 + read-write + + + DMAUDRIE1 + desc DMAUDRIE1 + 13 + 13 + read-write + + + DAC1CEN + desc DAC1CEN + 14 + 14 + read-write + + + EN2 + desc EN2 + 16 + 16 + read-write + + + BOFF2 + desc BOFF2 + 17 + 17 + read-write + + + TEN2 + desc TEN2 + 18 + 18 + read-write + + + TSEL2 + desc TSEL2 + 21 + 19 + read-write + + + WAVE2 + desc WAVE2 + 23 + 22 + read-write + + + MAMP2 + desc MAMP2 + 27 + 24 + read-write + + + DMAEN2 + desc DMAEN2 + 28 + 28 + read-write + + + DMAUDRIE2 + desc DMAUDRIE2 + 29 + 29 + read-write + + + DAC2CEN + desc DAC2CEN + 30 + 30 + read-write + + + + + SWTRIGR + desc SWTRIGR + 0x4 + 32 + write-only + 0x0 + + + SWTRIG1 + desc SWTRIG1 + 0 + 0 + write-only + + + SWTRIG2 + desc SWTRIG2 + 1 + 1 + write-only + + + + + DHR12R1 + desc DHR12R1 + 0x8 + 32 + read-write + 0x0 + + + DACC1DHR + desc DACC1DHR + 11 + 0 + read-write + + + + + DHR12L1 + desc DHR12L1 + 0xC + 32 + read-write + 0x0 + + + DACC1DHR + desc DACC1DHR + 14 + 3 + read-write + + + + + DHR8R1 + desc DHR8R1 + 0x10 + 32 + read-write + 0x0 + + + DACC1DHR + desc DACC1DHR + 7 + 0 + read-write + + + + + DHR12R2 + desc DHR12R2 + 0x14 + 32 + read-write + 0x0 + + + DACC2DHR + desc DACC2DHR + 11 + 0 + read-write + + + + + DHR12L2 + desc DHR12L2 + 0x18 + 32 + read-write + 0x0 + + + DACC2DHR + desc DACC2DHR + 15 + 4 + read-write + + + + + DHR8R2 + desc DHR8R2 + 0x1C + 32 + read-write + 0x0 + + + DACC2DHR + desc DACC2DHR + 7 + 0 + read-write + + + + + DHR12RD + desc DHR12RD + 0x20 + 32 + read-write + 0x0 + + + DACC1DHR + desc DACC1DHR + 11 + 0 + read-write + + + DACC2DHR + desc DACC2DHR + 27 + 16 + read-write + + + + + DHR12LD + desc DHR12LD + 0x24 + 32 + read-write + 0x0 + + + DACC1DHR + desc DACC1DHR + 15 + 4 + read-write + + + DACC2DHR + desc DACC2DHR + 31 + 20 + read-write + + + + + DHR8RD + desc DHR8RD + 0x28 + 32 + read-write + 0x0 + + + DACC1DHR + desc DACC1DHR + 7 + 0 + read-write + + + DACC2DHR + desc DACC2DHR + 15 + 8 + read-write + + + + + DOR1 + desc DOR1 + 0x2C + 32 + read-only + 0x0 + + + DACC1DOR + desc DACC1DOR + 11 + 0 + read-only + + + + + DOR2 + desc DOR2 + 0x30 + 32 + read-only + 0x0 + + + DACC2DOR + desc DACC2DOR + 11 + 0 + read-only + + + + + SR + desc SR + 0x34 + 32 + read-only + 0x0 + + + DMAUDR1 + desc DMAUDR1 + 13 + 13 + read-only + + + DMAUDR2 + desc DMAUDR2 + 29 + 29 + read-only + + + + + + + DBGMCU + Debug support + DBGMCU + 0x40015800 + + 0x0 + 0x400 + registers + + + + IDCODE + IDCODE + MCU Device ID Code Register + 0x0 + 0x20 + read-only + 0x0 + + + DBG_ID + DBG_ID + 0 + 16 + + + + + CR + CR + + Debug MCU Configuration + Register + + 0x4 + 0x20 + read-write + 0x0 + + + DBG_SLEEP + Debug Sleep Mode + 0 + 1 + + + DBG_STOP + Debug Stop Mode + 1 + 1 + + + + + APB_FZ1 + APB_FZ1 + APB Freeze Register1 + 0x8 + 0x20 + read-write + 0x0 + + + DBG_TIMER2_STOP + + Debug Timer 2 stopped when Core is + halted + + 0 + 1 + + + DBG_TIMER3_STOP + + Debug Timer 3 stopped when Core is + halted + + 1 + 1 + + + DBG_TIMER6_STOP + + Debug Timer 6 stopped when Core is + halted + + 4 + 1 + + + DBG_TIMER7_STOP + + Debug Timer 7 stopped when Core is + halted + + 5 + 1 + + + DBG_RTC_STOP + + Debug RTC stopped when Core is + halted + + 10 + 1 + + + DBG_WWDG_STOP + + Debug Window Wachdog stopped when Core + is halted + + 11 + 1 + + + DBG_IWDG_STOP + + Debug Independent Wachdog stopped when + Core is halted + + 12 + 1 + + + DBG_CAN_STOP + DBG_CAN_STOP + 19 + 1 + + + DBG_I2C1_SMBUS_TIMEOUT + DBG_I2C1_SMBUS_TIMEOUT + 21 + 1 + + + DBG_I2C2_SMBUS_TIMEOUT + DBG_I2C2_SMBUS_TIMEOUT + 22 + 1 + read-only + + + DBG_LPTIM_STOP + + Debug LPTIM stopped when Core is + halted + + 31 + 1 + + + + + APB_FZ2 + APB_FZ2 + APB Freeze Register2 + 0xC + 0x20 + read-write + 0x0 + + + DBG_TIMER1_STOP + + Debug Timer 1 stopped when Core is + halted + + 11 + 1 + + + DBG_TIMER14_STOP + + Debug Timer 14 stopped when Core is + halted + + 15 + 1 + + + DBG_TIMER15_STOP + + Debug Timer 15 stopped when Core is + halted + + 16 + 1 + + + DBG_TIMER16_STOP + + Debug Timer 16 stopped when Core is + halted + + 17 + 1 + + + DBG_TIMER17_STOP + + Debug Timer 17 stopped when Core is + halted + + 18 + 1 + + + + + + + DV + Divider + DV + 0x40023800 + + 0x0 + 0x400 + registers + + + + DEND + DEND + Dividend + 0x0 + 0x20 + read-write + 0x0 + + + DEND + Dividend + 0 + 32 + + + + + SOR + SOR + Divisor + 0x4 + 0x20 + read-write + 0x0 + + + SOR + Divisor + 0 + 32 + + + + + QUOT + QUOT + Quotient + 0x8 + 0x20 + read-only + 0x0 + + + QUOT + Quotient + 0 + 32 + + + + + REMA + REMA + Remainder + 0xC + 0x20 + read-only + 0x0 + + + REMA + Remainder + 0 + 32 + read-only + + + + + SIGN + SIGN + des SIGN + 0x10 + 0x20 + read-write + 0x0 + + + DIV_SIGN + des DIV_SIGN + 0 + 1 + + + + + STAT + STAT + des SIGN + 0x14 + 0x20 + read-write + 0x0 + + + DIV_END + des DIV_END + 0 + 1 + + + DIV_ZERO + des DIV_ZERO + 1 + 1 + + + + + + + DMA + Direct memory access + DMA + 0x40020000 + + 0x0 + 0x400 + registers + + + DMA1_Channel1 + DMA1 Channel 1 Interrupt + 9 + + + DMA1_Channel2_3 + DMA1 Channel 2 and Channel 3 Interrupt + 10 + + + DMA1_Channel4_5_6_7 + DMA1 Channel 4, 5, 6, 7 Interrupts + 11 + + + + ISR + desc ISR + 0x0 + 32 + read-only + 0x0 + + + GIF1 + desc GIF1 + 0 + 0 + read-only + + + TCIF1 + desc TCIF1 + 1 + 1 + read-only + + + HTIF1 + desc HTIF1 + 2 + 2 + read-only + + + TEIF1 + desc TEIF1 + 3 + 3 + read-only + + + GIF2 + desc GIF2 + 4 + 4 + read-only + + + TCIF2 + desc TCIF2 + 5 + 5 + read-only + + + HTIF2 + desc HTIF2 + 6 + 6 + read-only + + + TEIF2 + desc TEIF2 + 7 + 7 + read-only + + + GIF3 + desc GIF3 + 8 + 8 + read-only + + + TCIF3 + desc TCIF3 + 9 + 9 + read-only + + + HTIF3 + desc HTIF3 + 10 + 10 + read-only + + + TEIF3 + desc TEIF3 + 11 + 11 + read-only + + + GIF4 + desc GIF4 + 12 + 12 + read-only + + + TCIF4 + desc TCIF4 + 13 + 13 + read-only + + + HTIF4 + desc HTIF4 + 14 + 14 + read-only + + + TEIF4 + desc TEIF4 + 15 + 15 + read-only + + + GIF5 + desc GIF5 + 16 + 16 + read-only + + + TCIF5 + desc TCIF5 + 17 + 17 + read-only + + + HTIF5 + desc HTIF5 + 18 + 18 + read-only + + + TEIF5 + desc TEIF5 + 19 + 19 + read-only + + + GIF6 + desc GIF6 + 20 + 20 + read-only + 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0x28 + 32 + read-only + 0x0 + + + USB_CLK_EN + desc USB_CLK_EN + 0 + 0 + read-only + + + CAN_CLK_EN + desc CAN_CLK_EN + 1 + 1 + read-only + + + TIM2_CLK_EN + desc TIM2_CLK_EN + 2 + 2 + read-only + + + TIM3_CLK_EN + desc TIM3_CLK_EN + 3 + 3 + read-only + + + TIM7_CLK_EN + desc TIM7_CLK_EN + 4 + 4 + read-only + + + I2C2_CLK_EN + desc I2C2_CLK_EN + 5 + 5 + read-only + + + USART3_CLK_EN + desc USART3_CLK_EN + 6 + 6 + read-only + + + USART4_CLK_EN + desc USART4_CLK_EN + 7 + 7 + read-only + + + LCD_CLK_EN + desc LCD_CLK_EN + 8 + 8 + read-only + + + TIM14_CLK_EN + desc TIM14_CLK_EN + 9 + 9 + read-only + + + TIM15_CLK_EN + desc TIM15_CLK_EN + 10 + 10 + read-only + + + TIM17_CLK_EN + desc TIM17_CLK_EN + 11 + 11 + read-only + + + + + WRPR + desc WRPR + 0x2C + 32 + read-write + 0x0 + + + WRP + desc WRP + 15 + 0 + read-write + + + + + STCR + desc STCR + 0x90 + 32 + read-write + 0x00006400 + + + SLEEP_EN + desc SLEEP_EN + 0 + 0 + read-write + + + SLEEP_TIME + desc SLEEP_TIME + 15 + 8 + read-write + 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CHKRD3_PASS + 19 + 19 + read-only + + + + + TRMDR0 + desc TRMDR0 + 0x294 + 32 + read-only + 0x0 + + + BIAS_CR + desc BIAS_CR + 3 + 0 + read-only + + + TRIM_MR + desc TRIM_MR + 8 + 4 + read-only + + + TRIM_VREF + desc TRIM_VREF + 13 + 9 + read-only + + + TRIM_POR + desc TRIM_POR + 19 + 16 + read-only + + + TRIM_BG + desc TRIM_BG + 27 + 20 + read-only + + + + + TRMDR1 + desc TRMDR1 + 0x298 + 32 + read-only + 0x0 + + + LSI_TRIM + desc LSI_TRIM + 8 + 0 + read-only + + + HSI_TRIM + desc HSI_TRIM + 28 + 16 + read-only + + + HSI_FS + desc HSI_FS + 31 + 29 + read-only + + + + + TRMDR2 + desc TRMDR2 + 0x29C + 32 + read-only + 0x0 + + + FLASH_OP + desc FLASH_OP + 31 + 0 + read-only + + + + + TRMDR3 + desc TRMDR3 + 0x2A0 + 32 + read-only + 0x0 + + + FLASH_OP + desc FLASH_OP + 31 + 0 + read-only + + + + + TRMDR4 + desc TRMDR4 + 0x2A4 + 32 + read-only + 0x0 + + + FLASH_ERASE_VPOS + desc FLASH_ERASE_VPOS + 4 + 0 + read-only + + + FLASH_ERASE_VNEG + desc FLASH_ERASE_VNEG + 9 + 5 + read-only + + + FLASH_PROG_VPOS + desc FLASH_PROG_VPOS + 20 + 16 + read-only + + + FLASH_PROG_VNEG + desc FLASH_PROG_VNEG + 25 + 21 + read-only + + + + + TRMDR5 + desc TRMDR5 + 0x2A8 + 32 + read-only + 0x0 + + + FLASH_SIZE + desc FLASH_SIZE + 2 + 0 + read-only + + + SRAM_SIZE + desc SRAM_SIZE + 6 + 4 + read-only + + + TS_TRIM + desc TS_TRIM + 11 + 8 + read-only + + + + + TRMDR6 + desc TRMDR6 + 0x2AC + 32 + read-only + 0x0 + + + OPA0_TRIM + desc OPA0_TRIM + 3 + 0 + read-only + + + OPA1_TRIM + desc OPA1_TRIM + 7 + 4 + read-only + + + OPA2_TRIM + desc OPA2_TRIM + 11 + 8 + read-only + + + OPA3_TRIM + desc OPA3_TRIM + 15 + 12 + read-only + + + OPA4_TRIM + desc OPA4_TRIM + 19 + 16 + read-only + + + LCD_TRIM + desc LCD_TRIM + 27 + 20 + read-only + + + + + TRMDR7 + desc TRMDR7 + 0x2B0 + 32 + read-only + 0x0 + + + TS_DATA_0_TRIM + desc TS_DATA_0_TRIM + 11 + 0 + read-only + + + TS_DATA_1_TRIM + desc TS_DATA_1_TRIM + 23 + 12 + read-only + + + + + TRMDR8 + desc TRMDR8 + 0x2B4 + 32 + read-only + 0x0 + + + DAC_0_TRIM + desc DAC_0_TRIM + 11 + 0 + read-only + + + DAC_1_TRIM + desc DAC_1_TRIM + 23 + 12 + read-only + + + VREF_BUF_TRIM + desc VREF_BUF_TRIM + 28 + 24 + read-only + + + + + + + GPIOA + General-purpose I/Os + GPIO + 0x50000000 + + 0x0 + 0x400 + registers + + + + MODER + MODER + GPIO port mode register + 0x0 + 0x20 + read-write + 0xEBFFFFFF + + + MODE15 + + Port x configuration bits (y=0-15) + + 30 + 2 + + + MODE14 + + Port x configuration bits (y=0-15) + + 28 + 2 + + + MODE13 + + Port x configuration bits (y=0-15) + + 26 + 2 + + + MODE12 + + Port x configuration bits (y=0-15) + + 24 + 2 + + + MODE11 + + Port x configuration bits (y=0-15) + + 22 + 2 + + + MODE10 + + Port x configuration bits (y=0-15) + + 20 + 2 + + + MODE9 + + Port x configuration bits (y=0-15) + + 18 + 2 + + + MODE8 + + Port x configuration bits (y=0-15) + + 16 + 2 + + + MODE7 + + Port x configuration bits (y=0-15) + + 14 + 2 + + + MODE6 + + Port x configuration bits (y=0-15) + + 12 + 2 + + + MODE5 + + Port x configuration bits (y=0-15) + + 10 + 2 + + + MODE4 + + Port x configuration bits (y=0-15) + + 8 + 2 + + + MODE3 + + Port x configuration bits (y=0-15) + + 6 + 2 + + + MODE2 + + Port x configuration bits (y=0-15) + + 4 + 2 + + + MODE1 + + Port x configuration bits (y=0-15) + + 2 + 2 + + + MODE0 + + Port x configuration bits (y=0-15) + + 0 + 2 + + + + + OTYPER + OTYPER + GPIO port output type register + 0x4 + 0x20 + read-write + 0x00000000 + + + OT15 + + Port x configuration bits (y=0-15) + + 15 + 1 + + + OT14 + + Port x configuration bits (y=0-15) + + 14 + 1 + + + OT13 + + Port x configuration bits (y=0-15) + + 13 + 1 + + + OT12 + + Port x configuration bits (y=0-15) + + 12 + 1 + + + OT11 + + Port x configuration bits (y=0-15) + + 11 + 1 + + + OT10 + + Port x configuration bits (y=0-15) + + 10 + 1 + + + OT9 + + Port x configuration bits (y=0-15) + + 9 + 1 + + + OT8 + + Port x configuration bits (y=0-15) + + 8 + 1 + + + OT7 + + Port x configuration bits (y=0-15) + + 7 + 1 + + + OT6 + + Port x configuration bits (y=0-15) + + 6 + 1 + + + OT5 + + Port x configuration bits (y=0-15) + + 5 + 1 + + + OT4 + + Port x configuration bits (y=0-15) + + 4 + 1 + + + OT3 + + Port x configuration bits (y=0-15) + + 3 + 1 + + + OT2 + + Port x configuration bits (y=0-15) + + 2 + 1 + + + OT1 + + Port x configuration bits (y=0-15) + + 1 + 1 + + + OT0 + + Port x configuration bits (y=0-15) + + 0 + 1 + + + + + OSPEEDR + OSPEEDR + + GPIO port output speed + register + + 0x8 + 0x20 + read-write + 0x0C000000 + + + OSPEED15 + + Port x configuration bits (y=0-15) + + 30 + 2 + + + OSPEED14 + + Port x configuration bits (y=0-15) + + 28 + 2 + + + OSPEED13 + + Port x configuration bits (y=0-15) + + 26 + 2 + + + OSPEED12 + + Port x configuration bits (y=0-15) + + 24 + 2 + + + OSPEED11 + + Port x configuration bits (y=0-15) + + 22 + 2 + + + OSPEED10 + + Port x configuration bits (y=0-15) + + 20 + 2 + + + OSPEED9 + + Port x configuration bits (y=0-15) + + 18 + 2 + + + OSPEED8 + + Port x configuration bits (y=0-15) + + 16 + 2 + + + OSPEED7 + + Port x configuration bits (y=0-15) + + 14 + 2 + + + OSPEED6 + + Port x configuration bits (y=0-15) + + 12 + 2 + + + OSPEED5 + + Port x configuration bits (y=0-15) + + 10 + 2 + + + OSPEED4 + + Port x configuration bits (y=0-15) + + 8 + 2 + + + OSPEED3 + + Port x configuration bits (y=0-15) + + 6 + 2 + + + OSPEED2 + + Port x configuration bits (y=0-15) + + 4 + 2 + + + OSPEED1 + + Port x configuration bits (y=0-15) + + 2 + 2 + + + OSPEED0 + + Port x configuration bits (y=0-15) + + 0 + 2 + + + + + PUPDR + PUPDR + + GPIO port pull-up/pull-down + register + + 0xC + 0x20 + read-write + 0x24000000 + + + PUPD15 + + Port x configuration bits (y=0-15) + + 30 + 2 + + + PUPD14 + + Port x configuration bits (y=0-15) + + 28 + 2 + + + PUPD13 + + Port x configuration bits (y=0-15) + + 26 + 2 + + + PUPD12 + + Port x configuration bits (y=0-15) + + 24 + 2 + + + PUPD11 + + Port x configuration bits (y=0-15) + + 22 + 2 + + + PUPD10 + + Port x configuration bits (y=0-15) + + 20 + 2 + + + PUPD9 + + Port x configuration bits (y=0-15) + + 18 + 2 + + + PUPD8 + + Port x configuration bits (y=0-15) + + 16 + 2 + + + PUPD7 + + Port x configuration bits (y=0-15) + + 14 + 2 + + + PUPD6 + + Port x configuration bits (y=0-15) + + 12 + 2 + + + PUPD5 + + Port x configuration bits (y=0-15) + + 10 + 2 + + + PUPD4 + + Port x configuration bits (y=0-15) + + 8 + 2 + + + PUPD3 + + Port x configuration bits (y=0-15) + + 6 + 2 + + + PUPD2 + + Port x configuration bits (y=0-15) + + 4 + 2 + + + PUPD1 + + Port x configuration bits (y=0-15) + + 2 + 2 + + + PUPD0 + + Port x configuration bits (y=0-15) + + 0 + 2 + + + + + IDR + IDR + GPIO port input data register + 0x10 + 0x20 + read-only + 0x00000000 + + + ID15 + + Port input data (y=0-15) + + 15 + 1 + + + ID14 + + Port input data (y=0-15) + + 14 + 1 + + + ID13 + + Port input data (y=0-15) + + 13 + 1 + + + ID12 + + Port input data (y=0-15) + + 12 + 1 + + + ID11 + + Port input data (y=0-15) + + 11 + 1 + + + ID10 + + Port input data (y=0-15) + + 10 + 1 + + + ID9 + + Port input data (y=0-15) + + 9 + 1 + + + ID8 + + Port input data (y=0-15) + + 8 + 1 + + + ID7 + + Port input data (y=0-15) + + 7 + 1 + + + ID6 + + Port input data (y=0-15) + + 6 + 1 + + + ID5 + + Port input data (y=0-15) + + 5 + 1 + + + ID4 + + Port input data (y=0-15) + + 4 + 1 + + + ID3 + + Port input data (y=0-15) + + 3 + 1 + + + ID2 + + Port input data (y=0-15) + + 2 + 1 + + + ID1 + + Port input data (y=0-15) + + 1 + 1 + + + ID0 + + Port input data (y=0-15) + + 0 + 1 + + + + + ODR + ODR + GPIO port output data register + 0x14 + 0x20 + read-write + 0x00000000 + + + OD15 + + Port output data (y=0-15) + + 15 + 1 + + + OD14 + + Port output data (y=0-15) + + 14 + 1 + + + OD13 + + Port output data (y=0-15) + + 13 + 1 + + + OD12 + + Port output data (y=0-15) + + 12 + 1 + + + OD11 + + Port output data (y=0-15) + + 11 + 1 + + + OD10 + + Port output data (y=0-15) + + 10 + 1 + + + OD9 + + Port output data (y=0-15) + + 9 + 1 + + + OD8 + + Port output data (y=0-15) + + 8 + 1 + + + OD7 + + Port output data (y=0-15) + + 7 + 1 + + + OD6 + + Port output data (y=0-15) + + 6 + 1 + + + OD5 + + Port output data (y=0-15) + + 5 + 1 + + + OD4 + + Port output data (y=0-15) + + 4 + 1 + + + OD3 + + Port output data (y=0-15) + + 3 + 1 + + + OD2 + + Port output data (y=0-15) + + 2 + 1 + + + OD1 + + Port output data (y=0-15) + + 1 + 1 + + + OD0 + + Port output data (y=0-15) + + 0 + 1 + + + + + BSRR + BSRR + + GPIO port bit set/reset + register + + 0x18 + 0x20 + write-only + 0x00000000 + + + BR15 + + Port x reset bit y (y=0-15) + + 31 + 1 + + + BR14 + + Port x reset bit y (y=0-15) + + 30 + 1 + + + BR13 + + Port x reset bit y (y=0-15) + + 29 + 1 + + + BR12 + + Port x reset bit y (y=0-15) + + 28 + 1 + + + BR11 + + Port x reset bit y (y=0-15) + + 27 + 1 + + + BR10 + + Port x reset bit y (y=0-15) + + 26 + 1 + + + BR9 + + Port x reset bit y (y=0-15) + + 25 + 1 + + + BR8 + + Port x reset bit y (y=0-15) + + 24 + 1 + + + BR7 + + Port x reset bit y (y=0-15) + + 23 + 1 + + + BR6 + + Port x reset bit y (y=0-15) + + 22 + 1 + + + BR5 + + Port x reset bit y (y=0-15) + + 21 + 1 + + + BR4 + + Port x reset bit y (y=0-15) + + 20 + 1 + + + BR3 + + Port x reset bit y (y=0-15) + + 19 + 1 + + + BR2 + + Port x reset bit y (y=0-15) + + 18 + 1 + + + BR1 + + Port x reset bit y (y=0-15) + + 17 + 1 + + + BR0 + + Port x set bit y (y=0-15) + + 16 + 1 + + + BS15 + + Port x set bit y (y=0-15) + + 15 + 1 + + + BS14 + + Port x set bit y (y=0-15) + + 14 + 1 + + + BS13 + + Port x set bit y (y=0-15) + + 13 + 1 + + + BS12 + + Port x set bit y (y=0-15) + + 12 + 1 + + + BS11 + + Port x set bit y (y=0-15) + + 11 + 1 + + + BS10 + + Port x set bit y (y=0-15) + + 10 + 1 + + + BS9 + + Port x set bit y (y=0-15) + + 9 + 1 + + + BS8 + + Port x set bit y (y=0-15) + + 8 + 1 + + + BS7 + + Port x set bit y (y=0-15) + + 7 + 1 + + + BS6 + + Port x set bit y (y=0-15) + + 6 + 1 + + + BS5 + + Port x set bit y (y=0-15) + + 5 + 1 + + + BS4 + + Port x set bit y (y=0-15) + + 4 + 1 + + + BS3 + + Port x set bit y (y=0-15) + + 3 + 1 + + + BS2 + + Port x set bit y (y=0-15) + + 2 + 1 + + + BS1 + + Port x set bit y (y=0-15) + + 1 + 1 + + + BS0 + + Port x set bit y (y=0-15) + + 0 + 1 + + + + + LCKR + LCKR + + GPIO port configuration lock + register + + 0x1C + 0x20 + read-write + 0x00000000 + + + LCKK + + Port x lock (LCKK) + + 16 + 1 + + + LCK15 + + Port x lock bit y (y=0-15) + + 15 + 1 + + + LCK14 + + Port x lock bit y (y=0-15) + + 14 + 1 + + + LCK13 + + Port x lock bit y (y=0-15) + + 13 + 1 + + + LCK12 + + Port x lock bit y (y=0-15) + + 12 + 1 + + + LCK11 + + Port x lock bit y (y=0-15) + + 11 + 1 + + + LCK10 + + Port x lock bit y (y=0-15) + + 10 + 1 + + + LCK9 + + Port x lock bit y (y=0-15) + + 9 + 1 + + + LCK8 + + Port x lock bit y (y=0-15) + + 8 + 1 + + + LCK7 + + Port x lock bit y (y=0-15) + + 7 + 1 + + + LCK6 + + Port x lock bit y (y=0-15) + + 6 + 1 + + + LCK5 + + Port x lock bit y (y=0-15) + + 5 + 1 + + + LCK4 + + Port x lock bit y (y=0-15) + + 4 + 1 + + + LCK3 + + Port x lock bit y (y=0-15) + + 3 + 1 + + + LCK2 + + Port x lock bit y (y=0-15) + + 2 + 1 + + + LCK1 + + Port x lock bit y (y=0-15) + + 1 + 1 + + + LCK0 + + Port x lock bit y (y=0-15) + + 0 + 1 + + + + + AFRL + AFRL + + GPIO alternate function low + register + + 0x20 + 0x20 + read-write + 0x00000000 + + + AFSEL7 + + Alternate function selection for port x bit y (y=0-7) + + 28 + 4 + + + AFSEL6 + + Alternate function selection for port x bit y (y=0-7) + + 24 + 4 + + + AFSEL5 + + Alternate function selection for port x bit y (y=0-7) + + 20 + 4 + + + AFSEL4 + + Alternate function selection for port x bit y (y=0-7) + + 16 + 4 + + + AFSEL3 + + Alternate function selection for port x bit y (y=0-7) + + 12 + 4 + + + AFSEL2 + + Alternate function selection for port x bit y (y=0-7) + + 8 + 4 + + + AFSEL1 + + Alternate function selection for port x bit y (y=0-7) + + 4 + 4 + + + AFSEL0 + + Alternate function selection for port x bit y (y=0-7) + + 0 + 4 + + + + + AFRH + AFRH + + GPIO alternate function high + register + + 0x24 + 0x20 + read-write + 0x00000000 + + + AFSEL15 + + Alternate function selection for port x bit y (y=8-15) + + 28 + 4 + + + AFSEL14 + + Alternate function selection for port x bit y (y=8-15) + + 24 + 4 + + + AFSEL13 + + Alternate function selection for port x bit y (y=8-15) + + 20 + 4 + + + AFSEL12 + + Alternate function selection for port x bit y (y=8-15) + + 16 + 4 + + + AFSEL11 + + Alternate function selection for port x bit y (y=8-15) + + 12 + 4 + + + AFSEL10 + + Alternate function selection for port x bit y (y=8-15) + + 8 + 4 + + + AFSEL9 + + Alternate function selection for port x bit y (y=8-15) + + 4 + 4 + + + AFSEL8 + + Alternate function selection for port x bit y (y=8-15) + + 0 + 4 + + + + + BRR + BRR + port bit reset register + 0x28 + 0x20 + write-only + 0x00000000 + + + BR15 + Port Reset bit + 15 + 1 + + + BR14 + Port Reset bit + 14 + 1 + + + BR13 + Port Reset bit + 13 + 1 + + + BR12 + Port Reset bit + 12 + 1 + + + BR11 + Port Reset bit + 11 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desc CNTH + 0x18 + 32 + read-write + 0x0 + + + RTC_CNT + desc RTC_CNT + 15 + 0 + read-write + + + + + CNTL + desc CNTL + 0x1C + 32 + read-write + 0x0 + + + RTC_CNT + desc RTC_CNT + 15 + 0 + read-write + + + + + ALRH + desc ALRH + 0x20 + 32 + read-write + 0xFFFF + + + RTC_ALR + desc RTC_ALR + 15 + 0 + read-write + + + + + ALRL + desc ALRL + 0x24 + 32 + read-write + 0xFFFF + + + RTC_ALR + desc RTC_ALR + 15 + 0 + read-write + + + + + BKP_RTCCR + desc BKP_RTCCR + 0x2C + 32 + read-write + 0x0 + + + CAL + desc CAL + 6 + 0 + read-write + + + CCO + desc CCO + 7 + 7 + read-write + + + ASOE + desc ASOE + 8 + 8 + read-write + + + ASOS + desc ASOS + 9 + 9 + read-write + + + + + + + SPI1 + Serial peripheral interface + SPI + 0x40013000 + + 0x0 + 0x400 + registers + + + SPI1 + SPI1 global Interrupt + 25 + + + + CR1 + desc CR1 + 0x0 + 32 + read-write + 0x0 + + + CPHA + desc CPHA + 0 + 0 + read-write + + + CPOL + desc CPOL + 1 + 1 + read-write + + + MSTR + desc MSTR + 2 + 2 + read-write + + + BR + desc BR + 5 + 3 + read-write + + + SPE + desc SPE + 6 + 6 + read-write + + + LSBFIRST + desc LSBFIRST + 7 + 7 + read-write + + + SSI + desc SSI + 8 + 8 + read-write + + + SSM + desc SSM + 9 + 9 + read-write + + + RXONLY + desc RXONLY + 10 + 10 + read-write + + + DDF + desc DDF + 11 + 11 + read-write + + + CRCNEXT + desc CRCNEXT + 12 + 12 + read-write + + + CRCEN + desc CRCEN + 13 + 13 + read-write + + + BIDIOE + desc BIDIOE + 14 + 14 + read-write + + + BIDIMODE + desc BIDIMODE + 15 + 15 + read-write + + + + + CR2 + desc CR2 + 0x4 + 32 + read-write + 0x0 + + + RXDMAEN + desc RXDMAEN + 0 + 0 + read-write + + + TXDMAEN + desc TXDMAEN + 1 + 1 + read-write + + + SSOE + desc SSOE + 2 + 2 + read-write + + + CLRTXFIFO + desc CLRTXFIFO + 4 + 4 + read-write + + + ERRIE + desc ERRIE + 5 + 5 + read-write + + + RXNEIE + desc RXNEIE + 6 + 6 + read-write + + + TXEIE + desc TXEIE + 7 + 7 + read-write + + + FRXTH + desc FRXTH + 12 + 12 + read-write + + + LDMA_RX + desc LDMA_RX + 13 + 13 + read-write + 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TIM3_IC1_SRC + desc TIM3_IC1_SRC + 7 + 6 + read-write + + + ETR_SRC_TIM1 + desc ETR_SRC_TIM1 + 10 + 8 + read-write + + + ETR_SRC_TIM2 + desc ETR_SRC_TIM2 + 14 + 12 + read-write + + + ETR_SRC_TIM3 + desc ETR_SRC_TIM3 + 18 + 16 + read-write + + + GPIO_AHB_SEL + desc GPIO_AHB_SEL + 24 + 24 + read-write + + + + + CFGR2 + desc CFGR2 + 0x4 + 32 + read-write + 0x4 + + + LOCKUP_LOCK + desc LOCKUP_LOCK + 0 + 0 + read-write + + + PVD_LOCK + desc PVD_LOCK + 2 + 2 + read-write + + + COMP1_BRK_TIM1 + desc COMP1_BRK_TIM1 + 3 + 3 + read-write + + + COMP2_BRK_TIM1 + desc COMP2_BRK_TIM1 + 4 + 4 + read-write + + + COMP3_BRK_TIM1 + desc COMP3_BRK_TIM1 + 5 + 5 + read-write + + + COMP1_BRK_TIM15 + desc COMP1_BRK_TIM15 + 6 + 6 + read-write + + + COMP2_BRK_TIM15 + desc COMP2_BRK_TIM15 + 7 + 7 + read-write + + + COMP3_BRK_TIM15 + desc COMP3_BRK_TIM15 + 8 + 8 + read-write + + + COMP1_BRK_TIM16 + desc COMP1_BRK_TIM16 + 9 + 9 + read-write + + + COMP2_BRK_TIM16 + desc COMP2_BRK_TIM16 + 10 + 10 + read-write + + + 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0x8 + 32 + read-write + 0x0 + + + DMA1_MAP + desc DMA1_MAP + 5 + 0 + read-write + + + DMA2_MAP + desc DMA2_MAP + 13 + 8 + read-write + + + DMA3_MAP + desc DMA3_MAP + 21 + 16 + read-write + + + DMA4_MAP + desc DMA4_MAP + 29 + 24 + read-write + + + + + CFGR4 + desc CFGR4 + 0xC + 32 + read-write + 0x0 + + + DMA5_MAP + desc DMA5_MAP + 5 + 0 + read-write + + + DMA6_MAP + desc DMA6_MAP + 13 + 8 + read-write + + + DMA7_MAP + desc DMA7_MAP + 21 + 16 + read-write + + + + + PAENS + desc PAENS + 0x10 + 32 + read-write + 0x0 + + + PA_ENS + desc PA_ENS + 15 + 0 + read-write + + + + + PBENS + desc PBENS + 0x14 + 32 + read-write + 0x0 + + + PB_ENS + desc PB_ENS + 15 + 0 + read-write + + + + + PCENS + desc PCENS + 0x18 + 32 + read-write + 0x0 + + + PC_ENS + desc PC_ENS + 15 + 0 + read-write + + + + + PFENS + desc PFENS + 0x1C + 32 + read-write + 0x0 + + + PF_ENS + desc PF_ENS + 15 + 0 + read-write + + + + + EIIC + desc EIIC + 0x20 + 32 + read-write + 0x0 + + + PA_EIIC + desc PA_EIIC + 1 + 0 + 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+ SendStall + 13 + 1 + + + SentStall + SentStall + 14 + 1 + + + ClrDataTog + ClrDataTog + 15 + 1 + + + INMAXP + INMAXP + 16 + 1 + + + + + OUTCOUNT + OUTCOUNT + OUTCOUNT + 0x1C + 0x20 + write-only + 0x00000000 + + + OUTCOUNT + OUTCOUNT + 0 + 10 + + + + + + + WWDG + Window watchdog + WWDG + 0x40002C00 + + 0x0 + 0x400 + registers + + + WWDG + Window WatchDog Interrupt + 0 + + + + CR + CR + Control register (WWDG_CR) + 0x0 + 0x20 + read-write + 0x0000007F + + + WDGA + Activation bit + 7 + 1 + + + T + 7-bit counter (MSB to LSB) + 0 + 7 + + + + + CFR + CFR + + Configuration register + (WWDG_CFR) + + 0x4 + 0x20 + read-write + 0x0000007F + + + EWI + Early Wakeup Interrupt + 9 + 1 + + + WDGTB + Timer Base + 7 + 2 + + + W + 7-bit window value + 0 + 7 + + + + + SR + SR + Status register (WWDG_SR) + 0x8 + 0x20 + read-write + 0x00000000 + + + EWIF + Early Wakeup Interrupt flag + 0 + 1 + + + + + + + diff --git a/README.md b/README.md index 199bbb1..57a9fac 100644 --- a/README.md +++ b/README.md @@ -1,6 +1,18 @@ # py32f0-template -* Puya PY32F003/030 template project for GNU Arm Embedded Toolchain +* Puya PY32F0 template project for GNU Arm Embedded Toolchain +* Puya PY32F0 family: + * PY32F002x5 + * PY32F002Ax5 + * PY32F003x4 + * PY32F003x6 + * PY32F003x8 + * PY32F030x3 + * PY32F030x4 + * PY32F030x6 + * PY32F030x7 + * PY32F030x8 + * PY32F072xB * Supported programmers: J-Link, DAPLink/PyOCD * Supported IDE: VSCode @@ -8,6 +20,7 @@ ``` ├── Build # Build results +├── Docs # Datesheets and User Manuals ├── Examples │   ├── FreeRTOS # FreeRTOS examples │   ├── Raw # NonFreeRTOS examples @@ -16,12 +29,15 @@ │   ├── BSP # SysTick delay and printf for debug │   ├── BSP_LL # SysTick delay and printf for debug │   ├── CMSIS -│   ├── LDScripts # ld files +│   ├── LDScripts # LD files │   ├── PY32F0xx_HAL_Driver # MCU peripheral driver │   └── PY32F0xx_LL_Driver # MCU low layer peripheral driver ├── Makefile # Make config ├── Misc -│   └── Devices # FLM files +│   ├── Flash +│   │   ├── Devices # FLM files +│   │   └── Sources # Flash algorithm source code +│   └── SVD # SVD files ├── README.md ├── rules.mk # Pre-defined rules include in Makefile └── User # User application code @@ -29,7 +45,7 @@ # Requirements -* PY32F0 EVB or boards of PY32F003/030 series +* PY32F0 EVB or boards of PY32F002/003/030/072 series * Programmer * J-Link: J-Link OB programmer * PyOCD: DAPLink or J-Link @@ -59,11 +75,11 @@ sudo dpkg -i JLink_Linux_V770a_x86_64.deb ``` The default installation directory is */opt/SEGGER* -Copy all .FLM files from [Project directory]/Misc/Devices/Puya to [JLink directory]/Devices/Puya +Copy all .FLM files from [Project directory]/Misc/Flash/Devices/Puya to [JLink directory]/Devices/Puya ```bash cd py32f0-template -sudo cp -r Misc/Devices/* /opt/SEGGER/JLink/Devices/ +sudo cp -r Misc/Flash/Devices/* /opt/SEGGER/JLink/Devices/ ``` Edit JLinkDevices.xml