Puya Puya PY32F0xx_DFP PY32F0 1.0.0 Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz. CM0+ r0p1 little false false 4 false 8 32 32 read-write 0x00000000 0xFFFFFFFF ADC Analog to Digital Converter ADC 0x40012400 0x0 0x400 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 SR desc SR 0x0 32 read-write 0x0 AWD desc AWD 0 0 read-write EOC desc EOC 1 1 read-write JEOC desc JEOC 2 2 read-write JSTRT desc JSTRT 3 3 read-write STRT desc STRT 4 4 read-write OVER desc OVER 5 5 read-write CR1 desc CR1 0x4 32 read-write 0x0 AWDCH desc AWDCH 4 0 read-write EOCIE desc EOCIE 5 5 read-write AWDIE desc AWDIE 6 6 read-write JEOCIE desc JEOCIE 7 7 read-write SCAN desc SCAN 8 8 read-write AWDSGL desc AWDSGL 9 9 read-write JAUTO desc JAUTO 10 10 read-write DISCEN desc DISCEN 11 11 read-write JDISCEN desc JDISCEN 12 12 read-write DISCNUM desc DISCNUM 15 13 read-write JAWDEN desc JAWDEN 22 22 read-write AWDEN desc AWDEN 23 23 read-write RESSEL desc RESSEL 25 24 read-write ADSTP desc ADSTP 27 27 read-write MSBSEL desc MSBSEL 28 28 read-write OVETIE desc OVETIE 29 29 read-write CR2 desc CR2 0x8 32 read-write 0x0 ADON desc ADON 0 0 read-write CONT desc CONT 1 1 read-write CAL desc CAL 2 2 read-write RSTCAL desc RSTCAL 3 3 read-write DMA desc DMA 8 8 read-write ALIGN desc ALIGN 11 11 read-write JEXTSEL desc JEXTSEL 14 12 read-write JEXTTRIG desc JEXTTRIG 15 15 read-write EXTSEL desc EXTSEL 19 17 read-write EXTTRIG desc EXTTRIG 20 20 read-write JSWSTART desc JSWSTART 21 21 read-write SWSTART desc SWSTART 22 22 read-write TSVREFE desc TSVREFE 23 23 read-write VERFBUFFEREN desc VERFBUFFEREN 25 25 read-write VERFBUFFERSEL desc VERFBUFFERSEL 27 26 read-write SMPR1 desc SMPR1 0xC 32 read-write 0x0 SMP20 desc SMP20 2 0 read-write SMP21 desc SMP21 5 3 read-write SMP22 desc SMP22 8 6 read-write SMP23 desc SMP23 11 9 read-write SMPR2 desc SMPR2 0x10 32 read-write 0x0 SMP10 desc SMP10 2 0 read-write SMP11 desc SMP11 5 3 read-write SMP12 desc SMP12 8 6 read-write SMP13 desc SMP13 11 9 read-write SMP14 desc SMP14 14 12 read-write SMP15 desc SMP15 17 15 read-write SMP16 desc SMP16 20 18 read-write SMP17 desc SMP17 23 21 read-write SMP18 desc SMP18 26 24 read-write SMP19 desc SMP19 29 27 read-write SMPR3 desc SMPR2 0x14 32 read-write 0x0 SMP0 desc SMP0 2 0 read-write SMP1 desc SMP1 5 3 read-write SMP2 desc SMP2 8 6 read-write SMP3 desc SMP3 11 9 read-write SMP4 desc SMP4 14 12 read-write SMP5 desc SMP5 17 15 read-write SMP6 desc SMP6 20 18 read-write SMP7 desc SMP7 23 21 read-write SMP8 desc SMP8 26 24 read-write SMP9 desc SMP9 29 27 read-write JOFR1 desc JOFR1 0x18 32 read-write 0x0 JOFFSET1 desc JOFFSET1 11 0 read-write JOFR2 desc JOFR2 0x1C 32 read-write 0x0 JOFFSET2 desc JOFFSET2 11 0 read-write JOFR3 desc JOFR3 0x20 32 read-write 0x0 JOFFSET3 desc JOFFSET3 11 0 read-write JOFR4 desc JOFR4 0x24 32 read-write 0x0 JOFFSET4 desc JOFFSET4 11 0 read-write HTR desc HTR 0x28 32 read-write 0x0 HT desc HT 11 0 read-write LTR desc LTR 0x2C 32 read-write 0x0 LT desc LT 11 0 read-write SQR1 desc SQR1 0x30 32 read-write 0x0 SQ13 desc SQ13 4 0 read-write SQ14 desc SQ14 9 5 read-write SQ15 desc SQ15 14 10 read-write SQ16 desc SQ16 19 15 read-write L desc L 23 20 read-write SQR2 desc SQR2 0x34 32 read-write 0x0 SQ7 desc SQ7 4 0 read-write SQ8 desc SQ8 9 5 read-write SQ9 desc SQ9 14 10 read-write SQ10 desc SQ10 19 15 read-write SQ11 desc SQ11 24 20 read-write SQ12 desc SQ12 29 25 read-write SQR3 desc SQR3 0x38 32 read-write 0x0 SQ1 desc SQ1 4 0 read-write SQ2 desc SQ2 9 5 read-write SQ3 desc SQ3 14 10 read-write SQ4 desc SQ4 19 15 read-write SQ5 desc SQ5 24 20 read-write SQ6 desc SQ6 29 25 read-write JSQR desc JSQR 0x3C 32 read-write 0x0 JSQ1 desc JSQ1 4 0 read-write JSQ2 desc JSQ2 9 5 read-write JSQ3 desc JSQ3 14 10 read-write JSQ4 desc JSQ4 19 15 read-write JL desc JL 21 20 read-write JDR1 desc JDR1 0x40 32 read-only 0x0 JDR1 desc JDR1 15 0 read-only JDR2 desc JDR2 0x44 32 read-only 0x0 JDR2 desc JDR2 15 0 read-only JDR3 desc JDR3 0x48 32 read-only 0x0 JDR3 desc JDR3 15 0 read-only JDR4 desc JDR4 0x4C 32 read-only 0x0 JDR4 desc JDR4 15 0 read-only DR desc DR 0x50 32 read-only 0x0 DATA desc DATA 15 0 read-only CCSR desc CCSR 0x54 32 read-write 0x0 CALSEL desc CALSEL 11 11 read-write CALSMP desc CALSMP 13 12 read-write CALBYP desc CALBYP 14 14 read-write CALSET desc CALSET 15 15 read-write CALFAIL desc CALFAIL 30 30 read-write CALON desc CALON 31 31 read-only CALRR1 desc CALRR1 0x58 32 read-only 0x0 CALC10OUT desc CALC10OUT 7 0 read-only CALC11OUT desc CALC11OUT 15 8 read-only CALBOUT desc CALBOUT 23 16 read-only CALRR2 desc CALRR2 0x5C 32 read-only 0x0 CALC6OUT desc CALC6OUT 7 0 read-only CALC7OUT desc CALC7OUT 15 8 read-only CALC8OUT desc CALC8OUT 23 16 read-only CALC9OUT desc CALC9OUT 31 24 read-only CALFIR1 desc CALFIR1 0x60 32 read-write 0x0 CALC10IO desc CALC10IO 7 0 read-write CALC11IO desc CALC11IO 15 8 read-write CALBIO desc CALBIO 23 16 read-write CALFIR2 desc CALFIR2 0x64 32 read-write 0x0 CALC6IO desc CALC6IO 7 0 read-write CALC7IO desc CALC7IO 15 8 read-write CALC8IO desc CALC8IO 23 16 read-write CALC9IO desc CALC9IO 31 24 read-write CAN desc CAN CAN 0x40006400 0x0 0x400 registers CAN CAN global Interrupt 30 TSNCR desc TSNCR 0x0 32 read-write 0x2010801 VERSION desc VERSION 15 0 read-only CES desc CES 16 16 read-write ROP desc ROP 17 17 read-write TMSE desc TMSE 18 18 read-write TSEN desc TSEN 24 24 read-write TSPOS desc TSPOS 25 25 read-write ACBTR desc ACBTR 0x4 32 read-write 0x5050008 AC_SEG_1 desc AC_SEG_1 8 0 read-write AC_SEG_2 desc AC_SEG_2 22 16 read-write AC_SJW desc AC_SJW 30 24 read-write FDBTR desc FDBTR 0x8 32 read-write 0x2020003 FD_SEG_1 desc FD_SEG_1 7 0 read-write FD_SEG_2 desc FD_SEG_2 22 16 read-write FD_SJW desc FD_SJW 30 24 read-write XLBTR desc XLBTR 0xC 32 read-write 0x2020003 XL_SEG_1 desc XL_SEG_1 7 0 read-write XL_SEG_2 desc XL_SEG_2 22 16 read-write XL_SJW desc XL_SJW 30 24 read-write RLSSP desc RLSSP 0x10 32 read-write 0x77000000 PRESC desc PRESC 4 0 read-write FD_SSPOFF desc FD_SSPOFF 15 8 read-write XL_SSPOFF desc XL_SSPOFF 23 16 read-write REALIM desc REALIM 26 24 read-write RETLIM desc RETLIM 30 28 read-write IFR desc IFR 0x14 32 read-write 0x0 AIF desc AIF 0 0 read-write EIF desc EIF 1 1 read-write TSIF desc TSIF 2 2 read-write TPIF desc TPIF 3 3 read-write RAFIF desc RAFIF 4 4 read-write RFIF desc RFIF 5 5 read-write ROIF desc ROIF 6 6 read-write RIF desc RIF 7 7 read-write BEIF desc BEIF 8 8 read-write ALIF desc ALIF 9 9 read-write EPIF desc EPIF 10 10 read-write TTIF desc TTIF 11 11 read-write TEIF desc TEIF 12 12 read-write WTIF desc WTIF 13 13 read-write MDWIF desc MDWIF 14 14 read-write MDEIF desc MDEIF 15 15 read-write MAEIF desc MAEIF 16 16 read-write SEIF desc SEIF 17 17 read-write SWIF desc SWIF 18 18 read-write EPASS desc EPASS 30 30 read-only EWARN desc EWARN 31 31 read-only IER desc IER 0x18 32 read-write 0x468FE EIE desc EIE 1 1 read-write TSIE desc TSIE 2 2 read-write TPIE desc TPIE 3 3 read-write RAFIE desc RAFIE 4 4 read-write RFIE desc RFIE 5 5 read-write ROIE desc ROIE 6 6 read-write RIE desc RIE 7 7 read-write BEIE desc BEIE 8 8 read-write ALIE desc ALIE 9 9 read-write EPIE desc EPIE 10 10 read-write TTIE desc TTIE 11 11 read-write WTIE desc WTIE 13 13 read-write MDWIE desc MDWIE 14 14 read-write SWIE desc SWIE 18 18 read-write TSR desc TSR 0x1C 32 read-only 0x0 HANDLE_L desc HANDLE_L 7 0 read-only TSTAT_L desc TSTAT_L 10 8 read-only HANDLE_H desc HANDLE_H 23 16 read-only TSTAT_H desc TSTAT_H 26 24 read-only TTSL desc TTSL 0x20 32 read-only 0x2000000 TTS desc TTS 31 0 read-only TTSH desc TTSH 0x24 32 read-only 0x2000000 TTS desc TTS 31 0 read-only MCR desc MCR 0x28 32 read-write 0x900080 BUSOFF desc BUSOFF 0 0 read-write LBMI desc LBMI 5 5 read-write LBME desc LBME 6 6 read-write RESET desc RESET 7 7 read-write TSA desc TSA 8 8 read-write TSALL desc TSALL 9 9 read-write TSONE desc TSONE 10 10 read-write TPA desc TPA 11 11 read-write TPE desc TPE 12 12 read-write STBY desc STBY 13 13 read-write LOM desc LOM 14 14 read-write TBSEL desc TBSEL 15 15 read-write TSSTAT desc TSSTAT 17 16 read-only TSFF desc TSFF 18 18 read-only TTTBM desc TTTBM 20 20 read-write TSMODE desc TSMODE 21 21 read-write TSNEXT desc TSNEXT 22 22 read-write FD_ISO desc FD_ISO 23 23 read-write RSTAT desc RSTAT 25 24 read-only RBALL desc RBALL 27 27 read-write RREL desc RREL 28 28 read-write ROV desc ROV 29 29 read-only ROM desc ROM 30 30 read-write SACK desc SACK 31 31 read-write WECR desc WECR 0x2C 32 read-write 0x1B EWL desc EWL 3 0 read-write AFWL desc AFWL 7 4 read-write ALC desc ALC 12 8 read-only KOER desc KOER 15 13 read-only RECNT desc RECNT 23 16 read-only TECNT desc TECNT 31 24 read-only REFMSG desc REFMSG 0x30 32 read-write 0x0 REF_ID desc REF_ID 28 0 read-write REF_IDE desc REF_IDE 31 31 read-write TTCR desc TTCR 0x34 32 read-write 0x0 TTPTR desc TTPTR 5 0 read-write TTYPE desc TTYPE 10 8 read-write TEW desc TEW 15 12 read-write TBPTR desc TBPTR 21 16 read-write TBF desc TBF 22 22 read-write TBE desc TBE 23 23 read-write TTEN desc TTEN 24 24 read-write T_PRESC desc T_PRESC 26 25 read-write TTTR desc TTTR 0x38 32 read-write 0xFFFF0000 TT_TRIG desc TT_TRIG 15 0 read-write TT_WTRIG desc TT_WTRIG 31 16 read-write SCMS desc SCMS 0x3C 32 read-write 0x0 XMREN desc XMREN 0 0 read-write FSTIM desc FSTIM 3 1 read-write ACFA desc ACFA 24 24 read-write TXS desc TXS 25 25 read-only TXB desc TXB 26 26 read-only HELOC desc HELOC 28 27 read-only MPEN desc MPEN 31 31 read-write MESR desc MESR 0x40 32 read-write 0x0 MEBP1 desc MEBP1 5 0 read-write ME1EE desc ME1EE 6 6 read-write MEAEE desc MEAEE 7 7 read-write MEBP2 desc MEBP2 13 8 read-write ME2EE desc ME2EE 14 14 read-write MEEEC desc MEEEC 19 16 read-write MENEC desc MENEC 23 20 read-write MEL desc MEL 25 24 read-write MES desc MES 26 26 read-write ACFCR desc ACFCR 0x44 32 read-write 0x10000 ACFADR desc ACFADR 3 0 read-write AE_0 desc AE_0 16 16 read-write AE_1 desc AE_1 17 17 read-write AE_2 desc AE_2 18 18 read-write AE_3 desc AE_3 19 19 read-write AE_4 desc AE_4 20 20 read-write AE_5 desc AE_5 21 21 read-write AE_6 desc AE_6 22 22 read-write AE_7 desc AE_7 23 23 read-write AE_8 desc AE_8 24 24 read-write AE_9 desc AE_9 25 25 read-write AE_10 desc AE_10 26 26 read-write AE_11 desc AE_11 27 27 read-write AE_12 desc AE_12 28 28 read-write AE_13 desc AE_13 29 29 read-write AE_14 desc AE_14 30 30 read-write AE_15 desc AE_15 31 31 read-write PWMCR desc PWMCR 0xB8 32 read-write 0x2080400 PWMO desc PWMO 5 0 read-write PWMS desc PWMS 13 8 read-write PWML desc PWML 21 16 read-write COMP1 Comparator 1 COMP 0x40010200 0x0 0x10 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 CSR CSR COMP control and status register 0x0 0x20 read-write 0x00000000 COMP_OUT Comparator output status 30 1 VCSEL VCSEL 27 1 VCDIV_EN VCDIV_EN 26 1 VCDIV VCDIV 20 6 PWRMODE Comparator power mode selector 18 2 HYST Comparator hysteresis enable selector 16 1 POLARITY Comparator polarity selector 15 1 WINMODE Comparator non-inverting input selector for window mode 11 1 INPSEL Comparator signal selector for non-inverting input 6 4 INMSEL Comparator signal selector for inverting input INM 2 4 EN COMP enable bit 0 1 FR FR Comparator Filter register 0x4 0x20 read-write 0x00000000 FLTCNT1 Comparator filter and counter 16 16 FLTEN1 Filter enable bit 0 1 COMP2 Comparator2 COMP 0x40010210 0x0 0x10 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 CSR CSR COMP control and status register 0x0 0x20 read-write 0x00000000 COMP_OUT Comparator output status 30 1 PWRMODE Comparator power mode selector 18 2 POLARITY Comparator polarity selector 15 1 WINMODE Comparator non-inverting input selector for window mode 11 1 INPSEL Comparator signal selector for non-inverting input 6 4 INMSEL Comparator signal selector for inverting input INM 2 4 HYST Comparator hysteresis enable selector 1 1 EN COMP enable bit 0 1 FR FR Comparator Filter register 0x4 0x20 read-write 0x00000000 FLTCNT2 Comparator filter and counter 16 16 FLTEN2 Filter enable bit 0 1 COMP3 Comparator3 COMP 0x40010220 0x0 0x10 registers ADC_COMP ADC and COMP Interrupt through EXTI Lines 17 and 18 12 CSR CSR COMP control and status register 0x0 0x20 read-write 0x00000000 COMP_OUT Comparator output status 30 1 PWRMODE Comparator power mode selector 18 2 POLARITY Comparator polarity selector 15 1 INPSEL Comparator signal selector for non-inverting input 6 4 INMSEL Comparator signal selector for inverting input INM 2 4 HYST Comparator hysteresis enable selector 1 1 EN COMP enable bit 0 1 FR FR Comparator Filter register 0x4 0x20 read-write 0x00000000 FLTCNT3 Comparator filter and counter 16 16 FLTEN3 Filter enable bit 0 1 CRC CRC calculation unit CRC 0x40023000 0x0 0x400 registers DR DR Data register 0x0 0x20 read-write 0xFFFFFFFF DR Data Register 0 32 IDR IDR Independent Data register 0x4 0x20 read-write 0x00000000 IDR Independent Data register 0 8 CR CR Control register 0x8 0x20 write-only 0x00000000 RESET Reset bit 0 1 CTC desc CTC CTC 0x40006C00 0x0 0x400 registers RCC_CTC RCC and CTC global Interrupts 4 CTL0 desc CTL0 0x0 32 read-write 0x2000 CKOKIE desc CKOKIE 0 0 read-write CKWARNIE desc CKWARNIE 1 1 read-write ERRIE desc ERRIE 2 2 read-write EREFIE desc EREFIE 3 3 read-write CNTEN desc CNTEN 5 5 read-write AUTOTRIM desc AUTOTRIM 6 6 read-write SWREFPUL desc SWREFPUL 7 7 write-only TRIMVALUE desc TRIMVALUE 13 8 read-write CTL1 desc CTL1 0x4 32 read-write 0x2022BB7F RLVALUE desc RLVALUE 15 0 read-write CKLIM desc CKLIM 23 16 read-write REFPSC desc REFPSC 26 24 read-write REFSEL desc REFSEL 29 28 read-write REFPOL desc REFPOL 31 31 read-write SR desc SR 0x8 32 read-only 0x0 CKOKIF desc CKOKIF 0 0 read-only CKWARNIF desc CKWARNIF 1 1 read-only ERRIF desc ERRIF 2 2 read-only EREFIF desc EREFIF 3 3 read-only CKERR desc CKERR 8 8 read-only REFMISS desc REFMISS 9 9 read-only TRIMERR desc TRIMERR 10 10 read-only REFDIR desc REFDIR 15 15 read-only REFCAP desc REFCAP 31 16 read-only INTC desc INTC 0xC 32 write-only 0x0 CKOKIC desc CKOKIC 0 0 write-only CKWARNIC desc CKWARNIC 1 1 write-only ERRIC desc ERRIC 2 2 write-only EREFIC desc EREFIC 3 3 write-only DAC desc DAC DAC 0x40007400 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 CR desc CR 0x0 32 read-write 0x0 EN1 desc EN1 0 0 read-write BOFF1 desc BOFF1 1 1 read-write TEN1 desc TEN1 2 2 read-write TSEL1 desc TSEL1 5 3 read-write WAVE1 desc WAVE1 7 6 read-write MAMP1 desc MAMP1 11 8 read-write DMAEN1 desc DMAEN1 12 12 read-write DMAUDRIE1 desc DMAUDRIE1 13 13 read-write DAC1CEN desc DAC1CEN 14 14 read-write EN2 desc EN2 16 16 read-write BOFF2 desc BOFF2 17 17 read-write TEN2 desc TEN2 18 18 read-write TSEL2 desc TSEL2 21 19 read-write WAVE2 desc WAVE2 23 22 read-write MAMP2 desc MAMP2 27 24 read-write DMAEN2 desc DMAEN2 28 28 read-write DMAUDRIE2 desc DMAUDRIE2 29 29 read-write DAC2CEN desc DAC2CEN 30 30 read-write SWTRIGR desc SWTRIGR 0x4 32 write-only 0x0 SWTRIG1 desc SWTRIG1 0 0 write-only SWTRIG2 desc SWTRIG2 1 1 write-only DHR12R1 desc DHR12R1 0x8 32 read-write 0x0 DACC1DHR desc DACC1DHR 11 0 read-write DHR12L1 desc DHR12L1 0xC 32 read-write 0x0 DACC1DHR desc DACC1DHR 14 3 read-write DHR8R1 desc DHR8R1 0x10 32 read-write 0x0 DACC1DHR desc DACC1DHR 7 0 read-write DHR12R2 desc DHR12R2 0x14 32 read-write 0x0 DACC2DHR desc DACC2DHR 11 0 read-write DHR12L2 desc DHR12L2 0x18 32 read-write 0x0 DACC2DHR desc DACC2DHR 15 4 read-write DHR8R2 desc DHR8R2 0x1C 32 read-write 0x0 DACC2DHR desc DACC2DHR 7 0 read-write DHR12RD desc DHR12RD 0x20 32 read-write 0x0 DACC1DHR desc DACC1DHR 11 0 read-write DACC2DHR desc DACC2DHR 27 16 read-write DHR12LD desc DHR12LD 0x24 32 read-write 0x0 DACC1DHR desc DACC1DHR 15 4 read-write DACC2DHR desc DACC2DHR 31 20 read-write DHR8RD desc DHR8RD 0x28 32 read-write 0x0 DACC1DHR desc DACC1DHR 7 0 read-write DACC2DHR desc DACC2DHR 15 8 read-write DOR1 desc DOR1 0x2C 32 read-only 0x0 DACC1DOR desc DACC1DOR 11 0 read-only DOR2 desc DOR2 0x30 32 read-only 0x0 DACC2DOR desc DACC2DOR 11 0 read-only SR desc SR 0x34 32 read-only 0x0 DMAUDR1 desc DMAUDR1 13 13 read-only DMAUDR2 desc DMAUDR2 29 29 read-only DBGMCU Debug support DBGMCU 0x40015800 0x0 0x400 registers IDCODE IDCODE MCU Device ID Code Register 0x0 0x20 read-only 0x0 DBG_ID DBG_ID 0 16 CR CR Debug MCU Configuration Register 0x4 0x20 read-write 0x0 DBG_SLEEP Debug Sleep Mode 0 1 DBG_STOP Debug Stop Mode 1 1 APB_FZ1 APB_FZ1 APB Freeze Register1 0x8 0x20 read-write 0x0 DBG_TIMER2_STOP Debug Timer 2 stopped when Core is halted 0 1 DBG_TIMER3_STOP Debug Timer 3 stopped when Core is halted 1 1 DBG_TIMER6_STOP Debug Timer 6 stopped when Core is halted 4 1 DBG_TIMER7_STOP Debug Timer 7 stopped when Core is halted 5 1 DBG_RTC_STOP Debug RTC stopped when Core is halted 10 1 DBG_WWDG_STOP Debug Window Wachdog stopped when Core is halted 11 1 DBG_IWDG_STOP Debug Independent Wachdog stopped when Core is halted 12 1 DBG_CAN_STOP DBG_CAN_STOP 19 1 DBG_I2C1_SMBUS_TIMEOUT DBG_I2C1_SMBUS_TIMEOUT 21 1 DBG_I2C2_SMBUS_TIMEOUT DBG_I2C2_SMBUS_TIMEOUT 22 1 read-only DBG_LPTIM_STOP Debug LPTIM stopped when Core is halted 31 1 APB_FZ2 APB_FZ2 APB Freeze Register2 0xC 0x20 read-write 0x0 DBG_TIMER1_STOP Debug Timer 1 stopped when Core is halted 11 1 DBG_TIMER14_STOP Debug Timer 14 stopped when Core is halted 15 1 DBG_TIMER15_STOP Debug Timer 15 stopped when Core is halted 16 1 DBG_TIMER16_STOP Debug Timer 16 stopped when Core is halted 17 1 DBG_TIMER17_STOP Debug Timer 17 stopped when Core is halted 18 1 DV Divider DV 0x40023800 0x0 0x400 registers DEND DEND Dividend 0x0 0x20 read-write 0x0 DEND Dividend 0 32 SOR SOR Divisor 0x4 0x20 read-write 0x0 SOR Divisor 0 32 QUOT QUOT Quotient 0x8 0x20 read-only 0x0 QUOT Quotient 0 32 REMA REMA Remainder 0xC 0x20 read-only 0x0 REMA Remainder 0 32 read-only SIGN SIGN des SIGN 0x10 0x20 read-write 0x0 DIV_SIGN des DIV_SIGN 0 1 STAT STAT des SIGN 0x14 0x20 read-write 0x0 DIV_END des DIV_END 0 1 DIV_ZERO des DIV_ZERO 1 1 DMA Direct memory access DMA 0x40020000 0x0 0x400 registers DMA1_Channel1 DMA1 Channel 1 Interrupt 9 DMA1_Channel2_3 DMA1 Channel 2 and Channel 3 Interrupt 10 DMA1_Channel4_5_6_7 DMA1 Channel 4, 5, 6, 7 Interrupts 11 ISR desc ISR 0x0 32 read-only 0x0 GIF1 desc GIF1 0 0 read-only TCIF1 desc TCIF1 1 1 read-only HTIF1 desc HTIF1 2 2 read-only TEIF1 desc TEIF1 3 3 read-only GIF2 desc GIF2 4 4 read-only TCIF2 desc TCIF2 5 5 read-only HTIF2 desc HTIF2 6 6 read-only TEIF2 desc TEIF2 7 7 read-only GIF3 desc GIF3 8 8 read-only TCIF3 desc TCIF3 9 9 read-only HTIF3 desc HTIF3 10 10 read-only TEIF3 desc TEIF3 11 11 read-only GIF4 desc GIF4 12 12 read-only TCIF4 desc TCIF4 13 13 read-only HTIF4 desc HTIF4 14 14 read-only TEIF4 desc TEIF4 15 15 read-only GIF5 desc GIF5 16 16 read-only TCIF5 desc TCIF5 17 17 read-only HTIF5 desc HTIF5 18 18 read-only TEIF5 desc TEIF5 19 19 read-only GIF6 desc GIF6 20 20 read-only TCIF6 desc TCIF6 21 21 read-only HTIF6 desc HTIF6 22 22 read-only TEIF6 desc TEIF6 23 23 read-only GIF7 desc GIF7 24 24 read-only TCIF7 desc TCIF7 25 25 read-only HTIF7 desc HTIF7 26 26 read-only TEIF7 desc TEIF7 27 27 read-only IFCR desc IFCR 0x4 32 write-only 0x0 CGIF1 desc CGIF1 0 0 write-only CTCIF1 desc CTCIF1 1 1 write-only CHTIF1 desc CHTIF1 2 2 write-only CTEIF1 desc CTEIF1 3 3 write-only CGIF2 desc CGIF2 4 4 write-only CTCIF2 desc CTCIF2 5 5 write-only CHTIF2 desc CHTIF2 6 6 write-only CTEIF2 desc CTEIF2 7 7 write-only CGIF3 desc CGIF3 8 8 write-only CTCIF3 desc CTCIF3 9 9 write-only CHTIF3 desc CHTIF3 10 10 write-only CTEIF3 desc CTEIF3 11 11 write-only CGIF4 desc CGIF4 12 12 write-only CTCIF4 desc CTCIF4 13 13 write-only CHTIF4 desc CHTIF4 14 14 write-only CTEIF4 desc CTEIF4 15 15 write-only CGIF5 desc CGIF5 16 16 write-only CTCIF5 desc CTCIF5 17 17 write-only CHTIF5 desc CHTIF5 18 18 write-only CTEIF5 desc CTEIF5 19 19 write-only CGIF6 desc CGIF6 20 20 write-only CTCIF6 desc CTCIF6 21 21 write-only CHTIF6 desc CHTIF6 22 22 write-only CTEIF6 desc CTEIF6 23 23 write-only CGIF7 desc CGIF7 24 24 write-only CTCIF7 desc CTCIF7 25 25 write-only CHTIF7 desc CHTIF7 26 26 write-only CTEIF7 desc CTEIF7 27 27 write-only CCR1 desc CCR1 0x8 32 read-write 0x0 EN desc EN 0 0 read-write TCIE desc TCIE 1 1 read-write HTIE desc HTIE 2 2 read-write TEIE desc TEIE 3 3 read-write DIR desc DIR 4 4 read-write CIRC desc CIRC 5 5 read-write PINC desc PINC 6 6 read-write MINC desc MINC 7 7 read-write PSIZE desc PSIZE 9 8 read-write MSIZE desc MSIZE 11 10 read-write PL desc PL 13 12 read-write MEM2MEM desc MEM2MEM 14 14 read-write CNDTR1 desc CNDTR1 0xC 32 read-write 0x0 NDT desc NDT 15 0 read-write CPAR1 desc CPAR1 0x10 32 read-write 0x0 PA desc PA 31 0 read-write CMAR1 desc CMAR1 0x14 32 read-write 0x0 MA desc MA 31 0 read-write CCR2 desc CCR2 0x1C 32 read-write 0x0 EN desc EN 0 0 read-write TCIE desc TCIE 1 1 read-write HTIE desc HTIE 2 2 read-write TEIE desc TEIE 3 3 read-write DIR desc DIR 4 4 read-write CIRC desc CIRC 5 5 read-write PINC desc PINC 6 6 read-write MINC desc MINC 7 7 read-write PSIZE desc PSIZE 9 8 read-write MSIZE desc MSIZE 11 10 read-write PL desc PL 13 12 read-write MEM2MEM desc MEM2MEM 14 14 read-write CNDTR2 desc CNDTR2 0x20 32 read-write 0x0 NDT desc NDT 15 0 read-write CPAR2 desc CPAR2 0x24 32 read-write 0x0 PA desc PA 31 0 read-write CMAR2 desc CMAR2 0x28 32 read-write 0x0 MA desc MA 31 0 read-write CCR3 desc CCR3 0x30 32 read-write 0x0 EN desc EN 0 0 read-write TCIE desc TCIE 1 1 read-write HTIE desc HTIE 2 2 read-write TEIE desc TEIE 3 3 read-write DIR desc DIR 4 4 read-write CIRC desc CIRC 5 5 read-write PINC desc PINC 6 6 read-write MINC desc MINC 7 7 read-write PSIZE desc PSIZE 9 8 read-write MSIZE desc MSIZE 11 10 read-write PL desc PL 13 12 read-write MEM2MEM desc MEM2MEM 14 14 read-write CNDTR3 desc CNDTR3 0x34 32 read-write 0x0 NDT desc NDT 15 0 read-write CPAR3 desc CPAR3 0x38 32 read-write 0x0 PA desc PA 31 0 read-write CMAR3 desc CMAR3 0x3C 32 read-write 0x0 MA desc MA 31 0 read-write CCR4 desc CCR4 0x44 32 read-write 0x0 EN desc EN 0 0 read-write TCIE desc TCIE 1 1 read-write HTIE desc HTIE 2 2 read-write TEIE desc TEIE 3 3 read-write DIR desc DIR 4 4 read-write CIRC desc CIRC 5 5 read-write PINC desc PINC 6 6 read-write MINC desc MINC 7 7 read-write PSIZE desc PSIZE 9 8 read-write MSIZE desc MSIZE 11 10 read-write PL desc PL 13 12 read-write MEM2MEM desc MEM2MEM 14 14 read-write CNDTR4 desc CNDTR4 0x48 32 read-write 0x0 NDT desc NDT 15 0 read-write CPAR4 desc CPAR4 0x4C 32 read-write 0x0 PA desc PA 31 0 read-write CMAR4 desc CMAR4 0x50 32 read-write 0x0 MA desc MA 31 0 read-write CCR5 desc CCR5 0x58 32 read-write 0x0 EN desc EN 0 0 read-write TCIE desc TCIE 1 1 read-write HTIE desc HTIE 2 2 read-write TEIE desc TEIE 3 3 read-write DIR desc DIR 4 4 read-write CIRC desc CIRC 5 5 read-write PINC desc PINC 6 6 read-write MINC desc MINC 7 7 read-write PSIZE desc PSIZE 9 8 read-write MSIZE desc MSIZE 11 10 read-write PL desc PL 13 12 read-write MEM2MEM desc MEM2MEM 14 14 read-write CNDTR5 desc CNDTR5 0x5C 32 read-write 0x0 NDT desc NDT 15 0 read-write CPAR5 desc CPAR5 0x60 32 read-write 0x0 PA desc PA 31 0 read-write CMAR5 desc CMAR5 0x64 32 read-write 0x0 MA desc MA 31 0 read-write CCR6 desc CCR6 0x6C 32 read-write 0x0 EN desc EN 0 0 read-write TCIE desc TCIE 1 1 read-write HTIE desc HTIE 2 2 read-write TEIE desc TEIE 3 3 read-write DIR desc DIR 4 4 read-write CIRC desc CIRC 5 5 read-write PINC desc PINC 6 6 read-write MINC desc MINC 7 7 read-write PSIZE desc PSIZE 9 8 read-write MSIZE desc MSIZE 11 10 read-write PL desc PL 13 12 read-write MEM2MEM desc MEM2MEM 14 14 read-write CNDTR6 desc CNDTR6 0x70 32 read-write 0x0 NDT desc NDT 15 0 read-write CPAR6 desc CPAR6 0x74 32 read-write 0x0 PA desc PA 31 0 read-write CMAR6 desc CMAR6 0x78 32 read-write 0x0 MA desc MA 31 0 read-write CCR7 desc CCR7 0x80 32 read-write 0x0 EN desc EN 0 0 read-write TCIE desc TCIE 1 1 read-write HTIE desc HTIE 2 2 read-write TEIE desc TEIE 3 3 read-write DIR desc DIR 4 4 read-write CIRC desc CIRC 5 5 read-write PINC desc PINC 6 6 read-write MINC desc MINC 7 7 read-write PSIZE desc PSIZE 9 8 read-write MSIZE desc MSIZE 11 10 read-write PL desc PL 13 12 read-write MEM2MEM desc MEM2MEM 14 14 read-write CNDTR7 desc CNDTR7 0x84 32 read-write 0x0 NDT desc NDT 15 0 read-write CPAR7 desc CPAR7 0x88 32 read-write 0x0 PA desc PA 31 0 read-write CMAR7 desc CMAR7 0x8C 32 read-write 0x0 MA desc MA 31 0 read-write EXTI External interrupt/event controller EXTI 0x40021800 0x0 0x400 registers PVD PVD Interrupt through EXTI Lines 16 1 EXTI0_1 EXTI Line 0 and 1 Interrupt 5 EXTI2_3 EXTI Line 2 and 3 Interrupt 6 EXTI4_15 EXTI Line 4 to 15 Interrupt 7 RTSR RTSR EXTI rising trigger selection register 0x0 0x20 read-write 0x00000000 RT20 Rising trigger event configuration bit of Configurable Event input 20 1 RT19 Rising trigger event configuration bit of Configurable Event input 19 1 RT18 Rising trigger event configuration bit of Configurable Event input 18 1 RT17 Rising trigger event configuration bit of Configurable Event input 17 1 RT16 Rising trigger event configuration bit of Configurable Event input 16 1 RT15 Rising trigger event configuration bit of Configurable Event input 15 1 RT14 Rising trigger event configuration bit of Configurable Event input 14 1 RT13 Rising trigger event configuration bit of Configurable Event input 13 1 RT12 Rising trigger event configuration bit of Configurable Event input 12 1 RT11 Rising trigger event configuration bit of Configurable Event input 11 1 RT10 Rising trigger event configuration bit of Configurable Event input 10 1 RT9 Rising trigger event configuration bit of Configurable Event input 9 1 RT8 Rising trigger event configuration bit of Configurable Event input 8 1 RT7 Rising trigger event configuration bit of Configurable Event input 7 1 RT6 Rising trigger event configuration bit of Configurable Event input 6 1 RT5 Rising trigger event configuration bit of Configurable Event input 5 1 RT4 Rising trigger event configuration bit of Configurable Event input 4 1 RT3 Rising trigger event configuration bit of Configurable Event input 3 1 RT2 Rising trigger event configuration bit of Configurable Event input 2 1 RT1 Rising trigger event configuration bit of Configurable Event input 1 1 RT0 Rising trigger event configuration bit of Configurable Event input 0 1 FTSR FTSR EXTI falling trigger selection register 0x4 0x20 read-write 0x00000000 FT20 Falling trigger event configuration bit of Configurable Event input 20 1 FT19 Falling trigger event configuration bit of Configurable Event input 19 1 FT18 Falling trigger event configuration bit of Configurable Event input 18 1 FT17 Falling trigger event configuration bit of Configurable Event input 17 1 FT16 Falling trigger event configuration bit of Configurable Event input 16 1 FT15 Falling trigger event configuration bit of Configurable Event input 15 1 FT14 Falling trigger event configuration bit of Configurable Event input 14 1 FT13 Falling trigger event configuration bit of Configurable Event input 13 1 FT12 Falling trigger event configuration bit of Configurable Event input 12 1 FT11 Falling trigger event configuration bit of Configurable Event input 11 1 FT10 Falling trigger event configuration bit of Configurable Event input 10 1 FT9 Falling trigger event configuration bit of Configurable Event input 9 1 FT8 Falling trigger event configuration bit of Configurable Event input 8 1 FT7 Falling trigger event configuration bit of Configurable Event input 7 1 FT6 Falling trigger event configuration bit of Configurable Event input 6 1 FT5 Falling trigger event configuration bit of Configurable Event input 5 1 FT4 Falling trigger event configuration bit of Configurable Event input 4 1 FT3 Falling trigger event configuration bit of Configurable Event input 3 1 FT2 Falling trigger event configuration bit of Configurable Event input 2 1 FT1 Falling trigger event configuration bit of Configurable Event input 1 1 FT0 Falling trigger event configuration bit of Configurable Event input 0 1 SWIER SWIER EXTI software interrupt event register 0x8 0x20 read-write 0x00000000 SWI20 Rising trigger event configuration bit of Configurable Event input 20 1 SWI19 Rising trigger event configuration bit of Configurable Event input 19 1 SWI18 Rising trigger event configuration bit of Configurable Event input 18 1 SWI17 Rising trigger event configuration bit of Configurable Event input 17 1 SWI16 Rising trigger event configuration bit of Configurable Event input 16 1 SWI15 Rising trigger event configuration bit of Configurable Event input 15 1 SWI14 Rising trigger event configuration bit of Configurable Event input 14 1 SWI13 Rising trigger event configuration bit of Configurable Event input 13 1 SWI12 Rising trigger event configuration bit of Configurable Event input 12 1 SWI11 Rising trigger event configuration bit of Configurable Event input 11 1 SWI10 Rising trigger event configuration bit of Configurable Event input 10 1 SWI9 Rising trigger event configuration bit of Configurable Event input 9 1 SWI8 Rising trigger event configuration bit of Configurable Event input 8 1 SWI7 Rising trigger event configuration bit of Configurable Event input 7 1 SWI6 Rising trigger event configuration bit of Configurable Event input 6 1 SWI5 Rising trigger event configuration bit of Configurable Event input 5 1 SWI4 Rising trigger event configuration bit of Configurable Event input 4 1 SWI3 Rising trigger event configuration bit of Configurable Event input 3 1 SWI2 Rising trigger event configuration bit of Configurable Event input 2 1 SWI1 Rising trigger event configuration bit of Configurable Event input 1 1 SWI0 Rising trigger event configuration bit of Configurable Event input 0 1 PR PR EXTI pending register 0xC 0x20 read-write 0x00000000 PR20 configurable event inputs x rising edge Pending bit. 20 1 PR19 configurable event inputs x rising edge Pending bit. 19 1 PR18 configurable event inputs x rising edge Pending bit. 18 1 PR17 configurable event inputs x rising edge Pending bit. 17 1 PR16 configurable event inputs x rising edge Pending bit. 16 1 PR15 configurable event inputs x rising edge Pending bit. 15 1 PR14 configurable event inputs x rising edge Pending bit. 14 1 PR13 configurable event inputs x rising edge Pending bit 13 1 PR12 configurable event inputs x rising edge Pending bit. 12 1 PR11 configurable event inputs x rising edge Pending bit. 11 1 PR10 configurable event inputs x rising edge Pending bit. 10 1 PR9 configurable event inputs x rising edge Pending bit. 9 1 PR8 configurable event inputs x rising edge Pending bit. 8 1 PR7 configurable event inputs x rising edge Pending bit. 7 1 PR6 configurable event inputs x rising edge Pending bit. 6 1 PR5 configurable event inputs x rising edge Pending bit. 5 1 PR4 configurable event inputs x rising edge Pending bit. 4 1 PR3 configurable event inputs x rising edge Pending bit. 3 1 PR2 configurable event inputs x rising edge Pending bit. 2 1 PR1 configurable event inputs x rising edge Pending bit. 1 1 PR0 configurable event inputs x rising edge Pending bit. 0 1 EXTICR1 EXTICR1 EXTI external interrupt selection register 0x60 0x20 read-write 0x00000000 EXTI3 GPIO port selection 24 2 EXTI2 GPIO port selection 16 2 EXTI1 GPIO port selection 8 2 EXTI0 GPIO port selection 0 2 EXTICR2 EXTICR2 EXTI external interrupt selection register 0x64 0x20 read-write 0x00000000 EXTI7 GPIO port selection 24 2 EXTI6 GPIO port selection 16 2 EXTI5 GPIO port selection 8 2 EXTI4 GPIO port selection 0 2 EXTICR3 EXTICR3 EXTI external interrupt selection register 0x68 0x20 read-write 0x00000000 EXTI11 GPIO port selection 24 2 EXTI10 GPIO port selection 16 2 EXTI9 GPIO port selection 8 2 EXTI8 GPIO port selection 0 2 EXTICR4 EXTICR4 EXTI external interrupt selection register 0x6C 0x20 read-write 0x00000000 EXTI15 GPIO port selection 24 2 EXTI14 GPIO port selection 16 2 EXTI13 GPIO port selection 8 2 EXTI12 GPIO port selection 0 2 IMR IMR EXTI CPU wakeup with interrupt mask register 0x80 0x20 read-write 0xFFF80000 IM29 CPU wakeup with interrupt mask on event input 29 1 IM20 CPU wakeup with interrupt mask on event input 20 1 IM19 CPU wakeup with interrupt mask on event input 19 1 IM18 CPU wakeup with interrupt mask on event input 18 1 IM17 CPU wakeup with interrupt mask on event input 17 1 IM16 CPU wakeup with interrupt mask on event input 16 1 IM15 CPU wakeup with interrupt mask on event input 15 1 IM14 CPU wakeup with interrupt mask on event input 14 1 IM13 CPU wakeup with interrupt mask on event input 13 1 IM12 CPU wakeup with interrupt mask on event input 12 1 IM11 CPU wakeup with interrupt mask on event input 11 1 IM10 CPU wakeup with interrupt mask on event input 10 1 IM9 CPU wakeup with interrupt mask on event input 9 1 IM8 CPU wakeup with interrupt mask on event input 8 1 IM7 CPU wakeup with interrupt mask on event input 7 1 IM6 CPU wakeup with interrupt mask on event input 6 1 IM5 CPU wakeup with interrupt mask on event input 5 1 IM4 CPU wakeup with interrupt mask on event input 4 1 IM3 CPU wakeup with interrupt mask on event input 3 1 IM2 CPU wakeup with interrupt mask on event input 2 1 IM1 CPU wakeup with interrupt mask on event input 1 1 IM0 CPU wakeup with interrupt mask on event input 0 1 EMR EMR EXTI CPU wakeup with event mask register 0x84 0x20 read-write 0x00000000 EM29 CPU wakeup with event mask on event input 29 1 EM20 CPU wakeup with event mask on event input 20 1 EM19 CPU wakeup with event mask on event input 19 1 EM18 CPU wakeup with event mask on event input 18 1 EM17 CPU wakeup with event mask on event input 17 1 EM16 CPU wakeup with event mask on event input 16 1 EM15 CPU wakeup with event mask on event input 15 1 EM14 CPU wakeup with event mask on event input 14 1 EM13 CPU wakeup with event mask on event input 13 1 EM12 CPU wakeup with event mask on event input 12 1 EM11 CPU wakeup with event mask on event input 11 1 EM10 CPU wakeup with event mask on event input 10 1 EM9 CPU wakeup with event mask on event input 9 1 EM8 CPU wakeup with event mask on event input 8 1 EM7 CPU wakeup with event mask on event input 7 1 EM6 CPU wakeup with event mask on event input 6 1 EM5 CPU wakeup with event mask on event input 5 1 EM4 CPU wakeup with event mask on event input 4 1 EM3 CPU wakeup with event mask on event input 3 1 EM2 CPU wakeup with event mask on event input 2 1 EM1 CPU wakeup with event mask on event input 1 1 EM0 CPU wakeup with event mask on event input 0 1 FLASH desc FLASH FLASH 0x40022000 0x0 0x400 registers FLASH FLASH global Interrupt 3 ACR desc ACR 0x0 32 read-write 0x500 LATENCY desc LATENCY 1 0 read-write PRFTEN desc PRFTEN 8 8 read-write ICEN desc ICEN 9 9 read-write DCEN desc DCEN 10 10 read-write KEYR desc KEYR 0x8 32 write-only 0x0 KEY desc KEY 31 0 write-only OPTKEYR desc OPTKEYR 0xC 32 write-only 0x0 OPTKEY desc OPTKEY 31 0 write-only SR desc SR 0x10 32 read-write 0x0 EOP desc EOP 0 0 read-write WRPERR desc WRPERR 4 4 read-write OPTVERR desc OPTVERR 15 15 read-write BSY desc BSY 16 16 read-only CR desc CR 0x14 32 read-write 0x0 PG desc PG 0 0 read-write PER desc PER 1 1 read-write MER desc MER 2 2 read-write SER desc SER 11 11 read-write OPTSTRT desc OPTSTRT 17 17 read-write PGSTRT desc PGSTRT 19 19 read-write EOPIE desc EOPIE 24 24 read-write ERRIE desc ERRIE 25 25 read-write OBL_LAUNCH desc OBL_LAUNCH 27 27 read-write OPTLOCK desc OPTLOCK 30 30 read-write LOCK desc LOCK 31 31 read-write OPTR desc OPTR 0x20 32 read-only 0x0 RDP desc RDP 7 0 read-only IWDG_SW desc IWDG_SW 11 11 read-only WWDG_SW desc WWDG_SW 12 12 read-only NRST_MODE desc NRST_MODE 13 13 read-only NBOOT1 desc nBOOT1 14 14 read-only IWDG_STOP desc IWDG_STOP 15 15 read-only SDKR desc SDKR 0x24 32 read-only 0x0 SDK_STRT desc SDK_STRT 4 0 read-only BOR_EN desc BOR_EN 5 5 read-only SDK_END desc SDK_END 12 8 read-only BOR_LEV desc BOR_LEV 15 13 read-only PCK_EN desc PCK_EN 0x28 32 read-only 0x0 USB_CLK_EN desc USB_CLK_EN 0 0 read-only CAN_CLK_EN desc CAN_CLK_EN 1 1 read-only TIM2_CLK_EN desc TIM2_CLK_EN 2 2 read-only TIM3_CLK_EN desc TIM3_CLK_EN 3 3 read-only TIM7_CLK_EN desc TIM7_CLK_EN 4 4 read-only I2C2_CLK_EN desc I2C2_CLK_EN 5 5 read-only USART3_CLK_EN desc USART3_CLK_EN 6 6 read-only USART4_CLK_EN desc USART4_CLK_EN 7 7 read-only LCD_CLK_EN desc LCD_CLK_EN 8 8 read-only TIM14_CLK_EN desc TIM14_CLK_EN 9 9 read-only TIM15_CLK_EN desc TIM15_CLK_EN 10 10 read-only TIM17_CLK_EN desc TIM17_CLK_EN 11 11 read-only WRPR desc WRPR 0x2C 32 read-write 0x0 WRP desc WRP 15 0 read-write STCR desc STCR 0x90 32 read-write 0x00006400 SLEEP_EN desc SLEEP_EN 0 0 read-write SLEEP_TIME desc SLEEP_TIME 15 8 read-write TS0 desc TS0 0x100 32 read-write 0xB4 TS0 desc TS0 7 0 read-write TS1 desc TS1 0x104 32 read-write 0x1B0 TS1 desc TS1 8 0 read-write TS2P desc TS2P 0x108 32 read-write 0xB4 TS2P desc TS2P 7 0 read-write TPS3 desc TPS3 0x10C 32 read-write 0x6C0 TPS3 desc TPS3 10 0 read-write TS3 desc TS3 0x110 32 read-write 0xB4 TS3 desc TS3 7 0 read-write PERTPE desc PERTPE 0x114 32 read-write 0xEA60 PERTPE desc PERTPE 16 0 read-write SMERTPE desc SMERTPE 0x118 32 read-write 0xFD20 SMERTPE desc SMERTPE 16 0 read-write PRGTPE desc PRGTPE 0x11C 32 read-write 0x8CA0 PRGTPE desc PRGTPE 15 0 read-write PRETPE desc PRETPE 0x120 32 read-write 0x12C0 PRETPE desc PRETPE 13 0 read-write TRMLSR desc TRMLSR 0x290 32 read-only 0x0 PMU_TRIM0_ERR desc PMU_TRIM0_ERR 0 0 read-only PMU_TRIM1_ERR desc PMU_TRIM1_ERR 1 1 read-only HSI_TRIM_ERR desc HSI_TRIM_ERR 2 2 read-only LSI_TRIM_ERR desc LSI_TRIM_ERR 3 3 read-only FLASH_TRIM0_ERR desc FLASH_TRIM0_ERR 4 4 read-only FLASH_TRIM1_ERR desc FLASH_TRIM1_ERR 5 5 read-only FLASH_TRIM2_ERR desc FLASH_TRIM2_ERR 6 6 read-only FLASH_TRIM3_ERR desc FLASH_TRIM3_ERR 7 7 read-only FLASH_TRIM4_ERR desc FLASH_TRIM4_ERR 8 8 read-only FLASH_TRIM5_ERR desc FLASH_TRIM5_ERR 9 9 read-only TS_TRIM_ERR desc TS_TRIM_ERR 10 10 read-only CHIP_CFG_ERR desc CHIP_CFG_ERR 11 11 read-only CHKRD0_PASS desc CHKRD0_PASS 16 16 read-only CHKRD1_PASS desc CHKRD1_PASS 17 17 read-only CHKRD2_PASS desc CHKRD2_PASS 18 18 read-only CHKRD3_PASS desc CHKRD3_PASS 19 19 read-only TRMDR0 desc TRMDR0 0x294 32 read-only 0x0 BIAS_CR desc BIAS_CR 3 0 read-only TRIM_MR desc TRIM_MR 8 4 read-only TRIM_VREF desc TRIM_VREF 13 9 read-only TRIM_POR desc TRIM_POR 19 16 read-only TRIM_BG desc TRIM_BG 27 20 read-only TRMDR1 desc TRMDR1 0x298 32 read-only 0x0 LSI_TRIM desc LSI_TRIM 8 0 read-only HSI_TRIM desc HSI_TRIM 28 16 read-only HSI_FS desc HSI_FS 31 29 read-only TRMDR2 desc TRMDR2 0x29C 32 read-only 0x0 FLASH_OP desc FLASH_OP 31 0 read-only TRMDR3 desc TRMDR3 0x2A0 32 read-only 0x0 FLASH_OP desc FLASH_OP 31 0 read-only TRMDR4 desc TRMDR4 0x2A4 32 read-only 0x0 FLASH_ERASE_VPOS desc FLASH_ERASE_VPOS 4 0 read-only FLASH_ERASE_VNEG desc FLASH_ERASE_VNEG 9 5 read-only FLASH_PROG_VPOS desc FLASH_PROG_VPOS 20 16 read-only FLASH_PROG_VNEG desc FLASH_PROG_VNEG 25 21 read-only TRMDR5 desc TRMDR5 0x2A8 32 read-only 0x0 FLASH_SIZE desc FLASH_SIZE 2 0 read-only SRAM_SIZE desc SRAM_SIZE 6 4 read-only TS_TRIM desc TS_TRIM 11 8 read-only TRMDR6 desc TRMDR6 0x2AC 32 read-only 0x0 OPA0_TRIM desc OPA0_TRIM 3 0 read-only OPA1_TRIM desc OPA1_TRIM 7 4 read-only OPA2_TRIM desc OPA2_TRIM 11 8 read-only OPA3_TRIM desc OPA3_TRIM 15 12 read-only OPA4_TRIM desc OPA4_TRIM 19 16 read-only LCD_TRIM desc LCD_TRIM 27 20 read-only TRMDR7 desc TRMDR7 0x2B0 32 read-only 0x0 TS_DATA_0_TRIM desc TS_DATA_0_TRIM 11 0 read-only TS_DATA_1_TRIM desc TS_DATA_1_TRIM 23 12 read-only TRMDR8 desc TRMDR8 0x2B4 32 read-only 0x0 DAC_0_TRIM desc DAC_0_TRIM 11 0 read-only DAC_1_TRIM desc DAC_1_TRIM 23 12 read-only VREF_BUF_TRIM desc VREF_BUF_TRIM 28 24 read-only GPIOA General-purpose I/Os GPIO 0x50000000 0x0 0x400 registers MODER MODER GPIO port mode register 0x0 0x20 read-write 0xEBFFFFFF MODE15 Port x configuration bits (y=0-15) 30 2 MODE14 Port x configuration bits (y=0-15) 28 2 MODE13 Port x configuration bits (y=0-15) 26 2 MODE12 Port x configuration bits (y=0-15) 24 2 MODE11 Port x configuration bits (y=0-15) 22 2 MODE10 Port x configuration bits (y=0-15) 20 2 MODE9 Port x configuration bits (y=0-15) 18 2 MODE8 Port x configuration bits (y=0-15) 16 2 MODE7 Port x configuration bits (y=0-15) 14 2 MODE6 Port x configuration bits (y=0-15) 12 2 MODE5 Port x configuration bits (y=0-15) 10 2 MODE4 Port x configuration bits (y=0-15) 8 2 MODE3 Port x configuration bits (y=0-15) 6 2 MODE2 Port x configuration bits (y=0-15) 4 2 MODE1 Port x configuration bits (y=0-15) 2 2 MODE0 Port x configuration bits (y=0-15) 0 2 OTYPER OTYPER GPIO port output type register 0x4 0x20 read-write 0x00000000 OT15 Port x configuration bits (y=0-15) 15 1 OT14 Port x configuration bits (y=0-15) 14 1 OT13 Port x configuration bits (y=0-15) 13 1 OT12 Port x configuration bits (y=0-15) 12 1 OT11 Port x configuration bits (y=0-15) 11 1 OT10 Port x configuration bits (y=0-15) 10 1 OT9 Port x configuration bits (y=0-15) 9 1 OT8 Port x configuration bits (y=0-15) 8 1 OT7 Port x configuration bits (y=0-15) 7 1 OT6 Port x configuration bits (y=0-15) 6 1 OT5 Port x configuration bits (y=0-15) 5 1 OT4 Port x configuration bits (y=0-15) 4 1 OT3 Port x configuration bits (y=0-15) 3 1 OT2 Port x configuration bits (y=0-15) 2 1 OT1 Port x configuration bits (y=0-15) 1 1 OT0 Port x configuration bits (y=0-15) 0 1 OSPEEDR OSPEEDR GPIO port output speed register 0x8 0x20 read-write 0x0C000000 OSPEED15 Port x configuration bits (y=0-15) 30 2 OSPEED14 Port x configuration bits (y=0-15) 28 2 OSPEED13 Port x configuration bits (y=0-15) 26 2 OSPEED12 Port x configuration bits (y=0-15) 24 2 OSPEED11 Port x configuration bits (y=0-15) 22 2 OSPEED10 Port x configuration bits (y=0-15) 20 2 OSPEED9 Port x configuration bits (y=0-15) 18 2 OSPEED8 Port x configuration bits (y=0-15) 16 2 OSPEED7 Port x configuration bits (y=0-15) 14 2 OSPEED6 Port x configuration bits (y=0-15) 12 2 OSPEED5 Port x configuration bits (y=0-15) 10 2 OSPEED4 Port x configuration bits (y=0-15) 8 2 OSPEED3 Port x configuration bits (y=0-15) 6 2 OSPEED2 Port x configuration bits (y=0-15) 4 2 OSPEED1 Port x configuration bits (y=0-15) 2 2 OSPEED0 Port x configuration bits (y=0-15) 0 2 PUPDR PUPDR GPIO port pull-up/pull-down register 0xC 0x20 read-write 0x24000000 PUPD15 Port x configuration bits (y=0-15) 30 2 PUPD14 Port x configuration bits (y=0-15) 28 2 PUPD13 Port x configuration bits (y=0-15) 26 2 PUPD12 Port x configuration bits (y=0-15) 24 2 PUPD11 Port x configuration bits (y=0-15) 22 2 PUPD10 Port x configuration bits (y=0-15) 20 2 PUPD9 Port x configuration bits (y=0-15) 18 2 PUPD8 Port x configuration bits (y=0-15) 16 2 PUPD7 Port x configuration bits (y=0-15) 14 2 PUPD6 Port x configuration bits (y=0-15) 12 2 PUPD5 Port x configuration bits (y=0-15) 10 2 PUPD4 Port x configuration bits (y=0-15) 8 2 PUPD3 Port x configuration bits (y=0-15) 6 2 PUPD2 Port x configuration bits (y=0-15) 4 2 PUPD1 Port x configuration bits (y=0-15) 2 2 PUPD0 Port x configuration bits (y=0-15) 0 2 IDR IDR GPIO port input data register 0x10 0x20 read-only 0x00000000 ID15 Port input data (y=0-15) 15 1 ID14 Port input data (y=0-15) 14 1 ID13 Port input data (y=0-15) 13 1 ID12 Port input data (y=0-15) 12 1 ID11 Port input data (y=0-15) 11 1 ID10 Port input data (y=0-15) 10 1 ID9 Port input data (y=0-15) 9 1 ID8 Port input data (y=0-15) 8 1 ID7 Port input data (y=0-15) 7 1 ID6 Port input data (y=0-15) 6 1 ID5 Port input data (y=0-15) 5 1 ID4 Port input data (y=0-15) 4 1 ID3 Port input data (y=0-15) 3 1 ID2 Port input data (y=0-15) 2 1 ID1 Port input data (y=0-15) 1 1 ID0 Port input data (y=0-15) 0 1 ODR ODR GPIO port output data register 0x14 0x20 read-write 0x00000000 OD15 Port output data (y=0-15) 15 1 OD14 Port output data (y=0-15) 14 1 OD13 Port output data (y=0-15) 13 1 OD12 Port output data (y=0-15) 12 1 OD11 Port output data (y=0-15) 11 1 OD10 Port output data (y=0-15) 10 1 OD9 Port output data (y=0-15) 9 1 OD8 Port output data (y=0-15) 8 1 OD7 Port output data (y=0-15) 7 1 OD6 Port output data (y=0-15) 6 1 OD5 Port output data (y=0-15) 5 1 OD4 Port output data (y=0-15) 4 1 OD3 Port output data (y=0-15) 3 1 OD2 Port output data (y=0-15) 2 1 OD1 Port output data (y=0-15) 1 1 OD0 Port output data (y=0-15) 0 1 BSRR BSRR GPIO port bit set/reset register 0x18 0x20 write-only 0x00000000 BR15 Port x reset bit y (y=0-15) 31 1 BR14 Port x reset bit y (y=0-15) 30 1 BR13 Port x reset bit y (y=0-15) 29 1 BR12 Port x reset bit y (y=0-15) 28 1 BR11 Port x reset bit y (y=0-15) 27 1 BR10 Port x reset bit y (y=0-15) 26 1 BR9 Port x reset bit y (y=0-15) 25 1 BR8 Port x reset bit y (y=0-15) 24 1 BR7 Port x reset bit y (y=0-15) 23 1 BR6 Port x reset bit y (y=0-15) 22 1 BR5 Port x reset bit y (y=0-15) 21 1 BR4 Port x reset bit y (y=0-15) 20 1 BR3 Port x reset bit y (y=0-15) 19 1 BR2 Port x reset bit y (y=0-15) 18 1 BR1 Port x reset bit y (y=0-15) 17 1 BR0 Port x set bit y (y=0-15) 16 1 BS15 Port x set bit y (y=0-15) 15 1 BS14 Port x set bit y (y=0-15) 14 1 BS13 Port x set bit y (y=0-15) 13 1 BS12 Port x set bit y (y=0-15) 12 1 BS11 Port x set bit y (y=0-15) 11 1 BS10 Port x set bit y (y=0-15) 10 1 BS9 Port x set bit y (y=0-15) 9 1 BS8 Port x set bit y (y=0-15) 8 1 BS7 Port x set bit y (y=0-15) 7 1 BS6 Port x set bit y (y=0-15) 6 1 BS5 Port x set bit y (y=0-15) 5 1 BS4 Port x set bit y (y=0-15) 4 1 BS3 Port x set bit y (y=0-15) 3 1 BS2 Port x set bit y (y=0-15) 2 1 BS1 Port x set bit y (y=0-15) 1 1 BS0 Port x set bit y (y=0-15) 0 1 LCKR LCKR GPIO port configuration lock register 0x1C 0x20 read-write 0x00000000 LCKK Port x lock (LCKK) 16 1 LCK15 Port x lock bit y (y=0-15) 15 1 LCK14 Port x lock bit y (y=0-15) 14 1 LCK13 Port x lock bit y (y=0-15) 13 1 LCK12 Port x lock bit y (y=0-15) 12 1 LCK11 Port x lock bit y (y=0-15) 11 1 LCK10 Port x lock bit y (y=0-15) 10 1 LCK9 Port x lock bit y (y=0-15) 9 1 LCK8 Port x lock bit y (y=0-15) 8 1 LCK7 Port x lock bit y (y=0-15) 7 1 LCK6 Port x lock bit y (y=0-15) 6 1 LCK5 Port x lock bit y (y=0-15) 5 1 LCK4 Port x lock bit y (y=0-15) 4 1 LCK3 Port x lock bit y (y=0-15) 3 1 LCK2 Port x lock bit y (y=0-15) 2 1 LCK1 Port x lock bit y (y=0-15) 1 1 LCK0 Port x lock bit y (y=0-15) 0 1 AFRL AFRL GPIO alternate function low register 0x20 0x20 read-write 0x00000000 AFSEL7 Alternate function selection for port x bit y (y=0-7) 28 4 AFSEL6 Alternate function selection for port x bit y (y=0-7) 24 4 AFSEL5 Alternate function selection for port x bit y (y=0-7) 20 4 AFSEL4 Alternate function selection for port x bit y (y=0-7) 16 4 AFSEL3 Alternate function selection for port x bit y (y=0-7) 12 4 AFSEL2 Alternate function selection for port x bit y (y=0-7) 8 4 AFSEL1 Alternate function selection for port x bit y (y=0-7) 4 4 AFSEL0 Alternate function selection for port x bit y (y=0-7) 0 4 AFRH AFRH GPIO alternate function high register 0x24 0x20 read-write 0x00000000 AFSEL15 Alternate function selection for port x bit y (y=8-15) 28 4 AFSEL14 Alternate function selection for port x bit y (y=8-15) 24 4 AFSEL13 Alternate function selection for port x bit y (y=8-15) 20 4 AFSEL12 Alternate function selection for port x bit y (y=8-15) 16 4 AFSEL11 Alternate function selection for port x bit y (y=8-15) 12 4 AFSEL10 Alternate function selection for port x bit y (y=8-15) 8 4 AFSEL9 Alternate function selection for port x bit y (y=8-15) 4 4 AFSEL8 Alternate function selection for port x bit y (y=8-15) 0 4 BRR BRR port bit reset register 0x28 0x20 write-only 0x00000000 BR15 Port Reset bit 15 1 BR14 Port Reset bit 14 1 BR13 Port Reset bit 13 1 BR12 Port Reset bit 12 1 BR11 Port Reset bit 11 1 BR10 Port Reset bit 10 1 BR9 Port Reset bit 9 1 BR8 Port Reset bit 8 1 BR7 Port Reset bit 7 1 BR6 Port Reset bit 6 1 BR5 Port Reset bit 5 1 BR4 Port Reset bit 4 1 BR3 Port Reset bit 3 1 BR2 Port Reset bit 2 1 BR1 Port Reset bit 1 1 BR0 Port Reset bit 0 1 GPIOB General-purpose I/Os GPIO 0x50000400 0x0 0x400 registers GPIOC General-purpose I/Os GPIO 0x50000800 0x0 0x400 registers GPIOF General-purpose I/Os GPIO 0x50001400 0x0 0x400 registers I2C1 Inter integrated circuit I2C 0x40005400 0x0 0x400 registers I2C1 I2C1 global Interrupt 23 CR1 desc CR1 0x0 32 read-write 0x0 PE desc PE 0 0 read-write SMBUS desc SMBUS 1 1 read-write SMBTYPE desc SMBTYPE 3 3 read-write ENARP desc ENARP 4 4 read-write ENPEC desc ENPEC 5 5 read-write ENGC desc ENGC 6 6 read-write NOSTRETCH desc NOSTRETCH 7 7 read-write START desc START 8 8 read-write STOP desc STOP 9 9 read-write ACK desc ACK 10 10 read-write POS desc POS 11 11 read-write PEC desc PEC 12 12 read-write ALERT desc ALERT 13 13 read-write SWRST desc SWRST 15 15 read-write CR2 desc CR2 0x4 32 read-write 0x0 FREQ desc FREQ 5 0 read-write ITERREN desc ITERREN 8 8 read-write ITEVTEN desc ITEVTEN 9 9 read-write ITBUFEN desc ITBUFEN 10 10 read-write DMAEN desc DMAEN 11 11 read-write LAST desc LAST 12 12 read-write OAR1 desc OAR1 0x8 32 read-write 0x0 ADD0 desc ADD0 0 0 read-write ADD1_7 desc ADD1_7 7 1 read-write ADD8_9 desc ADD8_9 9 8 read-write ADDMODE desc ADDMODE 15 15 read-write OAR2 desc OAR2 0xC 32 read-write 0x0 ENDUAL desc ENDUAL 0 0 read-write ADD2 desc ADD2 7 1 read-write DR desc DR 0x10 32 read-write 0x0 DR desc DR 7 0 read-write SR1 desc SR1 0x14 32 read-write 0x0 SB desc SB 0 0 read-only ADDR desc ADDR 1 1 read-only BTF desc BTF 2 2 read-only ADD10 desc ADD10 3 3 read-only STOPF desc STOPF 4 4 read-only RXNE desc RXNE 6 6 read-only TXE desc TXE 7 7 read-only BERR desc BERR 8 8 read-write ARLO desc ARLO 9 9 read-write AF desc AF 10 10 read-write OVR desc OVR 11 11 read-write PECERR desc PECERR 12 12 read-write TIMEOUT desc TIMEOUT 14 14 read-write SMBALERT desc SMBALERT 15 15 read-write SR2 desc SR2 0x18 32 read-only 0x0 MSL desc MSL 0 0 read-only BUSY desc BUSY 1 1 read-only TRA desc TRA 2 2 read-only GENCALL desc GENCALL 4 4 read-only SMBDEFAULT desc SMBDEFAULT 5 5 read-only SMBHOST desc SMBHOST 6 6 read-only DUALF desc DUALF 7 7 read-only PEC desc PEC 15 8 read-only CCR desc CCR 0x1C 32 read-write 0x0 CCR desc CCR 11 0 read-write DUTY desc DUTY 14 14 read-write FS desc FS 15 15 read-write TRISE desc TRISE 0x20 32 read-write 0x2 TRISE desc TRISE 5 0 read-write I2C2 desc I2C I2C 0x40005800 0x0 0x400 registers I2C2 I2C2 Event Interrupt 24 IWDG Independent watchdog IWDG 0x40003000 0x0 0x400 registers KR KR Key register (IWDG_KR) 0x0 0x20 write-only 0x00000000 KEY Key value 0 16 PR PR Prescaler register (IWDG_PR) 0x4 0x20 read-write 0x00000000 PR Prescaler divider 0 3 RLR RLR Reload register (IWDG_RLR) 0x8 0x20 read-write 0x00000FFF RL Watchdog counter reload value 0 12 SR SR Status register (IWDG_SR) 0xC 0x20 read-only 0x00000000 RVU Watchdog counter reload value update 1 1 PVU Watchdog prescaler value update 0 1 LCD LCD CONTROLLER LCD 0x40002400 0x0 0x400 registers LCD LCD global Interrupt 8 CR0 CR0 Control register 0x0 0x20 read-write 0x0000 EN EN 0 1 LCDCLK LCDCLK 1 2 BIAS BIAS 6 1 DUTY DUTY 7 3 BSEL BSEL 10 3 CONTRAST CONTRAST 13 4 CR1 CR1 CR1 0x4 0x20 read-write 0x0000 BLINKCNT BLINKCNT 0 6 BLINKEN BLINKEN 6 1 MODE MODE 8 1 IE IE 10 1 INTF INTF 11 1 INTCLR INTCLR INTCLR 0x8 0x20 read-write 0x0000 INTF_CLR INTF_CLR 10 1 POEN0 POEN0 POEN0 0x0C 0x20 read-write 0x0000 S0 S0 0 1 S1 S1 1 1 S2 S2 2 1 S3 S3 3 1 S4 S4 4 1 S5 S5 5 1 S6 S6 6 1 S7 S7 7 1 S8 S8 8 1 S9 S9 9 1 S10 S10 10 1 S11 S11 11 1 S12 S12 12 1 S13 S13 13 1 S14 S14 14 1 S15 S15 15 1 S16 S16 16 1 S17 S17 17 1 S18 S18 18 1 S19 S19 19 1 S20 S20 20 1 S21 S21 21 1 S22 S22 22 1 S23 S23 23 1 S24 S24 24 1 S25 S25 25 1 S26 S26 26 1 S27 S27 27 1 S28 S28 28 1 S29 S29 29 1 S30 S30 30 1 S31 S31 31 1 POEN1 POEN1 POEN1 0x10 0x20 read-write 0x0000 S32 S32 0 1 S33 S33 1 1 S34 S34 2 1 S35 S35 3 1 S36 S36 4 1 S37 S37 5 1 S38 S38 6 1 S39 S39 7 1 C0 C0 8 1 C1 C1 9 1 C2 C2 10 1 C3 C3 11 1 MUX MUX 12 1 RAM0 RAM0 des RAM0 0x14 0x20 read-write 0x0000 D des D 0 32 RAM1 RAM1 des RAM1 0x18 0x20 read-write 0x0000 D des D 0 32 RAM2 RAM2 des RAM2 0x1C 0x20 read-write 0x0000 D des D 0 32 RAM3 RAM3 des RAM3 0x20 0x20 read-write 0x0000 D des D 0 32 RAM4 RAM4 des RAM4 0x24 0x20 read-write 0x0000 D des D 0 32 RAM5 RAM5 des RAM5 0x28 0x20 read-write 0x0000 D des D 0 32 RAM6 RAM6 des RAM6 0x2C 0x20 read-write 0x0000 D des D 0 32 RAM7 RAM7 des RAM7 0x30 0x20 read-write 0x0000 D des D 0 32 RAM8 RAM8 des RAM8 0x34 0x20 read-write 0x0000 D des D 0 8 RAM9 RAM9 des RAM9 0x38 0x20 read-write 0x0000 D des D 0 8 RAM10 RAM10 des RAM10 0x3C 0x20 read-write 0x0000 D des D 0 8 RAM11 RAM11 des RAM11 0x40 0x20 read-write 0x0000 D des D 0 8 RAM12 RAM12 des RAM12 0x44 0x20 read-write 0x0000 D des D 0 8 RAM13 RAM13 des RAM13 0x48 0x20 read-write 0x0000 D des D 0 8 RAM14 RAM14 des RAM14 0x4C 0x20 read-write 0x0000 D des D 0 8 RAM15 RAM15 des RAM15 0x50 0x20 read-write 0x0000 D des D 0 8 LPTIM1 Low power timer LPTIM1 0x40007C00 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 ISR ISR Interrupt and Status Register 0x0 0x20 read-only 0x00000000 ARRM Autoreload match 1 1 ARROK Autoreload match update OK 4 1 ICR ICR Interrupt Clear Register 0x4 0x20 write-only 0x00000000 ARRMCF Autoreload match Clear Flag 1 1 ARROKCF Autoreload match update OK Clear Flag 4 1 IER IER Interrupt Enable Register 0x8 0x20 read-write 0x00000000 ARRMIE Autoreload matchInterrupt Enable 1 1 ARROKIE Autoreload match update OK Interrupt Enable 4 1 CFGR CFGR Configuration Register 0xC 0x20 read-write 0x00000000 PRELOAD Registers update mode 22 1 PRESC Clock prescaler 9 3 CR CR Control Register 0x10 0x20 read-write 0x00000000 RSTARE Reset after read enable 4 1 CNTSTRT CNTSTRT 2 1 SNGSTRT LPTIM start in single mode 1 1 ENABLE LPTIM Enable 0 1 ARR ARR Autoreload Register 0x18 0x20 read-write 0x00000001 ARR Auto reload value 0 16 CNT CNT Counter Register 0x1C 0x20 read-only 0x00000000 CNT Counter value 0 16 OPA des OPA OPA 0x40010300 0x0 0x400 registers CR0 CR0 CR0 register 0x30 0x20 read-write 0xFFFFFFFF OP1OEN1 OP1OEN1 1 1 OP2OEN1 OP2OEN1 6 1 OP3OEN1 OP3OEN1 11 1 CR1 CR1 CR1 register 0x34 0x20 read-write 0x00000000 EN1 EN1 5 1 EN2 EN2 6 1 EN3 EN3 7 1 PWR Power control PWR 0x40007000 0x0 0x400 registers CR1 CR1 Power control register 1 0x0 0x20 read-write 0x00030000 HSION_CTRL HSI open time control 19 1 SRAM_RETV SRAM retention voltage control 16 3 LPR Low-power run 14 1 FLS_SLPTIME Flash wait time after wakeup from the stop mode 12 2 VOS Voltage scaling range selection 9 2 DBP Disable backup domain write protection 8 1 BIAS_CR_SEL MR Bias current selection 4 1 BIAS_CR MR Bias current 0 3 CR2 CR2 Power control register 2 0x4 0x20 read-write 0x00000500 FLT_TIME Digital filter time configuration 9 3 FLTEN Digital filter enable 8 1 PVDT Power voltage detector threshold selection 4 3 SRCSEL Power voltage detector volatage selection 2 1 PVDE Power voltage detector enable 0 1 SR SR Power status register 0x14 0x20 read-only 0x00000000 PVDO PVD output 11 1 RCC Reset and clock control RCC 0x40021000 0x0 0x400 registers RCC_CTC RCC and CTC global Interrupts 4 CR CR Clock control register 0x0 0x20 read-write 0x00000100 PLLRDY PLL clock ready flag 25 1 PLLON PLL enable 24 1 ADC_DIV ADC Frequency Division 21 2 CSSON Clock security system enable 19 1 HSEBYP HSE crystal oscillator bypass 18 1 HSERDY HSE clock ready flag 17 1 HSEON HSE clock enable 16 1 HSIDIV HSI16 clock division factor 11 3 HSIRDY HSI16 clock ready flag 10 1 HSION HSI16 clock enable 8 1 ICSCR ICSCR Internal clock sources calibration register 0x4 0x20 0x10000000 LSI_TRIM LSI clock trimming 16 9 read-write HSI_FS HSI frequency selection 13 3 read-write HSI_TRIM HSI clock trimming 0 13 read-write CFGR CFGR Clock configuration register 0x8 0x20 0x00000000 MCOPRE Microcontroller clock output prescaler 28 3 read-write MCOSEL Microcontroller clock output 24 3 read-write PPRE APB prescaler 12 3 read-write HPRE AHB prescaler 8 4 read-write SWS System clock switch status 3 3 read-only SW System clock switch 0 3 read-write PLLCFGR PLLCFGR PLL configuration register 0xC 0x20 0x00000000 PLLSRC PLL clock source selection 0 2 read-write PLLMUL PLLMUL 2 2 read-write ECSCR ECSCR External clock source control register 0x10 0x20 0x00000000 HSE_DRV HSE_DRV 0 2 read-write HSE_STARTUP HSE_STARTUP 3 2 read-write LSE_DRIVER LSE clock driver selection 16 2 read-write LSE_STARTUP LSE_STARTUP 20 2 read-write CIER CIER Clock interrupt enable register 0x18 0x20 read-write 0x00000000 PLLRDYIE PLL ready interrupt enable 5 1 HSERDYIE HSE ready interrupt enable 4 1 HSIRDYIE HSI ready interrupt enable 3 1 LSERDYIE LSE ready interrupt enable 1 1 LSIRDYIE LSI ready interrupt enable 0 1 CIFR CIFR Clock interrupt flag register 0x1C 0x20 read-only 0x00000000 LSECSSF LSE clock secure system interrupt flag 9 1 CSSF HSE clock secure system interrupt flag 8 1 PLLRDYF PLL ready interrupt flag 5 1 HSERDYF HSE ready interrupt flag 4 1 HSIRDYF HSI ready interrupt flag 3 1 LSERDYF LSE ready interrupt flag 1 1 LSIRDYF LSI ready interrupt flag 0 1 CICR CICR Clock interrupt clear register 0x20 0x20 write-only 0x00000000 LSECSSC LSE clock secure system interrupt flag clear 9 1 CSSC clock secure system interrupt flag clear 8 1 PLLRDYC PLL ready interrupt clear 5 1 HSERDYC HSE ready interrupt clear 4 1 HSIRDYC HSI ready interrupt clear 3 1 LSERDYC LSE ready interrupt clear 1 1 LSIRDYC LSI ready interrupt clear 0 1 IOPRSTR IOPRSTR GPIO reset register 0x24 0x20 read-write 0x00000000 GPIOFRST I/O port F reset 5 1 GPIOCRST I/O port F reset 2 1 GPIOBRST I/O port B reset 1 1 GPIOARST I/O port A reset 0 1 AHBRSTR AHBRSTR AHB peripheral reset register 0x28 0x20 read-write 0x00000000 DIVRST DIV reset 24 1 CRCRST CRC reset 12 1 DMARST DMA reset 0 1 APBRSTR1 APBRSTR1 APB peripheral reset register 1 0x2C 0x20 read-write 0x00000000 LPTIMRST Low Power Timer reset 31 1 OPARST OPARST 30 1 DACRST DACRST 29 1 PWRRST Power interface reset 28 1 CTCRST CTCRST 27 1 CANRST CANRST 25 1 USBRST USB reset 23 1 I2C2RST I2C2 reset 22 1 I2C1RST I2C1 reset 21 1 USART4RST USART4 reset 19 1 USART3RST USART3 reset 18 1 USART2RST USART2 reset 17 1 SPI2RST SPI2 reset 14 1 WWDGRST WWDG reset 11 1 RTCAPBRST RTCAPB reset 10 1 TIM7RST TIM7 timer reset 5 1 TIM6RST TIM6 timer reset 4 1 TIM3RST TIM3 timer reset 1 1 TIM2RST TIM2 timer reset 0 1 APBRSTR2 APBRSTR2 APB peripheral reset register 2 0x30 0x20 read-write 0x00000000 SYSCFGRST SYSCFG reset 0 1 ADCRST ADC reset 9 1 DBGRST DBG reset 10 1 TIM1RST TIM1 reset 11 1 SPI1RST SPI1 reset 12 1 USART1RST USART1 reset 14 1 TIM14RST TIM14 reset 15 1 TIM15RST TIM15 reset 16 1 TIM16RST TIM16 reset 17 1 TIM17RST TIM17 reset 18 1 COMP1RST COMP1 reset 20 1 COMP2RST COMP2 reset 21 1 COMP3RST COMP3 reset 22 1 LCDRST LCD reset 23 1 IOPENR IOPENR GPIO clock enable register 0x34 0x20 read-write 0x00000000 GPIOFEN I/O port F clock enable 5 1 GPIOCEN I/O port C clock enable 2 1 GPIOBEN I/O port B clock enable 1 1 GPIOAEN I/O port A clock enable 0 1 AHBENR AHBENR AHB peripheral clock enable register 0x38 0x20 read-write 0x00000000 DIVEN DIVEN 24 1 CRCEN CRC clock enable 12 1 SRAMEN SRAM memory interface clock enable 9 1 FLASHEN Flash memory interface clock enable 8 1 DMAEN DMA clock enable 0 1 APBENR1 APBENR1 APB peripheral clock enable register 1 0x3C 0x20 read-write 0x00000000 LPTIMEN LPTIM clock enable 31 1 OPAEN OPA clock enable 30 1 DACEN DAC clock enable 29 1 PWREN Power interface clock enable 28 1 CTCEN CTC clock enable 27 1 CANEN CAN clock enable 25 1 USBEN USB clock enable 23 1 I2C2EN I2C2 clock enable 22 1 I2C1EN I2C1 clock enable 21 1 USART4EN USART4 clock enable 19 1 USART3EN USART3 clock enable 18 1 USART2EN USART2 clock enable 17 1 SPI2EN SPI2 clock enable 14 1 WWDGEN WWDG clock enable 11 1 RTCAPBEN RTC APB clock enable 10 1 TIM7EN TIM7 timer clock enable 5 1 TIM6EN TIM6 timer clock enable 4 1 TIM3EN TIM3 timer clock enable 1 1 TIM2EN TIM2 timer clock enable 0 1 APBENR2 APBENR2 APB peripheral clock enable register 2 0x40 0x20 read-write 0x00000000 SYSCFGEN SYSCFG, COMP and VREFBUF clock enable 0 1 ADCEN ADCEN clock enable 9 1 DBGEN DBG clock enable 10 1 TIM1EN TIM1 clock enable 11 1 SPI1EN SPI1 clock enable 12 1 USART1EN USART1 clock enable 14 1 TIM14EN TIM14 clock enable 15 1 TIM15EN TIM15 clock enable 16 1 TIM16EN TIM16 clock enable 17 1 TIM17EN TIM17 clock enable 18 1 COMP1EN COMP1 clock enable 20 1 COMP2EN COMP2 clock enable 21 1 COMP3EN COMP3 clock enable 22 1 LCDEN LCD clock enable 23 1 CCIPR CCIPR Peripherals independent clock configuration register 0x54 0x20 read-write 0x00000000 LPTIM1SEL LPTIM1 clock source selection 18 2 COMP3SEL COMP3 clock source selection 10 1 COMP2SEL COMP2 clock source selection 9 1 COMP1SEL COMP1 clock source selection 8 1 PVDSEL PVD detect clock source selection 7 1 CANSEL CAN detect clock source selection 6 1 BDCR BDCR RTC domain control register 0x5C 0x20 read-write 0x00000000 LSCOSEL Low-speed clock output selection 25 1 LSCOEN Low-speed clock output (LSCO) enable 24 1 BDRST RTC domain software reset 16 1 RTCEN RTC clock source enable 15 1 RTCSEL RTC clock source selection 8 2 LSECSSD LSE CSS detect 6 1 LSECSSON LSE CSS enable 5 1 LSEBYP LSE oscillator bypass 2 1 LSERDY LSE oscillator ready 1 1 LSEON LSE oscillator enable 0 1 CSR CSR Control/status register 0x60 0x20 read-write 0x00000000 WWDGRSTF Window watchdog reset flag 30 1 IWDGRSTF Independent window watchdog reset flag 29 1 SFTRSTF Software reset flag 28 1 PWRRSTF BOR or POR/PDR flag 27 1 PINRSTF Pin reset flag 26 1 OBLRSTF Option byte loader reset flag 25 1 RMVF Remove reset flags 23 1 NRST_FLTDIS NRST_FLTDIS oscillator ready 8 1 LSIRDY LSI oscillator ready 1 1 LSION LSI oscillator enable 0 1 RTC desc RTC RTC 0x40002800 0x0 0x400 registers RTC RTC Interrupt through EXTI Lines 19 2 CRH desc CRH 0x0 32 read-write 0x0 SECIE desc SECIE 0 0 read-write ALRIE desc ALRIE 1 1 read-write OWIE desc OWIE 2 2 read-write CRL desc CRL 0x4 32 read-write 0x20 SECF desc SECF 0 0 read-write ALRF desc ALRF 1 1 read-write OWF desc OWF 2 2 read-write RSF desc RSF 3 3 read-write CNF desc CNF 4 4 read-write RTOFF desc RTOFF 5 5 read-only PRLH desc PRLH 0x8 32 write-only 0x0 PRL desc PRL 3 0 write-only PRLL desc PRLL 0xC 32 write-only 0x8000 PRL desc PRL 15 0 write-only DIVH desc DIVH 0x10 32 read-only 0x0 DIV desc DIV 3 0 read-only DIVL desc DIVL 0x14 32 read-only 0x8000 DIV desc DIV 15 0 read-only CNTH desc CNTH 0x18 32 read-write 0x0 RTC_CNT desc RTC_CNT 15 0 read-write CNTL desc CNTL 0x1C 32 read-write 0x0 RTC_CNT desc RTC_CNT 15 0 read-write ALRH desc ALRH 0x20 32 read-write 0xFFFF RTC_ALR desc RTC_ALR 15 0 read-write ALRL desc ALRL 0x24 32 read-write 0xFFFF RTC_ALR desc RTC_ALR 15 0 read-write BKP_RTCCR desc BKP_RTCCR 0x2C 32 read-write 0x0 CAL desc CAL 6 0 read-write CCO desc CCO 7 7 read-write ASOE desc ASOE 8 8 read-write ASOS desc ASOS 9 9 read-write SPI1 Serial peripheral interface SPI 0x40013000 0x0 0x400 registers SPI1 SPI1 global Interrupt 25 CR1 desc CR1 0x0 32 read-write 0x0 CPHA desc CPHA 0 0 read-write CPOL desc CPOL 1 1 read-write MSTR desc MSTR 2 2 read-write BR desc BR 5 3 read-write SPE desc SPE 6 6 read-write LSBFIRST desc LSBFIRST 7 7 read-write SSI desc SSI 8 8 read-write SSM desc SSM 9 9 read-write RXONLY desc RXONLY 10 10 read-write DDF desc DDF 11 11 read-write CRCNEXT desc CRCNEXT 12 12 read-write CRCEN desc CRCEN 13 13 read-write BIDIOE desc BIDIOE 14 14 read-write BIDIMODE desc BIDIMODE 15 15 read-write CR2 desc CR2 0x4 32 read-write 0x0 RXDMAEN desc RXDMAEN 0 0 read-write TXDMAEN desc TXDMAEN 1 1 read-write SSOE desc SSOE 2 2 read-write CLRTXFIFO desc CLRTXFIFO 4 4 read-write ERRIE desc ERRIE 5 5 read-write RXNEIE desc RXNEIE 6 6 read-write TXEIE desc TXEIE 7 7 read-write FRXTH desc FRXTH 12 12 read-write LDMA_RX desc LDMA_RX 13 13 read-write LDMA_TX desc LDMA_TX 14 14 read-write SR desc SR 0x8 32 read-write 0x2 RXNE desc RXNE 0 0 read-only TXE desc TXE 1 1 read-only CHSIDE desc CHSIDE 2 2 read-only UDR desc UDR 3 3 read-only CRCERR desc CRCERR 4 4 read-write MODF desc MODF 5 5 read-only OVR desc OVR 6 6 read-only BSY desc BSY 7 7 read-only FRLVL desc FRLVL 10 9 read-only FTLVL desc FTLVL 12 11 read-only DR desc DR 0xC 32 read-write 0x0 DR desc DR 15 0 read-write CRCPR desc CRCPR 0x10 32 read-write 0x7 CRCPOLY desc CRCPOLY 15 0 read-write RXCRCR desc RXCRCR 0x14 32 read-only 0x0 RXCRC desc RXCRC 15 0 read-only TXCRCR desc TXCRCR 0x18 32 read-only 0x0 TXCRC desc TXCRC 15 0 read-only I2SCFGR desc I2SCFGR 0x1C 32 read-write 0x0 CHLEN desc CHLEN 0 0 read-write DATLEN desc DATLEN 2 1 read-write CKPOL desc CKPOL 3 3 read-write I2SSTD desc I2SSTD 5 4 read-write PCMSYNC desc PCMSYNC 7 7 read-write I2SCFG desc I2SCFG 9 8 read-write I2SE desc I2SE 10 10 read-write I2SMOD desc I2SMOD 11 11 read-write I2SPR desc I2SPR 0x20 32 read-write 0x2 I2SDIV desc I2SDIV 7 0 read-write ODD desc ODD 8 8 read-write MCKOE desc MCKOE 9 9 read-write SPI2 0x40003800 SPI2 SPI2 global Interrupt 26 SYSCFG desc SYSCFG SYSCFG 0x40010000 0x0 0x200 registers CFGR1 desc CFGR1 0x0 32 read-write 0xFF0000 MEM_MODE desc MEM_MODE 1 0 read-write TIM1_IC1_SRC desc TIM1_IC1_SRC 3 2 read-write TIM2_IC4_SRC desc TIM2_IC4_SRC 5 4 read-write TIM3_IC1_SRC desc TIM3_IC1_SRC 7 6 read-write ETR_SRC_TIM1 desc ETR_SRC_TIM1 10 8 read-write ETR_SRC_TIM2 desc ETR_SRC_TIM2 14 12 read-write ETR_SRC_TIM3 desc ETR_SRC_TIM3 18 16 read-write GPIO_AHB_SEL desc GPIO_AHB_SEL 24 24 read-write CFGR2 desc CFGR2 0x4 32 read-write 0x4 LOCKUP_LOCK desc LOCKUP_LOCK 0 0 read-write PVD_LOCK desc PVD_LOCK 2 2 read-write COMP1_BRK_TIM1 desc COMP1_BRK_TIM1 3 3 read-write COMP2_BRK_TIM1 desc COMP2_BRK_TIM1 4 4 read-write COMP3_BRK_TIM1 desc COMP3_BRK_TIM1 5 5 read-write COMP1_BRK_TIM15 desc COMP1_BRK_TIM15 6 6 read-write COMP2_BRK_TIM15 desc COMP2_BRK_TIM15 7 7 read-write COMP3_BRK_TIM15 desc COMP3_BRK_TIM15 8 8 read-write COMP1_BRK_TIM16 desc COMP1_BRK_TIM16 9 9 read-write COMP2_BRK_TIM16 desc COMP2_BRK_TIM16 10 10 read-write COMP3_BRK_TIM16 desc COMP3_BRK_TIM16 11 11 read-write COMP1_BRK_TIM17 desc COMP1_BRK_TIM17 12 12 read-write COMP2_BRK_TIM17 desc COMP2_BRK_TIM17 13 13 read-write COMP3_BRK_TIM17 desc COMP3_BRK_TIM17 14 14 read-write COMP1_OCREF_CLR_TIM1 desc COMP1_OCREF_CLR_TIM1 15 15 read-write COMP1_OCREF_CLR_TIM2 desc COMP1_OCREF_CLR_TIM2 16 16 read-write COMP1_OCREF_CLR_TIM3 desc COMP1_OCREF_CLR_TIM3 17 17 read-write COMP2_OCREF_CLR_TIM1 desc COMP2_OCREF_CLR_TIM1 18 18 read-write COMP2_OCREF_CLR_TIM2 desc COMP2_OCREF_CLR_TIM2 19 19 read-write COMP2_OCREF_CLR_TIM3 desc COMP2_OCREF_CLR_TIM3 20 20 read-write COMP3_OCREF_CLR_TIM1 desc COMP3_OCREF_CLR_TIM1 21 21 read-write COMP3_OCREF_CLR_TIM2 desc COMP3_OCREF_CLR_TIM2 22 22 read-write COMP3_OCREF_CLR_TIM3 desc COMP3_OCREF_CLR_TIM3 23 23 read-write CFGR3 desc CFGR3 0x8 32 read-write 0x0 DMA1_MAP desc DMA1_MAP 5 0 read-write DMA2_MAP desc DMA2_MAP 13 8 read-write DMA3_MAP desc DMA3_MAP 21 16 read-write DMA4_MAP desc DMA4_MAP 29 24 read-write CFGR4 desc CFGR4 0xC 32 read-write 0x0 DMA5_MAP desc DMA5_MAP 5 0 read-write DMA6_MAP desc DMA6_MAP 13 8 read-write DMA7_MAP desc DMA7_MAP 21 16 read-write PAENS desc PAENS 0x10 32 read-write 0x0 PA_ENS desc PA_ENS 15 0 read-write PBENS desc PBENS 0x14 32 read-write 0x0 PB_ENS desc PB_ENS 15 0 read-write PCENS desc PCENS 0x18 32 read-write 0x0 PC_ENS desc PC_ENS 15 0 read-write PFENS desc PFENS 0x1C 32 read-write 0x0 PF_ENS desc PF_ENS 15 0 read-write EIIC desc EIIC 0x20 32 read-write 0x0 PA_EIIC desc PA_EIIC 1 0 read-write PB_EIIC desc PB_EIIC 16 8 read-write PF_EIIC desc PF_EIIC 25 24 read-write TIM1 Advanced timer TIM 0x40012C00 0x0 0x400 registers TIM1_BRK_UP_TRG_COM TIM1 Break, Update, Trigger and Commutation Interrupt 13 TIM1_CC TIM1 Capture Compare Interrupt 14 CR1 desc CR1 0x0 32 read-write 0x0 0x3FF CEN desc CEN 0 0 read-write UDIS desc UDIS 1 1 read-write URS desc URS 2 2 read-write OPM desc OPM 3 3 read-write DIR desc DIR 4 4 read-write CMS desc CMS 6 5 read-write ARPE desc ARPE 7 7 read-write CKD desc CKD 9 8 read-write CR2 desc CR2 0x4 32 read-write 0x0 0xF8 CCDS desc CCDS 3 3 read-write MMS desc MMS 6 4 read-write TI1S desc TI1S 7 7 read-write SMCR desc SMCR 0x8 32 read-write 0x0 0xFFF7 SMS desc SMS 2 0 read-write TS desc TS 6 4 read-write MSM desc MSM 7 7 read-write ETF desc ETF 11 8 read-write ETPS desc ETPS 13 12 read-write ECE desc ECE 14 14 read-write ETP desc ETP 15 15 read-write DIER desc DIER 0xC 32 read-write 0x0 0x5F5F UIE desc UIE 0 0 read-write CC1IE desc CC1IE 1 1 read-write CC2IE desc CC2IE 2 2 read-write CC3IE desc CC3IE 3 3 read-write CC4IE desc CC4IE 4 4 read-write TIE desc TIE 6 6 read-write UDE desc UDE 8 8 read-write CC1DE desc CC1DE 9 9 read-write CC2DE desc CC2DE 10 10 read-write CC3DE desc CC3DE 11 11 read-write CC4DE desc CC4DE 12 12 read-write TDE desc TDE 14 14 read-write SR desc SR 0x10 32 read-write 0x0 0x1E5F UIF desc UIF 0 0 read-write CC1IF desc CC1IF 1 1 read-write CC2IF desc CC2IF 2 2 read-write CC3IF desc CC3IF 3 3 read-write CC4IF desc CC4IF 4 4 read-write COMIF desc COMIF 5 5 read-write TIF desc TIF 6 6 read-write BIF desc BIF 7 7 read-write CC1OF desc CC1OF 9 9 read-write CC2OF desc CC2OF 10 10 read-write CC3OF desc CC3OF 11 11 read-write CC4OF desc CC4OF 12 12 read-write IC1IR desc IC1IR 16 16 read-write IC2IR desc IC2IR 17 17 read-write IC3IR desc IC3IR 18 18 read-write IC4IR desc IC3IR 19 19 read-write IC1IF desc IC1IF 20 20 read-write IC2IF desc IC2IF 21 21 read-write IC3IF desc IC3IF 22 22 read-write IC4IF desc IC3IF 23 23 read-write EGR desc EGR 0x14 32 write-only 0x0 0x5F UG desc UG 0 0 write-only CC1G Capture/Compare 1 Generation 1 1 write-only CC2G desc CC2G 2 2 write-only CC3G desc CC3G 3 3 write-only CC4G desc CC4G 4 4 write-only TG desc TG 6 6 write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write OC1FE desc OC1FE 2 2 read-write OC1PE desc OC1PE 3 3 read-write OC1M desc OC1M 6 4 read-write OC1CE desc OC1CE 7 7 read-write CC2S desc CC2S 9 8 read-write OC2FE desc OC2FE 10 10 read-write OC2PE desc OC2PE 11 11 read-write OC2M desc OC2M 14 12 read-write OC2CE desc OC2CE 15 15 read-write CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write IC1PSC desc IC1PSC 3 2 read-write IC1F desc IC1F 7 4 read-write CC2S desc CC2S 9 8 read-write IC2PSC desc IC2PSC 11 10 read-write IC2F desc IC2F 15 12 read-write CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C 32 read-write 0x0 0xFFFF CC3S desc CC3S 1 0 read-write OC3FE desc OC3FE 2 2 read-write OC3PE desc OC3PE 3 3 read-write OC3M desc OC3M 6 4 read-write OC3CE desc OC3CE 7 7 read-write CC4S desc CC4S 9 8 read-write OC4FE desc OC4FE 10 10 read-write OC4PE desc OC4PE 11 11 read-write OC4M desc OC4M 14 12 read-write OC4CE desc OC4CE 15 15 read-write CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C 32 read-write 0x0 0xFFFF CC3S desc CC3S 1 0 read-write IC3PSC desc IC3PSC 3 2 read-write IC3F desc IC3F 7 4 read-write CC4S desc CC4S 9 8 read-write IC4PSC desc IC4PSC 11 10 read-write IC4F desc IC4F 15 12 read-write CCER desc CCER 0x20 32 read-write 0x0 0x3333 CC1E desc CC1E 0 0 read-write CC1P desc CC1P 1 1 read-write CC2E desc CC2E 4 4 read-write CC2P desc CC2P 5 5 read-write CC3E desc CC3E 8 8 read-write CC3P desc CC3P 9 9 read-write CC4E desc CC4E 12 12 read-write CC4P desc CC4P 13 13 read-write CNT desc CNT 0x24 32 read-write 0x0 0xFFFF CNT desc CNT 15 0 read-write PSC desc PSC 0x28 32 read-write 0x0 0xFFFF PSC desc PSC 15 0 read-write ARR desc ARR 0x2C 32 read-write 0xFFFF 0xFFFF ARR desc ARR 15 0 read-write RCR desc RCR 0x30 32 read-write 0xFFFF 0xFFFF REP desc REP 7 0 read-write CCR1 desc CCR1 0x34 32 read-write 0x0 0xFFFF CCR1 desc CCR1 15 0 read-write CCR2 desc CCR2 0x38 32 read-write 0x0 0xFFFF CCR2 desc CCR2 15 0 read-write CCR3 desc CCR3 0x3C 32 read-write 0x0 0xFFFF CCR3 desc CCR3 15 0 read-write CCR4 desc CCR4 0x40 32 read-write 0x0 0xFFFF CCR4 desc CCR4 15 0 read-write BDTR desc BDTR 0x44 32 read-write 0x0 0xFFFF DTG desc DTG 7 0 read-write LOCK desc LOCK 9 8 read-write OSSI desc OSSI 10 10 read-write OSSR desc OSSR 11 11 read-write BKE desc BKE 12 12 read-write BKP desc BKP 13 13 read-write AOE desc AOE 14 14 read-write MOE desc MOE 15 15 read-write DCR desc DCR 0x48 32 read-write 0x0 0x1F1F DBA desc DBA 4 0 read-write DBL desc DBL 12 8 read-write DMAR desc DMAR 0x4C 32 read-write 0x0 0xFFFF DMAB desc DMAB 15 0 read-write TIM2 desc TIM TIM 0x40000000 0x0 0x400 registers TIM2 TIM2 global Interrupt 15 CR1 desc CR1 0x0 32 read-write 0x0 0x3FF CEN desc CEN 0 0 read-write UDIS desc UDIS 1 1 read-write URS desc URS 2 2 read-write OPM desc OPM 3 3 read-write DIR desc DIR 4 4 read-write CMS desc CMS 6 5 read-write ARPE desc ARPE 7 7 read-write CKD desc CKD 9 8 read-write CR2 desc CR2 0x4 32 read-write 0x0 0xF8 CCDS desc CCDS 3 3 read-write MMS desc MMS 6 4 read-write TI1S desc TI1S 7 7 read-write SMCR desc SMCR 0x8 32 read-write 0x0 0xFFF7 SMS desc SMS 2 0 read-write TS desc TS 6 4 read-write MSM desc MSM 7 7 read-write ETF desc ETF 11 8 read-write ETPS desc ETPS 13 12 read-write ECE desc ECE 14 14 read-write ETP desc ETP 15 15 read-write DIER desc DIER 0xC 32 read-write 0x0 0x5F5F UIE desc UIE 0 0 read-write CC1IE desc CC1IE 1 1 read-write CC2IE desc CC2IE 2 2 read-write CC3IE desc CC3IE 3 3 read-write CC4IE desc CC4IE 4 4 read-write TIE desc TIE 6 6 read-write UDE desc UDE 8 8 read-write CC1DE desc CC1DE 9 9 read-write CC2DE desc CC2DE 10 10 read-write CC3DE desc CC3DE 11 11 read-write CC4DE desc CC4DE 12 12 read-write TDE desc TDE 14 14 read-write SR desc SR 0x10 32 read-write 0x0 0x1E5F UIF desc UIF 0 0 read-write CC1IF desc CC1IF 1 1 read-write CC2IF desc CC2IF 2 2 read-write CC3IF desc CC3IF 3 3 read-write CC4IF desc CC4IF 4 4 read-write COMIF desc COMIF 5 5 read-write TIF desc TIF 6 6 read-write BIF desc BIF 7 7 read-write CC1OF desc CC1OF 9 9 read-write CC2OF desc CC2OF 10 10 read-write CC3OF desc CC3OF 11 11 read-write CC4OF desc CC4OF 12 12 read-write IC1IR desc IC1IR 16 16 read-write IC2IR desc IC2IR 17 17 read-write IC3IR desc IC3IR 18 18 read-write IC4IR desc IC3IR 19 19 read-write IC1IF desc IC1IF 20 20 read-write IC2IF desc IC2IF 21 21 read-write IC3IF desc IC3IF 22 22 read-write IC4IF desc IC3IF 23 23 read-write EGR desc EGR 0x14 32 write-only 0x0 0x5F UG desc UG 0 0 write-only CC1G Capture/Compare 1 Generation 1 1 write-only CC2G desc CC2G 2 2 write-only CC3G desc CC3G 3 3 write-only CC4G desc CC4G 4 4 write-only TG desc TG 6 6 write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write OC1FE desc OC1FE 2 2 read-write OC1PE desc OC1PE 3 3 read-write OC1M desc OC1M 6 4 read-write OC1CE desc OC1CE 7 7 read-write CC2S desc CC2S 9 8 read-write OC2FE desc OC2FE 10 10 read-write OC2PE desc OC2PE 11 11 read-write OC2M desc OC2M 14 12 read-write OC2CE desc OC2CE 15 15 read-write CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write IC1PSC desc IC1PSC 3 2 read-write IC1F desc IC1F 7 4 read-write CC2S desc CC2S 9 8 read-write IC2PSC desc IC2PSC 11 10 read-write IC2F desc IC2F 15 12 read-write CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C 32 read-write 0x0 0xFFFF CC3S desc CC3S 1 0 read-write OC3FE desc OC3FE 2 2 read-write OC3PE desc OC3PE 3 3 read-write OC3M desc OC3M 6 4 read-write OC3CE desc OC3CE 7 7 read-write CC4S desc CC4S 9 8 read-write OC4FE desc OC4FE 10 10 read-write OC4PE desc OC4PE 11 11 read-write OC4M desc OC4M 14 12 read-write OC4CE desc OC4CE 15 15 read-write CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C 32 read-write 0x0 0xFFFF CC3S desc CC3S 1 0 read-write IC3PSC desc IC3PSC 3 2 read-write IC3F desc IC3F 7 4 read-write CC4S desc CC4S 9 8 read-write IC4PSC desc IC4PSC 11 10 read-write IC4F desc IC4F 15 12 read-write CCER desc CCER 0x20 32 read-write 0x0 0x3333 CC1E desc CC1E 0 0 read-write CC1P desc CC1P 1 1 read-write CC2E desc CC2E 4 4 read-write CC2P desc CC2P 5 5 read-write CC3E desc CC3E 8 8 read-write CC3P desc CC3P 9 9 read-write CC4E desc CC4E 12 12 read-write CC4P desc CC4P 13 13 read-write CNT desc CNT 0x24 32 read-write 0x0 0xFFFF CNT desc CNT 15 0 read-write PSC desc PSC 0x28 32 read-write 0x0 0xFFFF PSC desc PSC 15 0 read-write ARR desc ARR 0x2C 32 read-write 0xFFFF 0xFFFF ARR desc ARR 15 0 read-write CCR1 desc CCR1 0x34 32 read-write 0x0 0xFFFF CCR1 desc CCR1 15 0 read-write CCR2 desc CCR2 0x38 32 read-write 0x0 0xFFFF CCR2 desc CCR2 15 0 read-write CCR3 desc CCR3 0x3C 32 read-write 0x0 0xFFFF CCR3 desc CCR3 15 0 read-write CCR4 desc CCR4 0x40 32 read-write 0x0 0xFFFF CCR4 desc CCR4 15 0 read-write DCR desc DCR 0x48 32 read-write 0x0 0x1F1F DBA desc DBA 4 0 read-write DBL desc DBL 12 8 read-write DMAR desc DMAR 0x4C 32 read-write 0x0 0xFFFF DMAB desc DMAB 15 0 read-write TIM3 General purpose timer TIM 0x40000400 0x00 0x400 registers TIM3 TIM3 global Interrupt 16 CR1 desc CR1 0x0 32 read-write 0x0 0x3FF CEN desc CEN 0 0 read-write UDIS desc UDIS 1 1 read-write URS desc URS 2 2 read-write OPM desc OPM 3 3 read-write DIR desc DIR 4 4 read-write CMS desc CMS 6 5 read-write ARPE desc ARPE 7 7 read-write CKD desc CKD 9 8 read-write CR2 desc CR2 0x4 32 read-write 0x0 0xF8 CCDS desc CCDS 3 3 read-write MMS desc MMS 6 4 read-write TI1S desc TI1S 7 7 read-write SMCR desc SMCR 0x8 32 read-write 0x0 0xFFF7 SMS desc SMS 2 0 read-write TS desc TS 6 4 read-write MSM desc MSM 7 7 read-write ETF desc ETF 11 8 read-write ETPS desc ETPS 13 12 read-write ECE desc ECE 14 14 read-write ETP desc ETP 15 15 read-write DIER desc DIER 0xC 32 read-write 0x0 0x5F5F UIE desc UIE 0 0 read-write CC1IE desc CC1IE 1 1 read-write CC2IE desc CC2IE 2 2 read-write CC3IE desc CC3IE 3 3 read-write CC4IE desc CC4IE 4 4 read-write TIE desc TIE 6 6 read-write UDE desc UDE 8 8 read-write CC1DE desc CC1DE 9 9 read-write CC2DE desc CC2DE 10 10 read-write CC3DE desc CC3DE 11 11 read-write CC4DE desc CC4DE 12 12 read-write TDE desc TDE 14 14 read-write SR desc SR 0x10 32 read-write 0x0 0x1E5F UIF desc UIF 0 0 read-write CC1IF desc CC1IF 1 1 read-write CC2IF desc CC2IF 2 2 read-write CC3IF desc CC3IF 3 3 read-write CC4IF desc CC4IF 4 4 read-write COMIF desc COMIF 5 5 read-write TIF desc TIF 6 6 read-write BIF desc BIF 7 7 read-write CC1OF desc CC1OF 9 9 read-write CC2OF desc CC2OF 10 10 read-write CC3OF desc CC3OF 11 11 read-write CC4OF desc CC4OF 12 12 read-write IC1IR desc IC1IR 16 16 read-write IC2IR desc IC2IR 17 17 read-write IC3IR desc IC3IR 18 18 read-write IC4IR desc IC3IR 19 19 read-write IC1IF desc IC1IF 20 20 read-write IC2IF desc IC2IF 21 21 read-write IC3IF desc IC3IF 22 22 read-write IC4IF desc IC3IF 23 23 read-write EGR desc EGR 0x14 32 write-only 0x0 0x5F UG desc UG 0 0 write-only CC1G Capture/Compare 1 Generation 1 1 write-only CC2G desc CC2G 2 2 write-only CC3G desc CC3G 3 3 write-only CC4G desc CC4G 4 4 write-only TG desc TG 6 6 write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write OC1FE desc OC1FE 2 2 read-write OC1PE desc OC1PE 3 3 read-write OC1M desc OC1M 6 4 read-write OC1CE desc OC1CE 7 7 read-write CC2S desc CC2S 9 8 read-write OC2FE desc OC2FE 10 10 read-write OC2PE desc OC2PE 11 11 read-write OC2M desc OC2M 14 12 read-write OC2CE desc OC2CE 15 15 read-write CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write IC1PSC desc IC1PSC 3 2 read-write IC1F desc IC1F 7 4 read-write CC2S desc CC2S 9 8 read-write IC2PSC desc IC2PSC 11 10 read-write IC2F desc IC2F 15 12 read-write CCMR2_OUTPUT desc CCMR2:OUTPUT 0x1C 32 read-write 0x0 0xFFFF CC3S desc CC3S 1 0 read-write OC3FE desc OC3FE 2 2 read-write OC3PE desc OC3PE 3 3 read-write OC3M desc OC3M 6 4 read-write OC3CE desc OC3CE 7 7 read-write CC4S desc CC4S 9 8 read-write OC4FE desc OC4FE 10 10 read-write OC4PE desc OC4PE 11 11 read-write OC4M desc OC4M 14 12 read-write OC4CE desc OC4CE 15 15 read-write CCMR2_INPUT desc CCMR2:INPUT CCMR2_OUTPUT 0x1C 32 read-write 0x0 0xFFFF CC3S desc CC3S 1 0 read-write IC3PSC desc IC3PSC 3 2 read-write IC3F desc IC3F 7 4 read-write CC4S desc CC4S 9 8 read-write IC4PSC desc IC4PSC 11 10 read-write IC4F desc IC4F 15 12 read-write CCER desc CCER 0x20 32 read-write 0x0 0x3333 CC1E desc CC1E 0 0 read-write CC1P desc CC1P 1 1 read-write CC2E desc CC2E 4 4 read-write CC2P desc CC2P 5 5 read-write CC3E desc CC3E 8 8 read-write CC3P desc CC3P 9 9 read-write CC4E desc CC4E 12 12 read-write CC4P desc CC4P 13 13 read-write CNT desc CNT 0x24 32 read-write 0x0 0xFFFF CNT desc CNT 15 0 read-write PSC desc PSC 0x28 32 read-write 0x0 0xFFFF PSC desc PSC 15 0 read-write ARR desc ARR 0x2C 32 read-write 0xFFFF 0xFFFF ARR desc ARR 15 0 read-write CCR1 desc CCR1 0x34 32 read-write 0x0 0xFFFF CCR1 desc CCR1 15 0 read-write CCR2 desc CCR2 0x38 32 read-write 0x0 0xFFFF CCR2 desc CCR2 15 0 read-write CCR3 desc CCR3 0x3C 32 read-write 0x0 0xFFFF CCR3 desc CCR3 15 0 read-write CCR4 desc CCR4 0x40 32 read-write 0x0 0xFFFF CCR4 desc CCR4 15 0 read-write DCR desc DCR 0x48 32 read-write 0x0 0x1F1F DBA desc DBA 4 0 read-write DBL desc DBL 12 8 read-write DMAR desc DMAR 0x4C 32 read-write 0x0 0xFFFF DMAB desc DMAB 15 0 read-write TIM6 desc TIM TIM 0x40001000 0x0 0x400 registers TIM6_LPTIM1_DAC TIM6, LPTIM1, DAC global Interrupts 17 CR1 desc CR1 0x0 32 read-write 0x0 0x3FF CEN desc CEN 0 0 read-write UDIS desc UDIS 1 1 read-write URS desc URS 2 2 read-write OPM desc OPM 3 3 read-write DIR desc DIR 4 4 read-write CMS desc CMS 6 5 read-write ARPE desc ARPE 7 7 read-write CKD desc CKD 9 8 read-write CR2 desc CR2 0x4 32 read-write 0x0 0xF8 CCDS desc CCDS 3 3 read-write MMS desc MMS 6 4 read-write TI1S desc TI1S 7 7 read-write DIER desc DIER 0xC 32 read-write 0x0 0x5F5F UIE desc UIE 0 0 read-write CC1IE desc CC1IE 1 1 read-write CC2IE desc CC2IE 2 2 read-write CC3IE desc CC3IE 3 3 read-write CC4IE desc CC4IE 4 4 read-write TIE desc TIE 6 6 read-write UDE desc UDE 8 8 read-write CC1DE desc CC1DE 9 9 read-write CC2DE desc CC2DE 10 10 read-write CC3DE desc CC3DE 11 11 read-write CC4DE desc CC4DE 12 12 read-write TDE desc TDE 14 14 read-write SR desc SR 0x10 32 read-write 0x0 0x1E5F UIF desc UIF 0 0 read-write CC1IF desc CC1IF 1 1 read-write CC2IF desc CC2IF 2 2 read-write CC3IF desc CC3IF 3 3 read-write CC4IF desc CC4IF 4 4 read-write COMIF desc COMIF 5 5 read-write TIF desc TIF 6 6 read-write BIF desc BIF 7 7 read-write CC1OF desc CC1OF 9 9 read-write CC2OF desc CC2OF 10 10 read-write CC3OF desc CC3OF 11 11 read-write CC4OF desc CC4OF 12 12 read-write IC1IR desc IC1IR 16 16 read-write IC2IR desc IC2IR 17 17 read-write IC3IR desc IC3IR 18 18 read-write IC4IR desc IC3IR 19 19 read-write IC1IF desc IC1IF 20 20 read-write IC2IF desc IC2IF 21 21 read-write IC3IF desc IC3IF 22 22 read-write IC4IF desc IC3IF 23 23 read-write EGR desc EGR 0x14 32 write-only 0x0 0x5F UG desc UG 0 0 write-only CC1G Capture/Compare 1 Generation 1 1 write-only CC2G desc CC2G 2 2 write-only CC3G desc CC3G 3 3 write-only CC4G desc CC4G 4 4 write-only TG desc TG 6 6 write-only CNT desc CNT 0x24 32 read-write 0x0 0xFFFF CNT desc CNT 15 0 read-write PSC desc PSC 0x28 32 read-write 0x0 0xFFFF PSC desc PSC 15 0 read-write ARR desc ARR 0x2C 32 read-write 0xFFFF 0xFFFF ARR desc ARR 15 0 read-write TIM7 desc TIM TIM 0x40001400 0x0 0x400 registers TIM7 TIM7 global Interrupt 18 TIM14 General purpose timer TIM 0x40002000 0x00 0x400 registers TIM14 TIM14 global Interrupt 19 CR1 desc CR1 0x0 32 read-write 0x0 0x3FF CEN desc CEN 0 0 read-write UDIS desc UDIS 1 1 read-write URS desc URS 2 2 read-write OPM desc OPM 3 3 read-write DIR desc DIR 4 4 read-write CMS desc CMS 6 5 read-write ARPE desc ARPE 7 7 read-write CKD desc CKD 9 8 read-write DIER desc DIER 0xC 32 read-write 0x0 0x5F5F UIE desc UIE 0 0 read-write CC1IE desc CC1IE 1 1 read-write CC2IE desc CC2IE 2 2 read-write CC3IE desc CC3IE 3 3 read-write CC4IE desc CC4IE 4 4 read-write TIE desc TIE 6 6 read-write UDE desc UDE 8 8 read-write CC1DE desc CC1DE 9 9 read-write CC2DE desc CC2DE 10 10 read-write CC3DE desc CC3DE 11 11 read-write CC4DE desc CC4DE 12 12 read-write TDE desc TDE 14 14 read-write SR desc SR 0x10 32 read-write 0x0 0x1E5F UIF desc UIF 0 0 read-write CC1IF desc CC1IF 1 1 read-write CC2IF desc CC2IF 2 2 read-write CC3IF desc CC3IF 3 3 read-write CC4IF desc CC4IF 4 4 read-write TIF desc TIF 6 6 read-write CC1OF desc CC1OF 9 9 read-write CC2OF desc CC2OF 10 10 read-write CC3OF desc CC3OF 11 11 read-write CC4OF desc CC4OF 12 12 read-write EGR desc EGR 0x14 32 write-only 0x0 0x5F UG desc UG 0 0 write-only CC1G Capture/Compare 1 Generation 1 1 write-only CC2G desc CC2G 2 2 write-only CC3G desc CC3G 3 3 write-only CC4G desc CC4G 4 4 write-only TG desc TG 6 6 write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write OC1FE desc OC1FE 2 2 read-write OC1PE desc OC1PE 3 3 read-write OC1M desc OC1M 6 4 read-write OC1CE desc OC1CE 7 7 read-write CC2S desc CC2S 9 8 read-write OC2FE desc OC2FE 10 10 read-write OC2PE desc OC2PE 11 11 read-write OC2M desc OC2M 14 12 read-write OC2CE desc OC2CE 15 15 read-write CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write IC1PSC desc IC1PSC 3 2 read-write IC1F desc IC1F 7 4 read-write CC2S desc CC2S 9 8 read-write IC2PSC desc IC2PSC 11 10 read-write IC2F desc IC2F 15 12 read-write CCER desc CCER 0x20 32 read-write 0x0 0x3333 CC1E desc CC1E 0 0 read-write CC1P desc CC1P 1 1 read-write CC2E desc CC2E 4 4 read-write CC2P desc CC2P 5 5 read-write CC3E desc CC3E 8 8 read-write CC3P desc CC3P 9 9 read-write CC4E desc CC4E 12 12 read-write CC4P desc CC4P 13 13 read-write CNT desc CNT 0x24 32 read-write 0x0 0xFFFF CNT desc CNT 15 0 read-write PSC desc PSC 0x28 32 read-write 0x0 0xFFFF PSC desc PSC 15 0 read-write ARR desc ARR 0x2C 32 read-write 0xFFFF 0xFFFF ARR desc ARR 15 0 read-write CCR1 desc CCR1 0x34 32 read-write 0x0 0xFFFF CCR1 desc CCR1 15 0 read-write OR desc OR 0x50 32 read-write 0x0 TI1_RMP desc TI1_RMP 1 0 read-write TIM15 0x40014000 0x0 0x400 registers TIM15 TIM15 global Interrupt 20 CR1 desc CR1 0x0 32 read-write 0x0 0x3FF CEN desc CEN 0 0 read-write UDIS desc UDIS 1 1 read-write URS desc URS 2 2 read-write OPM desc OPM 3 3 read-write DIR desc DIR 4 4 read-write CMS desc CMS 6 5 read-write ARPE desc ARPE 7 7 read-write CKD desc CKD 9 8 read-write CR2 desc CR2 0x4 32 read-write 0x0 0xF8 CCDS desc CCDS 3 3 read-write MMS desc MMS 6 4 read-write TI1S desc TI1S 7 7 read-write SMCR desc SMCR 0x8 32 read-write 0x0 0xFFF7 SMS desc SMS 2 0 read-write TS desc TS 6 4 read-write MSM desc MSM 7 7 read-write ETF desc ETF 11 8 read-write ETPS desc ETPS 13 12 read-write ECE desc ECE 14 14 read-write ETP desc ETP 15 15 read-write DIER desc DIER 0xC 32 read-write 0x0 0x5F5F UIE desc UIE 0 0 read-write CC1IE desc CC1IE 1 1 read-write CC2IE desc CC2IE 2 2 read-write CC3IE desc CC3IE 3 3 read-write CC4IE desc CC4IE 4 4 read-write TIE desc TIE 6 6 read-write UDE desc UDE 8 8 read-write CC1DE desc CC1DE 9 9 read-write CC2DE desc CC2DE 10 10 read-write CC3DE desc CC3DE 11 11 read-write CC4DE desc CC4DE 12 12 read-write TDE desc TDE 14 14 read-write SR desc SR 0x10 32 read-write 0x0 0x1E5F UIF desc UIF 0 0 read-write CC1IF desc CC1IF 1 1 read-write CC2IF desc CC2IF 2 2 read-write CC3IF desc CC3IF 3 3 read-write CC4IF desc CC4IF 4 4 read-write COMIF desc COMIF 5 5 read-write TIF desc TIF 6 6 read-write BIF desc BIF 7 7 read-write CC1OF desc CC1OF 9 9 read-write CC2OF desc CC2OF 10 10 read-write CC3OF desc CC3OF 11 11 read-write CC4OF desc CC4OF 12 12 read-write IC1IR desc IC1IR 16 16 read-write IC2IR desc IC2IR 17 17 read-write IC3IR desc IC3IR 18 18 read-write IC4IR desc IC3IR 19 19 read-write IC1IF desc IC1IF 20 20 read-write IC2IF desc IC2IF 21 21 read-write IC3IF desc IC3IF 22 22 read-write IC4IF desc IC3IF 23 23 read-write EGR desc EGR 0x14 32 write-only 0x0 0x5F UG desc UG 0 0 write-only CC1G Capture/Compare 1 Generation 1 1 write-only CC2G desc CC2G 2 2 write-only CC3G desc CC3G 3 3 write-only CC4G desc CC4G 4 4 write-only TG desc TG 6 6 write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write OC1FE desc OC1FE 2 2 read-write OC1PE desc OC1PE 3 3 read-write OC1M desc OC1M 6 4 read-write OC1CE desc OC1CE 7 7 read-write CC2S desc CC2S 9 8 read-write OC2FE desc OC2FE 10 10 read-write OC2PE desc OC2PE 11 11 read-write OC2M desc OC2M 14 12 read-write OC2CE desc OC2CE 15 15 read-write CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write IC1PSC desc IC1PSC 3 2 read-write IC1F desc IC1F 7 4 read-write CC2S desc CC2S 9 8 read-write IC2PSC desc IC2PSC 11 10 read-write IC2F desc IC2F 15 12 read-write CCER desc CCER 0x20 32 read-write 0x0 0x3333 CC1E desc CC1E 0 0 read-write CC1P desc CC1P 1 1 read-write CC2E desc CC2E 4 4 read-write CC2P desc CC2P 5 5 read-write CC3E desc CC3E 8 8 read-write CC3P desc CC3P 9 9 read-write CC4E desc CC4E 12 12 read-write CC4P desc CC4P 13 13 read-write CNT desc CNT 0x24 32 read-write 0x0 0xFFFF CNT desc CNT 15 0 read-write PSC desc PSC 0x28 32 read-write 0x0 0xFFFF PSC desc PSC 15 0 read-write ARR desc ARR 0x2C 32 read-write 0xFFFF 0xFFFF ARR desc ARR 15 0 read-write RCR desc RCR 0x30 32 read-write 0xFFFF 0xFFFF REP desc REP 7 0 read-write CCR1 desc CCR1 0x34 32 read-write 0x0 0xFFFF CCR1 desc CCR1 15 0 read-write CCR2 desc CCR2 0x38 32 read-write 0x0 0xFFFF CCR2 desc CCR2 15 0 read-write BDTR desc BDTR 0x44 32 read-write 0x0 0xFFFF DTG desc DTG 7 0 read-write LOCK desc LOCK 9 8 read-write OSSI desc OSSI 10 10 read-write OSSR desc OSSR 11 11 read-write BKE desc BKE 12 12 read-write BKP desc BKP 13 13 read-write AOE desc AOE 14 14 read-write MOE desc MOE 15 15 read-write DCR desc DCR 0x48 32 read-write 0x0 0x1F1F DBA desc DBA 4 0 read-write DBL desc DBL 12 8 read-write DMAR desc DMAR 0x4C 32 read-write 0x0 0xFFFF DMAB desc DMAB 15 0 read-write TIM16 General purpose timer TIM 0x40014400 0x00 0x400 registers TIM16 TIM16 global Interrupt 21 CR1 desc CR1 0x0 32 read-write 0x0 0x3FF CEN desc CEN 0 0 read-write UDIS desc UDIS 1 1 read-write URS desc URS 2 2 read-write OPM desc OPM 3 3 read-write DIR desc DIR 4 4 read-write CMS desc CMS 6 5 read-write ARPE desc ARPE 7 7 read-write CKD desc CKD 9 8 read-write CR2 desc CR2 0x4 32 read-write 0x0 0xF8 CCDS desc CCDS 3 3 read-write MMS desc MMS 6 4 read-write TI1S desc TI1S 7 7 read-write DIER desc DIER 0xC 32 read-write 0x0 0x5F5F UIE desc UIE 0 0 read-write CC1IE desc CC1IE 1 1 read-write CC2IE desc CC2IE 2 2 read-write CC3IE desc CC3IE 3 3 read-write CC4IE desc CC4IE 4 4 read-write TIE desc TIE 6 6 read-write UDE desc UDE 8 8 read-write CC1DE desc CC1DE 9 9 read-write CC2DE desc CC2DE 10 10 read-write CC3DE desc CC3DE 11 11 read-write CC4DE desc CC4DE 12 12 read-write TDE desc TDE 14 14 read-write SR desc SR 0x10 32 read-write 0x0 0x1E5F UIF desc UIF 0 0 read-write CC1IF desc CC1IF 1 1 read-write CC2IF desc CC2IF 2 2 read-write CC3IF desc CC3IF 3 3 read-write CC4IF desc CC4IF 4 4 read-write COMIF desc COMIF 5 5 read-write TIF desc TIF 6 6 read-write BIF desc BIF 7 7 read-write CC1OF desc CC1OF 9 9 read-write CC2OF desc CC2OF 10 10 read-write CC3OF desc CC3OF 11 11 read-write CC4OF desc CC4OF 12 12 read-write IC1IR desc IC1IR 16 16 read-write IC2IR desc IC2IR 17 17 read-write IC3IR desc IC3IR 18 18 read-write IC4IR desc IC3IR 19 19 read-write IC1IF desc IC1IF 20 20 read-write IC2IF desc IC2IF 21 21 read-write IC3IF desc IC3IF 22 22 read-write IC4IF desc IC3IF 23 23 read-write EGR desc EGR 0x14 32 write-only 0x0 0x5F UG desc UG 0 0 write-only CC1G Capture/Compare 1 Generation 1 1 write-only CC2G desc CC2G 2 2 write-only CC3G desc CC3G 3 3 write-only CC4G desc CC4G 4 4 write-only TG desc TG 6 6 write-only CCMR1_OUTPUT desc CCMR1:OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write OC1FE desc OC1FE 2 2 read-write OC1PE desc OC1PE 3 3 read-write OC1M desc OC1M 6 4 read-write OC1CE desc OC1CE 7 7 read-write CC2S desc CC2S 9 8 read-write OC2FE desc OC2FE 10 10 read-write OC2PE desc OC2PE 11 11 read-write OC2M desc OC2M 14 12 read-write OC2CE desc OC2CE 15 15 read-write CCMR1_INPUT desc CCMR1:INPUT CCMR1_OUTPUT 0x18 32 read-write 0x0 0xFFFF CC1S desc CC1S 1 0 read-write IC1PSC desc IC1PSC 3 2 read-write IC1F desc IC1F 7 4 read-write CC2S desc CC2S 9 8 read-write IC2PSC desc IC2PSC 11 10 read-write IC2F desc IC2F 15 12 read-write CCER desc CCER 0x20 32 read-write 0x0 0x3333 CC1E desc CC1E 0 0 read-write CC1P desc CC1P 1 1 read-write CC2E desc CC2E 4 4 read-write CC2P desc CC2P 5 5 read-write CC3E desc CC3E 8 8 read-write CC3P desc CC3P 9 9 read-write CC4E desc CC4E 12 12 read-write CC4P desc CC4P 13 13 read-write CNT desc CNT 0x24 32 read-write 0x0 0xFFFF CNT desc CNT 15 0 read-write PSC desc PSC 0x28 32 read-write 0x0 0xFFFF PSC desc PSC 15 0 read-write ARR desc ARR 0x2C 32 read-write 0xFFFF 0xFFFF ARR desc ARR 15 0 read-write RCR desc RCR 0x30 32 read-write 0xFFFF 0xFFFF REP desc REP 7 0 read-write CCR1 desc CCR1 0x34 32 read-write 0x0 0xFFFF CCR1 desc CCR1 15 0 read-write BDTR desc BDTR 0x44 32 read-write 0x0 0xFFFF DTG desc DTG 7 0 read-write LOCK desc LOCK 9 8 read-write OSSI desc OSSI 10 10 read-write OSSR desc OSSR 11 11 read-write BKE desc BKE 12 12 read-write BKP desc BKP 13 13 read-write AOE desc AOE 14 14 read-write MOE desc MOE 15 15 read-write DCR desc DCR 0x48 32 read-write 0x0 0x1F1F DBA desc DBA 4 0 read-write DBL desc DBL 12 8 read-write DMAR desc DMAR 0x4C 32 read-write 0x0 0xFFFF DMAB desc DMAB 15 0 read-write TIM17 0x40014800 TIM17 TIM17 global Interrupt 22 USART1 Universal synchronous asynchronous receiver transmitter USART 0x40013800 0x0 0x400 registers USART1 USART1 global Interrupt 27 SR desc SR 0x0 32 read-write 0xC0 PE desc PE 0 0 read-only FE desc FE 1 1 read-only NE desc NE 2 2 read-only ORE desc ORE 3 3 read-only IDLE desc IDLE 4 4 read-only RXNE desc RXNE 5 5 read-write TC desc TC 6 6 read-write TXE desc TXE 7 7 read-only LBD desc LBD 8 8 read-write CTS desc CTS 9 9 read-write ABRF desc ABRF 10 10 read-only ABRE desc ABRE 11 11 read-only ABRRQ desc ABRRQ 12 12 write-only DR desc DR 0x4 32 read-write 0x0 DR desc DR 8 0 read-write BRR desc BRR 0x8 32 read-write 0x0 DIV_FRACTION desc DIV_Fraction 3 0 read-write DIV_MANTISSA desc DIV_Mantissa 15 4 read-write CR1 desc CR1 0xC 32 read-write 0x0 SBK desc SBK 0 0 read-write RWU desc RWU 1 1 read-write RE desc RE 2 2 read-write TE desc TE 3 3 read-write IDLEIE desc IDLEIE 4 4 read-write RXNEIE desc RXNEIE 5 5 read-write TCIE desc TCIE 6 6 read-write TXEIE desc TXEIE 7 7 read-write PEIE desc PEIE 8 8 read-write PS desc PS 9 9 read-write PCE desc PCE 10 10 read-write WAKE desc WAKE 11 11 read-write M desc M 12 12 read-write UE desc UE 13 13 read-write CR2 desc CR2 0x10 32 read-write 0x0 ADD desc ADD 3 0 read-write LBDL desc LBDL 5 5 read-write LBDIE desc LBDIE 6 6 read-write LBCL desc LBCL 8 8 read-write CPHA desc CPHA 9 9 read-write CPOL desc CPOL 10 10 read-write CLKEN desc CLKEN 11 11 read-write STOP desc STOP 13 12 read-write LINEN desc LINEN 14 14 read-write CR3 desc CR3 0x14 32 read-write 0x0 EIE desc EIE 0 0 read-write IREN desc IREN 1 1 read-write IRLP desc IRLP 2 2 read-write HDSEL desc HDSEL 3 3 read-write NACK desc NACK 4 4 read-write SCEN desc SCEN 5 5 read-write DMAR desc DMAR 6 6 read-write DMAT desc DMAT 7 7 read-write RTSE desc RTSE 8 8 read-write CTSE desc CTSE 9 9 read-write CTSIE desc CTSIE 10 10 read-write OVER8 desc OVER8 11 11 read-write ABREN desc ABREN 12 12 read-write ABRMODE desc ABRMODE 14 13 read-write GTPR desc GTPR 0x18 32 read-write 0x0 PSC desc PSC 7 0 read-write GT desc GT 15 8 read-write USART2 0x40004400 USART2 USART2 global Interrupt 28 USART3 desc USART USART 0x40004800 0x0 0x400 registers USART3_4 USART3, 4 global Interrupts 29 USART4 desc USART USART 0x40004C00 0x0 0x400 registers USART3_4 USART3, 4 global Interrupts 29 USB USB USB 0x40005C00 0x0 0x400 registers USB USB global Interrupts 31 CR CR CR 0x0 0x20 read-write 0xFFFFFFFF ADD ADD 0 7 UPDATE UPDATE 7 1 Enable_Suspend Enable_Suspend 8 1 Suspend_Mode Suspend_Mode 9 1 Resume Resume 10 1 Reset Reset 11 1 ISO_Update ISO_Update 15 1 INTR INTR INTR 0x4 0x20 read-write 0x00000000 Suspend Suspend 0 1 Resume Resume 1 1 Reset Reset 2 1 SOF SOF 3 1 EP1OUT EP1OUT 9 1 EP2OUT EP2OUT 10 1 EP3OUT EP3OUT 11 1 EP4OUT EP4OUT 12 1 EP5OUT EP5OUT 13 1 EP0 EP0 16 1 EP1IN EP1IN 17 1 EP2IN EP2IN 18 1 EP3IN EP3IN 19 1 EP4IN EP4IN 20 1 EP5IN EP5IN 21 1 INTRE INTRE INTRE 0x8 0x20 read-write 0x00000000 EN_Suspend EN_Suspend 0 1 EN_Resume EN_Resume 1 1 EN_Reset EN_Reset 2 1 EN_SOF EN_SOF 3 1 EP1OUTE EP1OUTE 9 1 EP2OUTE EP2OUTE 10 1 EP3OUTE EP3OUTE 11 1 EP4OUTE EP4OUTE 12 1 EP5OUTE EP5OUTE 13 1 EP0 EP0 16 1 EP1INE EP1INE 17 1 EP2INE EP2INE 18 1 EP3INE EP3INE 19 1 EP4INE EP4INE 20 1 EP5INE EP5INE 21 1 FRAME FRAME FRAME 0xC 0x20 write-only 0x00000000 FramNUM FramNUM 0 11 INDEX INDEX 16 4 EP0CSR EP0CSR EP0CSR 0x10 0x20 write-only 0x00000000 OutPktRdy OutPktRdy 0 1 InPktRdy InPktRdy 1 1 SentStall SentStall 2 1 DataEnd DataEnd 3 1 SetupEnd SetupEnd 4 1 SendStall OutPktRdy 5 1 ServicedOutPktRdy ServicedOutPktRdy 6 1 ServicedSetupEnd ServicedSetupEnd 7 1 COUNT0 COUNT0 8 1 INEPxCSR INEPxCSR INEPxCSR 0x14 0x20 write-only 0x00000000 FrcDataTog FrcDataTog 3 1 DMAEnab DMAEnab 4 1 Mode Mode 5 1 ISO ISO 6 1 AutoSet AutoSet 7 1 InPktRdy InPktRdy 8 1 FIFONotEmpty FIFONotEmpty 9 1 UnderRun UnderRun 10 1 FlushFIFO FlushFIFO 11 1 SendStall SendStall 12 1 SentStall SentStall 13 1 ClrDataTog ClrDataTog 14 1 INMAXP INMAXP 16 1 OUTEPxCSR OUTEPxCSR OUTEPxCSR 0x18 0x20 write-only 0x00000000 DMAMode DMAMode 4 1 DMAEnab DMAEnab 5 1 ISO ISO 6 1 AutoClear AutoClear 7 1 OutPktRdy OutPktRdy 8 1 FIFOFull FIFOFull 9 1 OverRun OverRun 10 1 DataError DataError 11 1 FlushFIFO FlushFIFO 12 1 SendStall SendStall 13 1 SentStall SentStall 14 1 ClrDataTog ClrDataTog 15 1 INMAXP INMAXP 16 1 OUTCOUNT OUTCOUNT OUTCOUNT 0x1C 0x20 write-only 0x00000000 OUTCOUNT OUTCOUNT 0 10 WWDG Window watchdog WWDG 0x40002C00 0x0 0x400 registers WWDG Window WatchDog Interrupt 0 CR CR Control register (WWDG_CR) 0x0 0x20 read-write 0x0000007F WDGA Activation bit 7 1 T 7-bit counter (MSB to LSB) 0 7 CFR CFR Configuration register (WWDG_CFR) 0x4 0x20 read-write 0x0000007F EWI Early Wakeup Interrupt 9 1 WDGTB Timer Base 7 2 W 7-bit window value 0 7 SR SR Status register (WWDG_SR) 0x8 0x20 read-write 0x00000000 EWIF Early Wakeup Interrupt flag 0 1