/** ****************************************************************************** * @file py32f003x8.h * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. * This file contains all the peripheral register's definitions, bits * definitions and memory mapping for PY32F0xx devices. * @version v1.0.1 * ****************************************************************************** * @attention * *

© Copyright (c) Puya Semiconductor Co. * All rights reserved.

* *

* * This software component is licensed by ST under BSD 3-Clause license, * the "License"; You may not use this file except in compliance with the * License. You may obtain a copy of the License at: * opensource.org/licenses/BSD-3-Clause * ****************************************************************************** */ /** @addtogroup CMSIS_Device * @{ */ /** @addtogroup py32f003x8 * @{ */ #ifndef __PY32F003x8_H #define __PY32F003x8_H #ifdef __cplusplus extern "C" { #endif /* __cplusplus */ /** @addtogroup Configuration_section_for_CMSIS * @{ */ /** * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals */ #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */ #define __MPU_PRESENT 0 /*!< PY32F0xx do not provide MPU */ #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */ #define __NVIC_PRIO_BITS 2 /*!< PY32F0xx uses 2 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ /** * @} */ /** @addtogroup Peripheral_interrupt_number_definition * @{ */ /** * @brief PY32F0xx Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ /*!< Interrupt Number Definition */ typedef enum { /****** Cortex-M0+ Processor Exceptions Numbers ***************************************************************/ NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */ HardFault_IRQn = -13, /*!< 3 Cortex-M Hard Fault Interrupt */ SVC_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */ PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */ SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */ /****** PY32F0 specific Interrupt Numbers *********************************************************************/ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */ PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt(EXTI line 16) */ RTC_IRQn = 2, /*!< RTC interrupt through the EXTI line 19 */ FLASH_IRQn = 3, /*!< FLASH global Interrupt */ RCC_IRQn = 4, /*!< RCC global Interrupt */ EXTI0_1_IRQn = 5, /*!< EXTI 0 and 1 Interrupts */ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */ ADC_COMP_IRQn = 12, /*!< ADC&COMP Interrupts */ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */ TIM3_IRQn = 16, /*!< TIM3 global Interrupt */ LPTIM1_IRQn = 17, /*!< LPTIM1 global Interrupts */ TIM14_IRQn = 19, /*!< TIM14 global Interrupt */ TIM16_IRQn = 21, /*!< TIM16 global Interrupt */ TIM17_IRQn = 22, /*!< TIM17 global Interrupt */ I2C1_IRQn = 23, /*!< I2C1 Interrupt (combined with EXTI 23) */ SPI1_IRQn = 25, /*!< SPI1 Interrupt */ USART1_IRQn = 27, /*!< USART1 Interrupt */ USART2_IRQn = 28, /*!< USART2 Interrupt */ } IRQn_Type; /** * @} */ #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */ #include "system_py32f0xx.h" /* PY32F0xx System Header */ #include /** @addtogroup Peripheral_registers_structures * @{ */ /** * @brief Analog to Digital Converter */ typedef struct { __IO uint32_t ISR; /*!< ADC interrupt and status register, Address offset: 0x00 */ __IO uint32_t IER; /*!< ADC interrupt enable register, Address offset: 0x04 */ __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */ __IO uint32_t CFGR1; /*!< ADC configuration register 1, Address offset: 0x0C */ __IO uint32_t CFGR2; /*!< ADC configuration register 2, Address offset: 0x10 */ __IO uint32_t SMPR; /*!< ADC sampling time register, Address offset: 0x14 */ uint32_t RESERVED1[2]; /*!< Reserved, 0x18-0x1C */ __IO uint32_t TR; /*!< ADC analog watchdog 1 threshold register, Address offset: 0x20 */ uint32_t RESERVED2; /*!< Reserved, 0x24 */ __IO uint32_t CHSELR; /*!< ADC group regular sequencer register, Address offset: 0x28 */ uint32_t RESERVED3[5]; /*!< Reserved, 0x2C */ __IO uint32_t DR; /*!< ADC group regular data register, Address offset: 0x40 */ __IO uint32_t CCSR; /*!< ADC calibration configuration&status register Address offset: 0x44 */ } ADC_TypeDef; typedef struct { __IO uint32_t CCR; /*!< ADC common configuration register, Address offset: ADC1 base address + 0x308 */ } ADC_Common_TypeDef; /** * @brief CRC calculation unit */ typedef struct { __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */ __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */ __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */ } CRC_TypeDef; /** * @brief Comparator */ typedef struct { __IO uint32_t CSR; /*!< COMP control and status register, Address offset: 0x00 */ __IO uint32_t FR; /*!< COMP filter register, Address offset: 0x04 */ } COMP_TypeDef; typedef struct { __IO uint32_t CSR_ODD; /*!< COMP control and status register located in register of comparator instance odd, used for bits common to several COMP instances, Address offset: 0x00 */ __IO uint32_t FR_ODD; uint32_t RESERVED[2]; /*Reserved*/ __IO uint32_t CSR_EVEN; /*!< COMP control and status register located in register of comparator instance even, used for bits common to several COMP instances, Address offset: 0x04 */ __IO uint32_t FR_EVEN; } COMP_Common_TypeDef; /** * @brief Debug MCU */ typedef struct { __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */ __IO uint32_t CR; /*!< Debug configuration register, Address offset: 0x04 */ __IO uint32_t APBFZ1; /*!< Debug APB freeze register 1, Address offset: 0x08 */ __IO uint32_t APBFZ2; /*!< Debug APB freeze register 2, Address offset: 0x0C */ } DBGMCU_TypeDef; /** * @brief DMA Controller */ typedef struct { __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */ __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */ } DMA_TypeDef; typedef struct { __IO uint32_t CCR; /*!< DMA channel x configuration register */ __IO uint32_t CNDTR; /*!< DMA channel x number of data register */ __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */ __IO uint32_t CMAR; /*!< DMA channel x memory address register */ } DMA_Channel_TypeDef; /** * @brief Asynch Interrupt/Event Controller (EXTI) */ typedef struct { __IO uint32_t RTSR; /*!< EXTI Rising Trigger Selection Register 1, Address offset: 0x00 */ __IO uint32_t FTSR; /*!< EXTI Falling Trigger Selection Register 1, Address offset: 0x04 */ __IO uint32_t SWIER; /*!< EXTI Software Interrupt event Register 1, Address offset: 0x08 */ __IO uint32_t PR; /*!< EXTI Pending Register 1 Address offset: 0x0C */ uint32_t RESERVED1[4]; /*!< Reserved 1, 0x10 -- 0x1C */ uint32_t RESERVED2[5]; /*!< Reserved 2, 0x20 -- 0x30 */ uint32_t RESERVED3[11]; /*!< Reserved 3, 0x34 -- 0x5C */ __IO uint32_t EXTICR[3]; /*!< EXTI External Interrupt Configuration Register, 0x60 -- 0x68 */ uint32_t RESERVED4[5]; /*!< Reserved 5, 0x6C -- 0x7C */ __IO uint32_t IMR; /*!< EXTI Interrupt Mask Register , Address offset: 0x80 */ __IO uint32_t EMR; /*!< EXTI Event Mask Register , Address offset: 0x84 */ } EXTI_TypeDef; /** * @brief FLASH Registers */ typedef struct { __IO uint32_t ACR; /*!< FLASH Access Control register, Address offset: 0x00 */ uint32_t RESERVED1; /*!< Reserved1, Address offset: 0x04 */ __IO uint32_t KEYR; /*!< FLASH Key register, Address offset: 0x08 */ __IO uint32_t OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */ __IO uint32_t SR; /*!< FLASH Status register, Address offset: 0x10 */ __IO uint32_t CR; /*!< FLASH Control register, Address offset: 0x14 */ uint32_t RESERVED2[2]; /*!< Reserved2, Address offset: 0x18-0x1C */ __IO uint32_t OPTR; /*!< FLASH Option register, Address offset: 0x20 */ __IO uint32_t SDKR; /*!< FLASH SDK address register, Address offset: 0x24 */ uint32_t RESERVED3; /*!< Reserved2, Address offset: 0x28 */ __IO uint32_t WRPR; /*!< FLASH WRP address register, Address offset: 0x2C */ uint32_t RESERVED4[(0x90 - 0x2C) / 4 - 1]; __IO uint32_t STCR; /*!< FLASH sleep time config register, Address offset: 0x90 */ uint32_t RESERVED5[(0x100 - 0x90) / 4 - 1]; __IO uint32_t TS0; /*!< FLASH TS0 register, Address offset: 0x100 */ __IO uint32_t TS1; /*!< FLASH TS1 register, Address offset: 0x104 */ __IO uint32_t TS2P; /*!< FLASH TS2P register, Address offset: 0x108 */ __IO uint32_t TPS3; /*!< FLASH TPS3 register, Address offset: 0x10C */ __IO uint32_t TS3; /*!< FLASH TS3 register, Address offset: 0x110 */ __IO uint32_t PERTPE; /*!< FLASH PERTPE register, Address offset: 0x114 */ __IO uint32_t SMERTPE; /*!< FLASH SMERTPE register, Address offset: 0x118 */ __IO uint32_t PRGTPE; /*!< FLASH PRGTPE register, Address offset: 0x11C */ __IO uint32_t PRETPE; /*!< FLASH PRETPE register, Address offset: 0x120 */ } FLASH_TypeDef; /** * @brief Option Bytes */ typedef struct { __IO uint8_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */ __IO uint8_t USER; /*!< FLASH option byte user options, Address offset: 0x01 */ __IO uint8_t nRDP; /*!< Complemented FLASH option byte Read protection,Address offset: 0x02 */ __IO uint8_t nUSER; /*!< Complemented FLASH option byte user options, Address offset: 0x03 */ __IO uint8_t SDK_STRT; /*!< SDK area start address(stored in SDK[4:0]), Address offset: 0x04 */ __IO uint8_t SDK_END; /*!< SDK area end address(stored in SDK[12:8]), Address offset: 0x05 */ __IO uint8_t nSDK_STRT; /*!< Complemented SDK area start address, Address offset: 0x06 */ __IO uint8_t nSDK_END; /*!< Complemented SDK area end address, Address offset: 0x07 */ uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x08 */ __IO uint16_t WRP; /*!< FLASH option byte write protection, Address offset: 0x0C */ __IO uint16_t nWRP; /*!< Complemented FLASH option byte write protection,Address offset: 0x0E */ } OB_TypeDef; /** * @brief General Purpose I/O */ typedef struct { __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */ __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */ __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */ __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */ __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */ __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */ __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x18 */ __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */ __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */ __IO uint32_t BRR; /*!< GPIO Bit Reset register, Address offset: 0x28 */ } GPIO_TypeDef; /** * @brief Inter-integrated Circuit Interface */ typedef struct { __IO uint32_t CR1; __IO uint32_t CR2; __IO uint32_t OAR1; __IO uint32_t OAR2; __IO uint32_t DR; __IO uint32_t SR1; __IO uint32_t SR2; __IO uint32_t CCR; __IO uint32_t TRISE; } I2C_TypeDef; /** * @brief Independent WATCHDOG */ typedef struct { __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */ __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */ __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */ __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */ //__IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */ } IWDG_TypeDef; /** * @brief LPTIMER */ typedef struct { __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */ __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */ __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */ __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */ __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */ __IO uint32_t RESERVED1; /*!< RESERVED1, Address offset: 0x14 */ __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */ __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */ } LPTIM_TypeDef; /** * @brief Power Control */ typedef struct { __IO uint32_t CR1; /*!< PWR Power Control Register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< PWR Power Control Register 2, Address offset: 0x04 */ uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x08-0x10 */ __IO uint32_t SR; /*!< PWR Power Status Register, Address offset: 0x14 */ } PWR_TypeDef; /** * @brief Reset and Clock Control */ typedef struct { __IO uint32_t CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */ __IO uint32_t ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */ __IO uint32_t CFGR; /*!< RCC Regulated Domain Clocks Configuration Register, Address offset: 0x08 */ __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x0C */ __IO uint32_t ECSCR; /*!< RCC External clock source control register, Address offset: 0x10 */ __IO uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */ __IO uint32_t CIER; /*!< RCC Clock Interrupt Enable Register, Address offset: 0x18 */ __IO uint32_t CIFR; /*!< RCC Clock Interrupt Flag Register, Address offset: 0x1C */ __IO uint32_t CICR; /*!< RCC Clock Interrupt Clear Register, Address offset: 0x20 */ __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x24 */ __IO uint32_t AHBRSTR; /*!< RCC AHB peripherals reset register, Address offset: 0x28 */ __IO uint32_t APBRSTR1; /*!< RCC APB peripherals reset register 1, Address offset: 0x2C */ __IO uint32_t APBRSTR2; /*!< RCC APB peripherals reset register 2, Address offset: 0x30 */ __IO uint32_t IOPENR; /*!< RCC IO port enable register, Address offset: 0x34 */ __IO uint32_t AHBENR; /*!< RCC AHB peripherals clock enable register, Address offset: 0x38 */ __IO uint32_t APBENR1; /*!< RCC APB peripherals clock enable register1, Address offset: 0x3C */ __IO uint32_t APBENR2; /*!< RCC APB peripherals clock enable register2, Address offset: 0x40 */ uint32_t RESERVED2[4];/*!< Reserved, Address offset: 0x44-0x50 */ __IO uint32_t CCIPR; /*!< RCC Peripherals Independent Clocks Configuration Register, Address offset: 0x54 */ __IO uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */ __IO uint32_t BDCR; /*!< RCC Backup Domain Control Register, Address offset: 0x5C */ __IO uint32_t CSR; /*!< RCC Unregulated Domain Clock Control and Status Register, Address offset: 0x60 */ } RCC_TypeDef; /** * @brief Real-Time Clock */ typedef struct { __IO uint32_t CRH; __IO uint32_t CRL; __IO uint32_t PRLH; __IO uint32_t PRLL; __IO uint32_t DIVH; __IO uint32_t DIVL; __IO uint32_t CNTH; __IO uint32_t CNTL; __IO uint32_t ALRH; __IO uint32_t ALRL; uint32_t RESERVED1; __IO uint32_t BKP_RTCCR; } RTC_TypeDef; /** * @brief Serial Peripheral Interface */ typedef struct { __IO uint32_t CR1; /*!< SPI Control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */ __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */ __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */ } SPI_TypeDef; /** * @brief System configuration controller */ typedef struct { __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */ uint32_t RESERVED1[5]; /*!< Reserved, 0x04 --0x14 */ __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */ __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x1C */ } SYSCFG_TypeDef; /** * @brief TIM */ typedef struct { __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */ __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */ __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */ __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */ __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */ __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */ __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */ __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */ __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */ __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */ __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */ __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */ __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */ __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */ __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */ __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */ __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */ __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */ __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */ __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */ __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */ } TIM_TypeDef; /** * @brief Universal Synchronous Asynchronous Receiver Transmitter */ typedef struct { __IO uint32_t SR; /*!< USART Status register , Address offset: 0x00 */ __IO uint32_t DR; /*!< USART Data register, Address offset: 0x04 */ __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */ __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x0C */ __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x10 */ __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x14 */ __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */ } USART_TypeDef; /** * @brief Window WATCHDOG */ typedef struct { __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */ __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */ __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */ } WWDG_TypeDef; /** @addtogroup Peripheral_memory_map * @{ */ #define FLASH_BASE (0x08000000UL) /*!< FLASH base address */ #define FLASH_END (0x0800FFFFUL) /*!< FLASH end address */ #define FLASH_SIZE (FLASH_END - FLASH_BASE + 1) #define FLASH_PAGE_SIZE 0x00000080U /*!< FLASH Page Size, 128 Bytes */ #define FLASH_PAGE_NB (FLASH_SIZE / FLASH_PAGE_SIZE) #define FLASH_SECTOR_SIZE 0x00001000U /*!< FLASH Sector Size, 4096 Bytes */ #define FLASH_SECTOR_NB (FLASH_SIZE / FLASH_SECTOR_SIZE) #define SRAM_BASE (0x20000000UL) /*!< SRAM base address */ #define SRAM_END (0x20001FFFUL) /*!< SRAM end address */ #define PERIPH_BASE (0x40000000UL) /*!< Peripheral base address */ #define IOPORT_BASE (0x50000000UL) /*!< IOPORT base address */ /*!< Peripheral memory map */ #define APBPERIPH_BASE (PERIPH_BASE) #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL) /*!< APB peripherals */ #define TIM3_BASE (APBPERIPH_BASE + 0x00000400UL) #define TIM14_BASE (APBPERIPH_BASE + 0x00002000UL) #define RTC_BASE (APBPERIPH_BASE + 0x00002800UL) #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00UL) #define IWDG_BASE (APBPERIPH_BASE + 0x00003000UL) #define USART2_BASE (APBPERIPH_BASE + 0x00004400UL) #define I2C_BASE (APBPERIPH_BASE + 0x00005400UL) #define PWR_BASE (APBPERIPH_BASE + 0x00007000UL) #define LPTIM_BASE (APBPERIPH_BASE + 0x00007C00UL) #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000UL) #define COMP1_BASE (APBPERIPH_BASE + 0x00010200UL) #define COMP2_BASE (APBPERIPH_BASE + 0x00010210UL) #define ADC1_BASE (APBPERIPH_BASE + 0x00012400UL) #define ADC_BASE (APBPERIPH_BASE + 0x00012708UL) #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00UL) #define SPI1_BASE (APBPERIPH_BASE + 0x00013000UL) #define USART1_BASE (APBPERIPH_BASE + 0x00013800UL) #define TIM16_BASE (APBPERIPH_BASE + 0x00014400UL) #define TIM17_BASE (APBPERIPH_BASE + 0x00014800UL) #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800UL) /*!< AHB peripherals */ #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL) #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008UL) #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001CUL) #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030UL) #define RCC_BASE (AHBPERIPH_BASE + 0x00001000UL) #define EXTI_BASE (AHBPERIPH_BASE + 0x00001800UL) #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL) /*!< FLASH registers base address */ #define OB_BASE 0x1FFF0E80UL /*!< FLASH Option Bytes base address */ #define FLASHSIZE_BASE 0x1FFF0FFCUL /*!< FLASH Size register base address */ #define UID_BASE 0x1FFF0E00UL /*!< Unique device ID register base address */ #define CRC_BASE (AHBPERIPH_BASE + 0x00003000UL) /*!< IOPORT */ #define GPIOA_BASE (IOPORT_BASE + 0x00000000UL) #define GPIOB_BASE (IOPORT_BASE + 0x00000400UL) #define GPIOF_BASE (IOPORT_BASE + 0x00001400UL) /** * @} */ /** @addtogroup Peripheral_declaration * @{ */ #define TIM3 ((TIM_TypeDef *) TIM3_BASE) #define TIM14 ((TIM_TypeDef *) TIM14_BASE) #define RTC ((RTC_TypeDef *) RTC_BASE) #define WWDG ((WWDG_TypeDef *) WWDG_BASE) #define IWDG ((IWDG_TypeDef *) IWDG_BASE) #define USART2 ((USART_TypeDef *) USART2_BASE) #define I2C1 ((I2C_TypeDef *) I2C_BASE) #define I2C ((I2C_TypeDef *) I2C_BASE) /* Kept for legacy purpose */ #define PWR ((PWR_TypeDef *) PWR_BASE) #define LPTIM1 ((LPTIM_TypeDef *) LPTIM_BASE) #define LPTIM ((LPTIM_TypeDef *) LPTIM_BASE) /* Kept for legacy purpose */ #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE) #define COMP1 ((COMP_TypeDef *) COMP1_BASE) #define COMP2 ((COMP_TypeDef *) COMP2_BASE) #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE) #define ADC1 ((ADC_TypeDef *) ADC1_BASE) #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE) #define ADC ((ADC_Common_TypeDef *) ADC_BASE) /* Kept for legacy purpose */ #define TIM1 ((TIM_TypeDef *) TIM1_BASE) #define SPI1 ((SPI_TypeDef *) SPI1_BASE) #define USART1 ((USART_TypeDef *) USART1_BASE) #define TIM16 ((TIM_TypeDef *) TIM16_BASE) #define TIM17 ((TIM_TypeDef *) TIM17_BASE) #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE) #define DMA1 ((DMA_TypeDef *) DMA1_BASE) #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE) #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE) #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE) #define RCC ((RCC_TypeDef *) RCC_BASE) #define EXTI ((EXTI_TypeDef *) EXTI_BASE) #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE) #define OB ((OB_TypeDef *) OB_BASE) #define CRC ((CRC_TypeDef *) CRC_BASE) #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE) #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE) #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE) /** * @} */ /** @addtogroup Exported_constants * @{ */ /** @addtogroup Peripheral_Registers_Bits_Definition * @{ */ /******************************************************************************/ /* Peripheral Registers Bits Definition */ /******************************************************************************/ /******************************************************************************/ /* */ /* Analog to Digital Converter (ADC) */ /* */ /******************************************************************************/ /******************** Bits definition for ADC_ISR register ******************/ #define ADC_ISR_EOSMP_Pos (1U) #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */ #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC group regular end of sampling flag */ #define ADC_ISR_EOC_Pos (2U) #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */ #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC group regular end of unitary conversion flag */ #define ADC_ISR_EOSEQ_Pos (3U) #define ADC_ISR_EOSEQ_Msk (0x1UL << ADC_ISR_EOSEQ_Pos) /*!< 0x00000008 */ #define ADC_ISR_EOSEQ ADC_ISR_EOSEQ_Msk /*!< ADC group regular end of sequence conversions flag */ #define ADC_ISR_OVR_Pos (4U) #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */ #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC group regular overrun flag */ #define ADC_ISR_AWD_Pos (7U) #define ADC_ISR_AWD_Msk (0x1UL << ADC_ISR_AWD_Pos) /*!< 0x00000080 */ #define ADC_ISR_AWD ADC_ISR_AWD_Msk /*!< ADC analog watchdog 1 flag */ /******************** Bits definition for ADC_IER register ******************/ #define ADC_IER_EOSMPIE_Pos (1U) #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */ #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC group regular end of sampling interrupt */ #define ADC_IER_EOCIE_Pos (2U) #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */ #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC group regular end of unitary conversion interrupt */ #define ADC_IER_EOSEQIE_Pos (3U) #define ADC_IER_EOSEQIE_Msk (0x1UL << ADC_IER_EOSEQIE_Pos) /*!< 0x00000008 */ #define ADC_IER_EOSEQIE ADC_IER_EOSEQIE_Msk /*!< ADC group regular end of sequence conversions interrupt */ #define ADC_IER_OVRIE_Pos (4U) #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */ #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC group regular overrun interrupt */ #define ADC_IER_AWDIE_Pos (7U) #define ADC_IER_AWDIE_Msk (0x1UL << ADC_IER_AWDIE_Pos) /*!< 0x00000080 */ #define ADC_IER_AWDIE ADC_IER_AWDIE_Msk /*!< ADC analog watchdog 1 interrupt */ /******************** Bits definition for ADC_CR register *******************/ #define ADC_CR_ADEN_Pos (0U) #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */ #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC enable */ #define ADC_CR_ADSTART_Pos (2U) #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */ #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC group regular conversion start */ #define ADC_CR_ADSTP_Pos (4U) #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */ #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC group regular conversion stop */ #define ADC_CR_ADCAL_Pos (31U) #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */ #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC calibration */ /******************* Bits definition for ADC_CFGR1 register *****************/ #define ADC_CFGR1_DMAEN_Pos (0U) #define ADC_CFGR1_DMAEN_Msk (0x1UL << ADC_CFGR1_DMAEN_Pos) /*!< 0x00000001 */ #define ADC_CFGR1_DMAEN ADC_CFGR1_DMAEN_Msk /*!< ADC DMA transfer enable */ #define ADC_CFGR1_DMACFG_Pos (1U) #define ADC_CFGR1_DMACFG_Msk (0x1UL << ADC_CFGR1_DMACFG_Pos) /*!< 0x00000002 */ #define ADC_CFGR1_DMACFG ADC_CFGR1_DMACFG_Msk /*!< ADC DMA transfer configuration */ #define ADC_CFGR1_SCANDIR_Pos (2U) #define ADC_CFGR1_SCANDIR_Msk (0x1UL << ADC_CFGR1_SCANDIR_Pos) /*!< 0x00000004 */ #define ADC_CFGR1_SCANDIR ADC_CFGR1_SCANDIR_Msk /*!< ADC group regular sequencer scan direction */ #define ADC_CFGR1_RESSEL_Pos (3U) #define ADC_CFGR1_RESSEL_Msk (0x3UL << ADC_CFGR1_RESSEL_Pos) /*!< 0x00000018 */ #define ADC_CFGR1_RESSEL ADC_CFGR1_RESSEL_Msk /*!< ADC data resolution */ #define ADC_CFGR1_RESSEL_0 (0x1UL << ADC_CFGR1_RESSEL_Pos) /*!< 0x00000008 */ #define ADC_CFGR1_RESSEL_1 (0x2UL << ADC_CFGR1_RESSEL_Pos) /*!< 0x00000010 */ #define ADC_CFGR1_ALIGN_Pos (5U) #define ADC_CFGR1_ALIGN_Msk (0x1UL << ADC_CFGR1_ALIGN_Pos) /*!< 0x00000020 */ #define ADC_CFGR1_ALIGN ADC_CFGR1_ALIGN_Msk /*!< ADC data alignement */ #define ADC_CFGR1_EXTSEL_Pos (6U) #define ADC_CFGR1_EXTSEL_Msk (0x7UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x000001C0 */ #define ADC_CFGR1_EXTSEL ADC_CFGR1_EXTSEL_Msk /*!< ADC group regular external trigger source */ #define ADC_CFGR1_EXTSEL_0 (0x1UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000040 */ #define ADC_CFGR1_EXTSEL_1 (0x2UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000080 */ #define ADC_CFGR1_EXTSEL_2 (0x4UL << ADC_CFGR1_EXTSEL_Pos) /*!< 0x00000100 */ #define ADC_CFGR1_EXTEN_Pos (10U) #define ADC_CFGR1_EXTEN_Msk (0x3UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000C00 */ #define ADC_CFGR1_EXTEN ADC_CFGR1_EXTEN_Msk /*!< ADC group regular external trigger polarity */ #define ADC_CFGR1_EXTEN_0 (0x1UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000400 */ #define ADC_CFGR1_EXTEN_1 (0x2UL << ADC_CFGR1_EXTEN_Pos) /*!< 0x00000800 */ #define ADC_CFGR1_OVRMOD_Pos (12U) #define ADC_CFGR1_OVRMOD_Msk (0x1UL << ADC_CFGR1_OVRMOD_Pos) /*!< 0x00001000 */ #define ADC_CFGR1_OVRMOD ADC_CFGR1_OVRMOD_Msk /*!< ADC group regular overrun configuration */ #define ADC_CFGR1_CONT_Pos (13U) #define ADC_CFGR1_CONT_Msk (0x1UL << ADC_CFGR1_CONT_Pos) /*!< 0x00002000 */ #define ADC_CFGR1_CONT ADC_CFGR1_CONT_Msk /*!< ADC group regular continuous conversion mode */ #define ADC_CFGR1_WAIT_Pos (14U) #define ADC_CFGR1_WAIT_Msk (0x1UL << ADC_CFGR1_WAIT_Pos) /*!< 0x00004000 */ #define ADC_CFGR1_WAIT ADC_CFGR1_WAIT_Msk /*!< ADC low power auto wait */ #define ADC_CFGR1_DISCEN_Pos (16U) #define ADC_CFGR1_DISCEN_Msk (0x1UL << ADC_CFGR1_DISCEN_Pos) /*!< 0x00010000 */ #define ADC_CFGR1_DISCEN ADC_CFGR1_DISCEN_Msk /*!< ADC group regular sequencer discontinuous mode */ #define ADC_CFGR1_AWDSGL_Pos (22U) #define ADC_CFGR1_AWDSGL_Msk (0x1UL << ADC_CFGR1_AWDSGL_Pos) /*!< 0x00400000 */ #define ADC_CFGR1_AWDSGL ADC_CFGR1_AWDSGL_Msk /*!< ADC analog watchdog 1 monitoring a single channel or all channels */ #define ADC_CFGR1_AWDEN_Pos (23U) #define ADC_CFGR1_AWDEN_Msk (0x1UL << ADC_CFGR1_AWDEN_Pos) /*!< 0x00800000 */ #define ADC_CFGR1_AWDEN ADC_CFGR1_AWDEN_Msk /*!< ADC analog watchdog 1 enable on scope ADC group regular */ #define ADC_CFGR1_AWDCH_Pos (26U) #define ADC_CFGR1_AWDCH_Msk (0xFUL << ADC_CFGR1_AWDCH_Pos) /*!< 0x2C000000 */ #define ADC_CFGR1_AWDCH ADC_CFGR1_AWDCH_Msk /*!< ADC analog watchdog 1 monitored channel selection */ #define ADC_CFGR1_AWDCH_0 (0x01UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x04000000 */ #define ADC_CFGR1_AWDCH_1 (0x02UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x08000000 */ #define ADC_CFGR1_AWDCH_2 (0x04UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x10000000 */ #define ADC_CFGR1_AWDCH_3 (0x08UL << ADC_CFGR1_AWDCH_Pos) /*!< 0x20000000 */ /******************* Bits definition for ADC_CFGR2 register *****************/ #define ADC_CFGR2_CKMODE_Pos (28U) #define ADC_CFGR2_CKMODE_Msk (0xFUL << ADC_CFGR2_CKMODE_Pos) /*!< 0xC0000000 */ #define ADC_CFGR2_CKMODE ADC_CFGR2_CKMODE_Msk /*!< ADC clock source and prescaler (prescaler only for clock source synchronous) */ #define ADC_CFGR2_CKMODE_0 (0x1UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x10000000 */ #define ADC_CFGR2_CKMODE_1 (0x2UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x20000000 */ #define ADC_CFGR2_CKMODE_2 (0x4UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x40000000 */ #define ADC_CFGR2_CKMODE_3 (0x8UL << ADC_CFGR2_CKMODE_Pos) /*!< 0x80000000 */ /****************** Bit definition for ADC_SMPR register ********************/ #define ADC_SMPR_SMP_Pos (0U) #define ADC_SMPR_SMP_Msk (0x7UL << ADC_SMPR_SMP_Pos) /*!< 0x00000007 */ #define ADC_SMPR_SMP ADC_SMPR_SMP_Msk /*!< ADC group of channels sampling time 2 */ #define ADC_SMPR_SMP_0 (0x1UL << ADC_SMPR_SMP_Pos) /*!< 0x00000001 */ #define ADC_SMPR_SMP_1 (0x2UL << ADC_SMPR_SMP_Pos) /*!< 0x00000002 */ #define ADC_SMPR_SMP_2 (0x4UL << ADC_SMPR_SMP_Pos) /*!< 0x00000004 */ /******************* Bit definition for ADC_TR register ********************/ #define ADC_TR_LT_Pos (0U) #define ADC_TR_LT_Msk (0xFFFUL << ADC_TR_LT_Pos) /*!< 0x00000FFF */ #define ADC_TR_LT ADC_TR_LT_Msk /*!< ADC analog watchdog 1 threshold low */ #define ADC_TR_LT_0 (0x001UL << ADC_TR_LT_Pos) /*!< 0x00000001 */ #define ADC_TR_LT_1 (0x002UL << ADC_TR_LT_Pos) /*!< 0x00000002 */ #define ADC_TR_LT_2 (0x004UL << ADC_TR_LT_Pos) /*!< 0x00000004 */ #define ADC_TR_LT_3 (0x008UL << ADC_TR_LT_Pos) /*!< 0x00000008 */ #define ADC_TR_LT_4 (0x010UL << ADC_TR_LT_Pos) /*!< 0x00000010 */ #define ADC_TR_LT_5 (0x020UL << ADC_TR_LT_Pos) /*!< 0x00000020 */ #define ADC_TR_LT_6 (0x040UL << ADC_TR_LT_Pos) /*!< 0x00000040 */ #define ADC_TR_LT_7 (0x080UL << ADC_TR_LT_Pos) /*!< 0x00000080 */ #define ADC_TR_LT_8 (0x100UL << ADC_TR_LT_Pos) /*!< 0x00000100 */ #define ADC_TR_LT_9 (0x200UL << ADC_TR_LT_Pos) /*!< 0x00000200 */ #define ADC_TR_LT_10 (0x400UL << ADC_TR_LT_Pos) /*!< 0x00000400 */ #define ADC_TR_LT_11 (0x800UL << ADC_TR_LT_Pos) /*!< 0x00000800 */ #define ADC_TR_HT_Pos (16U) #define ADC_TR_HT_Msk (0xFFFUL << ADC_TR_HT_Pos) /*!< 0x0FFF0000 */ #define ADC_TR_HT ADC_TR_HT_Msk /*!< ADC Analog watchdog 1 threshold high */ #define ADC_TR_HT_0 (0x001UL << ADC_TR_HT_Pos) /*!< 0x00010000 */ #define ADC_TR_HT_1 (0x002UL << ADC_TR_HT_Pos) /*!< 0x00020000 */ #define ADC_TR_HT_2 (0x004UL << ADC_TR_HT_Pos) /*!< 0x00040000 */ #define ADC_TR_HT_3 (0x008UL << ADC_TR_HT_Pos) /*!< 0x00080000 */ #define ADC_TR_HT_4 (0x010UL << ADC_TR_HT_Pos) /*!< 0x00100000 */ #define ADC_TR_HT_5 (0x020UL << ADC_TR_HT_Pos) /*!< 0x00200000 */ #define ADC_TR_HT_6 (0x040UL << ADC_TR_HT_Pos) /*!< 0x00400000 */ #define ADC_TR_HT_7 (0x080UL << ADC_TR_HT_Pos) /*!< 0x00800000 */ #define ADC_TR_HT_8 (0x100UL << ADC_TR_HT_Pos) /*!< 0x01000000 */ #define ADC_TR_HT_9 (0x200UL << ADC_TR_HT_Pos) /*!< 0x02000000 */ #define ADC_TR_HT_10 (0x400UL << ADC_TR_HT_Pos) /*!< 0x04000000 */ #define ADC_TR_HT_11 (0x800UL << ADC_TR_HT_Pos) /*!< 0x08000000 */ /****************** Bit definition for ADC_CHSELR register ******************/ #define ADC_CHSELR_CHSEL_Pos (0U) #define ADC_CHSELR_CHSEL_Msk (0x1BFFUL << ADC_CHSELR_CHSEL_Pos) /*!< 0x00001BFF */ #define ADC_CHSELR_CHSEL ADC_CHSELR_CHSEL_Msk /*!< ADC group regular sequencer channels, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL12_Pos (12U) #define ADC_CHSELR_CHSEL12_Msk (0x1UL << ADC_CHSELR_CHSEL12_Pos) /*!< 0x00001000 */ #define ADC_CHSELR_CHSEL12 ADC_CHSELR_CHSEL12_Msk /*!< ADC group regular sequencer channel 12, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL11_Pos (11U) #define ADC_CHSELR_CHSEL11_Msk (0x1UL << ADC_CHSELR_CHSEL11_Pos) /*!< 0x00000800 */ #define ADC_CHSELR_CHSEL11 ADC_CHSELR_CHSEL11_Msk /*!< ADC group regular sequencer channel 11, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL9_Pos (9U) #define ADC_CHSELR_CHSEL9_Msk (0x1UL << ADC_CHSELR_CHSEL9_Pos) /*!< 0x00000200 */ #define ADC_CHSELR_CHSEL9 ADC_CHSELR_CHSEL9_Msk /*!< ADC group regular sequencer channel 9, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL8_Pos (8U) #define ADC_CHSELR_CHSEL8_Msk (0x1UL << ADC_CHSELR_CHSEL8_Pos) /*!< 0x00000100 */ #define ADC_CHSELR_CHSEL8 ADC_CHSELR_CHSEL8_Msk /*!< ADC group regular sequencer channel 8, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL7_Pos (7U) #define ADC_CHSELR_CHSEL7_Msk (0x1UL << ADC_CHSELR_CHSEL7_Pos) /*!< 0x00000080 */ #define ADC_CHSELR_CHSEL7 ADC_CHSELR_CHSEL7_Msk /*!< ADC group regular sequencer channel 7, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL6_Pos (6U) #define ADC_CHSELR_CHSEL6_Msk (0x1UL << ADC_CHSELR_CHSEL6_Pos) /*!< 0x00000040 */ #define ADC_CHSELR_CHSEL6 ADC_CHSELR_CHSEL6_Msk /*!< ADC group regular sequencer channel 6, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL5_Pos (5U) #define ADC_CHSELR_CHSEL5_Msk (0x1UL << ADC_CHSELR_CHSEL5_Pos) /*!< 0x00000020 */ #define ADC_CHSELR_CHSEL5 ADC_CHSELR_CHSEL5_Msk /*!< ADC group regular sequencer channel 5, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL4_Pos (4U) #define ADC_CHSELR_CHSEL4_Msk (0x1UL << ADC_CHSELR_CHSEL4_Pos) /*!< 0x00000010 */ #define ADC_CHSELR_CHSEL4 ADC_CHSELR_CHSEL4_Msk /*!< ADC group regular sequencer channel 4, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL3_Pos (3U) #define ADC_CHSELR_CHSEL3_Msk (0x1UL << ADC_CHSELR_CHSEL3_Pos) /*!< 0x00000008 */ #define ADC_CHSELR_CHSEL3 ADC_CHSELR_CHSEL3_Msk /*!< ADC group regular sequencer channel 3, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL2_Pos (2U) #define ADC_CHSELR_CHSEL2_Msk (0x1UL << ADC_CHSELR_CHSEL2_Pos) /*!< 0x00000004 */ #define ADC_CHSELR_CHSEL2 ADC_CHSELR_CHSEL2_Msk /*!< ADC group regular sequencer channel 2, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL1_Pos (1U) #define ADC_CHSELR_CHSEL1_Msk (0x1UL << ADC_CHSELR_CHSEL1_Pos) /*!< 0x00000002 */ #define ADC_CHSELR_CHSEL1 ADC_CHSELR_CHSEL1_Msk /*!< ADC group regular sequencer channel 1, available when ADC_CFGR1_CHSELRMOD is reset */ #define ADC_CHSELR_CHSEL0_Pos (0U) #define ADC_CHSELR_CHSEL0_Msk (0x1UL << ADC_CHSELR_CHSEL0_Pos) /*!< 0x00000001 */ #define ADC_CHSELR_CHSEL0 ADC_CHSELR_CHSEL0_Msk /*!< ADC group regular sequencer channel 0, available when ADC_CFGR1_CHSELRMOD is reset */ /******************** Bit definition for ADC_DR register ********************/ #define ADC_DR_DATA_Pos (0U) #define ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos) /*!< 0x0000FFFF */ #define ADC_DR_DATA ADC_DR_DATA_Msk /*!< ADC group regular conversion data */ #define ADC_DR_DATA_0 (0x0001UL << ADC_DR_DATA_Pos) /*!< 0x00000001 */ #define ADC_DR_DATA_1 (0x0002UL << ADC_DR_DATA_Pos) /*!< 0x00000002 */ #define ADC_DR_DATA_2 (0x0004UL << ADC_DR_DATA_Pos) /*!< 0x00000004 */ #define ADC_DR_DATA_3 (0x0008UL << ADC_DR_DATA_Pos) /*!< 0x00000008 */ #define ADC_DR_DATA_4 (0x0010UL << ADC_DR_DATA_Pos) /*!< 0x00000010 */ #define ADC_DR_DATA_5 (0x0020UL << ADC_DR_DATA_Pos) /*!< 0x00000020 */ #define ADC_DR_DATA_6 (0x0040UL << ADC_DR_DATA_Pos) /*!< 0x00000040 */ #define ADC_DR_DATA_7 (0x0080UL << ADC_DR_DATA_Pos) /*!< 0x00000080 */ #define ADC_DR_DATA_8 (0x0100UL << ADC_DR_DATA_Pos) /*!< 0x00000100 */ #define ADC_DR_DATA_9 (0x0200UL << ADC_DR_DATA_Pos) /*!< 0x00000200 */ #define ADC_DR_DATA_10 (0x0400UL << ADC_DR_DATA_Pos) /*!< 0x00000400 */ #define ADC_DR_DATA_11 (0x0800UL << ADC_DR_DATA_Pos) /*!< 0x00000800 */ #define ADC_DR_DATA_12 (0x1000UL << ADC_DR_DATA_Pos) /*!< 0x00001000 */ #define ADC_DR_DATA_13 (0x2000UL << ADC_DR_DATA_Pos) /*!< 0x00002000 */ #define ADC_DR_DATA_14 (0x4000UL << ADC_DR_DATA_Pos) /*!< 0x00004000 */ #define ADC_DR_DATA_15 (0x8000UL << ADC_DR_DATA_Pos) /*!< 0x00008000 */ /******************** Bit definition for ADC_CCSR register ********************/ #define ADC_CCSR_CALSEL_Pos (11U) #define ADC_CCSR_CALSEL_Msk (0x1UL << ADC_CCSR_CALSEL_Pos) /*!< 0x00000800 */ #define ADC_CCSR_CALSEL ADC_CCSR_CALSEL_Msk /*!< ADC calibration context selection */ #define ADC_CCSR_CALSMP_Pos (12U) #define ADC_CCSR_CALSMP_Msk (0x3UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00003000 */ #define ADC_CCSR_CALSMP ADC_CCSR_CALSMP_Msk /*!< ADC calibration sample time selection */ #define ADC_CCSR_CALSMP_0 (0x1UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00001000 */ #define ADC_CCSR_CALSMP_1 (0x2UL << ADC_CCSR_CALSMP_Pos) /*!< 0x00002000 */ #define ADC_CCSR_CALFAIL_Pos (30U) #define ADC_CCSR_CALFAIL_Msk (0x1UL << ADC_CCSR_CALFAIL_Pos) /*!< 0x40000000 */ #define ADC_CCSR_CALFAIL ADC_CCSR_CALFAIL_Msk /*!< ADC calibration fail flag */ #define ADC_CCSR_CALON_Pos (31U) #define ADC_CCSR_CALON_Msk (0x1UL << ADC_CCSR_CALON_Pos) /*!< 0x80000000 */ #define ADC_CCSR_CALON ADC_CCSR_CALON_Msk /*!< ADC calibration flag */ /************************* ADC Common registers *****************************/ /******************* Bit definition for ADC_CCR register ********************/ #define ADC_CCR_VREFEN_Pos (22U) #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */ #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< ADC internal path to VrefInt enable */ #define ADC_CCR_TSEN_Pos (23U) #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */ #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< ADC internal path to temperature sensor enable */ /******************************************************************************/ /* */ /* CRC calculation unit (CRC) */ /* */ /******************************************************************************/ /******************* Bit definition for CRC_DR register *********************/ #define CRC_DR_DR_Pos (0U) #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */ #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */ /******************* Bit definition for CRC_IDR register ********************/ #define CRC_IDR_IDR_Pos (0U) #define CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */ #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 8-bit data register bits */ /******************** Bit definition for CRC_CR register ********************/ #define CRC_CR_RESET_Pos (0U) #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */ #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */ /******************************************************************************/ /* */ /* Debug MCU (DBGMCU) */ /* */ /******************************************************************************/ /******************** Bit definition for DBG_IDCODE register *************/ #define DBGMCU_IDCODE_DEV_ID_Pos (0U) #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */ #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk #define DBGMCU_IDCODE_REV_ID_Pos (16U) #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */ #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk /******************** Bit definition for DBGMCU_CR register *****************/ #define DBGMCU_CR_DBG_STOP_Pos (1U) #define DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk /******************** Bit definition for DBGMCU_APB_FZ1 register ***********/ #define DBGMCU_APB_FZ1_DBG_TIM3_STOP_Pos (1U) #define DBGMCU_APB_FZ1_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_TIM3_STOP_Pos) /*!< 0x00000002 */ #define DBGMCU_APB_FZ1_DBG_TIM3_STOP DBGMCU_APB_FZ1_DBG_TIM3_STOP_Msk #define DBGMCU_APB_FZ1_DBG_RTC_STOP_Pos (10U) #define DBGMCU_APB_FZ1_DBG_RTC_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_RTC_STOP_Pos) /*!< 0x00000400 */ #define DBGMCU_APB_FZ1_DBG_RTC_STOP DBGMCU_APB_FZ1_DBG_RTC_STOP_Msk #define DBGMCU_APB_FZ1_DBG_WWDG_STOP_Pos (11U) #define DBGMCU_APB_FZ1_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_WWDG_STOP_Pos) /*!< 0x00000800 */ #define DBGMCU_APB_FZ1_DBG_WWDG_STOP DBGMCU_APB_FZ1_DBG_WWDG_STOP_Msk #define DBGMCU_APB_FZ1_DBG_IWDG_STOP_Pos (12U) #define DBGMCU_APB_FZ1_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_IWDG_STOP_Pos) /*!< 0x00001000 */ #define DBGMCU_APB_FZ1_DBG_IWDG_STOP DBGMCU_APB_FZ1_DBG_IWDG_STOP_Msk #define DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Pos (31U) #define DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Msk (0x1UL << DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Pos) /*!< 0x00001000 */ #define DBGMCU_APB_FZ1_DBG_LPTIM_STOP DBGMCU_APB_FZ1_DBG_LPTIM_STOP_Msk /******************** Bit definition for DBGMCU_APB_FZ2 register ************/ #define DBGMCU_APB_FZ2_DBG_TIM1_STOP_Pos (11U) #define DBGMCU_APB_FZ2_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM1_STOP_Pos) /*!< 0x00000800 */ #define DBGMCU_APB_FZ2_DBG_TIM1_STOP DBGMCU_APB_FZ2_DBG_TIM1_STOP_Msk #define DBGMCU_APB_FZ2_DBG_TIM14_STOP_Pos (15U) #define DBGMCU_APB_FZ2_DBG_TIM14_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM14_STOP_Pos) /*!< 0x00008000 */ #define DBGMCU_APB_FZ2_DBG_TIM14_STOP DBGMCU_APB_FZ2_DBG_TIM14_STOP_Msk #define DBGMCU_APB_FZ2_DBG_TIM16_STOP_Pos (17U) #define DBGMCU_APB_FZ2_DBG_TIM16_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM16_STOP_Pos) /*!< 0x00020000 */ #define DBGMCU_APB_FZ2_DBG_TIM16_STOP DBGMCU_APB_FZ2_DBG_TIM16_STOP_Msk #define DBGMCU_APB_FZ2_DBG_TIM17_STOP_Pos (18U) #define DBGMCU_APB_FZ2_DBG_TIM17_STOP_Msk (0x1UL << DBGMCU_APB_FZ2_DBG_TIM17_STOP_Pos) /*!< 0x00040000 */ #define DBGMCU_APB_FZ2_DBG_TIM17_STOP DBGMCU_APB_FZ2_DBG_TIM17_STOP_Msk /******************************************************************************/ /* */ /* DMA Controller (DMA) */ /* */ /******************************************************************************/ /******************* Bit definition for DMA_ISR register ********************/ #define DMA_ISR_GIF1_Pos (0U) #define DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos) /*!< 0x00000001 */ #define DMA_ISR_GIF1 DMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */ #define DMA_ISR_TCIF1_Pos (1U) #define DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos) /*!< 0x00000002 */ #define DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */ #define DMA_ISR_HTIF1_Pos (2U) #define DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos) /*!< 0x00000004 */ #define DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */ #define DMA_ISR_TEIF1_Pos (3U) #define DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos) /*!< 0x00000008 */ #define DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */ #define DMA_ISR_GIF2_Pos (4U) #define DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos) /*!< 0x00000010 */ #define DMA_ISR_GIF2 DMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */ #define DMA_ISR_TCIF2_Pos (5U) #define DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos) /*!< 0x00000020 */ #define DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */ #define DMA_ISR_HTIF2_Pos (6U) #define DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos) /*!< 0x00000040 */ #define DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */ #define DMA_ISR_TEIF2_Pos (7U) #define DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos) /*!< 0x00000080 */ #define DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */ #define DMA_ISR_GIF3_Pos (8U) #define DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos) /*!< 0x00000100 */ #define DMA_ISR_GIF3 DMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */ #define DMA_ISR_TCIF3_Pos (9U) #define DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos) /*!< 0x00000200 */ #define DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */ #define DMA_ISR_HTIF3_Pos (10U) #define DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos) /*!< 0x00000400 */ #define DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */ #define DMA_ISR_TEIF3_Pos (11U) #define DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos) /*!< 0x00000800 */ #define DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */ /******************* Bit definition for DMA_IFCR register *******************/ #define DMA_IFCR_CGIF1_Pos (0U) #define DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos) /*!< 0x00000001 */ #define DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clearr */ #define DMA_IFCR_CTCIF1_Pos (1U) #define DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos) /*!< 0x00000002 */ #define DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */ #define DMA_IFCR_CHTIF1_Pos (2U) #define DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos) /*!< 0x00000004 */ #define DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */ #define DMA_IFCR_CTEIF1_Pos (3U) #define DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos) /*!< 0x00000008 */ #define DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */ #define DMA_IFCR_CGIF2_Pos (4U) #define DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos) /*!< 0x00000010 */ #define DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */ #define DMA_IFCR_CTCIF2_Pos (5U) #define DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos) /*!< 0x00000020 */ #define DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */ #define DMA_IFCR_CHTIF2_Pos (6U) #define DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos) /*!< 0x00000040 */ #define DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */ #define DMA_IFCR_CTEIF2_Pos (7U) #define DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos) /*!< 0x00000080 */ #define DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */ #define DMA_IFCR_CGIF3_Pos (8U) #define DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos) /*!< 0x00000100 */ #define DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */ #define DMA_IFCR_CTCIF3_Pos (9U) #define DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos) /*!< 0x00000200 */ #define DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */ #define DMA_IFCR_CHTIF3_Pos (10U) #define DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos) /*!< 0x00000400 */ #define DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */ #define DMA_IFCR_CTEIF3_Pos (11U) #define DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos) /*!< 0x00000800 */ #define DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */ /******************* Bit definition for DMA_CCR register ********************/ #define DMA_CCR_EN_Pos (0U) #define DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos) /*!< 0x00000001 */ #define DMA_CCR_EN DMA_CCR_EN_Msk /*!< Channel enable */ #define DMA_CCR_TCIE_Pos (1U) #define DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos) /*!< 0x00000002 */ #define DMA_CCR_TCIE DMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */ #define DMA_CCR_HTIE_Pos (2U) #define DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos) /*!< 0x00000004 */ #define DMA_CCR_HTIE DMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */ #define DMA_CCR_TEIE_Pos (3U) #define DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos) /*!< 0x00000008 */ #define DMA_CCR_TEIE DMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */ #define DMA_CCR_DIR_Pos (4U) #define DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos) /*!< 0x00000010 */ #define DMA_CCR_DIR DMA_CCR_DIR_Msk /*!< Data transfer direction */ #define DMA_CCR_CIRC_Pos (5U) #define DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos) /*!< 0x00000020 */ #define DMA_CCR_CIRC DMA_CCR_CIRC_Msk /*!< Circular mode */ #define DMA_CCR_PINC_Pos (6U) #define DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos) /*!< 0x00000040 */ #define DMA_CCR_PINC DMA_CCR_PINC_Msk /*!< Peripheral increment mode */ #define DMA_CCR_MINC_Pos (7U) #define DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos) /*!< 0x00000080 */ #define DMA_CCR_MINC DMA_CCR_MINC_Msk /*!< Memory increment mode */ #define DMA_CCR_PSIZE_Pos (8U) #define DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000300 */ #define DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */ #define DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000100 */ #define DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos) /*!< 0x00000200 */ #define DMA_CCR_MSIZE_Pos (10U) #define DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */ #define DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */ #define DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000400 */ #define DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos) /*!< 0x00000800 */ #define DMA_CCR_PL_Pos (12U) #define DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos) /*!< 0x00003000 */ #define DMA_CCR_PL DMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/ #define DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos) /*!< 0x00001000 */ #define DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos) /*!< 0x00002000 */ #define DMA_CCR_MEM2MEM_Pos (14U) #define DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */ #define DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */ /****************** Bit definition for DMA_CNDTR register *******************/ #define DMA_CNDTR_NDT_Pos (0U) #define DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */ #define DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */ /****************** Bit definition for DMA_CPAR register ********************/ #define DMA_CPAR_PA_Pos (0U) #define DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CPAR_PA DMA_CPAR_PA_Msk /*!< Peripheral Address */ /****************** Bit definition for DMA_CMAR register ********************/ #define DMA_CMAR_MA_Pos (0U) #define DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos) /*!< 0xFFFFFFFF */ #define DMA_CMAR_MA DMA_CMAR_MA_Msk /*!< Memory Address */ /******************************************************************************/ /* */ /* External Interrupt/Event Controller (EXTI) */ /* */ /******************************************************************************/ /****************** Bit definition for EXTI_RTSR register ******************/ #define EXTI_RTSR_RT0_Pos (0U) #define EXTI_RTSR_RT0_Msk (0x1UL << EXTI_RTSR_RT0_Pos) /*!< 0x00000001 */ #define EXTI_RTSR_RT0 EXTI_RTSR_RT0_Msk /*!< Rising trigger configuration for input line 0 */ #define EXTI_RTSR_RT1_Pos (1U) #define EXTI_RTSR_RT1_Msk (0x1UL << EXTI_RTSR_RT1_Pos) /*!< 0x00000002 */ #define EXTI_RTSR_RT1 EXTI_RTSR_RT1_Msk /*!< Rising trigger configuration for input line 1 */ #define EXTI_RTSR_RT2_Pos (2U) #define EXTI_RTSR_RT2_Msk (0x1UL << EXTI_RTSR_RT2_Pos) /*!< 0x00000004 */ #define EXTI_RTSR_RT2 EXTI_RTSR_RT2_Msk /*!< Rising trigger configuration for input line 2 */ #define EXTI_RTSR_RT3_Pos (3U) #define EXTI_RTSR_RT3_Msk (0x1UL << EXTI_RTSR_RT3_Pos) /*!< 0x00000008 */ #define EXTI_RTSR_RT3 EXTI_RTSR_RT3_Msk /*!< Rising trigger configuration for input line 3 */ #define EXTI_RTSR_RT4_Pos (4U) #define EXTI_RTSR_RT4_Msk (0x1UL << EXTI_RTSR_RT4_Pos) /*!< 0x00000010 */ #define EXTI_RTSR_RT4 EXTI_RTSR_RT4_Msk /*!< Rising trigger configuration for input line 4 */ #define EXTI_RTSR_RT5_Pos (5U) #define EXTI_RTSR_RT5_Msk (0x1UL << EXTI_RTSR_RT5_Pos) /*!< 0x00000020 */ #define EXTI_RTSR_RT5 EXTI_RTSR_RT5_Msk /*!< Rising trigger configuration for input line 5 */ #define EXTI_RTSR_RT6_Pos (6U) #define EXTI_RTSR_RT6_Msk (0x1UL << EXTI_RTSR_RT6_Pos) /*!< 0x00000040 */ #define EXTI_RTSR_RT6 EXTI_RTSR_RT6_Msk /*!< Rising trigger configuration for input line 6 */ #define EXTI_RTSR_RT7_Pos (7U) #define EXTI_RTSR_RT7_Msk (0x1UL << EXTI_RTSR_RT7_Pos) /*!< 0x00000080 */ #define EXTI_RTSR_RT7 EXTI_RTSR_RT7_Msk /*!< Rising trigger configuration for input line 7 */ #define EXTI_RTSR_RT8_Pos (8U) #define EXTI_RTSR_RT8_Msk (0x1UL << EXTI_RTSR_RT8_Pos) /*!< 0x00000100 */ #define EXTI_RTSR_RT8 EXTI_RTSR_RT8_Msk /*!< Rising trigger configuration for input line 8 */ #define EXTI_RTSR_RT9_Pos (9U) #define EXTI_RTSR_RT9_Msk (0x1UL << EXTI_RTSR_RT9_Pos) /*!< 0x00000200 */ #define EXTI_RTSR_RT9 EXTI_RTSR_RT9_Msk /*!< Rising trigger configuration for input line 9 */ #define EXTI_RTSR_RT10_Pos (10U) #define EXTI_RTSR_RT10_Msk (0x1UL << EXTI_RTSR_RT10_Pos) /*!< 0x00000400 */ #define EXTI_RTSR_RT10 EXTI_RTSR_RT10_Msk /*!< Rising trigger configuration for input line 10 */ #define EXTI_RTSR_RT11_Pos (11U) #define EXTI_RTSR_RT11_Msk (0x1UL << EXTI_RTSR_RT11_Pos) /*!< 0x00000800 */ #define EXTI_RTSR_RT11 EXTI_RTSR_RT11_Msk /*!< Rising trigger configuration for input line 11 */ #define EXTI_RTSR_RT12_Pos (12U) #define EXTI_RTSR_RT12_Msk (0x1UL << EXTI_RTSR_RT12_Pos) /*!< 0x00001000 */ #define EXTI_RTSR_RT12 EXTI_RTSR_RT12_Msk /*!< Rising trigger configuration for input line 12 */ #define EXTI_RTSR_RT13_Pos (13U) #define EXTI_RTSR_RT13_Msk (0x1UL << EXTI_RTSR_RT13_Pos) /*!< 0x00002000 */ #define EXTI_RTSR_RT13 EXTI_RTSR_RT13_Msk /*!< Rising trigger configuration for input line 13 */ #define EXTI_RTSR_RT14_Pos (14U) #define EXTI_RTSR_RT14_Msk (0x1UL << EXTI_RTSR_RT14_Pos) /*!< 0x00004000 */ #define EXTI_RTSR_RT14 EXTI_RTSR_RT14_Msk /*!< Rising trigger configuration for input line 14 */ #define EXTI_RTSR_RT15_Pos (15U) #define EXTI_RTSR_RT15_Msk (0x1UL << EXTI_RTSR_RT15_Pos) /*!< 0x00008000 */ #define EXTI_RTSR_RT15 EXTI_RTSR_RT15_Msk /*!< Rising trigger configuration for input line 15 */ #define EXTI_RTSR_RT16_Pos (16U) #define EXTI_RTSR_RT16_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00010000 */ #define EXTI_RTSR_RT16 EXTI_RTSR_RT16_Msk /*!< Rising trigger configuration for input line 16 */ #define EXTI_RTSR_RT17_Pos (17U) #define EXTI_RTSR_RT17_Msk (0x1UL << EXTI_RTSR_RT16_Pos) /*!< 0x00020000 */ #define EXTI_RTSR_RT17 EXTI_RTSR_RT17_Msk /*!< Rising trigger configuration for input line 17 */ #define EXTI_RTSR_RT18_Pos (18U) #define EXTI_RTSR_RT18_Msk (0x1UL << EXTI_RTSR_RT18_Pos) /*!< 0x00040000 */ #define EXTI_RTSR_RT18 EXTI_RTSR_RT18_Msk /*!< Rising trigger configuration for input line 18 */ /****************** Bit definition for EXTI_FTSR register ******************/ #define EXTI_FTSR_FT0_Pos (0U) #define EXTI_FTSR_FT0_Msk (0x1UL << EXTI_FTSR_FT0_Pos) /*!< 0x00000001 */ #define EXTI_FTSR_FT0 EXTI_FTSR_FT0_Msk /*!< Falling trigger configuration for input line 0 */ #define EXTI_FTSR_FT1_Pos (1U) #define EXTI_FTSR_FT1_Msk (0x1UL << EXTI_FTSR_FT1_Pos) /*!< 0x00000002 */ #define EXTI_FTSR_FT1 EXTI_FTSR_FT1_Msk /*!< Falling trigger configuration for input line 1 */ #define EXTI_FTSR_FT2_Pos (2U) #define EXTI_FTSR_FT2_Msk (0x1UL << EXTI_FTSR_FT2_Pos) /*!< 0x00000004 */ #define EXTI_FTSR_FT2 EXTI_FTSR_FT2_Msk /*!< Falling trigger configuration for input line 2 */ #define EXTI_FTSR_FT3_Pos (3U) #define EXTI_FTSR_FT3_Msk (0x1UL << EXTI_FTSR_FT3_Pos) /*!< 0x00000008 */ #define EXTI_FTSR_FT3 EXTI_FTSR_FT3_Msk /*!< Falling trigger configuration for input line 3 */ #define EXTI_FTSR_FT4_Pos (4U) #define EXTI_FTSR_FT4_Msk (0x1UL << EXTI_FTSR_FT4_Pos) /*!< 0x00000010 */ #define EXTI_FTSR_FT4 EXTI_FTSR_FT4_Msk /*!< Falling trigger configuration for input line 4 */ #define EXTI_FTSR_FT5_Pos (5U) #define EXTI_FTSR_FT5_Msk (0x1UL << EXTI_FTSR_FT5_Pos) /*!< 0x00000020 */ #define EXTI_FTSR_FT5 EXTI_FTSR_FT5_Msk /*!< Falling trigger configuration for input line 5 */ #define EXTI_FTSR_FT6_Pos (6U) #define EXTI_FTSR_FT6_Msk (0x1UL << EXTI_FTSR_FT6_Pos) /*!< 0x00000040 */ #define EXTI_FTSR_FT6 EXTI_FTSR_FT6_Msk /*!< Falling trigger configuration for input line 6 */ #define EXTI_FTSR_FT7_Pos (7U) #define EXTI_FTSR_FT7_Msk (0x1UL << EXTI_FTSR_FT7_Pos) /*!< 0x00000080 */ #define EXTI_FTSR_FT7 EXTI_FTSR_FT7_Msk /*!< Falling trigger configuration for input line 7 */ #define EXTI_FTSR_FT8_Pos (8U) #define EXTI_FTSR_FT8_Msk (0x1UL << EXTI_FTSR_FT8_Pos) /*!< 0x00000100 */ #define EXTI_FTSR_FT8 EXTI_FTSR_FT8_Msk /*!< Falling trigger configuration for input line 8 */ #define EXTI_FTSR_FT9_Pos (9U) #define EXTI_FTSR_FT9_Msk (0x1UL << EXTI_FTSR_FT9_Pos) /*!< 0x00000200 */ #define EXTI_FTSR_FT9 EXTI_FTSR_FT9_Msk /*!< Falling trigger configuration for input line 9 */ #define EXTI_FTSR_FT10_Pos (10U) #define EXTI_FTSR_FT10_Msk (0x1UL << EXTI_FTSR_FT10_Pos) /*!< 0x00000400 */ #define EXTI_FTSR_FT10 EXTI_FTSR_FT10_Msk /*!< Falling trigger configuration for input line 10 */ #define EXTI_FTSR_FT11_Pos (11U) #define EXTI_FTSR_FT11_Msk (0x1UL << EXTI_FTSR_FT11_Pos) /*!< 0x00000800 */ #define EXTI_FTSR_FT11 EXTI_FTSR_FT11_Msk /*!< Falling trigger configuration for input line 11 */ #define EXTI_FTSR_FT12_Pos (12U) #define EXTI_FTSR_FT12_Msk (0x1UL << EXTI_FTSR_FT12_Pos) /*!< 0x00001000 */ #define EXTI_FTSR_FT12 EXTI_FTSR_FT12_Msk /*!< Falling trigger configuration for input line 12 */ #define EXTI_FTSR_FT13_Pos (13U) #define EXTI_FTSR_FT13_Msk (0x1UL << EXTI_FTSR_FT13_Pos) /*!< 0x00002000 */ #define EXTI_FTSR_FT13 EXTI_FTSR_FT13_Msk /*!< Falling trigger configuration for input line 13 */ #define EXTI_FTSR_FT14_Pos (14U) #define EXTI_FTSR_FT14_Msk (0x1UL << EXTI_FTSR_FT14_Pos) /*!< 0x00004000 */ #define EXTI_FTSR_FT14 EXTI_FTSR_FT14_Msk /*!< Falling trigger configuration for input line 14 */ #define EXTI_FTSR_FT15_Pos (15U) #define EXTI_FTSR_FT15_Msk (0x1UL << EXTI_FTSR_FT15_Pos) /*!< 0x00008000 */ #define EXTI_FTSR_FT15 EXTI_FTSR_FT15_Msk /*!< Falling trigger configuration for input line 15 */ #define EXTI_FTSR_FT16_Pos (16U) #define EXTI_FTSR_FT16_Msk (0x1UL << EXTI_FTSR_FT16_Pos) /*!< 0x00010000 */ #define EXTI_FTSR_FT16 EXTI_FTSR_FT16_Msk /*!< Falling trigger configuration for input line 16 */ #define EXTI_FTSR_FT17_Pos (17U) #define EXTI_FTSR_FT17_Msk (0x1UL << EXTI_FTSR_FT17_Pos) /*!< 0x00020000 */ #define EXTI_FTSR_FT17 EXTI_FTSR_FT17_Msk /*!< Falling trigger configuration for input line 17 */ #define EXTI_FTSR_FT18_Pos (18U) #define EXTI_FTSR_FT18_Msk (0x1UL << EXTI_FTSR_FT18_Pos) /*!< 0x00040000 */ #define EXTI_FTSR_FT18 EXTI_FTSR_FT18_Msk /*!< Falling trigger configuration for input line 18 */ /****************** Bit definition for EXTI_SWIER register *****************/ #define EXTI_SWIER_SWI0_Pos (0U) #define EXTI_SWIER_SWI0_Msk (0x1UL << EXTI_SWIER_SWI0_Pos) /*!< 0x00000001 */ #define EXTI_SWIER_SWI0 EXTI_SWIER_SWI0_Msk /*!< Software Interrupt on line 0 */ #define EXTI_SWIER_SWI1_Pos (1U) #define EXTI_SWIER_SWI1_Msk (0x1UL << EXTI_SWIER_SWI1_Pos) /*!< 0x00000002 */ #define EXTI_SWIER_SWI1 EXTI_SWIER_SWI1_Msk /*!< Software Interrupt on line 1 */ #define EXTI_SWIER_SWI2_Pos (2U) #define EXTI_SWIER_SWI2_Msk (0x1UL << EXTI_SWIER_SWI2_Pos) /*!< 0x00000004 */ #define EXTI_SWIER_SWI2 EXTI_SWIER_SWI2_Msk /*!< Software Interrupt on line 2 */ #define EXTI_SWIER_SWI3_Pos (3U) #define EXTI_SWIER_SWI3_Msk (0x1UL << EXTI_SWIER_SWI3_Pos) /*!< 0x00000008 */ #define EXTI_SWIER_SWI3 EXTI_SWIER_SWI3_Msk /*!< Software Interrupt on line 3 */ #define EXTI_SWIER_SWI4_Pos (4U) #define EXTI_SWIER_SWI4_Msk (0x1UL << EXTI_SWIER_SWI4_Pos) /*!< 0x00000010 */ #define EXTI_SWIER_SWI4 EXTI_SWIER_SWI4_Msk /*!< Software Interrupt on line 4 */ #define EXTI_SWIER_SWI5_Pos (5U) #define EXTI_SWIER_SWI5_Msk (0x1UL << EXTI_SWIER_SWI5_Pos) /*!< 0x00000020 */ #define EXTI_SWIER_SWI5 EXTI_SWIER_SWI5_Msk /*!< Software Interrupt on line 5 */ #define EXTI_SWIER_SWI6_Pos (6U) #define EXTI_SWIER_SWI6_Msk (0x1UL << EXTI_SWIER_SWI6_Pos) /*!< 0x00000040 */ #define EXTI_SWIER_SWI6 EXTI_SWIER_SWI6_Msk /*!< Software Interrupt on line 6 */ #define EXTI_SWIER_SWI7_Pos (7U) #define EXTI_SWIER_SWI7_Msk (0x1UL << EXTI_SWIER_SWI7_Pos) /*!< 0x00000080 */ #define EXTI_SWIER_SWI7 EXTI_SWIER_SWI7_Msk /*!< Software Interrupt on line 7 */ #define EXTI_SWIER_SWI8_Pos (8U) #define EXTI_SWIER_SWI8_Msk (0x1UL << EXTI_SWIER_SWI8_Pos) /*!< 0x00000100 */ #define EXTI_SWIER_SWI8 EXTI_SWIER_SWI8_Msk /*!< Software Interrupt on line 8 */ #define EXTI_SWIER_SWI9_Pos (9U) #define EXTI_SWIER_SWI9_Msk (0x1UL << EXTI_SWIER_SWI9_Pos) /*!< 0x00000200 */ #define EXTI_SWIER_SWI9 EXTI_SWIER_SWI9_Msk /*!< Software Interrupt on line 9 */ #define EXTI_SWIER_SWI10_Pos (10U) #define EXTI_SWIER_SWI10_Msk (0x1UL << EXTI_SWIER_SWI10_Pos) /*!< 0x00000400 */ #define EXTI_SWIER_SWI10 EXTI_SWIER_SWI10_Msk /*!< Software Interrupt on line 10 */ #define EXTI_SWIER_SWI11_Pos (11U) #define EXTI_SWIER_SWI11_Msk (0x1UL << EXTI_SWIER_SWI11_Pos) /*!< 0x00000800 */ #define EXTI_SWIER_SWI11 EXTI_SWIER_SWI11_Msk /*!< Software Interrupt on line 11 */ #define EXTI_SWIER_SWI12_Pos (12U) #define EXTI_SWIER_SWI12_Msk (0x1UL << EXTI_SWIER_SWI12_Pos) /*!< 0x00001000 */ #define EXTI_SWIER_SWI12 EXTI_SWIER_SWI12_Msk /*!< Software Interrupt on line 12 */ #define EXTI_SWIER_SWI13_Pos (13U) #define EXTI_SWIER_SWI13_Msk (0x1UL << EXTI_SWIER_SWI13_Pos) /*!< 0x00002000 */ #define EXTI_SWIER_SWI13 EXTI_SWIER_SWI13_Msk /*!< Software Interrupt on line 13 */ #define EXTI_SWIER_SWI14_Pos (14U) #define EXTI_SWIER_SWI14_Msk (0x1UL << EXTI_SWIER_SWI14_Pos) /*!< 0x00004000 */ #define EXTI_SWIER_SWI14 EXTI_SWIER_SWI14_Msk /*!< Software Interrupt on line 14 */ #define EXTI_SWIER_SWI15_Pos (15U) #define EXTI_SWIER_SWI15_Msk (0x1UL << EXTI_SWIER_SWI15_Pos) /*!< 0x00008000 */ #define EXTI_SWIER_SWI15 EXTI_SWIER_SWI15_Msk /*!< Software Interrupt on line 15 */ #define EXTI_SWIER_SWI16_Pos (16U) #define EXTI_SWIER_SWI16_Msk (0x1UL << EXTI_SWIER_SWI16_Pos) /*!< 0x00010000 */ #define EXTI_SWIER_SWI16 EXTI_SWIER_SWI16_Msk /*!< Software Interrupt on line 16 */ #define EXTI_SWIER_SWI17_Pos (17U) #define EXTI_SWIER_SWI17_Msk (0x1UL << EXTI_SWIER_SWI17_Pos) /*!< 0x00020000 */ #define EXTI_SWIER_SWI17 EXTI_SWIER_SWI17_Msk /*!< Software Interrupt on line 17 */ #define EXTI_SWIER_SWI18_Pos (18U) #define EXTI_SWIER_SWI18_Msk (0x1UL << EXTI_SWIER_SWI18_Pos) /*!< 0x00040000 */ #define EXTI_SWIER_SWI18 EXTI_SWIER_SWI18_Msk /*!< Software Interrupt on line 18*/ /******************* Bit definition for EXTI_PR register ******************/ #define EXTI_PR_PR0_Pos (0U) #define EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos) /*!< 0x00000001 */ #define EXTI_PR_PR0 EXTI_PR_PR0_Msk /*!< Rising Pending Interrupt Flag on line 0 */ #define EXTI_PR_PR1_Pos (1U) #define EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos) /*!< 0x00000002 */ #define EXTI_PR_PR1 EXTI_PR_PR1_Msk /*!< Rising Pending Interrupt Flag on line 1 */ #define EXTI_PR_PR2_Pos (2U) #define EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos) /*!< 0x00000004 */ #define EXTI_PR_PR2 EXTI_PR_PR2_Msk /*!< Rising Pending Interrupt Flag on line 2 */ #define EXTI_PR_PR3_Pos (3U) #define EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos) /*!< 0x00000008 */ #define EXTI_PR_PR3 EXTI_PR_PR3_Msk /*!< Rising Pending Interrupt Flag on line 3 */ #define EXTI_PR_PR_Pos (4U) #define EXTI_PR_PR_Msk (0x1UL <

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