mirror of
https://github.com/IcedRooibos/py32f0-template.git
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20253 lines
528 KiB
XML
20253 lines
528 KiB
XML
<?xml version="1.0" encoding="utf-8" standalone="no"?>
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<device schemaVersion="1.1"
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xmlns:xs="http://www.w3.org/2001/XMLSchema-instance"
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xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
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<vendor>Puya</vendor>
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<vendorID>Puya</vendorID>
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<name>PY32F0xx_DFP</name>
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<!-- name of part-->
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<series>PY32F0</series>
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<version>1.0.0</version>
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<description>Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz.</description>
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<cpu>
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<!-- details about the cpu embedded in the device -->
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<name>CM0+</name>
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<revision>r0p1</revision>
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<endian>little</endian>
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<mpuPresent>false</mpuPresent>
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<fpuPresent>false</fpuPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits>
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<!-- byte addressable memory -->
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<width>32</width>
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<!-- bus width is 32 bits -->
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<!-- default settings implicitly inherited by subsequent sections -->
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<size>32</size>
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<!-- this is the default size (number of bits) of all peripherals and register that do not define "size" themselves -->
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<access>read-write</access>
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<!-- default access permission for all subsequent registers -->
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<resetValue>0x00000000</resetValue>
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<!-- by default all bits of the registers are initialized to 0 on reset -->
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<resetMask>0xFFFFFFFF</resetMask>
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<!-- by default all 32Bits of the registers are used -->
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<peripherals>
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<peripheral>
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<name>ADC</name>
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<description>Analog to Digital Converter</description>
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<groupName>ADC</groupName>
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<baseAddress>0x40012400</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x400</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>ADC_COMP</name>
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<description>ADC and COMP Interrupt through EXTI Lines 17 and 18</description>
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<value>12</value>
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</interrupt>
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<registers>
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<register>
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<name>SR</name>
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<description>desc SR</description>
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<addressOffset>0x0</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<fields>
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<field>
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<name>AWD</name>
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<description>desc AWD</description>
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<msb>0</msb>
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<lsb>0</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>EOC</name>
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<description>desc EOC</description>
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<msb>1</msb>
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<lsb>1</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>JEOC</name>
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<description>desc JEOC</description>
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<msb>2</msb>
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<lsb>2</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>JSTRT</name>
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<description>desc JSTRT</description>
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<msb>3</msb>
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<lsb>3</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>STRT</name>
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<description>desc STRT</description>
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<msb>4</msb>
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<lsb>4</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>OVER</name>
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<description>desc OVER</description>
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<msb>5</msb>
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<lsb>5</lsb>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>CR1</name>
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<description>desc CR1</description>
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<addressOffset>0x4</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<fields>
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<field>
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<name>AWDCH</name>
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<description>desc AWDCH</description>
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<msb>4</msb>
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<lsb>0</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>EOCIE</name>
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<description>desc EOCIE</description>
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<msb>5</msb>
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<lsb>5</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>AWDIE</name>
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<description>desc AWDIE</description>
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<msb>6</msb>
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<lsb>6</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>JEOCIE</name>
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<description>desc JEOCIE</description>
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<msb>7</msb>
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<lsb>7</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SCAN</name>
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<description>desc SCAN</description>
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<msb>8</msb>
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<lsb>8</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>AWDSGL</name>
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<description>desc AWDSGL</description>
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<msb>9</msb>
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<lsb>9</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>JAUTO</name>
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<description>desc JAUTO</description>
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<msb>10</msb>
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<lsb>10</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>DISCEN</name>
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<description>desc DISCEN</description>
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<msb>11</msb>
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<lsb>11</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>JDISCEN</name>
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<description>desc JDISCEN</description>
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<msb>12</msb>
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<lsb>12</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>DISCNUM</name>
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<description>desc DISCNUM</description>
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<msb>15</msb>
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<lsb>13</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>JAWDEN</name>
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<description>desc JAWDEN</description>
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<msb>22</msb>
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<lsb>22</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>AWDEN</name>
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<description>desc AWDEN</description>
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<msb>23</msb>
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<lsb>23</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>RESSEL</name>
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<description>desc RESSEL</description>
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<msb>25</msb>
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<lsb>24</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>ADSTP</name>
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<description>desc ADSTP</description>
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<msb>27</msb>
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<lsb>27</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>MSBSEL</name>
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<description>desc MSBSEL</description>
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<msb>28</msb>
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<lsb>28</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>OVETIE</name>
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<description>desc OVETIE</description>
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<msb>29</msb>
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<lsb>29</lsb>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>CR2</name>
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<description>desc CR2</description>
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<addressOffset>0x8</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<fields>
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<field>
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<name>ADON</name>
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<description>desc ADON</description>
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<msb>0</msb>
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<lsb>0</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>CONT</name>
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<description>desc CONT</description>
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<msb>1</msb>
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<lsb>1</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>CAL</name>
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<description>desc CAL</description>
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<msb>2</msb>
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<lsb>2</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>RSTCAL</name>
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<description>desc RSTCAL</description>
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<msb>3</msb>
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<lsb>3</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>DMA</name>
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<description>desc DMA</description>
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<msb>8</msb>
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<lsb>8</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>ALIGN</name>
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<description>desc ALIGN</description>
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<msb>11</msb>
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<lsb>11</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>JEXTSEL</name>
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<description>desc JEXTSEL</description>
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<msb>14</msb>
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<lsb>12</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>JEXTTRIG</name>
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<description>desc JEXTTRIG</description>
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<msb>15</msb>
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<lsb>15</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>EXTSEL</name>
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<description>desc EXTSEL</description>
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<msb>19</msb>
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<lsb>17</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>EXTTRIG</name>
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<description>desc EXTTRIG</description>
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<msb>20</msb>
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<lsb>20</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>JSWSTART</name>
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<description>desc JSWSTART</description>
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<msb>21</msb>
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<lsb>21</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SWSTART</name>
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<description>desc SWSTART</description>
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<msb>22</msb>
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<lsb>22</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>TSVREFE</name>
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<description>desc TSVREFE</description>
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<msb>23</msb>
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<lsb>23</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>VERFBUFFEREN</name>
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<description>desc VERFBUFFEREN</description>
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<msb>25</msb>
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<lsb>25</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>VERFBUFFERSEL</name>
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<description>desc VERFBUFFERSEL</description>
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<msb>27</msb>
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<lsb>26</lsb>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>SMPR1</name>
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<description>desc SMPR1</description>
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<addressOffset>0xC</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<fields>
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<field>
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<name>SMP20</name>
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<description>desc SMP20</description>
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<msb>2</msb>
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<lsb>0</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SMP21</name>
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<description>desc SMP21</description>
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<msb>5</msb>
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<lsb>3</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SMP22</name>
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<description>desc SMP22</description>
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<msb>8</msb>
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<lsb>6</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SMP23</name>
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<description>desc SMP23</description>
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<msb>11</msb>
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<lsb>9</lsb>
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<access>read-write</access>
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</field>
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</fields>
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</register>
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<register>
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<name>SMPR2</name>
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<description>desc SMPR2</description>
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<addressOffset>0x10</addressOffset>
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<size>32</size>
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<access>read-write</access>
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<resetValue>0x0</resetValue>
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<fields>
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<field>
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<name>SMP10</name>
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<description>desc SMP10</description>
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<msb>2</msb>
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<lsb>0</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SMP11</name>
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<description>desc SMP11</description>
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<msb>5</msb>
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<lsb>3</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SMP12</name>
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<description>desc SMP12</description>
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<msb>8</msb>
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<lsb>6</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SMP13</name>
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<description>desc SMP13</description>
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<msb>11</msb>
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<lsb>9</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SMP14</name>
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<description>desc SMP14</description>
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<msb>14</msb>
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<lsb>12</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SMP15</name>
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<description>desc SMP15</description>
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<msb>17</msb>
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<lsb>15</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SMP16</name>
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<description>desc SMP16</description>
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|
<msb>20</msb>
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<lsb>18</lsb>
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<access>read-write</access>
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</field>
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<field>
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<name>SMP17</name>
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<description>desc SMP17</description>
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|
<msb>23</msb>
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<lsb>21</lsb>
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<access>read-write</access>
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</field>
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|
<field>
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<name>SMP18</name>
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|
<description>desc SMP18</description>
|
|
<msb>26</msb>
|
|
<lsb>24</lsb>
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|
<access>read-write</access>
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|
</field>
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|
<field>
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<name>SMP19</name>
|
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<description>desc SMP19</description>
|
|
<msb>29</msb>
|
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<lsb>27</lsb>
|
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<access>read-write</access>
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|
</field>
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|
</fields>
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</register>
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|
<register>
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<name>SMPR3</name>
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<description>desc SMPR2</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
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|
<field>
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|
<name>SMP0</name>
|
|
<description>desc SMP0</description>
|
|
<msb>2</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMP1</name>
|
|
<description>desc SMP1</description>
|
|
<msb>5</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMP2</name>
|
|
<description>desc SMP2</description>
|
|
<msb>8</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMP3</name>
|
|
<description>desc SMP3</description>
|
|
<msb>11</msb>
|
|
<lsb>9</lsb>
|
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<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMP4</name>
|
|
<description>desc SMP4</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMP5</name>
|
|
<description>desc SMP5</description>
|
|
<msb>17</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMP6</name>
|
|
<description>desc SMP6</description>
|
|
<msb>20</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMP7</name>
|
|
<description>desc SMP7</description>
|
|
<msb>23</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMP8</name>
|
|
<description>desc SMP8</description>
|
|
<msb>26</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMP9</name>
|
|
<description>desc SMP9</description>
|
|
<msb>29</msb>
|
|
<lsb>27</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JOFR1</name>
|
|
<description>desc JOFR1</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JOFFSET1</name>
|
|
<description>desc JOFFSET1</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JOFR2</name>
|
|
<description>desc JOFR2</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JOFFSET2</name>
|
|
<description>desc JOFFSET2</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JOFR3</name>
|
|
<description>desc JOFR3</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JOFFSET3</name>
|
|
<description>desc JOFFSET3</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JOFR4</name>
|
|
<description>desc JOFR4</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JOFFSET4</name>
|
|
<description>desc JOFFSET4</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>HTR</name>
|
|
<description>desc HTR</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HT</name>
|
|
<description>desc HT</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LTR</name>
|
|
<description>desc LTR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LT</name>
|
|
<description>desc LT</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR1</name>
|
|
<description>desc SQR1</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ13</name>
|
|
<description>desc SQ13</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ14</name>
|
|
<description>desc SQ14</description>
|
|
<msb>9</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ15</name>
|
|
<description>desc SQ15</description>
|
|
<msb>14</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ16</name>
|
|
<description>desc SQ16</description>
|
|
<msb>19</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>L</name>
|
|
<description>desc L</description>
|
|
<msb>23</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR2</name>
|
|
<description>desc SQR2</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ7</name>
|
|
<description>desc SQ7</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ8</name>
|
|
<description>desc SQ8</description>
|
|
<msb>9</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ9</name>
|
|
<description>desc SQ9</description>
|
|
<msb>14</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ10</name>
|
|
<description>desc SQ10</description>
|
|
<msb>19</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ11</name>
|
|
<description>desc SQ11</description>
|
|
<msb>24</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ12</name>
|
|
<description>desc SQ12</description>
|
|
<msb>29</msb>
|
|
<lsb>25</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SQR3</name>
|
|
<description>desc SQR3</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SQ1</name>
|
|
<description>desc SQ1</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ2</name>
|
|
<description>desc SQ2</description>
|
|
<msb>9</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ3</name>
|
|
<description>desc SQ3</description>
|
|
<msb>14</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ4</name>
|
|
<description>desc SQ4</description>
|
|
<msb>19</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ5</name>
|
|
<description>desc SQ5</description>
|
|
<msb>24</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SQ6</name>
|
|
<description>desc SQ6</description>
|
|
<msb>29</msb>
|
|
<lsb>25</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JSQR</name>
|
|
<description>desc JSQR</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JSQ1</name>
|
|
<description>desc JSQ1</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>JSQ2</name>
|
|
<description>desc JSQ2</description>
|
|
<msb>9</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>JSQ3</name>
|
|
<description>desc JSQ3</description>
|
|
<msb>14</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>JSQ4</name>
|
|
<description>desc JSQ4</description>
|
|
<msb>19</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>JL</name>
|
|
<description>desc JL</description>
|
|
<msb>21</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR1</name>
|
|
<description>desc JDR1</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDR1</name>
|
|
<description>desc JDR1</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR2</name>
|
|
<description>desc JDR2</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDR2</name>
|
|
<description>desc JDR2</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR3</name>
|
|
<description>desc JDR3</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDR3</name>
|
|
<description>desc JDR3</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>JDR4</name>
|
|
<description>desc JDR4</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>JDR4</name>
|
|
<description>desc JDR4</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>desc DR</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DATA</name>
|
|
<description>desc DATA</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCSR</name>
|
|
<description>desc CCSR</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALSEL</name>
|
|
<description>desc CALSEL</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALSMP</name>
|
|
<description>desc CALSMP</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALBYP</name>
|
|
<description>desc CALBYP</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALSET</name>
|
|
<description>desc CALSET</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALFAIL</name>
|
|
<description>desc CALFAIL</description>
|
|
<msb>30</msb>
|
|
<lsb>30</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALON</name>
|
|
<description>desc CALON</description>
|
|
<msb>31</msb>
|
|
<lsb>31</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALRR1</name>
|
|
<description>desc CALRR1</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALC10OUT</name>
|
|
<description>desc CALC10OUT</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALC11OUT</name>
|
|
<description>desc CALC11OUT</description>
|
|
<msb>15</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALBOUT</name>
|
|
<description>desc CALBOUT</description>
|
|
<msb>23</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALRR2</name>
|
|
<description>desc CALRR2</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALC6OUT</name>
|
|
<description>desc CALC6OUT</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALC7OUT</name>
|
|
<description>desc CALC7OUT</description>
|
|
<msb>15</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALC8OUT</name>
|
|
<description>desc CALC8OUT</description>
|
|
<msb>23</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CALC9OUT</name>
|
|
<description>desc CALC9OUT</description>
|
|
<msb>31</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALFIR1</name>
|
|
<description>desc CALFIR1</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALC10IO</name>
|
|
<description>desc CALC10IO</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALC11IO</name>
|
|
<description>desc CALC11IO</description>
|
|
<msb>15</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALBIO</name>
|
|
<description>desc CALBIO</description>
|
|
<msb>23</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALFIR2</name>
|
|
<description>desc CALFIR2</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALC6IO</name>
|
|
<description>desc CALC6IO</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALC7IO</name>
|
|
<description>desc CALC7IO</description>
|
|
<msb>15</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALC8IO</name>
|
|
<description>desc CALC8IO</description>
|
|
<msb>23</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CALC9IO</name>
|
|
<description>desc CALC9IO</description>
|
|
<msb>31</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CAN</name>
|
|
<description>desc CAN</description>
|
|
<groupName>CAN</groupName>
|
|
<baseAddress>0x40006400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>CAN</name>
|
|
<description>CAN global Interrupt</description>
|
|
<value>30</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>TSNCR</name>
|
|
<description>desc TSNCR</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2010801</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>VERSION</name>
|
|
<description>desc VERSION</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CES</name>
|
|
<description>desc CES</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ROP</name>
|
|
<description>desc ROP</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TMSE</name>
|
|
<description>desc TMSE</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSEN</name>
|
|
<description>desc TSEN</description>
|
|
<msb>24</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSPOS</name>
|
|
<description>desc TSPOS</description>
|
|
<msb>25</msb>
|
|
<lsb>25</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACBTR</name>
|
|
<description>desc ACBTR</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x5050008</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AC_SEG_1</name>
|
|
<description>desc AC_SEG_1</description>
|
|
<msb>8</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AC_SEG_2</name>
|
|
<description>desc AC_SEG_2</description>
|
|
<msb>22</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AC_SJW</name>
|
|
<description>desc AC_SJW</description>
|
|
<msb>30</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FDBTR</name>
|
|
<description>desc FDBTR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2020003</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FD_SEG_1</name>
|
|
<description>desc FD_SEG_1</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FD_SEG_2</name>
|
|
<description>desc FD_SEG_2</description>
|
|
<msb>22</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FD_SJW</name>
|
|
<description>desc FD_SJW</description>
|
|
<msb>30</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>XLBTR</name>
|
|
<description>desc XLBTR</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2020003</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XL_SEG_1</name>
|
|
<description>desc XL_SEG_1</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XL_SEG_2</name>
|
|
<description>desc XL_SEG_2</description>
|
|
<msb>22</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XL_SJW</name>
|
|
<description>desc XL_SJW</description>
|
|
<msb>30</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RLSSP</name>
|
|
<description>desc RLSSP</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x77000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>desc PRESC</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FD_SSPOFF</name>
|
|
<description>desc FD_SSPOFF</description>
|
|
<msb>15</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>XL_SSPOFF</name>
|
|
<description>desc XL_SSPOFF</description>
|
|
<msb>23</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REALIM</name>
|
|
<description>desc REALIM</description>
|
|
<msb>26</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RETLIM</name>
|
|
<description>desc RETLIM</description>
|
|
<msb>30</msb>
|
|
<lsb>28</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFR</name>
|
|
<description>desc IFR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AIF</name>
|
|
<description>desc AIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EIF</name>
|
|
<description>desc EIF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSIF</name>
|
|
<description>desc TSIF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TPIF</name>
|
|
<description>desc TPIF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RAFIF</name>
|
|
<description>desc RAFIF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFIF</name>
|
|
<description>desc RFIF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ROIF</name>
|
|
<description>desc ROIF</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RIF</name>
|
|
<description>desc RIF</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BEIF</name>
|
|
<description>desc BEIF</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALIF</name>
|
|
<description>desc ALIF</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPIF</name>
|
|
<description>desc EPIF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TTIF</name>
|
|
<description>desc TTIF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIF</name>
|
|
<description>desc TEIF</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WTIF</name>
|
|
<description>desc WTIF</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MDWIF</name>
|
|
<description>desc MDWIF</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MDEIF</name>
|
|
<description>desc MDEIF</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAEIF</name>
|
|
<description>desc MAEIF</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SEIF</name>
|
|
<description>desc SEIF</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWIF</name>
|
|
<description>desc SWIF</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPASS</name>
|
|
<description>desc EPASS</description>
|
|
<msb>30</msb>
|
|
<lsb>30</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EWARN</name>
|
|
<description>desc EWARN</description>
|
|
<msb>31</msb>
|
|
<lsb>31</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<description>desc IER</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x468FE</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EIE</name>
|
|
<description>desc EIE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSIE</name>
|
|
<description>desc TSIE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TPIE</name>
|
|
<description>desc TPIE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RAFIE</name>
|
|
<description>desc RAFIE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RFIE</name>
|
|
<description>desc RFIE</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ROIE</name>
|
|
<description>desc ROIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RIE</name>
|
|
<description>desc RIE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BEIE</name>
|
|
<description>desc BEIE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALIE</name>
|
|
<description>desc ALIE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EPIE</name>
|
|
<description>desc EPIE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TTIE</name>
|
|
<description>desc TTIE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WTIE</name>
|
|
<description>desc WTIE</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MDWIE</name>
|
|
<description>desc MDWIE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWIE</name>
|
|
<description>desc SWIE</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TSR</name>
|
|
<description>desc TSR</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HANDLE_L</name>
|
|
<description>desc HANDLE_L</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TSTAT_L</name>
|
|
<description>desc TSTAT_L</description>
|
|
<msb>10</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HANDLE_H</name>
|
|
<description>desc HANDLE_H</description>
|
|
<msb>23</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TSTAT_H</name>
|
|
<description>desc TSTAT_H</description>
|
|
<msb>26</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTSL</name>
|
|
<description>desc TTSL</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TTS</name>
|
|
<description>desc TTS</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTSH</name>
|
|
<description>desc TTSH</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x2000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TTS</name>
|
|
<description>desc TTS</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MCR</name>
|
|
<description>desc MCR</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x900080</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BUSOFF</name>
|
|
<description>desc BUSOFF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LBMI</name>
|
|
<description>desc LBMI</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LBME</name>
|
|
<description>desc LBME</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>desc RESET</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSA</name>
|
|
<description>desc TSA</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSALL</name>
|
|
<description>desc TSALL</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSONE</name>
|
|
<description>desc TSONE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TPA</name>
|
|
<description>desc TPA</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TPE</name>
|
|
<description>desc TPE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STBY</name>
|
|
<description>desc STBY</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOM</name>
|
|
<description>desc LOM</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBSEL</name>
|
|
<description>desc TBSEL</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSSTAT</name>
|
|
<description>desc TSSTAT</description>
|
|
<msb>17</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TSFF</name>
|
|
<description>desc TSFF</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TTTBM</name>
|
|
<description>desc TTTBM</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSMODE</name>
|
|
<description>desc TSMODE</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSNEXT</name>
|
|
<description>desc TSNEXT</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FD_ISO</name>
|
|
<description>desc FD_ISO</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSTAT</name>
|
|
<description>desc RSTAT</description>
|
|
<msb>25</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RBALL</name>
|
|
<description>desc RBALL</description>
|
|
<msb>27</msb>
|
|
<lsb>27</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RREL</name>
|
|
<description>desc RREL</description>
|
|
<msb>28</msb>
|
|
<lsb>28</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ROV</name>
|
|
<description>desc ROV</description>
|
|
<msb>29</msb>
|
|
<lsb>29</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ROM</name>
|
|
<description>desc ROM</description>
|
|
<msb>30</msb>
|
|
<lsb>30</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SACK</name>
|
|
<description>desc SACK</description>
|
|
<msb>31</msb>
|
|
<lsb>31</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WECR</name>
|
|
<description>desc WECR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1B</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EWL</name>
|
|
<description>desc EWL</description>
|
|
<msb>3</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AFWL</name>
|
|
<description>desc AFWL</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALC</name>
|
|
<description>desc ALC</description>
|
|
<msb>12</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>KOER</name>
|
|
<description>desc KOER</description>
|
|
<msb>15</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RECNT</name>
|
|
<description>desc RECNT</description>
|
|
<msb>23</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TECNT</name>
|
|
<description>desc TECNT</description>
|
|
<msb>31</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REFMSG</name>
|
|
<description>desc REFMSG</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REF_ID</name>
|
|
<description>desc REF_ID</description>
|
|
<msb>28</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REF_IDE</name>
|
|
<description>desc REF_IDE</description>
|
|
<msb>31</msb>
|
|
<lsb>31</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTCR</name>
|
|
<description>desc TTCR</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TTPTR</name>
|
|
<description>desc TTPTR</description>
|
|
<msb>5</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TTYPE</name>
|
|
<description>desc TTYPE</description>
|
|
<msb>10</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEW</name>
|
|
<description>desc TEW</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBPTR</name>
|
|
<description>desc TBPTR</description>
|
|
<msb>21</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBF</name>
|
|
<description>desc TBF</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TBE</name>
|
|
<description>desc TBE</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TTEN</name>
|
|
<description>desc TTEN</description>
|
|
<msb>24</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>T_PRESC</name>
|
|
<description>desc T_PRESC</description>
|
|
<msb>26</msb>
|
|
<lsb>25</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TTTR</name>
|
|
<description>desc TTTR</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TT_TRIG</name>
|
|
<description>desc TT_TRIG</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TT_WTRIG</name>
|
|
<description>desc TT_WTRIG</description>
|
|
<msb>31</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SCMS</name>
|
|
<description>desc SCMS</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>XMREN</name>
|
|
<description>desc XMREN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FSTIM</name>
|
|
<description>desc FSTIM</description>
|
|
<msb>3</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACFA</name>
|
|
<description>desc ACFA</description>
|
|
<msb>24</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXS</name>
|
|
<description>desc TXS</description>
|
|
<msb>25</msb>
|
|
<lsb>25</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXB</name>
|
|
<description>desc TXB</description>
|
|
<msb>26</msb>
|
|
<lsb>26</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HELOC</name>
|
|
<description>desc HELOC</description>
|
|
<msb>28</msb>
|
|
<lsb>27</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>MPEN</name>
|
|
<description>desc MPEN</description>
|
|
<msb>31</msb>
|
|
<lsb>31</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>MESR</name>
|
|
<description>desc MESR</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MEBP1</name>
|
|
<description>desc MEBP1</description>
|
|
<msb>5</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ME1EE</name>
|
|
<description>desc ME1EE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEAEE</name>
|
|
<description>desc MEAEE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEBP2</name>
|
|
<description>desc MEBP2</description>
|
|
<msb>13</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ME2EE</name>
|
|
<description>desc ME2EE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEEEC</name>
|
|
<description>desc MEEEC</description>
|
|
<msb>19</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MENEC</name>
|
|
<description>desc MENEC</description>
|
|
<msb>23</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEL</name>
|
|
<description>desc MEL</description>
|
|
<msb>25</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MES</name>
|
|
<description>desc MES</description>
|
|
<msb>26</msb>
|
|
<lsb>26</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ACFCR</name>
|
|
<description>desc ACFCR</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x10000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ACFADR</name>
|
|
<description>desc ACFADR</description>
|
|
<msb>3</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_0</name>
|
|
<description>desc AE_0</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_1</name>
|
|
<description>desc AE_1</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_2</name>
|
|
<description>desc AE_2</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_3</name>
|
|
<description>desc AE_3</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_4</name>
|
|
<description>desc AE_4</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_5</name>
|
|
<description>desc AE_5</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_6</name>
|
|
<description>desc AE_6</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_7</name>
|
|
<description>desc AE_7</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_8</name>
|
|
<description>desc AE_8</description>
|
|
<msb>24</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_9</name>
|
|
<description>desc AE_9</description>
|
|
<msb>25</msb>
|
|
<lsb>25</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_10</name>
|
|
<description>desc AE_10</description>
|
|
<msb>26</msb>
|
|
<lsb>26</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_11</name>
|
|
<description>desc AE_11</description>
|
|
<msb>27</msb>
|
|
<lsb>27</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_12</name>
|
|
<description>desc AE_12</description>
|
|
<msb>28</msb>
|
|
<lsb>28</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_13</name>
|
|
<description>desc AE_13</description>
|
|
<msb>29</msb>
|
|
<lsb>29</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_14</name>
|
|
<description>desc AE_14</description>
|
|
<msb>30</msb>
|
|
<lsb>30</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AE_15</name>
|
|
<description>desc AE_15</description>
|
|
<msb>31</msb>
|
|
<lsb>31</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PWMCR</name>
|
|
<description>desc PWMCR</description>
|
|
<addressOffset>0xB8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2080400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PWMO</name>
|
|
<description>desc PWMO</description>
|
|
<msb>5</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWMS</name>
|
|
<description>desc PWMS</description>
|
|
<msb>13</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PWML</name>
|
|
<description>desc PWML</description>
|
|
<msb>21</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>COMP1</name>
|
|
<description>Comparator 1</description>
|
|
<groupName>COMP</groupName>
|
|
<baseAddress>0x40010200</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC_COMP</name>
|
|
<description>ADC and COMP Interrupt through EXTI Lines 17 and 18</description>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<displayName>CSR</displayName>
|
|
<description>COMP control and status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_OUT</name>
|
|
<description>Comparator output status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCSEL</name>
|
|
<description>VCSEL</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCDIV_EN</name>
|
|
<description>VCDIV_EN</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VCDIV</name>
|
|
<description>VCDIV</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWRMODE</name>
|
|
<description>
|
|
Comparator power mode
|
|
selector
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>
|
|
Comparator hysteresis enable
|
|
selector
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POLARITY</name>
|
|
<description>
|
|
Comparator polarity
|
|
selector
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMODE</name>
|
|
<description>
|
|
Comparator non-inverting input
|
|
selector for window mode
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>
|
|
Comparator signal selector for
|
|
non-inverting input
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INMSEL</name>
|
|
<description>
|
|
Comparator signal selector for
|
|
inverting input INM
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>COMP enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR</name>
|
|
<displayName>FR</displayName>
|
|
<description>
|
|
Comparator Filter
|
|
register
|
|
</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTCNT1</name>
|
|
<description>Comparator filter and counter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLTEN1</name>
|
|
<description>Filter enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>COMP2</name>
|
|
<description>Comparator2</description>
|
|
<groupName>COMP</groupName>
|
|
<baseAddress>0x40010210</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC_COMP</name>
|
|
<description>ADC and COMP Interrupt through EXTI Lines 17 and 18</description>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<displayName>CSR</displayName>
|
|
<description>COMP control and status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_OUT</name>
|
|
<description>Comparator output status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWRMODE</name>
|
|
<description>
|
|
Comparator power mode
|
|
selector
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POLARITY</name>
|
|
<description>
|
|
Comparator polarity
|
|
selector
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WINMODE</name>
|
|
<description>
|
|
Comparator non-inverting input
|
|
selector for window mode
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>
|
|
Comparator signal selector for
|
|
non-inverting input
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INMSEL</name>
|
|
<description>
|
|
Comparator signal selector for
|
|
inverting input INM
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>
|
|
Comparator hysteresis enable
|
|
selector
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>COMP enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR</name>
|
|
<displayName>FR</displayName>
|
|
<description>
|
|
Comparator Filter
|
|
register
|
|
</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTCNT2</name>
|
|
<description>Comparator filter and counter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLTEN2</name>
|
|
<description>Filter enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>COMP3</name>
|
|
<description>Comparator3</description>
|
|
<groupName>COMP</groupName>
|
|
<baseAddress>0x40010220</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x10</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>ADC_COMP</name>
|
|
<description>ADC and COMP Interrupt through EXTI Lines 17 and 18</description>
|
|
<value>12</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CSR</name>
|
|
<displayName>CSR</displayName>
|
|
<description>COMP control and status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>COMP_OUT</name>
|
|
<description>Comparator output status</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWRMODE</name>
|
|
<description>
|
|
Comparator power mode
|
|
selector
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POLARITY</name>
|
|
<description>
|
|
Comparator polarity
|
|
selector
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INPSEL</name>
|
|
<description>
|
|
Comparator signal selector for
|
|
non-inverting input
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INMSEL</name>
|
|
<description>
|
|
Comparator signal selector for
|
|
inverting input INM
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HYST</name>
|
|
<description>
|
|
Comparator hysteresis enable
|
|
selector
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>COMP enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FR</name>
|
|
<displayName>FR</displayName>
|
|
<description>
|
|
Comparator Filter
|
|
register
|
|
</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLTCNT3</name>
|
|
<description>Comparator filter and counter</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLTEN3</name>
|
|
<description>Filter enable bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>CRC calculation unit</description>
|
|
<groupName>CRC</groupName>
|
|
<baseAddress>0x40023000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>Data register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>Data Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<displayName>IDR</displayName>
|
|
<description>Independent Data register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDR</name>
|
|
<description>Independent Data register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Reset bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CTC</name>
|
|
<description>desc CTC</description>
|
|
<groupName>CTC</groupName>
|
|
<baseAddress>0x40006C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RCC_CTC</name>
|
|
<description>RCC and CTC global Interrupts</description>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CTL0</name>
|
|
<description>desc CTL0</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKOKIE</name>
|
|
<description>desc CKOKIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKWARNIE</name>
|
|
<description>desc CKWARNIE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>desc ERRIE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EREFIE</name>
|
|
<description>desc EREFIE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNTEN</name>
|
|
<description>desc CNTEN</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AUTOTRIM</name>
|
|
<description>desc AUTOTRIM</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWREFPUL</name>
|
|
<description>desc SWREFPUL</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIMVALUE</name>
|
|
<description>desc TRIMVALUE</description>
|
|
<msb>13</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CTL1</name>
|
|
<description>desc CTL1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2022BB7F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RLVALUE</name>
|
|
<description>desc RLVALUE</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKLIM</name>
|
|
<description>desc CKLIM</description>
|
|
<msb>23</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFPSC</name>
|
|
<description>desc REFPSC</description>
|
|
<msb>26</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFSEL</name>
|
|
<description>desc REFSEL</description>
|
|
<msb>29</msb>
|
|
<lsb>28</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>REFPOL</name>
|
|
<description>desc REFPOL</description>
|
|
<msb>31</msb>
|
|
<lsb>31</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKOKIF</name>
|
|
<description>desc CKOKIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CKWARNIF</name>
|
|
<description>desc CKWARNIF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRIF</name>
|
|
<description>desc ERRIF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EREFIF</name>
|
|
<description>desc EREFIF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CKERR</name>
|
|
<description>desc CKERR</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REFMISS</name>
|
|
<description>desc REFMISS</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIMERR</name>
|
|
<description>desc TRIMERR</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REFDIR</name>
|
|
<description>desc REFDIR</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>REFCAP</name>
|
|
<description>desc REFCAP</description>
|
|
<msb>31</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTC</name>
|
|
<description>desc INTC</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CKOKIC</name>
|
|
<description>desc CKOKIC</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CKWARNIC</name>
|
|
<description>desc CKWARNIC</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRIC</name>
|
|
<description>desc ERRIC</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>EREFIC</name>
|
|
<description>desc EREFIC</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DAC</name>
|
|
<description>desc DAC</description>
|
|
<groupName>DAC</groupName>
|
|
<baseAddress>0x40007400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM6_LPTIM1_DAC</name>
|
|
<description>TIM6, LPTIM1, DAC global Interrupts</description>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>desc CR</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN1</name>
|
|
<description>desc EN1</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOFF1</name>
|
|
<description>desc BOFF1</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEN1</name>
|
|
<description>desc TEN1</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSEL1</name>
|
|
<description>desc TSEL1</description>
|
|
<msb>5</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAVE1</name>
|
|
<description>desc WAVE1</description>
|
|
<msb>7</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAMP1</name>
|
|
<description>desc MAMP1</description>
|
|
<msb>11</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN1</name>
|
|
<description>desc DMAEN1</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAUDRIE1</name>
|
|
<description>desc DMAUDRIE1</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DAC1CEN</name>
|
|
<description>desc DAC1CEN</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EN2</name>
|
|
<description>desc EN2</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BOFF2</name>
|
|
<description>desc BOFF2</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEN2</name>
|
|
<description>desc TEN2</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TSEL2</name>
|
|
<description>desc TSEL2</description>
|
|
<msb>21</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAVE2</name>
|
|
<description>desc WAVE2</description>
|
|
<msb>23</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MAMP2</name>
|
|
<description>desc MAMP2</description>
|
|
<msb>27</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN2</name>
|
|
<description>desc DMAEN2</description>
|
|
<msb>28</msb>
|
|
<lsb>28</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAUDRIE2</name>
|
|
<description>desc DMAUDRIE2</description>
|
|
<msb>29</msb>
|
|
<lsb>29</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DAC2CEN</name>
|
|
<description>desc DAC2CEN</description>
|
|
<msb>30</msb>
|
|
<lsb>30</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWTRIGR</name>
|
|
<description>desc SWTRIGR</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWTRIG1</name>
|
|
<description>desc SWTRIG1</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SWTRIG2</name>
|
|
<description>desc SWTRIG2</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12R1</name>
|
|
<description>desc DHR12R1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>desc DACC1DHR</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12L1</name>
|
|
<description>desc DHR12L1</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>desc DACC1DHR</description>
|
|
<msb>14</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR8R1</name>
|
|
<description>desc DHR8R1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>desc DACC1DHR</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12R2</name>
|
|
<description>desc DHR12R2</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>desc DACC2DHR</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12L2</name>
|
|
<description>desc DHR12L2</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>desc DACC2DHR</description>
|
|
<msb>15</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR8R2</name>
|
|
<description>desc DHR8R2</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>desc DACC2DHR</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12RD</name>
|
|
<description>desc DHR12RD</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>desc DACC1DHR</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>desc DACC2DHR</description>
|
|
<msb>27</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR12LD</name>
|
|
<description>desc DHR12LD</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>desc DACC1DHR</description>
|
|
<msb>15</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>desc DACC2DHR</description>
|
|
<msb>31</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DHR8RD</name>
|
|
<description>desc DHR8RD</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DHR</name>
|
|
<description>desc DACC1DHR</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DACC2DHR</name>
|
|
<description>desc DACC2DHR</description>
|
|
<msb>15</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOR1</name>
|
|
<description>desc DOR1</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC1DOR</name>
|
|
<description>desc DACC1DOR</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DOR2</name>
|
|
<description>desc DOR2</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DACC2DOR</name>
|
|
<description>desc DACC2DOR</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAUDR1</name>
|
|
<description>desc DMAUDR1</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAUDR2</name>
|
|
<description>desc DMAUDR2</description>
|
|
<msb>29</msb>
|
|
<lsb>29</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DBGMCU</name>
|
|
<description>Debug support</description>
|
|
<groupName>DBGMCU</groupName>
|
|
<baseAddress>0x40015800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>IDCODE</name>
|
|
<displayName>IDCODE</displayName>
|
|
<description>MCU Device ID Code Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_ID</name>
|
|
<description>DBG_ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>
|
|
Debug MCU Configuration
|
|
Register
|
|
</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_SLEEP</name>
|
|
<description>Debug Sleep Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_STOP</name>
|
|
<description>Debug Stop Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB_FZ1</name>
|
|
<displayName>APB_FZ1</displayName>
|
|
<description>APB Freeze Register1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_TIMER2_STOP</name>
|
|
<description>
|
|
Debug Timer 2 stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIMER3_STOP</name>
|
|
<description>
|
|
Debug Timer 3 stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIMER6_STOP</name>
|
|
<description>
|
|
Debug Timer 6 stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIMER7_STOP</name>
|
|
<description>
|
|
Debug Timer 7 stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_RTC_STOP</name>
|
|
<description>
|
|
Debug RTC stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_WWDG_STOP</name>
|
|
<description>
|
|
Debug Window Wachdog stopped when Core
|
|
is halted
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_IWDG_STOP</name>
|
|
<description>
|
|
Debug Independent Wachdog stopped when
|
|
Core is halted
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_CAN_STOP</name>
|
|
<description>DBG_CAN_STOP</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_I2C1_SMBUS_TIMEOUT</name>
|
|
<description>DBG_I2C1_SMBUS_TIMEOUT</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_I2C2_SMBUS_TIMEOUT</name>
|
|
<description>DBG_I2C2_SMBUS_TIMEOUT</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DBG_LPTIM_STOP</name>
|
|
<description>
|
|
Debug LPTIM stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB_FZ2</name>
|
|
<displayName>APB_FZ2</displayName>
|
|
<description>APB Freeze Register2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_TIMER1_STOP</name>
|
|
<description>
|
|
Debug Timer 1 stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIMER14_STOP</name>
|
|
<description>
|
|
Debug Timer 14 stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIMER15_STOP</name>
|
|
<description>
|
|
Debug Timer 15 stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIMER16_STOP</name>
|
|
<description>
|
|
Debug Timer 16 stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_TIMER17_STOP</name>
|
|
<description>
|
|
Debug Timer 17 stopped when Core is
|
|
halted
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DV</name>
|
|
<description>Divider</description>
|
|
<groupName>DV</groupName>
|
|
<baseAddress>0x40023800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DEND</name>
|
|
<displayName>DEND</displayName>
|
|
<description>Dividend</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DEND</name>
|
|
<description>Dividend</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SOR</name>
|
|
<displayName>SOR</displayName>
|
|
<description>Divisor</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SOR</name>
|
|
<description>Divisor</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>QUOT</name>
|
|
<displayName>QUOT</displayName>
|
|
<description>Quotient</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>QUOT</name>
|
|
<description>Quotient</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>REMA</name>
|
|
<displayName>REMA</displayName>
|
|
<description>Remainder</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REMA</name>
|
|
<description>Remainder</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SIGN</name>
|
|
<displayName>SIGN</displayName>
|
|
<description>des SIGN</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_SIGN</name>
|
|
<description>des DIV_SIGN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STAT</name>
|
|
<displayName>STAT</displayName>
|
|
<description>des SIGN</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_END</name>
|
|
<description>des DIV_END</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV_ZERO</name>
|
|
<description>des DIV_ZERO</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DMA</name>
|
|
<description>Direct memory access</description>
|
|
<groupName>DMA</groupName>
|
|
<baseAddress>0x40020000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>DMA1_Channel1</name>
|
|
<description>DMA1 Channel 1 Interrupt</description>
|
|
<value>9</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_Channel2_3</name>
|
|
<description>DMA1 Channel 2 and Channel 3 Interrupt</description>
|
|
<value>10</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>DMA1_Channel4_5_6_7</name>
|
|
<description>DMA1 Channel 4, 5, 6, 7 Interrupts</description>
|
|
<value>11</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ISR</name>
|
|
<description>desc ISR</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GIF1</name>
|
|
<description>desc GIF1</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIF1</name>
|
|
<description>desc TCIF1</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIF1</name>
|
|
<description>desc HTIF1</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIF1</name>
|
|
<description>desc TEIF1</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GIF2</name>
|
|
<description>desc GIF2</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIF2</name>
|
|
<description>desc TCIF2</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIF2</name>
|
|
<description>desc HTIF2</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIF2</name>
|
|
<description>desc TEIF2</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GIF3</name>
|
|
<description>desc GIF3</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIF3</name>
|
|
<description>desc TCIF3</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIF3</name>
|
|
<description>desc HTIF3</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIF3</name>
|
|
<description>desc TEIF3</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GIF4</name>
|
|
<description>desc GIF4</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIF4</name>
|
|
<description>desc TCIF4</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIF4</name>
|
|
<description>desc HTIF4</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIF4</name>
|
|
<description>desc TEIF4</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GIF5</name>
|
|
<description>desc GIF5</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIF5</name>
|
|
<description>desc TCIF5</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIF5</name>
|
|
<description>desc HTIF5</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIF5</name>
|
|
<description>desc TEIF5</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GIF6</name>
|
|
<description>desc GIF6</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIF6</name>
|
|
<description>desc TCIF6</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIF6</name>
|
|
<description>desc HTIF6</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIF6</name>
|
|
<description>desc TEIF6</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GIF7</name>
|
|
<description>desc GIF7</description>
|
|
<msb>24</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIF7</name>
|
|
<description>desc TCIF7</description>
|
|
<msb>25</msb>
|
|
<lsb>25</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIF7</name>
|
|
<description>desc HTIF7</description>
|
|
<msb>26</msb>
|
|
<lsb>26</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIF7</name>
|
|
<description>desc TEIF7</description>
|
|
<msb>27</msb>
|
|
<lsb>27</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IFCR</name>
|
|
<description>desc IFCR</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CGIF1</name>
|
|
<description>desc CGIF1</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF1</name>
|
|
<description>desc CTCIF1</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF1</name>
|
|
<description>desc CHTIF1</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF1</name>
|
|
<description>desc CTEIF1</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CGIF2</name>
|
|
<description>desc CGIF2</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF2</name>
|
|
<description>desc CTCIF2</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF2</name>
|
|
<description>desc CHTIF2</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF2</name>
|
|
<description>desc CTEIF2</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CGIF3</name>
|
|
<description>desc CGIF3</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF3</name>
|
|
<description>desc CTCIF3</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF3</name>
|
|
<description>desc CHTIF3</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF3</name>
|
|
<description>desc CTEIF3</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CGIF4</name>
|
|
<description>desc CGIF4</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF4</name>
|
|
<description>desc CTCIF4</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF4</name>
|
|
<description>desc CHTIF4</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF4</name>
|
|
<description>desc CTEIF4</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CGIF5</name>
|
|
<description>desc CGIF5</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF5</name>
|
|
<description>desc CTCIF5</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF5</name>
|
|
<description>desc CHTIF5</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF5</name>
|
|
<description>desc CTEIF5</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CGIF6</name>
|
|
<description>desc CGIF6</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF6</name>
|
|
<description>desc CTCIF6</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF6</name>
|
|
<description>desc CHTIF6</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF6</name>
|
|
<description>desc CTEIF6</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CGIF7</name>
|
|
<description>desc CGIF7</description>
|
|
<msb>24</msb>
|
|
<lsb>24</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTCIF7</name>
|
|
<description>desc CTCIF7</description>
|
|
<msb>25</msb>
|
|
<lsb>25</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHTIF7</name>
|
|
<description>desc CHTIF7</description>
|
|
<msb>26</msb>
|
|
<lsb>26</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTEIF7</name>
|
|
<description>desc CTEIF7</description>
|
|
<msb>27</msb>
|
|
<lsb>27</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>desc EN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>desc TCIE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>desc HTIE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>desc TEIE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>desc CIRC</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>desc PINC</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>desc MINC</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>desc PSIZE</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>desc MSIZE</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>desc PL</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>desc MEM2MEM</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR1</name>
|
|
<description>desc CNDTR1</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>desc NDT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR1</name>
|
|
<description>desc CPAR1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>desc PA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR1</name>
|
|
<description>desc CMAR1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>desc MA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>desc EN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>desc TCIE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>desc HTIE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>desc TEIE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>desc CIRC</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>desc PINC</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>desc MINC</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>desc PSIZE</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>desc MSIZE</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>desc PL</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>desc MEM2MEM</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR2</name>
|
|
<description>desc CNDTR2</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>desc NDT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR2</name>
|
|
<description>desc CPAR2</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>desc PA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR2</name>
|
|
<description>desc CMAR2</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>desc MA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR3</name>
|
|
<description>desc CCR3</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>desc EN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>desc TCIE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>desc HTIE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>desc TEIE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>desc CIRC</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>desc PINC</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>desc MINC</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>desc PSIZE</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>desc MSIZE</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>desc PL</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>desc MEM2MEM</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR3</name>
|
|
<description>desc CNDTR3</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>desc NDT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR3</name>
|
|
<description>desc CPAR3</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>desc PA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR3</name>
|
|
<description>desc CMAR3</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>desc MA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR4</name>
|
|
<description>desc CCR4</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>desc EN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>desc TCIE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>desc HTIE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>desc TEIE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>desc CIRC</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>desc PINC</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>desc MINC</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>desc PSIZE</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>desc MSIZE</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>desc PL</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>desc MEM2MEM</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR4</name>
|
|
<description>desc CNDTR4</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>desc NDT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR4</name>
|
|
<description>desc CPAR4</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>desc PA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR4</name>
|
|
<description>desc CMAR4</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>desc MA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR5</name>
|
|
<description>desc CCR5</description>
|
|
<addressOffset>0x58</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>desc EN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>desc TCIE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>desc HTIE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>desc TEIE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>desc CIRC</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>desc PINC</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>desc MINC</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>desc PSIZE</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>desc MSIZE</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>desc PL</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>desc MEM2MEM</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR5</name>
|
|
<description>desc CNDTR5</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>desc NDT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR5</name>
|
|
<description>desc CPAR5</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>desc PA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR5</name>
|
|
<description>desc CMAR5</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>desc MA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR6</name>
|
|
<description>desc CCR6</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>desc EN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>desc TCIE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>desc HTIE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>desc TEIE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>desc CIRC</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>desc PINC</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>desc MINC</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>desc PSIZE</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>desc MSIZE</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>desc PL</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>desc MEM2MEM</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR6</name>
|
|
<description>desc CNDTR6</description>
|
|
<addressOffset>0x70</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>desc NDT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR6</name>
|
|
<description>desc CPAR6</description>
|
|
<addressOffset>0x74</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>desc PA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR6</name>
|
|
<description>desc CMAR6</description>
|
|
<addressOffset>0x78</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>desc MA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR7</name>
|
|
<description>desc CCR7</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>desc EN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>desc TCIE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HTIE</name>
|
|
<description>desc HTIE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TEIE</name>
|
|
<description>desc TEIE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CIRC</name>
|
|
<description>desc CIRC</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PINC</name>
|
|
<description>desc PINC</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MINC</name>
|
|
<description>desc MINC</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PSIZE</name>
|
|
<description>desc PSIZE</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSIZE</name>
|
|
<description>desc MSIZE</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PL</name>
|
|
<description>desc PL</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MEM2MEM</name>
|
|
<description>desc MEM2MEM</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNDTR7</name>
|
|
<description>desc CNDTR7</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>NDT</name>
|
|
<description>desc NDT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CPAR7</name>
|
|
<description>desc CPAR7</description>
|
|
<addressOffset>0x88</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA</name>
|
|
<description>desc PA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CMAR7</name>
|
|
<description>desc CMAR7</description>
|
|
<addressOffset>0x8C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MA</name>
|
|
<description>desc MA</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EXTI</name>
|
|
<description>
|
|
External interrupt/event
|
|
controller
|
|
</description>
|
|
<groupName>EXTI</groupName>
|
|
<baseAddress>0x40021800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>PVD</name>
|
|
<description>PVD Interrupt through EXTI Lines 16</description>
|
|
<value>1</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI0_1</name>
|
|
<description>EXTI Line 0 and 1 Interrupt</description>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI2_3</name>
|
|
<description>EXTI Line 2 and 3 Interrupt</description>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI4_15</name>
|
|
<description>EXTI Line 4 to 15 Interrupt</description>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RTSR</name>
|
|
<displayName>RTSR</displayName>
|
|
<description>
|
|
EXTI rising trigger selection
|
|
register
|
|
</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RT20</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT19</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT18</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT17</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT16</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT15</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT14</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT13</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT12</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT11</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT10</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT9</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT8</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT7</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT6</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT5</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT4</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT3</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT2</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT1</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT0</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTSR</name>
|
|
<displayName>FTSR</displayName>
|
|
<description>
|
|
EXTI falling trigger selection
|
|
register
|
|
</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FT20</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT19</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT18</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT17</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT16</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT15</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT14</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT13</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT12</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT11</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT10</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT9</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT8</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT7</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT6</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT5</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT4</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT3</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT2</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT1</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT0</name>
|
|
<description>
|
|
Falling trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWIER</name>
|
|
<displayName>SWIER</displayName>
|
|
<description>
|
|
EXTI software interrupt event
|
|
register
|
|
</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWI20</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI19</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI18</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI17</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI16</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI15</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI14</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI13</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI12</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI11</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI10</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI9</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI8</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI7</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI6</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI5</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI4</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI3</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI2</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI1</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI0</name>
|
|
<description>
|
|
Rising trigger event configuration bit
|
|
of Configurable Event input
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<displayName>PR</displayName>
|
|
<description>
|
|
EXTI pending
|
|
register
|
|
</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PR20</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR19</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR18</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR17</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR16</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR15</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR14</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR13</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR12</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR11</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR10</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR9</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR8</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR7</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR6</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR5</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR4</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR3</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR2</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR1</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR0</name>
|
|
<description>
|
|
configurable event inputs x rising edge
|
|
Pending bit.
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTICR1</name>
|
|
<displayName>EXTICR1</displayName>
|
|
<description>
|
|
EXTI external interrupt selection
|
|
register
|
|
</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI3</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI2</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI1</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI0</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTICR2</name>
|
|
<displayName>EXTICR2</displayName>
|
|
<description>
|
|
EXTI external interrupt selection
|
|
register
|
|
</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI7</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI6</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI5</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI4</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTICR3</name>
|
|
<displayName>EXTICR3</displayName>
|
|
<description>
|
|
EXTI external interrupt selection
|
|
register
|
|
</description>
|
|
<addressOffset>0x68</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI11</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI10</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI9</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI8</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTICR4</name>
|
|
<displayName>EXTICR4</displayName>
|
|
<description>
|
|
EXTI external interrupt selection
|
|
register
|
|
</description>
|
|
<addressOffset>0x6C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI15</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI14</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI13</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI12</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<displayName>IMR</displayName>
|
|
<description>
|
|
EXTI CPU wakeup with interrupt mask
|
|
register
|
|
</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFF80000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IM29</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM20</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM19</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM18</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM17</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM16</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM15</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM14</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM13</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM12</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM11</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM10</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM9</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM8</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM7</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM6</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM5</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM4</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM3</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM2</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM1</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM0</name>
|
|
<description>
|
|
CPU wakeup with interrupt mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR</name>
|
|
<displayName>EMR</displayName>
|
|
<description>
|
|
EXTI CPU wakeup with event mask
|
|
register
|
|
</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EM29</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM20</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM19</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM18</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM17</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM16</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM15</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM14</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM13</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM12</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM11</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM10</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM9</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM8</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM7</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM6</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM5</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM4</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>
|
|
CPU wakeup with event mask on event
|
|
input
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLASH</name>
|
|
<description>desc FLASH</description>
|
|
<groupName>FLASH</groupName>
|
|
<baseAddress>0x40022000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FLASH</name>
|
|
<description>FLASH global Interrupt</description>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ACR</name>
|
|
<description>desc ACR</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x500</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LATENCY</name>
|
|
<description>desc LATENCY</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PRFTEN</name>
|
|
<description>desc PRFTEN</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ICEN</name>
|
|
<description>desc ICEN</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DCEN</name>
|
|
<description>desc DCEN</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYR</name>
|
|
<description>desc KEYR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>desc KEY</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPTKEYR</name>
|
|
<description>desc OPTKEYR</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OPTKEY</name>
|
|
<description>desc OPTKEY</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EOP</name>
|
|
<description>desc EOP</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WRPERR</name>
|
|
<description>desc WRPERR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPTVERR</name>
|
|
<description>desc OPTVERR</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>desc BSY</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<description>desc CR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PG</name>
|
|
<description>desc PG</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>desc PER</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MER</name>
|
|
<description>desc MER</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SER</name>
|
|
<description>desc SER</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPTSTRT</name>
|
|
<description>desc OPTSTRT</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PGSTRT</name>
|
|
<description>desc PGSTRT</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>EOPIE</name>
|
|
<description>desc EOPIE</description>
|
|
<msb>24</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>desc ERRIE</description>
|
|
<msb>25</msb>
|
|
<lsb>25</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OBL_LAUNCH</name>
|
|
<description>desc OBL_LAUNCH</description>
|
|
<msb>27</msb>
|
|
<lsb>27</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPTLOCK</name>
|
|
<description>desc OPTLOCK</description>
|
|
<msb>30</msb>
|
|
<lsb>30</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>desc LOCK</description>
|
|
<msb>31</msb>
|
|
<lsb>31</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPTR</name>
|
|
<description>desc OPTR</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RDP</name>
|
|
<description>desc RDP</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IWDG_SW</name>
|
|
<description>desc IWDG_SW</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>WWDG_SW</name>
|
|
<description>desc WWDG_SW</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NRST_MODE</name>
|
|
<description>desc NRST_MODE</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NBOOT1</name>
|
|
<description>desc nBOOT1</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IWDG_STOP</name>
|
|
<description>desc IWDG_STOP</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDKR</name>
|
|
<description>desc SDKR</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SDK_STRT</name>
|
|
<description>desc SDK_STRT</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BOR_EN</name>
|
|
<description>desc BOR_EN</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SDK_END</name>
|
|
<description>desc SDK_END</description>
|
|
<msb>12</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BOR_LEV</name>
|
|
<description>desc BOR_LEV</description>
|
|
<msb>15</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCK_EN</name>
|
|
<description>desc PCK_EN</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>USB_CLK_EN</name>
|
|
<description>desc USB_CLK_EN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CAN_CLK_EN</name>
|
|
<description>desc CAN_CLK_EN</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIM2_CLK_EN</name>
|
|
<description>desc TIM2_CLK_EN</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIM3_CLK_EN</name>
|
|
<description>desc TIM3_CLK_EN</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIM7_CLK_EN</name>
|
|
<description>desc TIM7_CLK_EN</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>I2C2_CLK_EN</name>
|
|
<description>desc I2C2_CLK_EN</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USART3_CLK_EN</name>
|
|
<description>desc USART3_CLK_EN</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>USART4_CLK_EN</name>
|
|
<description>desc USART4_CLK_EN</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LCD_CLK_EN</name>
|
|
<description>desc LCD_CLK_EN</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIM14_CLK_EN</name>
|
|
<description>desc TIM14_CLK_EN</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIM15_CLK_EN</name>
|
|
<description>desc TIM15_CLK_EN</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TIM17_CLK_EN</name>
|
|
<description>desc TIM17_CLK_EN</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRPR</name>
|
|
<description>desc WRPR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRP</name>
|
|
<description>desc WRP</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STCR</name>
|
|
<description>desc STCR</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00006400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEP_EN</name>
|
|
<description>desc SLEEP_EN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SLEEP_TIME</name>
|
|
<description>desc SLEEP_TIME</description>
|
|
<msb>15</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TS0</name>
|
|
<description>desc TS0</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xB4</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS0</name>
|
|
<description>desc TS0</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TS1</name>
|
|
<description>desc TS1</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x1B0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS1</name>
|
|
<description>desc TS1</description>
|
|
<msb>8</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TS2P</name>
|
|
<description>desc TS2P</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xB4</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS2P</name>
|
|
<description>desc TS2P</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPS3</name>
|
|
<description>desc TPS3</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x6C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TPS3</name>
|
|
<description>desc TPS3</description>
|
|
<msb>10</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TS3</name>
|
|
<description>desc TS3</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xB4</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS3</name>
|
|
<description>desc TS3</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERTPE</name>
|
|
<description>desc PERTPE</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xEA60</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERTPE</name>
|
|
<description>desc PERTPE</description>
|
|
<msb>16</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMERTPE</name>
|
|
<description>desc SMERTPE</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFD20</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMERTPE</name>
|
|
<description>desc SMERTPE</description>
|
|
<msb>16</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRGTPE</name>
|
|
<description>desc PRGTPE</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x8CA0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRGTPE</name>
|
|
<description>desc PRGTPE</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRETPE</name>
|
|
<description>desc PRETPE</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x12C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRETPE</name>
|
|
<description>desc PRETPE</description>
|
|
<msb>13</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRMLSR</name>
|
|
<description>desc TRMLSR</description>
|
|
<addressOffset>0x290</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PMU_TRIM0_ERR</name>
|
|
<description>desc PMU_TRIM0_ERR</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PMU_TRIM1_ERR</name>
|
|
<description>desc PMU_TRIM1_ERR</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HSI_TRIM_ERR</name>
|
|
<description>desc HSI_TRIM_ERR</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LSI_TRIM_ERR</name>
|
|
<description>desc LSI_TRIM_ERR</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_TRIM0_ERR</name>
|
|
<description>desc FLASH_TRIM0_ERR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_TRIM1_ERR</name>
|
|
<description>desc FLASH_TRIM1_ERR</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_TRIM2_ERR</name>
|
|
<description>desc FLASH_TRIM2_ERR</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_TRIM3_ERR</name>
|
|
<description>desc FLASH_TRIM3_ERR</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_TRIM4_ERR</name>
|
|
<description>desc FLASH_TRIM4_ERR</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_TRIM5_ERR</name>
|
|
<description>desc FLASH_TRIM5_ERR</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TS_TRIM_ERR</name>
|
|
<description>desc TS_TRIM_ERR</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHIP_CFG_ERR</name>
|
|
<description>desc CHIP_CFG_ERR</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHKRD0_PASS</name>
|
|
<description>desc CHKRD0_PASS</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHKRD1_PASS</name>
|
|
<description>desc CHKRD1_PASS</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHKRD2_PASS</name>
|
|
<description>desc CHKRD2_PASS</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHKRD3_PASS</name>
|
|
<description>desc CHKRD3_PASS</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRMDR0</name>
|
|
<description>desc TRMDR0</description>
|
|
<addressOffset>0x294</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BIAS_CR</name>
|
|
<description>desc BIAS_CR</description>
|
|
<msb>3</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIM_MR</name>
|
|
<description>desc TRIM_MR</description>
|
|
<msb>8</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIM_VREF</name>
|
|
<description>desc TRIM_VREF</description>
|
|
<msb>13</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIM_POR</name>
|
|
<description>desc TRIM_POR</description>
|
|
<msb>19</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRIM_BG</name>
|
|
<description>desc TRIM_BG</description>
|
|
<msb>27</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRMDR1</name>
|
|
<description>desc TRMDR1</description>
|
|
<addressOffset>0x298</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSI_TRIM</name>
|
|
<description>desc LSI_TRIM</description>
|
|
<msb>8</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HSI_TRIM</name>
|
|
<description>desc HSI_TRIM</description>
|
|
<msb>28</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>HSI_FS</name>
|
|
<description>desc HSI_FS</description>
|
|
<msb>31</msb>
|
|
<lsb>29</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRMDR2</name>
|
|
<description>desc TRMDR2</description>
|
|
<addressOffset>0x29C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_OP</name>
|
|
<description>desc FLASH_OP</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRMDR3</name>
|
|
<description>desc TRMDR3</description>
|
|
<addressOffset>0x2A0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_OP</name>
|
|
<description>desc FLASH_OP</description>
|
|
<msb>31</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRMDR4</name>
|
|
<description>desc TRMDR4</description>
|
|
<addressOffset>0x2A4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_ERASE_VPOS</name>
|
|
<description>desc FLASH_ERASE_VPOS</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_ERASE_VNEG</name>
|
|
<description>desc FLASH_ERASE_VNEG</description>
|
|
<msb>9</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PROG_VPOS</name>
|
|
<description>desc FLASH_PROG_VPOS</description>
|
|
<msb>20</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FLASH_PROG_VNEG</name>
|
|
<description>desc FLASH_PROG_VNEG</description>
|
|
<msb>25</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRMDR5</name>
|
|
<description>desc TRMDR5</description>
|
|
<addressOffset>0x2A8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLASH_SIZE</name>
|
|
<description>desc FLASH_SIZE</description>
|
|
<msb>2</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SRAM_SIZE</name>
|
|
<description>desc SRAM_SIZE</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TS_TRIM</name>
|
|
<description>desc TS_TRIM</description>
|
|
<msb>11</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRMDR6</name>
|
|
<description>desc TRMDR6</description>
|
|
<addressOffset>0x2AC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OPA0_TRIM</name>
|
|
<description>desc OPA0_TRIM</description>
|
|
<msb>3</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA1_TRIM</name>
|
|
<description>desc OPA1_TRIM</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA2_TRIM</name>
|
|
<description>desc OPA2_TRIM</description>
|
|
<msb>11</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA3_TRIM</name>
|
|
<description>desc OPA3_TRIM</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OPA4_TRIM</name>
|
|
<description>desc OPA4_TRIM</description>
|
|
<msb>19</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LCD_TRIM</name>
|
|
<description>desc LCD_TRIM</description>
|
|
<msb>27</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRMDR7</name>
|
|
<description>desc TRMDR7</description>
|
|
<addressOffset>0x2B0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS_DATA_0_TRIM</name>
|
|
<description>desc TS_DATA_0_TRIM</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TS_DATA_1_TRIM</name>
|
|
<description>desc TS_DATA_1_TRIM</description>
|
|
<msb>23</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRMDR8</name>
|
|
<description>desc TRMDR8</description>
|
|
<addressOffset>0x2B4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DAC_0_TRIM</name>
|
|
<description>desc DAC_0_TRIM</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DAC_1_TRIM</name>
|
|
<description>desc DAC_1_TRIM</description>
|
|
<msb>23</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>VREF_BUF_TRIM</name>
|
|
<description>desc VREF_BUF_TRIM</description>
|
|
<msb>28</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOA</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x50000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MODER</name>
|
|
<displayName>MODER</displayName>
|
|
<description>GPIO port mode register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xEBFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODE15</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE14</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE13</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE12</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE11</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE10</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE8</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE7</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE6</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE5</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE4</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE0</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTYPER</name>
|
|
<displayName>OTYPER</displayName>
|
|
<description>GPIO port output type register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OT15</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT14</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT13</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT12</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT11</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT10</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT9</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT8</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT7</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT6</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT5</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT4</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT3</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT2</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT1</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT0</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSPEEDR</name>
|
|
<displayName>OSPEEDR</displayName>
|
|
<description>
|
|
GPIO port output speed
|
|
register
|
|
</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0C000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSPEED15</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED14</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED13</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED12</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED11</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED10</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED9</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED8</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED7</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED6</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED5</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED4</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED3</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED2</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED1</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED0</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUPDR</name>
|
|
<displayName>PUPDR</displayName>
|
|
<description>
|
|
GPIO port pull-up/pull-down
|
|
register
|
|
</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x24000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUPD15</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD14</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD13</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD12</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD11</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD10</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD9</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD8</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD7</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD6</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD5</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD4</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD3</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD2</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD1</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD0</name>
|
|
<description>
|
|
Port x configuration bits (y=0-15)
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<displayName>IDR</displayName>
|
|
<description>GPIO port input data register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID15</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID14</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID13</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID12</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID11</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID10</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID9</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID8</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID7</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID6</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID5</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID4</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID3</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID2</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>
|
|
Port input data (y=0-15)
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODR</name>
|
|
<displayName>ODR</displayName>
|
|
<description>GPIO port output data register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OD15</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD14</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD13</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD12</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD11</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD10</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD9</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD8</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD7</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD6</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD5</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD4</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD3</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD2</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD1</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD0</name>
|
|
<description>
|
|
Port output data (y=0-15)
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BSRR</name>
|
|
<displayName>BSRR</displayName>
|
|
<description>
|
|
GPIO port bit set/reset
|
|
register
|
|
</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>
|
|
Port x reset bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS15</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS14</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS13</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS12</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS11</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS10</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS9</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS8</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS7</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS6</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS5</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS4</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS3</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS2</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS1</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS0</name>
|
|
<description>
|
|
Port x set bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCKR</name>
|
|
<displayName>LCKR</displayName>
|
|
<description>
|
|
GPIO port configuration lock
|
|
register
|
|
</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCKK</name>
|
|
<description>
|
|
Port x lock (LCKK)
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK15</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK14</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK13</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK12</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK11</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK10</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK9</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK8</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK7</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK6</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK5</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK4</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK3</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK2</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK1</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK0</name>
|
|
<description>
|
|
Port x lock bit y (y=0-15)
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRL</name>
|
|
<displayName>AFRL</displayName>
|
|
<description>
|
|
GPIO alternate function low
|
|
register
|
|
</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFSEL7</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=0-7)
|
|
</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL6</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=0-7)
|
|
</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL5</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=0-7)
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL4</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=0-7)
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL3</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=0-7)
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL2</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=0-7)
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL1</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=0-7)
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL0</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=0-7)
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRH</name>
|
|
<displayName>AFRH</displayName>
|
|
<description>
|
|
GPIO alternate function high
|
|
register
|
|
</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFSEL15</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=8-15)
|
|
</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL14</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=8-15)
|
|
</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL13</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=8-15)
|
|
</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL12</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=8-15)
|
|
</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL11</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=8-15)
|
|
</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL10</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=8-15)
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL9</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=8-15)
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL8</name>
|
|
<description>
|
|
Alternate function selection for port x bit y (y=8-15)
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<displayName>BRR</displayName>
|
|
<description>port bit reset register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOB</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x50000400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOC</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x50000800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOA">
|
|
<name>GPIOF</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x50001400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C1</name>
|
|
<description>Inter integrated circuit</description>
|
|
<groupName>I2C</groupName>
|
|
<baseAddress>0x40005400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C1</name>
|
|
<description>I2C1 global Interrupt</description>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>desc PE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMBUS</name>
|
|
<description>desc SMBUS</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMBTYPE</name>
|
|
<description>desc SMBTYPE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENARP</name>
|
|
<description>desc ENARP</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENPEC</name>
|
|
<description>desc ENPEC</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ENGC</name>
|
|
<description>desc ENGC</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NOSTRETCH</name>
|
|
<description>desc NOSTRETCH</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>desc START</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>desc STOP</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>desc ACK</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>POS</name>
|
|
<description>desc POS</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>desc PEC</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALERT</name>
|
|
<description>desc ALERT</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>desc SWRST</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FREQ</name>
|
|
<description>desc FREQ</description>
|
|
<msb>5</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ITERREN</name>
|
|
<description>desc ITERREN</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ITEVTEN</name>
|
|
<description>desc ITEVTEN</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ITBUFEN</name>
|
|
<description>desc ITBUFEN</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>desc DMAEN</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LAST</name>
|
|
<description>desc LAST</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OAR1</name>
|
|
<description>desc OAR1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADD0</name>
|
|
<description>desc ADD0</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADD1_7</name>
|
|
<description>desc ADD1_7</description>
|
|
<msb>7</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADD8_9</name>
|
|
<description>desc ADD8_9</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDMODE</name>
|
|
<description>desc ADDMODE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OAR2</name>
|
|
<description>desc OAR2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ENDUAL</name>
|
|
<description>desc ENDUAL</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ADD2</name>
|
|
<description>desc ADD2</description>
|
|
<msb>7</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>desc DR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>desc DR</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR1</name>
|
|
<description>desc SR1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SB</name>
|
|
<description>desc SB</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>desc ADDR</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BTF</name>
|
|
<description>desc BTF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADD10</name>
|
|
<description>desc ADD10</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOPF</name>
|
|
<description>desc STOPF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>desc RXNE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>desc TXE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BERR</name>
|
|
<description>desc BERR</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARLO</name>
|
|
<description>desc ARLO</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AF</name>
|
|
<description>desc AF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>desc OVR</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PECERR</name>
|
|
<description>desc PECERR</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIMEOUT</name>
|
|
<description>desc TIMEOUT</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SMBALERT</name>
|
|
<description>desc SMBALERT</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR2</name>
|
|
<description>desc SR2</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MSL</name>
|
|
<description>desc MSL</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>desc BUSY</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TRA</name>
|
|
<description>desc TRA</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>GENCALL</name>
|
|
<description>desc GENCALL</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SMBDEFAULT</name>
|
|
<description>desc SMBDEFAULT</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SMBHOST</name>
|
|
<description>desc SMBHOST</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>DUALF</name>
|
|
<description>desc DUALF</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>desc PEC</description>
|
|
<msb>15</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<description>desc CCR</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CCR</name>
|
|
<description>desc CCR</description>
|
|
<msb>11</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DUTY</name>
|
|
<description>desc DUTY</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FS</name>
|
|
<description>desc FS</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRISE</name>
|
|
<description>desc TRISE</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>TRISE</name>
|
|
<description>desc TRISE</description>
|
|
<msb>5</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="I2C1">
|
|
<name>I2C2</name>
|
|
<description>desc I2C</description>
|
|
<groupName>I2C</groupName>
|
|
<baseAddress>0x40005800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C2</name>
|
|
<description>I2C2 Event Interrupt</description>
|
|
<value>24</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IWDG</name>
|
|
<description>Independent watchdog</description>
|
|
<groupName>IWDG</groupName>
|
|
<baseAddress>0x40003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>KR</name>
|
|
<displayName>KR</displayName>
|
|
<description>Key register (IWDG_KR)</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Key value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<displayName>PR</displayName>
|
|
<description>Prescaler register (IWDG_PR)</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Prescaler divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RLR</name>
|
|
<displayName>RLR</displayName>
|
|
<description>Reload register (IWDG_RLR)</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000FFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RL</name>
|
|
<description>
|
|
Watchdog counter reload
|
|
value
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>Status register (IWDG_SR)</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RVU</name>
|
|
<description>
|
|
Watchdog counter reload value
|
|
update
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVU</name>
|
|
<description>
|
|
Watchdog prescaler value
|
|
update
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LCD</name>
|
|
<description>LCD CONTROLLER</description>
|
|
<groupName>LCD</groupName>
|
|
<baseAddress>0x40002400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>LCD</name>
|
|
<description>LCD global Interrupt</description>
|
|
<value>8</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<displayName>CR0</displayName>
|
|
<description>Control register </description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN</name>
|
|
<description>EN</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCDCLK</name>
|
|
<description>LCDCLK</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAS</name>
|
|
<description>BIAS</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUTY</name>
|
|
<description>DUTY</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BSEL</name>
|
|
<description>BSEL</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CONTRAST</name>
|
|
<description>CONTRAST</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>CR1</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BLINKCNT</name>
|
|
<description>BLINKCNT</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BLINKEN</name>
|
|
<description>BLINKEN</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE</name>
|
|
<description>MODE</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IE</name>
|
|
<description>IE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INTF</name>
|
|
<description>INTF</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTCLR</name>
|
|
<displayName>INTCLR</displayName>
|
|
<description>INTCLR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>INTF_CLR</name>
|
|
<description>INTF_CLR</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POEN0</name>
|
|
<displayName>POEN0</displayName>
|
|
<description>POEN0</description>
|
|
<addressOffset>0x0C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>S0</name>
|
|
<description>S0</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S1</name>
|
|
<description>S1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S2</name>
|
|
<description>S2</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S3</name>
|
|
<description>S3</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S4</name>
|
|
<description>S4</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S5</name>
|
|
<description>S5</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S6</name>
|
|
<description>S6</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S7</name>
|
|
<description>S7</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S8</name>
|
|
<description>S8</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S9</name>
|
|
<description>S9</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S10</name>
|
|
<description>S10</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S11</name>
|
|
<description>S11</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S12</name>
|
|
<description>S12</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S13</name>
|
|
<description>S13</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S14</name>
|
|
<description>S14</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S15</name>
|
|
<description>S15</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S16</name>
|
|
<description>S16</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S17</name>
|
|
<description>S17</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S18</name>
|
|
<description>S18</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S19</name>
|
|
<description>S19</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S20</name>
|
|
<description>S20</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S21</name>
|
|
<description>S21</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S22</name>
|
|
<description>S22</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S23</name>
|
|
<description>S23</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S24</name>
|
|
<description>S24</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S25</name>
|
|
<description>S25</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S26</name>
|
|
<description>S26</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S27</name>
|
|
<description>S27</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S28</name>
|
|
<description>S28</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S29</name>
|
|
<description>S29</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S30</name>
|
|
<description>S30</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S31</name>
|
|
<description>S31</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>POEN1</name>
|
|
<displayName>POEN1</displayName>
|
|
<description>POEN1</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>S32</name>
|
|
<description>S32</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S33</name>
|
|
<description>S33</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S34</name>
|
|
<description>S34</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S35</name>
|
|
<description>S35</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S36</name>
|
|
<description>S36</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S37</name>
|
|
<description>S37</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S38</name>
|
|
<description>S38</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>S39</name>
|
|
<description>S39</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C0</name>
|
|
<description>C0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C1</name>
|
|
<description>C1</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C2</name>
|
|
<description>C2</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>C3</name>
|
|
<description>C3</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MUX</name>
|
|
<description>MUX</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM0</name>
|
|
<displayName>RAM0</displayName>
|
|
<description>des RAM0</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM1</name>
|
|
<displayName>RAM1</displayName>
|
|
<description>des RAM1</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM2</name>
|
|
<displayName>RAM2</displayName>
|
|
<description>des RAM2</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM3</name>
|
|
<displayName>RAM3</displayName>
|
|
<description>des RAM3</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM4</name>
|
|
<displayName>RAM4</displayName>
|
|
<description>des RAM4</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM5</name>
|
|
<displayName>RAM5</displayName>
|
|
<description>des RAM5</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM6</name>
|
|
<displayName>RAM6</displayName>
|
|
<description>des RAM6</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM7</name>
|
|
<displayName>RAM7</displayName>
|
|
<description>des RAM7</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM8</name>
|
|
<displayName>RAM8</displayName>
|
|
<description>des RAM8</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM9</name>
|
|
<displayName>RAM9</displayName>
|
|
<description>des RAM9</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM10</name>
|
|
<displayName>RAM10</displayName>
|
|
<description>des RAM10</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM11</name>
|
|
<displayName>RAM11</displayName>
|
|
<description>des RAM11</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM12</name>
|
|
<displayName>RAM12</displayName>
|
|
<description>des RAM12</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM13</name>
|
|
<displayName>RAM13</displayName>
|
|
<description>des RAM13</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM14</name>
|
|
<displayName>RAM14</displayName>
|
|
<description>des RAM14</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RAM15</name>
|
|
<displayName>RAM15</displayName>
|
|
<description>des RAM15</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>D</name>
|
|
<description>des D</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPTIM1</name>
|
|
<description>Low power timer</description>
|
|
<groupName>LPTIM1</groupName>
|
|
<baseAddress>0x40007C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM6_LPTIM1_DAC</name>
|
|
<description>TIM6, LPTIM1, DAC global Interrupts</description>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>Interrupt and Status Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARRM</name>
|
|
<description>Autoreload match</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARROK</name>
|
|
<description>Autoreload match update OK</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>Interrupt Clear Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARRMCF</name>
|
|
<description>
|
|
Autoreload match Clear
|
|
Flag
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARROKCF</name>
|
|
<description>
|
|
Autoreload match update OK
|
|
Clear Flag
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<displayName>IER</displayName>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARRMIE</name>
|
|
<description>
|
|
Autoreload matchInterrupt
|
|
Enable
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARROKIE</name>
|
|
<description>
|
|
Autoreload match update
|
|
OK Interrupt Enable
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR</name>
|
|
<displayName>CFGR</displayName>
|
|
<description>Configuration Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRELOAD</name>
|
|
<description>Registers update mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Clock prescaler</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RSTARE</name>
|
|
<description>Reset after read enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNTSTRT</name>
|
|
<description>CNTSTRT</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SNGSTRT</name>
|
|
<description>LPTIM start in single mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>LPTIM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<displayName>ARR</displayName>
|
|
<description>Autoreload Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>Auto reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>Counter Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>OPA</name>
|
|
<description>des OPA</description>
|
|
<groupName>OPA</groupName>
|
|
<baseAddress>0x40010300</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR0</name>
|
|
<displayName>CR0</displayName>
|
|
<description>CR0 register</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OP1OEN1</name>
|
|
<description>OP1OEN1</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OP2OEN1</name>
|
|
<description>OP2OEN1</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OP3OEN1</name>
|
|
<description>OP3OEN1</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>CR1 register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN1</name>
|
|
<description>EN1</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN2</name>
|
|
<description>EN2</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN3</name>
|
|
<description>EN3</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PWR</name>
|
|
<description>Power control</description>
|
|
<groupName>PWR</groupName>
|
|
<baseAddress>0x40007000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>Power control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00030000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HSION_CTRL</name>
|
|
<description>HSI open time control</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAM_RETV</name>
|
|
<description>SRAM retention voltage control</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPR</name>
|
|
<description>Low-power run</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLS_SLPTIME</name>
|
|
<description>Flash wait time after wakeup from the stop mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VOS</name>
|
|
<description>
|
|
Voltage scaling range
|
|
selection
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBP</name>
|
|
<description>
|
|
Disable backup domain write
|
|
protection
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAS_CR_SEL</name>
|
|
<description>MR Bias current selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAS_CR</name>
|
|
<description>MR Bias current</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>Power control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000500</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLT_TIME</name>
|
|
<description>Digital filter time configuration</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLTEN</name>
|
|
<description>Digital filter enable </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVDT</name>
|
|
<description>
|
|
Power voltage detector threshold
|
|
selection
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRCSEL</name>
|
|
<description>
|
|
Power voltage detector volatage
|
|
selection
|
|
</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVDE</name>
|
|
<description>
|
|
Power voltage detector
|
|
enable
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>Power status register </description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PVDO</name>
|
|
<description>PVD output</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RCC</name>
|
|
<description>Reset and clock control</description>
|
|
<groupName>RCC</groupName>
|
|
<baseAddress>0x40021000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RCC_CTC</name>
|
|
<description>RCC and CTC global Interrupts</description>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Clock control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLLRDY</name>
|
|
<description>PLL clock ready flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLON</name>
|
|
<description>PLL enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADC_DIV</name>
|
|
<description>ADC Frequency Division</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSSON</name>
|
|
<description>
|
|
Clock security system
|
|
enable
|
|
</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSEBYP</name>
|
|
<description>
|
|
HSE crystal oscillator
|
|
bypass
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSERDY</name>
|
|
<description>HSE clock ready flag</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSEON</name>
|
|
<description>HSE clock enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIDIV</name>
|
|
<description>
|
|
HSI16 clock division
|
|
factor
|
|
</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDY</name>
|
|
<description>HSI16 clock ready flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSION</name>
|
|
<description>HSI16 clock enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSCR</name>
|
|
<displayName>ICSCR</displayName>
|
|
<description>
|
|
Internal clock sources calibration
|
|
register
|
|
</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x10000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSI_TRIM</name>
|
|
<description>LSI clock trimming</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSI_FS</name>
|
|
<description>HSI frequency selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSI_TRIM</name>
|
|
<description>HSI clock trimming</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR</name>
|
|
<displayName>CFGR</displayName>
|
|
<description>Clock configuration register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCOPRE</name>
|
|
<description>
|
|
Microcontroller clock output
|
|
prescaler
|
|
</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MCOSEL</name>
|
|
<description>
|
|
Microcontroller clock
|
|
output
|
|
</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PPRE</name>
|
|
<description>APB prescaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPRE</name>
|
|
<description>AHB prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWS</name>
|
|
<description>System clock switch status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>System clock switch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PLLCFGR</name>
|
|
<displayName>PLLCFGR</displayName>
|
|
<description>PLL configuration register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLLSRC</name>
|
|
<description>PLL clock source selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PLLMUL</name>
|
|
<description>PLLMUL</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECSCR</name>
|
|
<displayName>ECSCR</displayName>
|
|
<description>External clock source control register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HSE_DRV</name>
|
|
<description>HSE_DRV</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSE_STARTUP</name>
|
|
<description>HSE_STARTUP</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSE_DRIVER</name>
|
|
<description>LSE clock driver selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSE_STARTUP</name>
|
|
<description>LSE_STARTUP</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIER</name>
|
|
<displayName>CIER</displayName>
|
|
<description>
|
|
Clock interrupt enable
|
|
register
|
|
</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PLLRDYIE</name>
|
|
<description>PLL ready interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSERDYIE</name>
|
|
<description>HSE ready interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDYIE</name>
|
|
<description>HSI ready interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDYIE</name>
|
|
<description>LSE ready interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSIRDYIE</name>
|
|
<description>LSI ready interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIFR</name>
|
|
<displayName>CIFR</displayName>
|
|
<description>Clock interrupt flag register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSECSSF</name>
|
|
<description>LSE clock secure system interrupt flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSSF</name>
|
|
<description>HSE clock secure system interrupt flag</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLRDYF</name>
|
|
<description>PLL ready interrupt flag</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSERDYF</name>
|
|
<description>HSE ready interrupt flag</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDYF</name>
|
|
<description>HSI ready interrupt flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDYF</name>
|
|
<description>LSE ready interrupt flag</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSIRDYF</name>
|
|
<description>LSI ready interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CICR</name>
|
|
<displayName>CICR</displayName>
|
|
<description>Clock interrupt clear register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSECSSC</name>
|
|
<description>LSE clock secure system interrupt flag clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CSSC</name>
|
|
<description>clock secure system interrupt flag clear</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PLLRDYC</name>
|
|
<description>PLL ready interrupt clear</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSERDYC</name>
|
|
<description>HSE ready interrupt clear</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDYC</name>
|
|
<description>HSI ready interrupt clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDYC</name>
|
|
<description>LSE ready interrupt clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSIRDYC</name>
|
|
<description>LSI ready interrupt clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOPRSTR</name>
|
|
<displayName>IOPRSTR</displayName>
|
|
<description>GPIO reset register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GPIOFRST</name>
|
|
<description>I/O port F reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOCRST</name>
|
|
<description>I/O port F reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOBRST</name>
|
|
<description>I/O port B reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOARST</name>
|
|
<description>I/O port A reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBRSTR</name>
|
|
<displayName>AHBRSTR</displayName>
|
|
<description>AHB peripheral reset register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIVRST</name>
|
|
<description>DIV reset</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCRST</name>
|
|
<description>CRC reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMARST</name>
|
|
<description>DMA reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBRSTR1</name>
|
|
<displayName>APBRSTR1</displayName>
|
|
<description>
|
|
APB peripheral reset register
|
|
1
|
|
</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPTIMRST</name>
|
|
<description>Low Power Timer reset</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPARST</name>
|
|
<description>OPARST</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACRST</name>
|
|
<description>DACRST</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWRRST</name>
|
|
<description>Power interface reset</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCRST</name>
|
|
<description>CTCRST</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CANRST</name>
|
|
<description>CANRST</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBRST</name>
|
|
<description>USB reset</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2RST</name>
|
|
<description>I2C2 reset</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1RST</name>
|
|
<description>I2C1 reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART4RST</name>
|
|
<description>USART4 reset</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART3RST</name>
|
|
<description>USART3 reset</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART2RST</name>
|
|
<description>USART2 reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI2RST</name>
|
|
<description>SPI2 reset</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWDGRST</name>
|
|
<description>WWDG reset</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCAPBRST</name>
|
|
<description>RTCAPB reset</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM7RST</name>
|
|
<description>TIM7 timer reset</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM6RST</name>
|
|
<description>TIM6 timer reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM3RST</name>
|
|
<description>TIM3 timer reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM2RST</name>
|
|
<description>TIM2 timer reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBRSTR2</name>
|
|
<displayName>APBRSTR2</displayName>
|
|
<description>
|
|
APB peripheral reset register
|
|
2
|
|
</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCFGRST</name>
|
|
<description>SYSCFG reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADCRST</name>
|
|
<description>ADC reset</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBGRST</name>
|
|
<description>DBG reset</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM1RST</name>
|
|
<description>TIM1 reset</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI1RST</name>
|
|
<description>SPI1 reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1RST</name>
|
|
<description>USART1 reset</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM14RST</name>
|
|
<description>TIM14 reset</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM15RST</name>
|
|
<description>TIM15 reset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM16RST</name>
|
|
<description>TIM16 reset</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM17RST</name>
|
|
<description>TIM17 reset</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP1RST</name>
|
|
<description>COMP1 reset</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP2RST</name>
|
|
<description>COMP2 reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP3RST</name>
|
|
<description>COMP3 reset</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCDRST</name>
|
|
<description>LCD reset</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOPENR</name>
|
|
<displayName>IOPENR</displayName>
|
|
<description>GPIO clock enable register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GPIOFEN</name>
|
|
<description>I/O port F clock enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOCEN</name>
|
|
<description>I/O port C clock enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOBEN</name>
|
|
<description>I/O port B clock enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOAEN</name>
|
|
<description>I/O port A clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBENR</name>
|
|
<displayName>AHBENR</displayName>
|
|
<description>
|
|
AHB peripheral clock enable
|
|
register
|
|
</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIVEN</name>
|
|
<description>DIVEN</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>CRC clock enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAMEN</name>
|
|
<description>
|
|
SRAM memory interface clock
|
|
enable
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLASHEN</name>
|
|
<description>
|
|
Flash memory interface clock
|
|
enable
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBENR1</name>
|
|
<displayName>APBENR1</displayName>
|
|
<description>
|
|
APB peripheral clock enable register
|
|
1
|
|
</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPTIMEN</name>
|
|
<description>LPTIM clock enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
|
|
<field>
|
|
<name>OPAEN</name>
|
|
<description>OPA clock enable</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DACEN</name>
|
|
<description>DAC clock enable</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWREN</name>
|
|
<description>
|
|
Power interface clock
|
|
enable
|
|
</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTCEN</name>
|
|
<description>CTC clock enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CANEN</name>
|
|
<description>CAN clock enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USBEN</name>
|
|
<description>USB clock enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C2EN</name>
|
|
<description>I2C2 clock enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C1EN</name>
|
|
<description>I2C1 clock enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART4EN</name>
|
|
<description>USART4 clock enable</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART3EN</name>
|
|
<description>USART3 clock enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART2EN</name>
|
|
<description>USART2 clock enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI2EN</name>
|
|
<description>SPI2 clock enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWDGEN</name>
|
|
<description>WWDG clock enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCAPBEN</name>
|
|
<description>RTC APB clock enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM7EN</name>
|
|
<description>TIM7 timer clock enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM6EN</name>
|
|
<description>TIM6 timer clock enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM3EN</name>
|
|
<description>TIM3 timer clock enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM2EN</name>
|
|
<description>TIM2 timer clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBENR2</name>
|
|
<displayName>APBENR2</displayName>
|
|
<description>
|
|
APB peripheral clock enable register
|
|
2
|
|
</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SYSCFGEN</name>
|
|
<description>
|
|
SYSCFG, COMP and VREFBUF clock
|
|
enable
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADCEN</name>
|
|
<description>ADCEN clock enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>DBG clock enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM1EN</name>
|
|
<description>TIM1 clock enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI1EN</name>
|
|
<description>SPI1 clock enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1EN</name>
|
|
<description>USART1 clock enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM14EN</name>
|
|
<description>TIM14 clock enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM15EN</name>
|
|
<description>TIM15 clock enable</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM16EN</name>
|
|
<description>TIM16 clock enable</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM17EN</name>
|
|
<description>TIM17 clock enable</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP1EN</name>
|
|
<description>COMP1 clock enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP2EN</name>
|
|
<description>COMP2 clock enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP3EN</name>
|
|
<description>COMP3 clock enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCDEN</name>
|
|
<description>LCD clock enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCIPR</name>
|
|
<displayName>CCIPR</displayName>
|
|
<description>
|
|
Peripherals independent clock configuration
|
|
register
|
|
</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPTIM1SEL</name>
|
|
<description>
|
|
LPTIM1 clock source
|
|
selection
|
|
</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP3SEL</name>
|
|
<description>
|
|
COMP3 clock source
|
|
selection
|
|
</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP2SEL</name>
|
|
<description>
|
|
COMP2 clock source
|
|
selection
|
|
</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COMP1SEL</name>
|
|
<description>
|
|
COMP1 clock source
|
|
selection
|
|
</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVDSEL</name>
|
|
<description>
|
|
PVD detect clock source
|
|
selection
|
|
</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CANSEL</name>
|
|
<description>
|
|
CAN detect clock source
|
|
selection
|
|
</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDCR</name>
|
|
<displayName>BDCR</displayName>
|
|
<description>RTC domain control register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSCOSEL</name>
|
|
<description>
|
|
Low-speed clock output
|
|
selection
|
|
</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSCOEN</name>
|
|
<description>
|
|
Low-speed clock output (LSCO)
|
|
enable
|
|
</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BDRST</name>
|
|
<description>RTC domain software reset</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCEN</name>
|
|
<description>RTC clock source enable</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTCSEL</name>
|
|
<description>RTC clock source selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSECSSD</name>
|
|
<description>LSE CSS detect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSECSSON</name>
|
|
<description>LSE CSS enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSEBYP</name>
|
|
<description>LSE oscillator bypass</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDY</name>
|
|
<description>LSE oscillator ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSEON</name>
|
|
<description>LSE oscillator enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR</name>
|
|
<displayName>CSR</displayName>
|
|
<description>Control/status register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WWDGRSTF</name>
|
|
<description>Window watchdog reset flag</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IWDGRSTF</name>
|
|
<description>
|
|
Independent window watchdog reset
|
|
flag
|
|
</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SFTRSTF</name>
|
|
<description>Software reset flag</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWRRSTF</name>
|
|
<description>BOR or POR/PDR flag</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINRSTF</name>
|
|
<description>Pin reset flag</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OBLRSTF</name>
|
|
<description>
|
|
Option byte loader reset
|
|
flag
|
|
</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RMVF</name>
|
|
<description>Remove reset flags</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRST_FLTDIS</name>
|
|
<description>NRST_FLTDIS oscillator ready</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSIRDY</name>
|
|
<description>LSI oscillator ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSION</name>
|
|
<description>LSI oscillator enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RTC</name>
|
|
<description>desc RTC</description>
|
|
<groupName>RTC</groupName>
|
|
<baseAddress>0x40002800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RTC</name>
|
|
<description>RTC Interrupt through EXTI Lines 19</description>
|
|
<value>2</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CRH</name>
|
|
<description>desc CRH</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SECIE</name>
|
|
<description>desc SECIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRIE</name>
|
|
<description>desc ALRIE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OWIE</name>
|
|
<description>desc OWIE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRL</name>
|
|
<description>desc CRL</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x20</resetValue>
|
|
|
|
<fields>
|
|
<field>
|
|
<name>SECF</name>
|
|
<description>desc SECF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ALRF</name>
|
|
<description>desc ALRF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OWF</name>
|
|
<description>desc OWF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RSF</name>
|
|
<description>desc RSF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CNF</name>
|
|
<description>desc CNF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTOFF</name>
|
|
<description>desc RTOFF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRLH</name>
|
|
<description>desc PRLH</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRL</name>
|
|
<description>desc PRL</description>
|
|
<msb>3</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRLL</name>
|
|
<description>desc PRLL</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x8000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRL</name>
|
|
<description>desc PRL</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIVH</name>
|
|
<description>desc DIVH</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>desc DIV</description>
|
|
<msb>3</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIVL</name>
|
|
<description>desc DIVL</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x8000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV</name>
|
|
<description>desc DIV</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTH</name>
|
|
<description>desc CNTH</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RTC_CNT</name>
|
|
<description>desc RTC_CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNTL</name>
|
|
<description>desc CNTL</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RTC_CNT</name>
|
|
<description>desc RTC_CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALRH</name>
|
|
<description>desc ALRH</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RTC_ALR</name>
|
|
<description>desc RTC_ALR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ALRL</name>
|
|
<description>desc ALRL</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RTC_ALR</name>
|
|
<description>desc RTC_ALR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BKP_RTCCR</name>
|
|
<description>desc BKP_RTCCR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CAL</name>
|
|
<description>desc CAL</description>
|
|
<msb>6</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CCO</name>
|
|
<description>desc CCO</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASOE</name>
|
|
<description>desc ASOE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ASOS</name>
|
|
<description>desc ASOS</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI1</name>
|
|
<description>Serial peripheral interface</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40013000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI1</name>
|
|
<description>SPI1 global Interrupt</description>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>desc CPHA</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>desc CPOL</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>desc MSTR</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BR</name>
|
|
<description>desc BR</description>
|
|
<msb>5</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SPE</name>
|
|
<description>desc SPE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSBFIRST</name>
|
|
<description>desc LSBFIRST</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSI</name>
|
|
<description>desc SSI</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>desc SSM</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXONLY</name>
|
|
<description>desc RXONLY</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DDF</name>
|
|
<description>desc DDF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCNEXT</name>
|
|
<description>desc CRCNEXT</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>desc CRCEN</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIDIOE</name>
|
|
<description>desc BIDIOE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIDIMODE</name>
|
|
<description>desc BIDIMODE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXDMAEN</name>
|
|
<description>desc RXDMAEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAEN</name>
|
|
<description>desc TXDMAEN</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSOE</name>
|
|
<description>desc SSOE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLRTXFIFO</name>
|
|
<description>desc CLRTXFIFO</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>desc ERRIE</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXNEIE</name>
|
|
<description>desc RXNEIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEIE</name>
|
|
<description>desc TXEIE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRXTH</name>
|
|
<description>desc FRXTH</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LDMA_RX</name>
|
|
<description>desc LDMA_RX</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LDMA_TX</name>
|
|
<description>desc LDMA_TX</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>desc RXNE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>desc TXE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHSIDE</name>
|
|
<description>desc CHSIDE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UDR</name>
|
|
<description>desc UDR</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>desc CRCERR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>desc MODF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>desc OVR</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>desc BSY</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRLVL</name>
|
|
<description>desc FRLVL</description>
|
|
<msb>10</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FTLVL</name>
|
|
<description>desc FTLVL</description>
|
|
<msb>12</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>desc DR</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>desc DR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCPR</name>
|
|
<description>desc CRCPR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCPOLY</name>
|
|
<description>desc CRCPOLY</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCRCR</name>
|
|
<description>desc RXCRCR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCRC</name>
|
|
<description>desc RXCRC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCRCR</name>
|
|
<description>desc TXCRCR</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCRC</name>
|
|
<description>desc TXCRC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SCFGR</name>
|
|
<description>desc I2SCFGR</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHLEN</name>
|
|
<description>desc CHLEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATLEN</name>
|
|
<description>desc DATLEN</description>
|
|
<msb>2</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKPOL</name>
|
|
<description>desc CKPOL</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SSTD</name>
|
|
<description>desc I2SSTD</description>
|
|
<msb>5</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCMSYNC</name>
|
|
<description>desc PCMSYNC</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SCFG</name>
|
|
<description>desc I2SCFG</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SE</name>
|
|
<description>desc I2SE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SMOD</name>
|
|
<description>desc I2SMOD</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SPR</name>
|
|
<description>desc I2SPR</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>I2SDIV</name>
|
|
<description>desc I2SDIV</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODD</name>
|
|
<description>desc ODD</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MCKOE</name>
|
|
<description>desc MCKOE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="SPI1">
|
|
<name>SPI2</name>
|
|
<baseAddress>0x40003800</baseAddress>
|
|
<interrupt>
|
|
<name>SPI2</name>
|
|
<description>SPI2 global Interrupt</description>
|
|
<value>26</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SYSCFG</name>
|
|
<description>desc SYSCFG</description>
|
|
<groupName>SYSCFG</groupName>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x200</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CFGR1</name>
|
|
<description>desc CFGR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFF0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MEM_MODE</name>
|
|
<description>desc MEM_MODE</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIM1_IC1_SRC</name>
|
|
<description>desc TIM1_IC1_SRC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIM2_IC4_SRC</name>
|
|
<description>desc TIM2_IC4_SRC</description>
|
|
<msb>5</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIM3_IC1_SRC</name>
|
|
<description>desc TIM3_IC1_SRC</description>
|
|
<msb>7</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETR_SRC_TIM1</name>
|
|
<description>desc ETR_SRC_TIM1</description>
|
|
<msb>10</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETR_SRC_TIM2</name>
|
|
<description>desc ETR_SRC_TIM2</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETR_SRC_TIM3</name>
|
|
<description>desc ETR_SRC_TIM3</description>
|
|
<msb>18</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GPIO_AHB_SEL</name>
|
|
<description>desc GPIO_AHB_SEL</description>
|
|
<msb>24</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR2</name>
|
|
<description>desc CFGR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LOCKUP_LOCK</name>
|
|
<description>desc LOCKUP_LOCK</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PVD_LOCK</name>
|
|
<description>desc PVD_LOCK</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1_BRK_TIM1</name>
|
|
<description>desc COMP1_BRK_TIM1</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP2_BRK_TIM1</name>
|
|
<description>desc COMP2_BRK_TIM1</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP3_BRK_TIM1</name>
|
|
<description>desc COMP3_BRK_TIM1</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1_BRK_TIM15</name>
|
|
<description>desc COMP1_BRK_TIM15</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP2_BRK_TIM15</name>
|
|
<description>desc COMP2_BRK_TIM15</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP3_BRK_TIM15</name>
|
|
<description>desc COMP3_BRK_TIM15</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1_BRK_TIM16</name>
|
|
<description>desc COMP1_BRK_TIM16</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP2_BRK_TIM16</name>
|
|
<description>desc COMP2_BRK_TIM16</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP3_BRK_TIM16</name>
|
|
<description>desc COMP3_BRK_TIM16</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1_BRK_TIM17</name>
|
|
<description>desc COMP1_BRK_TIM17</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP2_BRK_TIM17</name>
|
|
<description>desc COMP2_BRK_TIM17</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP3_BRK_TIM17</name>
|
|
<description>desc COMP3_BRK_TIM17</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1_OCREF_CLR_TIM1</name>
|
|
<description>desc COMP1_OCREF_CLR_TIM1</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1_OCREF_CLR_TIM2</name>
|
|
<description>desc COMP1_OCREF_CLR_TIM2</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP1_OCREF_CLR_TIM3</name>
|
|
<description>desc COMP1_OCREF_CLR_TIM3</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP2_OCREF_CLR_TIM1</name>
|
|
<description>desc COMP2_OCREF_CLR_TIM1</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP2_OCREF_CLR_TIM2</name>
|
|
<description>desc COMP2_OCREF_CLR_TIM2</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP2_OCREF_CLR_TIM3</name>
|
|
<description>desc COMP2_OCREF_CLR_TIM3</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP3_OCREF_CLR_TIM1</name>
|
|
<description>desc COMP3_OCREF_CLR_TIM1</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP3_OCREF_CLR_TIM2</name>
|
|
<description>desc COMP3_OCREF_CLR_TIM2</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMP3_OCREF_CLR_TIM3</name>
|
|
<description>desc COMP3_OCREF_CLR_TIM3</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR3</name>
|
|
<description>desc CFGR3</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMA1_MAP</name>
|
|
<description>desc DMA1_MAP</description>
|
|
<msb>5</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMA2_MAP</name>
|
|
<description>desc DMA2_MAP</description>
|
|
<msb>13</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMA3_MAP</name>
|
|
<description>desc DMA3_MAP</description>
|
|
<msb>21</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMA4_MAP</name>
|
|
<description>desc DMA4_MAP</description>
|
|
<msb>29</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR4</name>
|
|
<description>desc CFGR4</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMA5_MAP</name>
|
|
<description>desc DMA5_MAP</description>
|
|
<msb>5</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMA6_MAP</name>
|
|
<description>desc DMA6_MAP</description>
|
|
<msb>13</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMA7_MAP</name>
|
|
<description>desc DMA7_MAP</description>
|
|
<msb>21</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PAENS</name>
|
|
<description>desc PAENS</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA_ENS</name>
|
|
<description>desc PA_ENS</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PBENS</name>
|
|
<description>desc PBENS</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PB_ENS</name>
|
|
<description>desc PB_ENS</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PCENS</name>
|
|
<description>desc PCENS</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PC_ENS</name>
|
|
<description>desc PC_ENS</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PFENS</name>
|
|
<description>desc PFENS</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PF_ENS</name>
|
|
<description>desc PF_ENS</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EIIC</name>
|
|
<description>desc EIIC</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PA_EIIC</name>
|
|
<description>desc PA_EIIC</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB_EIIC</name>
|
|
<description>desc PB_EIIC</description>
|
|
<msb>16</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PF_EIIC</name>
|
|
<description>desc PF_EIIC</description>
|
|
<msb>25</msb>
|
|
<lsb>24</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM1</name>
|
|
<description>Advanced timer</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40012C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM1_BRK_UP_TRG_COM</name>
|
|
<description>TIM1 Break, Update, Trigger and Commutation Interrupt</description>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM1_CC</name>
|
|
<description>TIM1 Capture Compare Interrupt</description>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>desc CEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>desc UDIS</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>desc URS</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>desc OPM</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>desc CMS</description>
|
|
<msb>6</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>desc ARPE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>desc CKD</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>desc CCDS</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>desc MMS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>desc TI1S</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCR</name>
|
|
<description>desc SMCR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFF7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMS</name>
|
|
<description>desc SMS</description>
|
|
<msb>2</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>desc TS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>desc MSM</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETF</name>
|
|
<description>desc ETF</description>
|
|
<msb>11</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETPS</name>
|
|
<description>desc ETPS</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ECE</name>
|
|
<description>desc ECE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETP</name>
|
|
<description>desc ETP</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<description>desc DIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>desc UIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>desc CC1IE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>desc CC2IE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>desc CC3IE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>desc CC4IE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>desc TIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>desc UDE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>desc CC1DE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>desc CC2DE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3DE</name>
|
|
<description>desc CC3DE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4DE</name>
|
|
<description>desc CC4DE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>desc TDE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1E5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>desc UIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>desc CC1IF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>desc CC2IF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>desc CC3IF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>desc CC4IF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>desc COMIF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>desc TIF</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>desc BIF</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>desc CC1OF</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>desc CC2OF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>desc CC3OF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>desc CC4OF</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IR</name>
|
|
<description>desc IC1IR</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IR</name>
|
|
<description>desc IC2IR</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IF</name>
|
|
<description>desc IC1IF</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IF</name>
|
|
<description>desc IC2IF</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<description>desc EGR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>desc UG</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/Compare 1 Generation</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>desc CC2G</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>desc CC3G</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>desc CC4G</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>desc TG</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_OUTPUT</name>
|
|
<description>desc CCMR1:OUTPUT</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>desc OC1FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>desc OC1PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>desc OC1M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1CE</name>
|
|
<description>desc OC1CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2FE</name>
|
|
<description>desc OC2FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2PE</name>
|
|
<description>desc OC2PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2M</name>
|
|
<description>desc OC2M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2CE</name>
|
|
<description>desc OC2CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_INPUT</name>
|
|
<description>desc CCMR1:INPUT</description>
|
|
<alternateRegister>CCMR1_OUTPUT</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1PSC</name>
|
|
<description>desc IC1PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>desc IC1F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2PSC</name>
|
|
<description>desc IC2PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2F</name>
|
|
<description>desc IC2F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_OUTPUT</name>
|
|
<description>desc CCMR2:OUTPUT</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>desc CC3S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3FE</name>
|
|
<description>desc OC3FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3PE</name>
|
|
<description>desc OC3PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3M</name>
|
|
<description>desc OC3M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3CE</name>
|
|
<description>desc OC3CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>desc CC4S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4FE</name>
|
|
<description>desc OC4FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4PE</name>
|
|
<description>desc OC4PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4M</name>
|
|
<description>desc OC4M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4CE</name>
|
|
<description>desc OC4CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_INPUT</name>
|
|
<description>desc CCMR2:INPUT</description>
|
|
<alternateRegister>CCMR2_OUTPUT</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>desc CC3S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3PSC</name>
|
|
<description>desc IC3PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3F</name>
|
|
<description>desc IC3F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>desc CC4S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4PSC</name>
|
|
<description>desc IC4PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4F</name>
|
|
<description>desc IC4F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<description>desc CCER</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3333</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>desc CC1E</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>desc CC1P</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2E</name>
|
|
<description>desc CC2E</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2P</name>
|
|
<description>desc CC2P</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3E</name>
|
|
<description>desc CC3E</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3P</name>
|
|
<description>desc CC3P</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4E</name>
|
|
<description>desc CC4E</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4P</name>
|
|
<description>desc CC4P</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>desc RCR</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>desc REP</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR3</name>
|
|
<description>desc CCR3</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR3</name>
|
|
<description>desc CCR3</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR4</name>
|
|
<description>desc CCR4</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR4</name>
|
|
<description>desc CCR4</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTR</name>
|
|
<description>desc BDTR</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTG</name>
|
|
<description>desc DTG</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>desc LOCK</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSI</name>
|
|
<description>desc OSSI</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSR</name>
|
|
<description>desc OSSR</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BKE</name>
|
|
<description>desc BKE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>desc BKP</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AOE</name>
|
|
<description>desc AOE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOE</name>
|
|
<description>desc MOE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<description>desc DCR</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1F1F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBA</name>
|
|
<description>desc DBA</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBL</name>
|
|
<description>desc DBL</description>
|
|
<msb>12</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAR</name>
|
|
<description>desc DMAR</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAB</name>
|
|
<description>desc DMAB</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM2</name>
|
|
<description>desc TIM</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM2</name>
|
|
<description>TIM2 global Interrupt</description>
|
|
<value>15</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>desc CEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>desc UDIS</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>desc URS</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>desc OPM</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>desc CMS</description>
|
|
<msb>6</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>desc ARPE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>desc CKD</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>desc CCDS</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>desc MMS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>desc TI1S</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCR</name>
|
|
<description>desc SMCR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFF7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMS</name>
|
|
<description>desc SMS</description>
|
|
<msb>2</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>desc TS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>desc MSM</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETF</name>
|
|
<description>desc ETF</description>
|
|
<msb>11</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETPS</name>
|
|
<description>desc ETPS</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ECE</name>
|
|
<description>desc ECE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETP</name>
|
|
<description>desc ETP</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<description>desc DIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>desc UIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>desc CC1IE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>desc CC2IE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>desc CC3IE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>desc CC4IE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>desc TIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>desc UDE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>desc CC1DE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>desc CC2DE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3DE</name>
|
|
<description>desc CC3DE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4DE</name>
|
|
<description>desc CC4DE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>desc TDE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1E5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>desc UIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>desc CC1IF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>desc CC2IF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>desc CC3IF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>desc CC4IF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>desc COMIF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>desc TIF</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>desc BIF</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>desc CC1OF</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>desc CC2OF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>desc CC3OF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>desc CC4OF</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IR</name>
|
|
<description>desc IC1IR</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IR</name>
|
|
<description>desc IC2IR</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IF</name>
|
|
<description>desc IC1IF</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IF</name>
|
|
<description>desc IC2IF</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<description>desc EGR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>desc UG</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/Compare 1 Generation</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>desc CC2G</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>desc CC3G</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>desc CC4G</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>desc TG</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_OUTPUT</name>
|
|
<description>desc CCMR1:OUTPUT</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>desc OC1FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>desc OC1PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>desc OC1M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1CE</name>
|
|
<description>desc OC1CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2FE</name>
|
|
<description>desc OC2FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2PE</name>
|
|
<description>desc OC2PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2M</name>
|
|
<description>desc OC2M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2CE</name>
|
|
<description>desc OC2CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_INPUT</name>
|
|
<description>desc CCMR1:INPUT</description>
|
|
<alternateRegister>CCMR1_OUTPUT</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1PSC</name>
|
|
<description>desc IC1PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>desc IC1F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2PSC</name>
|
|
<description>desc IC2PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2F</name>
|
|
<description>desc IC2F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_OUTPUT</name>
|
|
<description>desc CCMR2:OUTPUT</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>desc CC3S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3FE</name>
|
|
<description>desc OC3FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3PE</name>
|
|
<description>desc OC3PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3M</name>
|
|
<description>desc OC3M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3CE</name>
|
|
<description>desc OC3CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>desc CC4S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4FE</name>
|
|
<description>desc OC4FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4PE</name>
|
|
<description>desc OC4PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4M</name>
|
|
<description>desc OC4M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4CE</name>
|
|
<description>desc OC4CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_INPUT</name>
|
|
<description>desc CCMR2:INPUT</description>
|
|
<alternateRegister>CCMR2_OUTPUT</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>desc CC3S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3PSC</name>
|
|
<description>desc IC3PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3F</name>
|
|
<description>desc IC3F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>desc CC4S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4PSC</name>
|
|
<description>desc IC4PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4F</name>
|
|
<description>desc IC4F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<description>desc CCER</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3333</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>desc CC1E</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>desc CC1P</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2E</name>
|
|
<description>desc CC2E</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2P</name>
|
|
<description>desc CC2P</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3E</name>
|
|
<description>desc CC3E</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3P</name>
|
|
<description>desc CC3P</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4E</name>
|
|
<description>desc CC4E</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4P</name>
|
|
<description>desc CC4P</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR3</name>
|
|
<description>desc CCR3</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR3</name>
|
|
<description>desc CCR3</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR4</name>
|
|
<description>desc CCR4</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR4</name>
|
|
<description>desc CCR4</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<description>desc DCR</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1F1F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBA</name>
|
|
<description>desc DBA</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBL</name>
|
|
<description>desc DBL</description>
|
|
<msb>12</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAR</name>
|
|
<description>desc DMAR</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAB</name>
|
|
<description>desc DMAB</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM3</name>
|
|
<description>General purpose timer</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40000400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM3</name>
|
|
<description>TIM3 global Interrupt</description>
|
|
<value>16</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>desc CEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>desc UDIS</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>desc URS</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>desc OPM</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>desc CMS</description>
|
|
<msb>6</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>desc ARPE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>desc CKD</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>desc CCDS</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>desc MMS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>desc TI1S</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCR</name>
|
|
<description>desc SMCR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFF7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMS</name>
|
|
<description>desc SMS</description>
|
|
<msb>2</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>desc TS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>desc MSM</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETF</name>
|
|
<description>desc ETF</description>
|
|
<msb>11</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETPS</name>
|
|
<description>desc ETPS</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ECE</name>
|
|
<description>desc ECE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETP</name>
|
|
<description>desc ETP</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<description>desc DIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>desc UIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>desc CC1IE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>desc CC2IE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>desc CC3IE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>desc CC4IE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>desc TIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>desc UDE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>desc CC1DE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>desc CC2DE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3DE</name>
|
|
<description>desc CC3DE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4DE</name>
|
|
<description>desc CC4DE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>desc TDE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1E5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>desc UIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>desc CC1IF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>desc CC2IF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>desc CC3IF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>desc CC4IF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>desc COMIF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>desc TIF</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>desc BIF</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>desc CC1OF</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>desc CC2OF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>desc CC3OF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>desc CC4OF</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IR</name>
|
|
<description>desc IC1IR</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IR</name>
|
|
<description>desc IC2IR</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IF</name>
|
|
<description>desc IC1IF</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IF</name>
|
|
<description>desc IC2IF</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<description>desc EGR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>desc UG</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/Compare 1 Generation</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>desc CC2G</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>desc CC3G</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>desc CC4G</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>desc TG</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_OUTPUT</name>
|
|
<description>desc CCMR1:OUTPUT</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>desc OC1FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>desc OC1PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>desc OC1M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1CE</name>
|
|
<description>desc OC1CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2FE</name>
|
|
<description>desc OC2FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2PE</name>
|
|
<description>desc OC2PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2M</name>
|
|
<description>desc OC2M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2CE</name>
|
|
<description>desc OC2CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_INPUT</name>
|
|
<description>desc CCMR1:INPUT</description>
|
|
<alternateRegister>CCMR1_OUTPUT</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1PSC</name>
|
|
<description>desc IC1PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>desc IC1F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2PSC</name>
|
|
<description>desc IC2PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2F</name>
|
|
<description>desc IC2F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_OUTPUT</name>
|
|
<description>desc CCMR2:OUTPUT</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>desc CC3S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3FE</name>
|
|
<description>desc OC3FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3PE</name>
|
|
<description>desc OC3PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3M</name>
|
|
<description>desc OC3M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3CE</name>
|
|
<description>desc OC3CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>desc CC4S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4FE</name>
|
|
<description>desc OC4FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4PE</name>
|
|
<description>desc OC4PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4M</name>
|
|
<description>desc OC4M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4CE</name>
|
|
<description>desc OC4CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_INPUT</name>
|
|
<description>desc CCMR2:INPUT</description>
|
|
<alternateRegister>CCMR2_OUTPUT</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>desc CC3S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3PSC</name>
|
|
<description>desc IC3PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3F</name>
|
|
<description>desc IC3F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>desc CC4S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4PSC</name>
|
|
<description>desc IC4PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4F</name>
|
|
<description>desc IC4F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<description>desc CCER</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3333</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>desc CC1E</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>desc CC1P</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2E</name>
|
|
<description>desc CC2E</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2P</name>
|
|
<description>desc CC2P</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3E</name>
|
|
<description>desc CC3E</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3P</name>
|
|
<description>desc CC3P</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4E</name>
|
|
<description>desc CC4E</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4P</name>
|
|
<description>desc CC4P</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR3</name>
|
|
<description>desc CCR3</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR3</name>
|
|
<description>desc CCR3</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR4</name>
|
|
<description>desc CCR4</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR4</name>
|
|
<description>desc CCR4</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<description>desc DCR</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1F1F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBA</name>
|
|
<description>desc DBA</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBL</name>
|
|
<description>desc DBL</description>
|
|
<msb>12</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAR</name>
|
|
<description>desc DMAR</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAB</name>
|
|
<description>desc DMAB</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM6</name>
|
|
<description>desc TIM</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM6_LPTIM1_DAC</name>
|
|
<description>TIM6, LPTIM1, DAC global Interrupts</description>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>desc CEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>desc UDIS</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>desc URS</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>desc OPM</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>desc CMS</description>
|
|
<msb>6</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>desc ARPE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>desc CKD</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>desc CCDS</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>desc MMS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>desc TI1S</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<description>desc DIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>desc UIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>desc CC1IE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>desc CC2IE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>desc CC3IE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>desc CC4IE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>desc TIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>desc UDE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>desc CC1DE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>desc CC2DE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3DE</name>
|
|
<description>desc CC3DE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4DE</name>
|
|
<description>desc CC4DE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>desc TDE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1E5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>desc UIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>desc CC1IF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>desc CC2IF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>desc CC3IF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>desc CC4IF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>desc COMIF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>desc TIF</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>desc BIF</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>desc CC1OF</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>desc CC2OF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>desc CC3OF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>desc CC4OF</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IR</name>
|
|
<description>desc IC1IR</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IR</name>
|
|
<description>desc IC2IR</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IF</name>
|
|
<description>desc IC1IF</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IF</name>
|
|
<description>desc IC2IF</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<description>desc EGR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>desc UG</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/Compare 1 Generation</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>desc CC2G</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>desc CC3G</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>desc CC4G</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>desc TG</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM6">
|
|
<name>TIM7</name>
|
|
<description>desc TIM</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40001400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM7</name>
|
|
<description>TIM7 global Interrupt</description>
|
|
<value>18</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM14</name>
|
|
<description>General purpose timer</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40002000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM14</name>
|
|
<description>TIM14 global Interrupt</description>
|
|
<value>19</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>desc CEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>desc UDIS</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>desc URS</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>desc OPM</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>desc CMS</description>
|
|
<msb>6</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>desc ARPE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>desc CKD</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<description>desc DIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>desc UIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>desc CC1IE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>desc CC2IE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>desc CC3IE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>desc CC4IE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>desc TIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>desc UDE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>desc CC1DE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>desc CC2DE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3DE</name>
|
|
<description>desc CC3DE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4DE</name>
|
|
<description>desc CC4DE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>desc TDE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1E5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>desc UIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>desc CC1IF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>desc CC2IF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>desc CC3IF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>desc CC4IF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>desc TIF</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>desc CC1OF</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>desc CC2OF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>desc CC3OF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>desc CC4OF</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<description>desc EGR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>desc UG</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/Compare 1 Generation</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>desc CC2G</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>desc CC3G</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>desc CC4G</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>desc TG</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_OUTPUT</name>
|
|
<description>desc CCMR1:OUTPUT</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>desc OC1FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>desc OC1PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>desc OC1M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1CE</name>
|
|
<description>desc OC1CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2FE</name>
|
|
<description>desc OC2FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2PE</name>
|
|
<description>desc OC2PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2M</name>
|
|
<description>desc OC2M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2CE</name>
|
|
<description>desc OC2CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_INPUT</name>
|
|
<description>desc CCMR1:INPUT</description>
|
|
<alternateRegister>CCMR1_OUTPUT</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1PSC</name>
|
|
<description>desc IC1PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>desc IC1F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2PSC</name>
|
|
<description>desc IC2PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2F</name>
|
|
<description>desc IC2F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<description>desc CCER</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3333</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>desc CC1E</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>desc CC1P</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2E</name>
|
|
<description>desc CC2E</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2P</name>
|
|
<description>desc CC2P</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3E</name>
|
|
<description>desc CC3E</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3P</name>
|
|
<description>desc CC3P</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4E</name>
|
|
<description>desc CC4E</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4P</name>
|
|
<description>desc CC4P</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OR</name>
|
|
<description>desc OR</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TI1_RMP</name>
|
|
<description>desc TI1_RMP</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM15</name>
|
|
<baseAddress>0x40014000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM15</name>
|
|
<description>TIM15 global Interrupt</description>
|
|
<value>20</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>desc CEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>desc UDIS</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>desc URS</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>desc OPM</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>desc CMS</description>
|
|
<msb>6</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>desc ARPE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>desc CKD</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>desc CCDS</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>desc MMS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>desc TI1S</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCR</name>
|
|
<description>desc SMCR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFF7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMS</name>
|
|
<description>desc SMS</description>
|
|
<msb>2</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>desc TS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>desc MSM</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETF</name>
|
|
<description>desc ETF</description>
|
|
<msb>11</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETPS</name>
|
|
<description>desc ETPS</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ECE</name>
|
|
<description>desc ECE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETP</name>
|
|
<description>desc ETP</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<description>desc DIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>desc UIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>desc CC1IE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>desc CC2IE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>desc CC3IE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>desc CC4IE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>desc TIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>desc UDE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>desc CC1DE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>desc CC2DE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3DE</name>
|
|
<description>desc CC3DE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4DE</name>
|
|
<description>desc CC4DE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>desc TDE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1E5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>desc UIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>desc CC1IF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>desc CC2IF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>desc CC3IF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>desc CC4IF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>desc COMIF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>desc TIF</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>desc BIF</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>desc CC1OF</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>desc CC2OF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>desc CC3OF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>desc CC4OF</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IR</name>
|
|
<description>desc IC1IR</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IR</name>
|
|
<description>desc IC2IR</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IF</name>
|
|
<description>desc IC1IF</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IF</name>
|
|
<description>desc IC2IF</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<description>desc EGR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>desc UG</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/Compare 1 Generation</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>desc CC2G</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>desc CC3G</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>desc CC4G</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>desc TG</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_OUTPUT</name>
|
|
<description>desc CCMR1:OUTPUT</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>desc OC1FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>desc OC1PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>desc OC1M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1CE</name>
|
|
<description>desc OC1CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2FE</name>
|
|
<description>desc OC2FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2PE</name>
|
|
<description>desc OC2PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2M</name>
|
|
<description>desc OC2M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2CE</name>
|
|
<description>desc OC2CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_INPUT</name>
|
|
<description>desc CCMR1:INPUT</description>
|
|
<alternateRegister>CCMR1_OUTPUT</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1PSC</name>
|
|
<description>desc IC1PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>desc IC1F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2PSC</name>
|
|
<description>desc IC2PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2F</name>
|
|
<description>desc IC2F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<description>desc CCER</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3333</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>desc CC1E</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>desc CC1P</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2E</name>
|
|
<description>desc CC2E</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2P</name>
|
|
<description>desc CC2P</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3E</name>
|
|
<description>desc CC3E</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3P</name>
|
|
<description>desc CC3P</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4E</name>
|
|
<description>desc CC4E</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4P</name>
|
|
<description>desc CC4P</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>desc RCR</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>desc REP</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTR</name>
|
|
<description>desc BDTR</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTG</name>
|
|
<description>desc DTG</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>desc LOCK</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSI</name>
|
|
<description>desc OSSI</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSR</name>
|
|
<description>desc OSSR</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BKE</name>
|
|
<description>desc BKE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>desc BKP</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AOE</name>
|
|
<description>desc AOE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOE</name>
|
|
<description>desc MOE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<description>desc DCR</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1F1F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBA</name>
|
|
<description>desc DBA</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBL</name>
|
|
<description>desc DBL</description>
|
|
<msb>12</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAR</name>
|
|
<description>desc DMAR</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAB</name>
|
|
<description>desc DMAB</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM16</name>
|
|
<description>General purpose timer</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40014400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x00</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM16</name>
|
|
<description>TIM16 global Interrupt</description>
|
|
<value>21</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>desc CEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>desc UDIS</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>desc URS</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>desc OPM</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>desc CMS</description>
|
|
<msb>6</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>desc ARPE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>desc CKD</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>desc CCDS</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>desc MMS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>desc TI1S</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<description>desc DIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>desc UIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>desc CC1IE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>desc CC2IE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>desc CC3IE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>desc CC4IE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>desc TIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>desc UDE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>desc CC1DE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>desc CC2DE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3DE</name>
|
|
<description>desc CC3DE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4DE</name>
|
|
<description>desc CC4DE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>desc TDE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1E5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>desc UIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>desc CC1IF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>desc CC2IF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>desc CC3IF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>desc CC4IF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>desc COMIF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>desc TIF</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>desc BIF</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>desc CC1OF</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>desc CC2OF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>desc CC3OF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>desc CC4OF</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IR</name>
|
|
<description>desc IC1IR</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IR</name>
|
|
<description>desc IC2IR</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IF</name>
|
|
<description>desc IC1IF</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IF</name>
|
|
<description>desc IC2IF</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<description>desc EGR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>desc UG</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/Compare 1 Generation</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>desc CC2G</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>desc CC3G</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>desc CC4G</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>desc TG</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_OUTPUT</name>
|
|
<description>desc CCMR1:OUTPUT</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>desc OC1FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>desc OC1PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>desc OC1M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1CE</name>
|
|
<description>desc OC1CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2FE</name>
|
|
<description>desc OC2FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2PE</name>
|
|
<description>desc OC2PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2M</name>
|
|
<description>desc OC2M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2CE</name>
|
|
<description>desc OC2CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_INPUT</name>
|
|
<description>desc CCMR1:INPUT</description>
|
|
<alternateRegister>CCMR1_OUTPUT</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1PSC</name>
|
|
<description>desc IC1PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>desc IC1F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2PSC</name>
|
|
<description>desc IC2PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2F</name>
|
|
<description>desc IC2F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<description>desc CCER</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3333</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>desc CC1E</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>desc CC1P</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2E</name>
|
|
<description>desc CC2E</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2P</name>
|
|
<description>desc CC2P</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3E</name>
|
|
<description>desc CC3E</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3P</name>
|
|
<description>desc CC3P</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4E</name>
|
|
<description>desc CC4E</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4P</name>
|
|
<description>desc CC4P</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>desc RCR</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>desc REP</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTR</name>
|
|
<description>desc BDTR</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTG</name>
|
|
<description>desc DTG</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>desc LOCK</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSI</name>
|
|
<description>desc OSSI</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSR</name>
|
|
<description>desc OSSR</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BKE</name>
|
|
<description>desc BKE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>desc BKP</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AOE</name>
|
|
<description>desc AOE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOE</name>
|
|
<description>desc MOE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<description>desc DCR</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1F1F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBA</name>
|
|
<description>desc DBA</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBL</name>
|
|
<description>desc DBL</description>
|
|
<msb>12</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAR</name>
|
|
<description>desc DMAR</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAB</name>
|
|
<description>desc DMAB</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="TIM16">
|
|
<name>TIM17</name>
|
|
<baseAddress>0x40014800</baseAddress>
|
|
<interrupt>
|
|
<name>TIM17</name>
|
|
<description>TIM17 global Interrupt</description>
|
|
<value>22</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART1</name>
|
|
<description>
|
|
Universal synchronous asynchronous receiver
|
|
transmitter
|
|
</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40013800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART1</name>
|
|
<description>USART1 global Interrupt</description>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>desc PE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>desc FE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NE</name>
|
|
<description>desc NE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ORE</name>
|
|
<description>desc ORE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>desc IDLE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>desc RXNE</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>desc TC</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>desc TXE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>LBD</name>
|
|
<description>desc LBD</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>desc CTS</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ABRF</name>
|
|
<description>desc ABRF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ABRE</name>
|
|
<description>desc ABRE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ABRRQ</name>
|
|
<description>desc ABRRQ</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>desc DR</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>desc DR</description>
|
|
<msb>8</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<description>desc BRR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_FRACTION</name>
|
|
<description>desc DIV_Fraction</description>
|
|
<msb>3</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIV_MANTISSA</name>
|
|
<description>desc DIV_Mantissa</description>
|
|
<msb>15</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SBK</name>
|
|
<description>desc SBK</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>desc RWU</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>desc RE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>desc TE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDLEIE</name>
|
|
<description>desc IDLEIE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXNEIE</name>
|
|
<description>desc RXNEIE</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>desc TCIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEIE</name>
|
|
<description>desc TXEIE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>desc PEIE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>desc PS</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>desc PCE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>desc WAKE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>desc M</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UE</name>
|
|
<description>desc UE</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADD</name>
|
|
<description>desc ADD</description>
|
|
<msb>3</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LBDL</name>
|
|
<description>desc LBDL</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LBDIE</name>
|
|
<description>desc LBDIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LBCL</name>
|
|
<description>desc LBCL</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>desc CPHA</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>desc CPOL</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>desc CLKEN</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>desc STOP</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LINEN</name>
|
|
<description>desc LINEN</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR3</name>
|
|
<description>desc CR3</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EIE</name>
|
|
<description>desc EIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>desc IREN</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IRLP</name>
|
|
<description>desc IRLP</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HDSEL</name>
|
|
<description>desc HDSEL</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>NACK</name>
|
|
<description>desc NACK</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SCEN</name>
|
|
<description>desc SCEN</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAR</name>
|
|
<description>desc DMAR</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DMAT</name>
|
|
<description>desc DMAT</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RTSE</name>
|
|
<description>desc RTSE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSE</name>
|
|
<description>desc CTSE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CTSIE</name>
|
|
<description>desc CTSIE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVER8</name>
|
|
<description>desc OVER8</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ABREN</name>
|
|
<description>desc ABREN</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ABRMODE</name>
|
|
<description>desc ABRMODE</description>
|
|
<msb>14</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GTPR</name>
|
|
<description>desc GTPR</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>GT</name>
|
|
<description>desc GT</description>
|
|
<msb>15</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="USART1">
|
|
<name>USART2</name>
|
|
<baseAddress>0x40004400</baseAddress>
|
|
<interrupt>
|
|
<name>USART2</name>
|
|
<description>USART2 global Interrupt</description>
|
|
<value>28</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="USART1">
|
|
<name>USART3</name>
|
|
<description>desc USART</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40004800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART3_4</name>
|
|
<description>USART3, 4 global Interrupts</description>
|
|
<value>29</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral derivedFrom="USART1">
|
|
<name>USART4</name>
|
|
<description>desc USART</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40004C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART3_4</name>
|
|
<description>USART3, 4 global Interrupts</description>
|
|
<value>29</value>
|
|
</interrupt>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USB</name>
|
|
<description>USB</description>
|
|
<groupName>USB</groupName>
|
|
<baseAddress>0x40005C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USB</name>
|
|
<description>USB global Interrupts</description>
|
|
<value>31</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>CR</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADD</name>
|
|
<description>ADD</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UPDATE</name>
|
|
<description>UPDATE</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Enable_Suspend</name>
|
|
<description>Enable_Suspend</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Suspend_Mode</name>
|
|
<description>Suspend_Mode</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Resume</name>
|
|
<description>Resume</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Reset</name>
|
|
<description>Reset</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISO_Update</name>
|
|
<description>ISO_Update</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTR</name>
|
|
<displayName>INTR</displayName>
|
|
<description>INTR</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>Suspend</name>
|
|
<description>Suspend</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Resume</name>
|
|
<description>Resume</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Reset</name>
|
|
<description>Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SOF</name>
|
|
<description>SOF</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP1OUT</name>
|
|
<description>EP1OUT</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP2OUT</name>
|
|
<description>EP2OUT</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP3OUT</name>
|
|
<description>EP3OUT</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP4OUT</name>
|
|
<description>EP4OUT</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP5OUT</name>
|
|
<description>EP5OUT</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP0</name>
|
|
<description>EP0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP1IN</name>
|
|
<description>EP1IN</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP2IN</name>
|
|
<description>EP2IN</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP3IN</name>
|
|
<description>EP3IN</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP4IN</name>
|
|
<description>EP4IN</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP5IN</name>
|
|
<description>EP5IN</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INTRE</name>
|
|
<displayName>INTRE</displayName>
|
|
<description>INTRE</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EN_Suspend</name>
|
|
<description>EN_Suspend</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN_Resume</name>
|
|
<description>EN_Resume</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN_Reset</name>
|
|
<description>EN_Reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EN_SOF</name>
|
|
<description>EN_SOF</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP1OUTE</name>
|
|
<description>EP1OUTE</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP2OUTE</name>
|
|
<description>EP2OUTE</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP3OUTE</name>
|
|
<description>EP3OUTE</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP4OUTE</name>
|
|
<description>EP4OUTE</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP5OUTE</name>
|
|
<description>EP5OUTE</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP0</name>
|
|
<description>EP0</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP1INE</name>
|
|
<description>EP1INE</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP2INE</name>
|
|
<description>EP2INE</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP3INE</name>
|
|
<description>EP3INE</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP4INE</name>
|
|
<description>EP4INE</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EP5INE</name>
|
|
<description>EP5INE</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FRAME</name>
|
|
<displayName>FRAME</displayName>
|
|
<description>FRAME</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FramNUM</name>
|
|
<description>FramNUM</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INDEX</name>
|
|
<description>INDEX</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EP0CSR</name>
|
|
<displayName>EP0CSR</displayName>
|
|
<description>EP0CSR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OutPktRdy</name>
|
|
<description>OutPktRdy</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>InPktRdy</name>
|
|
<description>InPktRdy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SentStall</name>
|
|
<description>SentStall</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DataEnd</name>
|
|
<description>DataEnd</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SetupEnd</name>
|
|
<description>SetupEnd</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SendStall</name>
|
|
<description>OutPktRdy</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ServicedOutPktRdy</name>
|
|
<description>ServicedOutPktRdy</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ServicedSetupEnd</name>
|
|
<description>ServicedSetupEnd</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>COUNT0</name>
|
|
<description>COUNT0</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>INEPxCSR</name>
|
|
<displayName>INEPxCSR</displayName>
|
|
<description>INEPxCSR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FrcDataTog</name>
|
|
<description>FrcDataTog</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEnab</name>
|
|
<description>DMAEnab</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>Mode</name>
|
|
<description>Mode</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISO</name>
|
|
<description>ISO</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AutoSet</name>
|
|
<description>AutoSet</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>InPktRdy</name>
|
|
<description>InPktRdy</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FIFONotEmpty</name>
|
|
<description>FIFONotEmpty</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>UnderRun</name>
|
|
<description>UnderRun</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FlushFIFO</name>
|
|
<description>FlushFIFO</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SendStall</name>
|
|
<description>SendStall</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SentStall</name>
|
|
<description>SentStall</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ClrDataTog</name>
|
|
<description>ClrDataTog</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INMAXP</name>
|
|
<description>INMAXP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OUTEPxCSR</name>
|
|
<displayName>OUTEPxCSR</displayName>
|
|
<description>OUTEPxCSR</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DMAMode</name>
|
|
<description>DMAMode</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEnab</name>
|
|
<description>DMAEnab</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ISO</name>
|
|
<description>ISO</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AutoClear</name>
|
|
<description>AutoClear</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OutPktRdy</name>
|
|
<description>OutPktRdy</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FIFOFull</name>
|
|
<description>FIFOFull</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OverRun</name>
|
|
<description>OverRun</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DataError</name>
|
|
<description>DataError</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FlushFIFO</name>
|
|
<description>FlushFIFO</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SendStall</name>
|
|
<description>SendStall</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SentStall</name>
|
|
<description>SentStall</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ClrDataTog</name>
|
|
<description>ClrDataTog</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>INMAXP</name>
|
|
<description>INMAXP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
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<name>OUTCOUNT</name>
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<displayName>OUTCOUNT</displayName>
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<description>OUTCOUNT</description>
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<addressOffset>0x1C</addressOffset>
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<size>0x20</size>
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<access>write-only</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>OUTCOUNT</name>
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<description>OUTCOUNT</description>
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<bitOffset>0</bitOffset>
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<bitWidth>10</bitWidth>
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</field>
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</fields>
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</register>
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</registers>
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</peripheral>
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<peripheral>
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<name>WWDG</name>
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<description>Window watchdog</description>
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<groupName>WWDG</groupName>
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<baseAddress>0x40002C00</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x400</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>WWDG</name>
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<description>Window WatchDog Interrupt</description>
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<value>0</value>
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</interrupt>
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<registers>
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<register>
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<name>CR</name>
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<displayName>CR</displayName>
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<description>Control register (WWDG_CR)</description>
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<addressOffset>0x0</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x0000007F</resetValue>
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<fields>
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<field>
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<name>WDGA</name>
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<description>Activation bit</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>T</name>
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<description>7-bit counter (MSB to LSB)</description>
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<bitOffset>0</bitOffset>
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<bitWidth>7</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CFR</name>
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<displayName>CFR</displayName>
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<description>
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Configuration register
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(WWDG_CFR)
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</description>
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<addressOffset>0x4</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x0000007F</resetValue>
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|
<fields>
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<field>
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<name>EWI</name>
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<description>Early Wakeup Interrupt</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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|
<field>
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<name>WDGTB</name>
|
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<description>Timer Base</description>
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|
<bitOffset>7</bitOffset>
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|
<bitWidth>2</bitWidth>
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|
</field>
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|
<field>
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<name>W</name>
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<description>7-bit window value</description>
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<bitOffset>0</bitOffset>
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<bitWidth>7</bitWidth>
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|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
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<name>SR</name>
|
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<displayName>SR</displayName>
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<description>Status register (WWDG_SR)</description>
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<addressOffset>0x8</addressOffset>
|
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<size>0x20</size>
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|
<access>read-write</access>
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|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EWIF</name>
|
|
<description>Early Wakeup Interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
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</peripheral>
|
|
</peripherals>
|
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</device>
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