mirror of
https://github.com/IcedRooibos/py32f0-template.git
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543 lines
20 KiB
C
543 lines
20 KiB
C
/* -----------------------------------------------------------------------------
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* Copyright (c) 2014 - 2019 ARM Ltd.
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*
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* This software is provided 'as-is', without any express or implied warranty.
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* In no event will the authors be held liable for any damages arising from
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* the use of this software. Permission is granted to anyone to use this
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* software for any purpose, including commercial applications, and to alter
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* it and redistribute it freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software in
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* a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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*
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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*
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*
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* $Date: 2021-7-1
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* $Revision: V1.0.0
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*
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* Project: Flash Programming Functions for Puya PY32F0xx Flash
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* --------------------------------------------------------------------------- */
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/* History:
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* Version 1.0.0
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* Initial release
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*/
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#include "FlashOS.h" // FlashOS Structures
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typedef volatile unsigned char vu8;
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typedef unsigned char u8;
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typedef volatile unsigned short vu16;
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typedef unsigned short u16;
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typedef volatile unsigned long vu32;
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typedef unsigned long u32;
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#define M8(adr) (*((vu8 *) (adr)))
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#define M16(adr) (*((vu16 *) (adr)))
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#define M32(adr) (*((vu32 *) (adr)))
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#define SET_BIT(REG, BIT) ((REG) |= (BIT))
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#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
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#define READ_BIT(REG, BIT) ((REG) & (BIT))
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#define CLEAR_REG(REG) ((REG) = (0x0))
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#define WRITE_REG(REG, VAL) ((REG) = (VAL))
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#define READ_REG(REG) ((REG))
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#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
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// Peripheral Memory Map
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#define RCC_BASE 0x40021000
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#define IWDG_BASE 0x40003000
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#define FLASH_BASE 0x40022000
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#define RCC ((RCC_TypeDef*) RCC_BASE)
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#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
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#define FLASH ((FLASH_TypeDef*) FLASH_BASE)
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typedef struct
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{
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vu32 CR; /*!< RCC Clock Sources Control Register, Address offset: 0x00 */
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vu32 ICSCR; /*!< RCC Internal Clock Sources Calibration Register, Address offset: 0x04 */
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} RCC_TypeDef;
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// Independent WATCHDOG
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typedef struct {
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vu32 KR; /*!< IWDG Key register, Address offset: 0x00 */
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vu32 PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
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vu32 RLR; /*!< IWDG Reload register, Address offset: 0x08 */
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vu32 SR; /*!< IWDG Status register, Address offset: 0x0C */
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} IWDG_TypeDef;
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// Flash Registers
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typedef struct {
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vu32 ACR; /*!< FLASH Access Control register, Address offset: 0x00 */
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vu32 RESERVED1; /*!< Reserved1, Address offset: 0x04 */
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vu32 KEYR; /*!< FLASH Key register, Address offset: 0x08 */
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vu32 OPTKEYR; /*!< FLASH Option Key register, Address offset: 0x0C */
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vu32 SR; /*!< FLASH Status register, Address offset: 0x10 */
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vu32 CR; /*!< FLASH Control register, Address offset: 0x14 */
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vu32 RESERVED2[2]; /*!< Reserved2, Address offset: 0x18-0x1C */
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vu32 OPTR; /*!< FLASH Option register, Address offset: 0x20 */
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vu32 SDKR; /*!< FLASH SDK address register, Address offset: 0x24 */
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vu32 RESERVED3; /*!< Reserved2, Address offset: 0x28 */
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vu32 WRPR; /*!< FLASH WRP address register, Address offset: 0x2C */
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vu32 RESERVED4[(0x90 - 0x2C) / 4 - 1];
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vu32 STCR; /*!< FLASH sleep time config register, Address offset: 0x90 */
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vu32 RESERVED5[(0x100 - 0x90) / 4 - 1];
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vu32 TS0; /*!< FLASH TS0 register, Address offset: 0x100 */
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vu32 TS1; /*!< FLASH TS1 register, Address offset: 0x104 */
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vu32 TS2P; /*!< FLASH TS2P register, Address offset: 0x108 */
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vu32 TPS3; /*!< FLASH TPS3 register, Address offset: 0x10C */
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vu32 TS3; /*!< FLASH TS3 register, Address offset: 0x110 */
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vu32 PERTPE; /*!< FLASH PERTPE register, Address offset: 0x114 */
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vu32 SMERTPE; /*!< FLASH SMERTPE register, Address offset: 0x118 */
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vu32 PRGTPE; /*!< FLASH PRGTPE register, Address offset: 0x11C */
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vu32 PRETPE; /*!< FLASH PRETPE register, Address offset: 0x120 */
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} FLASH_TypeDef;
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// Flash Keys
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#define FLASH_KEY1 ((unsigned int)0x45670123)
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#define FLASH_KEY2 ((unsigned int)0xCDEF89AB)
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#define FLASH_OPTKEY1 ((unsigned int)0x08192A3B)
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#define FLASH_OPTKEY2 ((unsigned int)0x4C5D6E7F)
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// Flash Control Register definitions
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#define FLASH_CR_PG_Pos (0U)
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#define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000001 */
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#define FLASH_CR_PG FLASH_CR_PG_Msk
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#define FLASH_CR_PER_Pos (1U)
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#define FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos) /*!< 0x00000002 */
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#define FLASH_CR_PER FLASH_CR_PER_Msk
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#define FLASH_CR_MER_Pos (2U)
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#define FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos) /*!< 0x00000004 */
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#define FLASH_CR_MER FLASH_CR_MER_Msk
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#define FLASH_CR_SER_Pos (11U)
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#define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000800 */
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#define FLASH_CR_SER FLASH_CR_SER_Msk
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#define FLASH_CR_OPTSTRT_Pos (17U)
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#define FLASH_CR_OPTSTRT_Msk (0x1UL << FLASH_CR_OPTSTRT_Pos) /*!< 0x00020000 */
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#define FLASH_CR_OPTSTRT FLASH_CR_OPTSTRT_Msk
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#define FLASH_CR_PGSTRT_Pos (19U)
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#define FLASH_CR_PGSTRT_Msk (0x1UL << FLASH_CR_PGSTRT_Pos) /*!< 0x00080000 */
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#define FLASH_CR_PGSTRT FLASH_CR_PGSTRT_Msk
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#define FLASH_CR_EOPIE_Pos (24U)
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#define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x01000000 */
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#define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk
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#define FLASH_CR_ERRIE_Pos (25U)
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#define FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos) /*!< 0x02000000 */
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#define FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk
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#define FLASH_CR_OBL_LAUNCH_Pos (27U)
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#define FLASH_CR_OBL_LAUNCH_Msk (0x1UL << FLASH_CR_OBL_LAUNCH_Pos) /*!< 0x08000000 */
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#define FLASH_CR_OBL_LAUNCH FLASH_CR_OBL_LAUNCH_Msk
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#define FLASH_CR_OPTLOCK_Pos (30U)
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#define FLASH_CR_OPTLOCK_Msk (0x1UL << FLASH_CR_OPTLOCK_Pos) /*!< 0x40000000 */
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#define FLASH_CR_OPTLOCK FLASH_CR_OPTLOCK_Msk
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#define FLASH_CR_LOCK_Pos (31U)
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#define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x80000000 */
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#define FLASH_CR_LOCK FLASH_CR_LOCK_Msk
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// Flash Status Register definitions
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#define FLASH_SR_EOP_Pos (0U)
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#define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00000001 */
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#define FLASH_SR_EOP FLASH_SR_EOP_Msk
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#define FLASH_SR_WRPERR_Pos (4U)
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#define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00000010 */
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#define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk
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#define FLASH_SR_OPTVERR_Pos (15U)
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#define FLASH_SR_OPTVERR_Msk (0x1UL << FLASH_SR_OPTVERR_Pos) /*!< 0x00008000 */
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#define FLASH_SR_OPTVERR FLASH_SR_OPTVERR_Msk
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#define FLASH_SR_BSY_Pos (16U)
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#define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00010000 */
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#define FLASH_SR_BSY FLASH_SR_BSY_Msk
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#define FLASH_OPTR_IWDG_SW_Pos (12U)
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#define FLASH_OPTR_IWDG_SW_Msk (0x1UL << FLASH_OPTR_IWDG_SW_Pos) /*!< 0x00010000 */
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#define FLASH_OPTR_IWDG_SW FLASH_OPTR_IWDG_SW_Msk
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#define FLASH_OPTR_WWDG_SW_Pos (13U)
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#define FLASH_OPTR_WWDG_SW_Msk (0x1UL << FLASH_OPTR_WWDG_SW_Pos) /*!< 0x00080000 */
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#define FLASH_OPTR_WWDG_SW FLASH_OPTR_WWDG_SW_Msk
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u32 RCC_ICSCR_HSI_FS_RESTORE;
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void InitRccAndFlashParam(void);
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void UnInitRccAndFlashParam(void);
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/*
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* Initialize Flash Programming Functions
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* Parameter: adr: Device Base Address
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* clk: Clock Frequency (Hz)
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* fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify)
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* Return Value: 0 - OK, 1 - Failed
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*/
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#ifdef FLASH_MEM
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int Init(unsigned long adr, unsigned long clk, unsigned long fnc)
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{
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FLASH->KEYR = FLASH_KEY1; // Unlock Flash
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FLASH->KEYR = FLASH_KEY2;
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InitRccAndFlashParam();
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FLASH->ACR = 0x00000000; // Zero Wait State, no Prefetch
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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if ((FLASH->OPTR & FLASH_OPTR_IWDG_SW) == 0x00) // Test if IWDG is running (IWDG in HW mode)
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{
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// Set IWDG time out to ~32.768 second
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IWDG->KR = 0x5555; // Enable write access to IWDG_PR and IWDG_RLR
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IWDG->PR = 0x06; // Set prescaler to 256
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IWDG->RLR = 0xFFF; // Set reload value to 4095
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}
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return (0);
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}
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#endif
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#ifdef FLASH_OPT
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int Init(unsigned long adr, unsigned long clk, unsigned long fnc)
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{
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FLASH->KEYR = FLASH_KEY1; // Unlock Flash
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FLASH->KEYR = FLASH_KEY2;
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InitRccAndFlashParam();
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FLASH->OPTKEYR = FLASH_OPTKEY1; // Unlock Option Bytes
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FLASH->OPTKEYR = FLASH_OPTKEY2;
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FLASH->ACR = 0x00000000; // Zero Wait State, no Prefetch
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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if ((FLASH->OPTR & 0x1000) == 0x00) // Test if IWDG is running (IWDG in HW mode)
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{
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// Set IWDG time out to ~32.768 second
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IWDG->KR = 0x5555; // Enable write access to IWDG_PR and IWDG_RLR
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IWDG->PR = 0x06; // Set prescaler to 256
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IWDG->RLR = 0xFFF; // Set reload value to 4095
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}
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return (0);
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}
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#endif
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/*
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* De-Initialize Flash Programming Functions
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* Parameter: fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify)
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* Return Value: 0 - OK, 1 - Failed
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*/
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#ifdef FLASH_MEM
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int UnInit(unsigned long fnc)
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{
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UnInitRccAndFlashParam();
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FLASH->CR |= FLASH_CR_LOCK; // Lock Flash
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return (0);
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}
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#endif
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#ifdef FLASH_OPT
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int UnInit(unsigned long fnc)
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{
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UnInitRccAndFlashParam();
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FLASH->CR |= FLASH_CR_LOCK; // Lock Flash
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FLASH->CR |= FLASH_CR_OPTLOCK; // Lock Option Bytes
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return (0);
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}
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#endif
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/*
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* Erase complete Flash Memory
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* Return Value: 0 - OK, 1 - Failed
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*/
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#ifdef FLASH_MEM
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int EraseChip(void)
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{
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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FLASH->CR |= FLASH_CR_MER; // Mass Erase Enabled
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FLASH->CR |= FLASH_CR_EOPIE;
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M32(0x08000000) = 0xFF;
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__asm("DSB");
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while (FLASH->SR & FLASH_SR_BSY)
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{
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IWDG->KR = 0xAAAA; // Reload IWDG
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}
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FLASH->CR &= ~FLASH_CR_MER; // Mass Erase Disabled
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FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE
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if (FLASH_SR_EOP != (FLASH->SR & FLASH_SR_EOP)) // Check for FLASH_SR_EOP
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{
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FLASH->SR |= FLASH_SR_EOP;
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return (1); // Failed
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}
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return (0); // Done
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}
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#endif
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#ifdef FLASH_OPT
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int EraseChip(void)
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{
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/* erase chip is not needed for
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- Flash Option bytes
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- Flash One Time Programmable bytes
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*/
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return (0); // Done
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}
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#endif
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/*
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* Erase Sector in Flash Memory
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* Parameter: adr: Sector Address
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* Return Value: 0 - OK, 1 - Failed
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*/
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#ifdef FLASH_MEM
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int EraseSector(unsigned long adr)
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{
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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FLASH->CR |= FLASH_CR_SER; // Sector Erase Enabled
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FLASH->CR |= FLASH_CR_EOPIE;
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M32(adr) = 0xFF; // Sector Address
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__asm("DSB");
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while (FLASH->SR & FLASH_SR_BSY)
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{
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IWDG->KR = 0xAAAA; // Reload IWDG
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}
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FLASH->CR &= ~FLASH_CR_SER; // Sector Erase Disabled
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FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE
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// if (FLASH_EOP != (FLASH->SR & FLASH_EOP)) { // Check for FLASH_SR_EOP
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// FLASH->SR |= FLASH_EOP;
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// return (1); // Failed
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// }
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return (0); // Done
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}
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#endif
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#ifdef FLASH_OPT
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int EraseSector(unsigned long adr)
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{
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/* erase sector is not needed for
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- Flash Option bytes
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- Flash One Time Programmable bytes
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*/
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return (0); // Done
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}
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#endif
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/*
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* Blank Check Checks if Memory is Blank
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* Parameter: adr: Block Start Address
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* sz: Block Size (in bytes)
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* pat: Block Pattern
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* Return Value: 0 - OK, 1 - Failed
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*/
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int BlankCheck(unsigned long adr, unsigned long sz, unsigned char pat)
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{
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return (1); // Always Force Erase
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}
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/*
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* Program Page in Flash Memory
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* Parameter: adr: Page Start Address
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* sz: Page Size
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* buf: Page Data
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* Return Value: 0 - OK, 1 - Failed
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*/
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#ifdef FLASH_MEM
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int ProgramPage(unsigned long adr, unsigned long sz, unsigned char *buf)
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{
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sz = (sz + 127) & ~127; // Adjust size for 32 Words
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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while (sz)
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{
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FLASH->CR |= FLASH_CR_PG; // Programming Enabled
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FLASH->CR |= FLASH_CR_EOPIE;
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for (u8 i = 0; i < 32; i++)
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{
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M32(adr + i * 4) = *((u32 *)(buf + i * 4)); // Program the first word of the Double Word
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if (i == 30)
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{
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FLASH->CR |= FLASH_CR_PGSTRT;
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}
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}
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__asm("DSB");
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while (FLASH->SR & FLASH_SR_BSY)
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{
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IWDG->KR = 0xAAAA; // Reload IWDG
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}
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FLASH->CR &= ~FLASH_CR_PG; // Programming Disabled
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FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE
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// if (FLASH_EOP != (FLASH->SR & FLASH_EOP)) { // Check for FLASH_SR_EOP
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// FLASH->SR |= FLASH_EOP;
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// return (1); // Failed
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// }
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adr += 128; // Go to next Page
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buf += 128;
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sz -= 128;
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}
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return (0); // Done
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}
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#endif // FLASH_MEM
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#ifdef FLASH_OPT
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int ProgramPage(unsigned long adr, unsigned long sz, unsigned char *buf)
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{
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u32 optr;
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u32 sdkr;
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u32 wrpr;
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optr = *((u32 *)(buf + 0x00));
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sdkr = *((u32 *)(buf + 0x04));
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wrpr = *((u32 *)(buf + 0x0C));
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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FLASH->OPTR = (optr & 0x0000FFFF); // Write OPTR values
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FLASH->SDKR = (sdkr & 0x0000FFFF); // Write SDKR values
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FLASH->WRPR = (wrpr & 0x0000FFFF); // Write WRPR values
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FLASH->CR |= FLASH_CR_OPTSTRT;
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FLASH->CR |= FLASH_CR_EOPIE;
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M32(0x40022080) = 0xFF;
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__asm("DSB");
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FLASH->CR &= ~FLASH_CR_OPTSTRT; // Programming Disabled
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FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE
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//FLASH->CR |= FLASH_CR_OBL_LAUNCH;
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return (0); // Done
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}
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#endif // FLASH_OPT
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/*
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* Verify Flash Contents
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* Parameter: adr: Start Address
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* sz: Size (in bytes)
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* buf: Data
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* Return Value: (adr+sz) - OK, Failed Address
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*/
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#ifdef FLASH_OPT
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unsigned long Verify(unsigned long adr, unsigned long sz, unsigned char *buf)
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{
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u32 optr;
|
|
u32 sdkr;
|
|
u32 wrpr;
|
|
|
|
optr = *((u32 *)(buf + 0x00));
|
|
sdkr = *((u32 *)(buf + 0x04));
|
|
wrpr = *((u32 *)(buf + 0x0C));
|
|
|
|
if (M32(adr + 0x00) != optr)
|
|
{
|
|
return (adr + 0x00);
|
|
}
|
|
if (M32(adr + 0x04) != sdkr)
|
|
{
|
|
return (adr + 0x04);
|
|
}
|
|
if (M32(adr + 0x0C) != wrpr)
|
|
{
|
|
return (adr + 0x0C);
|
|
}
|
|
|
|
return (adr + sz);
|
|
}
|
|
#endif // FLASH_OPT
|
|
|
|
|
|
#define RCC_CR_HSIRDY_Pos (10U)
|
|
#define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000400 */
|
|
#define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
|
|
#define RCC_ICSCR_HSI_TRIM_Pos (0U)
|
|
#define RCC_ICSCR_HSI_TRIM_Msk (0x1FFFUL << RCC_ICSCR_HSI_TRIM_Pos) /*!< 0x00001FFF */
|
|
#define RCC_ICSCR_HSI_TRIM RCC_ICSCR_HSI_TRIM_Msk /*!< HSITRIM[14:8] bits */
|
|
#define RCC_ICSCR_HSI_FS_Pos (13U)
|
|
#define RCC_ICSCR_HSI_FS_Msk (0x7UL << RCC_ICSCR_HSI_FS_Pos) /*!< 0x0000E000 */
|
|
#define RCC_ICSCR_HSI_FS RCC_ICSCR_HSI_FS_Msk /*!< HSIFS[15:13] bits */
|
|
#define RCC_ICSCR_HSI_FS_0 (0x01UL << RCC_ICSCR_HSI_FS_Pos) /*!< 0x00002000 */
|
|
#define RCC_ICSCR_HSI_FS_1 (0x02UL << RCC_ICSCR_HSI_FS_Pos) /*!< 0x00004000 */
|
|
#define RCC_ICSCR_HSI_FS_2 (0x04UL << RCC_ICSCR_HSI_FS_Pos) /*!< 0x00008000 */
|
|
|
|
void InitRccAndFlashParam(void)
|
|
{
|
|
RCC_ICSCR_HSI_FS_RESTORE = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS);
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_FS, RCC_ICSCR_HSI_FS_2);//HSI_24MHz
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F10)&RCC_ICSCR_HSI_TRIM);
|
|
while (RCC_CR_HSIRDY != READ_BIT(RCC->CR, RCC_CR_HSIRDY));
|
|
|
|
FLASH->TS0 = ((M32(0x1FFF0F1C + 4 * 0x14) >> 0) & 0x000000FF);
|
|
FLASH->TS3 = ((M32(0x1FFF0F1C + 4 * 0x14) >> 8) & 0x000000FF);
|
|
FLASH->TS1 = ((M32(0x1FFF0F1C + 4 * 0x14) >> 16) & 0x000001FF);
|
|
FLASH->TS2P = ((M32(0x1FFF0F20 + 4 * 0x14) >> 0) & 0x000000FF);
|
|
FLASH->TPS3 = ((M32(0x1FFF0F20 + 4 * 0x14) >> 16) & 0x000007FF);
|
|
FLASH->PERTPE = ((M32(0x1FFF0F24 + 4 * 0x14) >> 0) & 0x0001FFFF);
|
|
FLASH->SMERTPE = ((M32(0x1FFF0F28 + 4 * 0x14) >> 0) & 0x0001FFFF);
|
|
FLASH->PRGTPE = ((M32(0x1FFF0F2C + 4 * 0x14) >> 0) & 0x0000FFFF);
|
|
FLASH->PRETPE = ((M32(0x1FFF0F2C + 4 * 0x14) >> 16) & 0x0000FFFF);
|
|
}
|
|
|
|
void UnInitRccAndFlashParam(void)
|
|
{
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_FS, RCC_ICSCR_HSI_FS_RESTORE);
|
|
switch (RCC_ICSCR_HSI_FS_RESTORE)
|
|
{
|
|
case RCC_ICSCR_HSI_FS_2://24MHz
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F10)&RCC_ICSCR_HSI_TRIM);
|
|
break;
|
|
case (RCC_ICSCR_HSI_FS_1|RCC_ICSCR_HSI_FS_0)://22.12MHz
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F0C)&RCC_ICSCR_HSI_TRIM);
|
|
break;
|
|
case RCC_ICSCR_HSI_FS_1://16MHz
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F08)&RCC_ICSCR_HSI_TRIM);
|
|
break;
|
|
case RCC_ICSCR_HSI_FS_0://8MHz
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F04)&RCC_ICSCR_HSI_TRIM);
|
|
break;
|
|
default://4MHz
|
|
MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F00)&RCC_ICSCR_HSI_TRIM);
|
|
break;
|
|
}
|
|
while (RCC_CR_HSIRDY != READ_BIT(RCC->CR, RCC_CR_HSIRDY));
|
|
}
|