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68 lines
1.9 KiB
C
68 lines
1.9 KiB
C
/**
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******************************************************************************
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* @file system_py32f072xx.h
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* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File for
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* PY32F072xx Device Series
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* @version v1.0.0
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*
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* This file refers the CMSIS standard, some adjustments are made according to Puya chips */
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#ifndef SYSTEM_PY32F072XX_H
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#define SYSTEM_PY32F072XX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
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extern const uint32_t AHBPrescTable[16]; /*!< AHB prescalers table values */
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extern const uint32_t APBPrescTable[8]; /*!< APB prescalers table values */
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System and update the SystemCoreClock variable.
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*/
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extern void SystemInit(void);
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/**
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* Update SystemCoreClock variable
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*
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* @param none
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* @return none
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*
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* @brief Updates the SystemCoreClock with current core Clock
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* retrieved from cpu registers.
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*/
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extern void SystemCoreClockUpdate(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* SYSTEM_PY32F072XX_H */
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