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https://github.com/IcedRooibos/py32f0-template.git
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138 lines
3.2 KiB
C
138 lines
3.2 KiB
C
/* ----------------------------------------------------------------------
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* Project: CMSIS DSP Library
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* Title: arm_and_u16.c
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* Description: uint16_t bitwise AND
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*
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* $Date: 23 April 2021
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* $Revision: V1.9.0
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*
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* Target Processor: Cortex-M and Cortex-A cores
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* -------------------------------------------------------------------- */
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/*
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* Copyright (C) 2010-2021 ARM Limited or its affiliates. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "dsp/basic_math_functions.h"
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/**
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@ingroup groupMath
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*/
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/**
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@defgroup And Vector bitwise AND
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Compute the logical bitwise AND.
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There are separate functions for uint32_t, uint16_t, and uint7_t data types.
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*/
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/**
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@addtogroup And
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@{
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*/
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/**
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@brief Compute the logical bitwise AND of two fixed-point vectors.
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@param[in] pSrcA points to input vector A
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@param[in] pSrcB points to input vector B
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@param[out] pDst points to output vector
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@param[in] blockSize number of samples in each vector
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@return none
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*/
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void arm_and_u16(
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const uint16_t * pSrcA,
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const uint16_t * pSrcB,
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uint16_t * pDst,
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uint32_t blockSize)
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{
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uint32_t blkCnt; /* Loop counter */
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#if defined(ARM_MATH_MVEI) && !defined(ARM_MATH_AUTOVECTORIZE)
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uint16x8_t vecSrcA, vecSrcB;
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/* Compute 8 outputs at a time */
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blkCnt = blockSize >> 3;
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while (blkCnt > 0U)
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{
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vecSrcA = vld1q(pSrcA);
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vecSrcB = vld1q(pSrcB);
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vst1q(pDst, vandq_u16(vecSrcA, vecSrcB) );
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pSrcA += 8;
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pSrcB += 8;
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pDst += 8;
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/* Decrement the loop counter */
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blkCnt--;
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}
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/* Tail */
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blkCnt = blockSize & 7;
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if (blkCnt > 0U)
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{
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mve_pred16_t p0 = vctp16q(blkCnt);
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vecSrcA = vld1q(pSrcA);
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vecSrcB = vld1q(pSrcB);
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vstrhq_p(pDst, vandq_u16(vecSrcA, vecSrcB), p0);
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}
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#else
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#if defined(ARM_MATH_NEON) && !defined(ARM_MATH_AUTOVECTORIZE)
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uint16x8_t vecA, vecB;
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/* Compute 8 outputs at a time */
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blkCnt = blockSize >> 3U;
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while (blkCnt > 0U)
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{
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vecA = vld1q_u16(pSrcA);
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vecB = vld1q_u16(pSrcB);
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vst1q_u16(pDst, vandq_u16(vecA, vecB) );
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pSrcA += 8;
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pSrcB += 8;
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pDst += 8;
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/* Decrement the loop counter */
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blkCnt--;
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}
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/* Tail */
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blkCnt = blockSize & 7;
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#else
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/* Initialize blkCnt with number of samples */
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blkCnt = blockSize;
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#endif
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while (blkCnt > 0U)
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{
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*pDst++ = (*pSrcA++)&(*pSrcB++);
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/* Decrement the loop counter */
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blkCnt--;
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}
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#endif /* if defined(ARM_MATH_MVEI) */
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}
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/**
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@} end of And group
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*/
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