mirror of
https://github.com/IcedRooibos/py32f0-template.git
synced 2025-10-30 17:32:05 -07:00
469 lines
18 KiB
C
Executable File
469 lines
18 KiB
C
Executable File
/**
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******************************************************************************
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* @file py32f0xx_hal_rcc_ex.h
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* @author MCU Application Team
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* @brief Header file of RCC HAL Extended module.
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef __PY32F0xx_HAL_RCC_EX_H
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#define __PY32F0xx_HAL_RCC_EX_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "py32f0xx_hal_def.h"
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/** @addtogroup PY32F0xx_HAL_Driver
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* @{
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*/
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/** @addtogroup RCCEx
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* @{
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*/
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/* Exported types ------------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
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* @{
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*/
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/**
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* @brief RCC extended clocks structure definition
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*/
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typedef struct
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{
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uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
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This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
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#if defined(RCC_CCIPR_PVDSEL)
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uint32_t PvdClockSelection; /*!< Specifies PVD clock source.
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This parameter can be a value of @ref RCCEx_PVD_Clock_Source */
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#endif
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#if defined(RCC_CCIPR_COMP1SEL)
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uint32_t Comp1ClockSelection; /*!< Specifies COMP1 clock source.
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This parameter can be a value of @ref RCCEx_COMP1_Clock_Source */
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#endif
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#if defined(RCC_CCIPR_COMP2SEL)
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uint32_t Comp2ClockSelection; /*!< Specifies COMP2 clock source.
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This parameter can be a value of @ref RCCEx_COMP2_Clock_Source */
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#endif
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#if defined(RCC_CCIPR_LPTIMSEL)
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uint32_t LptimClockSelection; /*!< Specifies LPTIM1 clock source
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This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
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#endif
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#if defined(RCC_BDCR_RTCSEL)
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uint32_t RTCClockSelection; /*!< Specifies RTC clock source.
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This parameter can be a value of @ref RCC_RTC_Clock_Source */
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#endif
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} RCC_PeriphCLKInitTypeDef;
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/**
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* @}
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*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
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* @{
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*/
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#if defined(RCC_BDCR_LSCOSEL)
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/** @defgroup RCCEx_LSCO_Clock_Source Low Speed Clock Source
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* @{
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*/
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#define RCC_LSCOSOURCE_LSI 0x00000000U /*!< LSI selection for low speed clock output */
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#if defined(RCC_LSE_SUPPORT)
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#define RCC_LSCOSOURCE_LSE RCC_BDCR_LSCOSEL /*!< LSE selection for low speed clock output */
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#endif
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/**
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* @}
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*/
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#endif
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/** @defgroup RCCEx_Periph_Clock_Selection Periph Clock Selection
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* @{
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*/
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#if defined(RCC_CCIPR_PVDSEL)
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#define RCC_PERIPHCLK_PVD 0x00000001U
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#endif /* RCC_CCIPR_PVDSEL */
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#if defined(RCC_CCIPR_COMP1SEL)
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#define RCC_PERIPHCLK_COMP1 0x00000002U
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#endif /* RCC_CCIPR_COMP1SEL */
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#if defined(RCC_CCIPR_COMP2SEL)
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#define RCC_PERIPHCLK_COMP2 0x00000020U
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#endif /* RCC_CCIPR_COMP2SEL */
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#if defined(RCC_CCIPR_LPTIMSEL)
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#define RCC_PERIPHCLK_LPTIM 0x00000200U
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#endif /* RCC_CCIPR_LPTIM1SEL */
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#if defined(RCC_CCIPR_ADCSEL)
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#define RCC_PERIPHCLK_ADC 0x00004000U
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#endif /* RCC_CCIPR_ADCSEL */
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#if defined(RCC_BDCR_RTCSEL)
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#define RCC_PERIPHCLK_RTC 0x00020000U
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#endif /* RCC_BDCR_RTCSEL */
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/**
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* @}
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*/
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#if defined(RCC_CCIPR_PVDSEL)
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/** @defgroup RCCEx_PVD_Clock_Source RCC PVD Clock Source
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* @{
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*/
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#define RCC_PVDCLKSOURCE_PCLK 0x00000000U /*!< APB clock selected as PVD clock */
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#define RCC_PVDCLKSOURCE_LSC RCC_CCIPR_PVDSEL /*!< LSC clock selected as PVD clock */
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/**
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* @}
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*/
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#endif
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#if defined(RCC_CCIPR_COMP1SEL)
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/** @defgroup RCCEx_COMP1_Clock_Source RCC COMP1 Clock Source
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* @{
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*/
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#define RCC_COMP1CLKSOURCE_PCLK 0x00000000U /*!< APB clock selected as COMP1 clock */
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#define RCC_COMP1CLKSOURCE_LSC RCC_CCIPR_COMP1SEL /*!< LSC clock selected as COMP1 clock */
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/**
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* @}
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*/
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#endif /* RCC_CCIPR_COMP1SEL */
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#if defined(RCC_CCIPR_COMP2SEL)
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/** @defgroup RCCEx_COMP2_Clock_Source RCC COMP2 Clock Source
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* @{
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*/
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#define RCC_COMP2CLKSOURCE_PCLK 0x00000000U /*!< APB clock selected as COMP2 clock */
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#define RCC_COMP2CLKSOURCE_LSC RCC_CCIPR_COMP2SEL /*!< LSC clock selected as COMP2 clock */
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/**
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* @}
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*/
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#endif /* RCC_CCIPR_COMP1SEL */
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#if defined(RCC_CCIPR_LPTIMSEL)
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/** @defgroup RCCEx_LPTIM1_Clock_Source RCC LPTIM1 Clock Source
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* @{
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*/
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#define RCC_LPTIMCLKSOURCE_PCLK 0x00000000U /*!< APB clock selected as LPTimer 1 clock */
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#define RCC_LPTIMCLKSOURCE_LSI RCC_CCIPR_LPTIMSEL_0 /*!< LSI clock selected as LPTimer 1 clock */
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#if defined(RCC_LSE_SUPPORT)
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#define RCC_LPTIMCLKSOURCE_LSE RCC_CCIPR_LPTIMSEL /*!< LSE clock selected as LPTimer 1 clock */
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#endif
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/**
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* @}
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*/
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#endif /* RCC_CCIPR_LPTIM1SEL */
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/**
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* @}
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*/
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/* Exported macros -----------------------------------------------------------*/
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/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
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* @{
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*/
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#if defined(RCC_CCIPR_PVDSEL)
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/** @brief Macro to configure the PVD clock (PVDCLK).
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*
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* @param __PVD_CLKSOURCE__ specifies the PVD clock source.
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* This parameter can be one of the following values:
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* @arg @ref RCC_PVDCLKSOURCE_PCLK PCLK selected as PVD clock
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* @arg @ref RCC_PVDCLKSOURCE_LSC LSC selected as PVD clock
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*/
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#define __HAL_RCC_PVD_CONFIG(__PVD_CLKSOURCE__) \
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MODIFY_REG(RCC->CCIPR, RCC_CCIPR_PVDSEL, (uint32_t)(__PVD_CLKSOURCE__))
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/** @brief Macro to get the PVD clock source.
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* @retval The clock source can be one of the following values:
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* @arg @ref RCC_PVDCLKSOURCE_PCLK PCLK selected as PVD clock
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* @arg @ref RCC_PVDCLKSOURCE_LSC LSC selected as PVD clock
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*/
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#define __HAL_RCC_GET_PVD_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_PVDSEL)))
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#endif /* RCC_CCIPR_PVDSEL */
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#if defined(RCC_CCIPR_COMP1SEL)
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/** @brief Macro to configure the COMP1 clock (COMP1CLK).
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*
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* @param __COMP1_CLKSOURCE__ specifies the COMP1 clock source.
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* This parameter can be one of the following values:
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* @arg @ref RCC_COMP1CLKSOURCE_PCLK PCLK selected as COMP1 clock
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* @arg @ref RCC_COMP1CLKSOURCE_HSI LSC selected as COMP1 clock
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*/
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#define __HAL_RCC_COMP1_CONFIG(__COMP1_CLKSOURCE__) \
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MODIFY_REG(RCC->CCIPR, RCC_CCIPR_COMP1SEL, (uint32_t)(__COMP1_CLKSOURCE__))
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/** @brief Macro to get the COMP1 clock source.
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* @retval The clock source can be one of the following values:
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* @arg @ref RCC_COMP1CLKSOURCE_PCLK1 PCLK selected as COMP1 clock
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* @arg @ref RCC_COMP1CLKSOURCE_HSI LSC selected as COMP1 clock
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*/
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#define __HAL_RCC_GET_COMP1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_COMP1SEL)))
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#endif /* RCC_CCIPR_COMP1SEL */
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#if defined(RCC_CCIPR_COMP2SEL)
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/** @brief Macro to configure the COMP2 clock (COMP2CLK).
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*
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* @param __COMP2_CLKSOURCE__ specifies the COMP2 clock source.
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* This parameter can be one of the following values:
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* @arg @ref RCC_COMP2CLKSOURCE_PCLK PCLK selected as COMP2 clock
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* @arg @ref RCC_COMP2CLKSOURCE_HSI LSC selected as COMP2 clock
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*/
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#define __HAL_RCC_COMP2_CONFIG(__COMP2_CLKSOURCE__) \
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MODIFY_REG(RCC->CCIPR, RCC_CCIPR_COMP2SEL, (uint32_t)(__COMP2_CLKSOURCE__))
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/** @brief Macro to get the COMP2 clock source.
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* @retval The clock source can be one of the following values:
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* @arg @ref RCC_COMP2CLKSOURCE_PCLK1 PCLK selected as COMP2 clock
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* @arg @ref RCC_COMP2CLKSOURCE_HSI LSC selected as COMP2 clock
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*/
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#define __HAL_RCC_GET_COMP2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_COMP2SEL)))
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#endif /* RCC_CCIPR_COMP2SEL */
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#if defined(RCC_CCIPR_LPUART1SEL)
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/** @brief Macro to configure the LPUART1 clock (LPUART1CLK).
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*
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* @param __LPUART1_CLKSOURCE__ specifies the LPUART1 clock source.
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* This parameter can be one of the following values:
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* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
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* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
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* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
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* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
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*/
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#define __HAL_RCC_LPUART1_CONFIG(__LPUART1_CLKSOURCE__) \
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MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1_CLKSOURCE__))
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/** @brief Macro to get the LPUART1 clock source.
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* @retval The clock source can be one of the following values:
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* @arg @ref RCC_LPUART1CLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
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* @arg @ref RCC_LPUART1CLKSOURCE_HSI HSI selected as LPUART1 clock
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* @arg @ref RCC_LPUART1CLKSOURCE_SYSCLK System Clock selected as LPUART1 clock
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* @arg @ref RCC_LPUART1CLKSOURCE_LSE LSE selected as LPUART1 clock
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*/
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#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
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#endif /* RCC_CCIPR_LPUART1SEL */
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#if defined(RCC_CCIPR_LPTIMSEL)
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/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
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*
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* @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
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* This parameter can be one of the following values:
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* @arg @ref RCC_LPTIM1CLKSOURCE_PCLK1 PCLK1 selected as LPTIM1 clock
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* @arg @ref RCC_LPTIM1CLKSOURCE_LSI HSI selected as LPTIM1 clock
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* @arg @ref RCC_LPTIM1CLKSOURCE_HSI LSI selected as LPTIM1 clock
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* @arg @ref RCC_LPTIM1CLKSOURCE_LSE LSE selected as LPTIM1 clock
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* @note Depending on devices and packages, some clocks may not be available.
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* Refer to device datasheet for clocks availability.
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*/
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#define __HAL_RCC_LPTIM_CONFIG(__LPTIM1_CLKSOURCE__) \
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MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIMSEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
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/** @brief Macro to get the LPTIM clock source.
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* @retval The clock source can be one of the following values:
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* @arg @ref RCC_LPTIMCLKSOURCE_PCLK1 PCLK1 selected as LPUART1 clock
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* @arg @ref RCC_LPTIMCLKSOURCE_LSI HSI selected as LPUART1 clock
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* @arg @ref RCC_LPTIMCLKSOURCE_LSE LSE selected as LPUART1 clock
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* @note Depending on devices and packages, some clocks may not be available.
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* Refer to device datasheet for clocks availability.
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*/
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#define __HAL_RCC_GET_LPTIM_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIMSEL)))
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#endif /* RCC_CCIPR_LPTIM1SEL */
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#if defined(RCC_CCIPR_TIM1SEL)
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/** @brief Macro to configure the TIM1 interface clock
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* @param __TIM1_CLKSOURCE__ specifies the TIM1 digital interface clock source.
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* This parameter can be one of the following values:
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* @arg @ref RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock
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* @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock
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*/
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#define __HAL_RCC_TIM1_CONFIG(__TIM1_CLKSOURCE__) \
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MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM1SEL, (uint32_t)(__TIM1_CLKSOURCE__))
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/** @brief Macro to get the TIM1 clock source.
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* @retval The clock source can be one of the following values:
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* @arg @ref RCC_TIM1CLKSOURCE_PLL PLLQ Output Clock selected as TIM1 clock
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* @arg @ref RCC_TIM1CLKSOURCE_PCLK1 System Clock selected as TIM1 clock
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*/
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#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM1SEL)))
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#endif /* RCC_CCIPR_TIM1SEL */
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#if defined(RCC_CCIPR_TIM15SEL)
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/** @brief Macro to configure the TIM15 interface clock
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* @param __TIM15_CLKSOURCE__ specifies the TIM15 digital interface clock source.
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* This parameter can be one of the following values:
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* @arg RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock
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* @arg RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock
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*/
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#define __HAL_RCC_TIM15_CONFIG(__TIM15_CLKSOURCE__) \
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MODIFY_REG(RCC->CCIPR, RCC_CCIPR_TIM15SEL, (uint32_t)(__TIM15_CLKSOURCE__))
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/** @brief Macro to get the TIM15 clock source.
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* @retval The clock source can be one of the following values:
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* @arg @ref RCC_TIM15CLKSOURCE_PLL PLLQ Output Clock selected as TIM15 clock
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* @arg @ref RCC_TIM15CLKSOURCE_PCLK1 System Clock selected as TIM15 clock
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*/
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#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_TIM15SEL)))
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#endif /* RCC_CCIPR_TIM15SEL */
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/** @defgroup RCCEx_Flags_Interrupts_Management Flags Interrupts Management
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* @brief macros to manage the specified RCC Flags and interrupts.
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* @{
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported functions --------------------------------------------------------*/
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/** @addtogroup RCCEx_Exported_Functions
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* @{
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*/
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/** @addtogroup RCCEx_Exported_Functions_Group1
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* @{
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*/
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HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
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void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
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uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
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/**
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* @}
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*/
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/** @addtogroup RCCEx_Exported_Functions_Group2
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* @{
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*/
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#if defined(RCC_BDCR_LSCOEN)
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void HAL_RCCEx_EnableLSCO(uint32_t LSCOSource);
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void HAL_RCCEx_DisableLSCO(void);
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#endif
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Private macros ------------------------------------------------------------*/
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/** @defgroup RCCEx_Private_Macros RCCEx Private Macros
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* @{
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*/
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#if defined(RCC_BDCR_LSCOSEL)
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#if defined(RCC_LSE_SUPPORT)
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#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI) || \
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((__SOURCE__) == RCC_LSCOSOURCE_LSE))
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#else
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#define IS_RCC_LSCOSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LSCOSOURCE_LSI))
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#endif
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#endif
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#if defined(RCC_LSE_SUPPORT)
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#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
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(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \
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((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
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((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
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((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
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#else
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#define IS_RCC_USART1CLKSOURCE(__SOURCE__) \
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(((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK1) || \
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((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
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((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
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#endif
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#if defined(RCC_CCIPR_PVDSEL)
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#define IS_RCC_PVDCLKSOURCE(__SOURCE__) \
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(((__SOURCE__) == RCC_PVDCLKSOURCE_PCLK) || \
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((__SOURCE__) == RCC_PVDCLKSOURCE_LSC))
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#endif /* RCC_CCIPR_PVDSEL */
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#if defined(RCC_CCIPR_COMP1SEL)
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#define IS_RCC_COMP1CLKSOURCE(__SOURCE__) \
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(((__SOURCE__) == RCC_COMP1CLKSOURCE_PCLK) || \
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((__SOURCE__) == RCC_COMP1CLKSOURCE_LSC))
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#endif /* RCC_CCIPR_COMP1SEL */
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#if defined(RCC_CCIPR_COMP2SEL)
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#define IS_RCC_COMP2CLKSOURCE(__SOURCE__) \
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(((__SOURCE__) == RCC_COMP2CLKSOURCE_PCLK) || \
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((__SOURCE__) == RCC_COMP2CLKSOURCE_LSC))
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#endif /* RCC_CCIPR_COMP2SEL */
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#if defined(RCC_CCIPR_LPTIMSEL)
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#if defined(RCC_LSE_SUPPORT)
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#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \
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(((__SOURCE__) == RCC_LPTIMCLKSOURCE_PCLK)|| \
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((__SOURCE__) == RCC_LPTIMCLKSOURCE_LSI) || \
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((__SOURCE__) == RCC_LPTIMCLKSOURCE_LSE))
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#else
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#define IS_RCC_LPTIM1CLKSOURCE(__SOURCE__) \
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(((__SOURCE__) == RCC_LPTIMCLKSOURCE_PCLK)|| \
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((__SOURCE__) == RCC_LPTIMCLKSOURCE_LSI))
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#endif
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#endif /* RCC_CCIPR_LPTIM1SEL */
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#if defined(PY32F002APRE)
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#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
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((((__SELECTION__) & RCC_PERIPHCLK_LPTIM) == RCC_PERIPHCLK_LPTIM))
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#else
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#define IS_RCC_PERIPHCLOCK(__SELECTION__) \
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((((__SELECTION__) & RCC_PERIPHCLK_COMP1) == RCC_PERIPHCLK_COMP1) || \
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(((__SELECTION__) & RCC_PERIPHCLK_COMP2) == RCC_PERIPHCLK_COMP2) || \
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(((__SELECTION__) & RCC_PERIPHCLK_PVD) == RCC_PERIPHCLK_PVD) || \
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(((__SELECTION__) & RCC_PERIPHCLK_LPTIM) == RCC_PERIPHCLK_LPTIM) || \
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(((__SELECTION__) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
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#endif
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif
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#endif /* __PY32F0xx_HAL_RCC_EX_H */
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/************************ (C) COPYRIGHT Puya *****END OF FILE****/
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