mirror of
https://github.com/IcedRooibos/py32f0-template.git
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597 lines
20 KiB
C
597 lines
20 KiB
C
/**
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******************************************************************************
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* @file py32f0xx_ll_bus.h
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* @author MCU Application Team
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* @brief Header file of BUS LL module.
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@verbatim
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##### RCC Limitations #####
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==============================================================================
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[..]
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A delay between an RCC peripheral clock enable and the effective peripheral
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enabling should be taken into account in order to manage the peripheral read/write
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from/to registers.
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(+) This delay depends on the peripheral mapping.
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(++) AHB & APB1 peripherals, 1 dummy read is necessary
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[..]
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Workarounds:
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(#) For AHB & APB1 peripherals, a dummy read to the peripheral register has been
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inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
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@endverbatim
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******************************************************************************
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* @attention
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*
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* <h2><center>© Copyright (c) Puya Semiconductor Co.
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* All rights reserved.</center></h2>
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*
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* <h2><center>© Copyright (c) 2016 STMicroelectronics.
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* All rights reserved.</center></h2>
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*
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* This software component is licensed by ST under BSD 3-Clause license,
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* the "License"; You may not use this file except in compliance with the
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* License. You may obtain a copy of the License at:
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* opensource.org/licenses/BSD-3-Clause
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*
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******************************************************************************
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*/
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/* Define to prevent recursive inclusion -------------------------------------*/
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#ifndef PY32F0XX_LL_BUS_H
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#define PY32F0XX_LL_BUS_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* Includes ------------------------------------------------------------------*/
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#include "py32f0xx.h"
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/** @addtogroup py32f0xx_LL_Driver
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* @{
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*/
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#if defined(RCC)
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/** @defgroup BUS_LL BUS
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* @{
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*/
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/* Private types -------------------------------------------------------------*/
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/* Private variables ---------------------------------------------------------*/
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/* Private constants ---------------------------------------------------------*/
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/* Private macros ------------------------------------------------------------*/
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/* Exported types ------------------------------------------------------------*/
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/* Exported constants --------------------------------------------------------*/
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/** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
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* @{
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*/
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/** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
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* @{
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*/
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#define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#if (defined(DMA) || defined(DMA1))
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#define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHBENR_DMAEN
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#endif
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#define LL_AHB1_GRP1_PERIPH_FLASH RCC_AHBENR_FLASHEN
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#define LL_AHB1_GRP1_PERIPH_SRAM RCC_AHBENR_SRAMEN
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#define LL_AHB1_GRP1_PERIPH_CRC RCC_AHBENR_CRCEN
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
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* @{
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*/
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#define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#if defined(TIM3)
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#define LL_APB1_GRP1_PERIPH_TIM3 RCC_APBENR1_TIM3EN
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#endif
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#if defined(RTC)
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#define LL_APB1_GRP1_PERIPH_RTC RCC_APBENR1_RTCAPBEN
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#endif
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#if defined(WWDG)
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#define LL_APB1_GRP1_PERIPH_WWDG RCC_APBENR1_WWDGEN
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#endif
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#if defined(SPI2)
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#define LL_APB1_GRP1_PERIPH_SPI2 RCC_APBENR1_SPI2EN
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#endif
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#if defined(USART2)
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#define LL_APB1_GRP1_PERIPH_USART2 RCC_APBENR1_USART2EN
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#endif
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#define LL_APB1_GRP1_PERIPH_I2C1 RCC_APBENR1_I2CEN
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#define LL_APB1_GRP1_PERIPH_DBGMCU RCC_APBENR1_DBGEN
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#define LL_APB1_GRP1_PERIPH_PWR RCC_APBENR1_PWREN
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#define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APBENR1_LPTIMEN
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_APB1_GRP2_PERIPH APB1 GRP2 PERIPH
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* @{
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*/
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#define LL_APB1_GRP2_PERIPH_ALL 0xFFFFFFFFU
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#define LL_APB1_GRP2_PERIPH_SYSCFG RCC_APBENR2_SYSCFGEN
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#define LL_APB1_GRP2_PERIPH_TIM1 RCC_APBENR2_TIM1EN
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#define LL_APB1_GRP2_PERIPH_SPI1 RCC_APBENR2_SPI1EN
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#define LL_APB1_GRP2_PERIPH_USART1 RCC_APBENR2_USART1EN
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#if defined(TIM14)
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#define LL_APB1_GRP2_PERIPH_TIM14 RCC_APBENR2_TIM14EN
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#endif
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#define LL_APB1_GRP2_PERIPH_TIM16 RCC_APBENR2_TIM16EN
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#if defined(TIM17)
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#define LL_APB1_GRP2_PERIPH_TIM17 RCC_APBENR2_TIM17EN
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#endif
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#define LL_APB1_GRP2_PERIPH_ADC1 RCC_APBENR2_ADCEN
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#if defined(COMP1)
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#define LL_APB1_GRP2_PERIPH_COMP1 RCC_APBENR2_COMP1EN
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#endif
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#if defined(COMP2)
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#define LL_APB1_GRP2_PERIPH_COMP2 RCC_APBENR2_COMP2EN
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#endif
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#if defined(LED)
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#define LL_APB1_GRP2_PERIPH_LED RCC_APBENR2_LEDEN
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#endif
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EC_IOP_GRP1_PERIPH IOP GRP1 PERIPH
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* @{
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*/
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#define LL_IOP_GRP1_PERIPH_ALL 0xFFFFFFFFU
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#define LL_IOP_GRP1_PERIPH_GPIOA RCC_IOPENR_GPIOAEN
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#define LL_IOP_GRP1_PERIPH_GPIOB RCC_IOPENR_GPIOBEN
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#define LL_IOP_GRP1_PERIPH_GPIOF RCC_IOPENR_GPIOFEN
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/**
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* @}
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*/
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/**
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* @}
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*/
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/* Exported macro ------------------------------------------------------------*/
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/* Exported functions --------------------------------------------------------*/
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/** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
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* @{
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*/
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/** @defgroup BUS_LL_EF_AHB1 AHB1
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* @{
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*/
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/**
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* @brief Enable AHB1 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
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{
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__IO uint32_t tmpreg;
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SET_BIT(RCC->AHBENR, Periphs);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->AHBENR, Periphs);
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(void)tmpreg;
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}
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/**
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* @brief Check if AHB1 peripheral clock is enabled or not
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval State of Periphs (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
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{
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return ((READ_BIT(RCC->AHBENR, Periphs) == Periphs) ? 1UL : 0UL);
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}
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/**
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* @brief Disable AHB1 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_FLASH
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* @arg @ref LL_AHB1_GRP1_PERIPH_SRAM
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->AHBENR, Periphs);
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}
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/**
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* @brief Force AHB1 peripherals reset.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
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{
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SET_BIT(RCC->AHBRSTR, Periphs);
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}
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/**
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* @brief Release AHB1 peripherals reset.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_AHB1_GRP1_PERIPH_ALL
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* @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
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* @arg @ref LL_AHB1_GRP1_PERIPH_CRC
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->AHBRSTR, Periphs);
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}
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EF_APB1_GRP1 APB1 GRP1
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* @{
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*/
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/**
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* @brief Enable APB1 GRP1 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
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* @arg @ref LL_APB1_GRP1_PERIPH_RTC
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* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
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* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
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* @arg @ref LL_APB1_GRP1_PERIPH_USART2
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* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
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* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
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* @arg @ref LL_APB1_GRP1_PERIPH_PWR
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* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
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{
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__IO uint32_t tmpreg;
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SET_BIT(RCC->APBENR1, Periphs);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->APBENR1, Periphs);
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(void)tmpreg;
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}
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/**
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* @brief Check if APB1 GRP1 peripheral clock is enabled or not
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
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* @arg @ref LL_APB1_GRP1_PERIPH_RTC
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* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
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* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
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* @arg @ref LL_APB1_GRP1_PERIPH_USART2
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* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
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* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
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* @arg @ref LL_APB1_GRP1_PERIPH_PWR
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* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval State of Periphs (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
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{
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return ((READ_BIT(RCC->APBENR1, Periphs) == (Periphs)) ? 1UL : 0UL);
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}
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/**
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* @brief Disable APB1 GRP1 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
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* @arg @ref LL_APB1_GRP1_PERIPH_RTC
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* @arg @ref LL_APB1_GRP1_PERIPH_WWDG
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* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
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* @arg @ref LL_APB1_GRP1_PERIPH_USART2
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* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
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* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
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* @arg @ref LL_APB1_GRP1_PERIPH_PWR
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* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->APBENR1, Periphs);
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}
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/**
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* @brief Force APB1 GRP1 peripherals reset.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
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* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
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* @arg @ref LL_APB1_GRP1_PERIPH_USART2
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* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
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* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
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* @arg @ref LL_APB1_GRP1_PERIPH_PWR
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* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
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{
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SET_BIT(RCC->APBRSTR1, Periphs);
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}
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/**
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* @brief Release APB1 GRP1 peripherals reset.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP1_PERIPH_TIM3
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* @arg @ref LL_APB1_GRP1_PERIPH_SPI2
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* @arg @ref LL_APB1_GRP1_PERIPH_USART2
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* @arg @ref LL_APB1_GRP1_PERIPH_I2C1
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* @arg @ref LL_APB1_GRP1_PERIPH_DBGMCU
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* @arg @ref LL_APB1_GRP1_PERIPH_PWR
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* @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->APBRSTR1, Periphs);
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}
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EF_APB1_GRP2 APB1 GRP2
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* @{
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*/
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/**
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* @brief Enable APB1 GRP2 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
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* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
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* @arg @ref LL_APB1_GRP2_PERIPH_USART1
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM14
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
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* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
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* @arg @ref LL_APB1_GRP2_PERIPH_COMP1
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* @arg @ref LL_APB1_GRP2_PERIPH_COMP2
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* @arg @ref LL_APB1_GRP2_PERIPH_LED
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_APB1_GRP2_EnableClock(uint32_t Periphs)
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{
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__IO uint32_t tmpreg;
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SET_BIT(RCC->APBENR2, Periphs);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->APBENR2, Periphs);
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(void)tmpreg;
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}
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/**
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* @brief Check if APB1 GRP2 peripheral clock is enabled or not
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
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* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
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* @arg @ref LL_APB1_GRP2_PERIPH_USART1
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM14
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
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* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
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* @arg @ref LL_APB1_GRP2_PERIPH_COMP1
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* @arg @ref LL_APB1_GRP2_PERIPH_COMP2
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* @arg @ref LL_APB1_GRP2_PERIPH_LED
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval State of Periphs (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_APB1_GRP2_IsEnabledClock(uint32_t Periphs)
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{
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return ((READ_BIT(RCC->APBENR2, Periphs) == (Periphs)) ? 1UL : 0UL);
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}
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/**
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* @brief Disable APB1 GRP2 peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
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* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
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* @arg @ref LL_APB1_GRP2_PERIPH_USART1
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM14
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
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* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
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* @arg @ref LL_APB1_GRP2_PERIPH_COMP1
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* @arg @ref LL_APB1_GRP2_PERIPH_COMP2
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* @arg @ref LL_APB1_GRP2_PERIPH_LED
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_APB1_GRP2_DisableClock(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->APBENR2, Periphs);
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}
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/**
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* @brief Force APB1 GRP2 peripherals reset.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP2_PERIPH_ALL
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* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
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* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
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* @arg @ref LL_APB1_GRP2_PERIPH_USART1
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM14
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
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* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
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* @arg @ref LL_APB1_GRP2_PERIPH_COMP1
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* @arg @ref LL_APB1_GRP2_PERIPH_COMP2
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* @arg @ref LL_APB1_GRP2_PERIPH_LED
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @retval None
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*/
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__STATIC_INLINE void LL_APB1_GRP2_ForceReset(uint32_t Periphs)
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{
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SET_BIT(RCC->APBRSTR2, Periphs);
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}
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/**
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* @brief Release APB1 GRP2 peripherals reset.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_APB1_GRP2_PERIPH_ALL
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* @arg @ref LL_APB1_GRP2_PERIPH_SYSCFG
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM1
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* @arg @ref LL_APB1_GRP2_PERIPH_SPI1
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* @arg @ref LL_APB1_GRP2_PERIPH_USART1
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM14
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM16
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* @arg @ref LL_APB1_GRP2_PERIPH_TIM17
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* @arg @ref LL_APB1_GRP2_PERIPH_ADC1
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* @arg @ref LL_APB1_GRP2_PERIPH_COMP1
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* @arg @ref LL_APB1_GRP2_PERIPH_COMP2
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* @arg @ref LL_APB1_GRP2_PERIPH_LED
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* @note Depending on devices and packages, some peripherals may not be available.
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* Refer to device datasheet for peripherals availability.
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* @note (*) peripheral not available on all devices
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* @retval None
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*/
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__STATIC_INLINE void LL_APB1_GRP2_ReleaseReset(uint32_t Periphs)
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{
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CLEAR_BIT(RCC->APBRSTR2, Periphs);
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}
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/**
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* @}
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*/
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/** @defgroup BUS_LL_EF_IOP IOP
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* @{
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*/
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/**
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* @brief Enable IOP peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
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* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
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* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
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* @retval None
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*/
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__STATIC_INLINE void LL_IOP_GRP1_EnableClock(uint32_t Periphs)
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{
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__IO uint32_t tmpreg;
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SET_BIT(RCC->IOPENR, Periphs);
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/* Delay after an RCC peripheral clock enabling */
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tmpreg = READ_BIT(RCC->IOPENR, Periphs);
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(void)tmpreg;
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}
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/**
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* @brief Check if IOP peripheral clock is enabled or not
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
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* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
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* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
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* @retval State of Periphs (1 or 0).
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*/
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__STATIC_INLINE uint32_t LL_IOP_GRP1_IsEnabledClock(uint32_t Periphs)
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{
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return ((READ_BIT(RCC->IOPENR, Periphs) == Periphs) ? 1UL : 0UL);
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}
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/**
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* @brief Disable IOP peripherals clock.
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* @param Periphs This parameter can be a combination of the following values:
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* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
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* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
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* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
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* @retval None
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*/
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__STATIC_INLINE void LL_IOP_GRP1_DisableClock(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->IOPENR, Periphs);
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|
}
|
|
|
|
/**
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|
* @brief Disable IOP peripherals clock.
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_ALL
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|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
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* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
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|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
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|
* @retval None
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|
*/
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__STATIC_INLINE void LL_IOP_GRP1_ForceReset(uint32_t Periphs)
|
|
{
|
|
SET_BIT(RCC->IOPRSTR, Periphs);
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|
}
|
|
|
|
/**
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|
* @brief Release IOP peripherals reset.
|
|
* @param Periphs This parameter can be a combination of the following values:
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_ALL
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|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOA
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOB
|
|
* @arg @ref LL_IOP_GRP1_PERIPH_GPIOF
|
|
* @retval None
|
|
*/
|
|
__STATIC_INLINE void LL_IOP_GRP1_ReleaseReset(uint32_t Periphs)
|
|
{
|
|
CLEAR_BIT(RCC->IOPRSTR, Periphs);
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|
}
|
|
/**
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|
* @}
|
|
*/
|
|
|
|
|
|
/**
|
|
* @}
|
|
*/
|
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|
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/**
|
|
* @}
|
|
*/
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|
#endif /* RCC */
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/**
|
|
* @}
|
|
*/
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|
|
|
#ifdef __cplusplus
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|
}
|
|
#endif
|
|
|
|
#endif /* PY32F0XX_LL_BUS_H */
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/************************ (C) COPYRIGHT Puya *****END OF FILE****/
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