mirror of
https://github.com/IcedRooibos/py32f0-template.git
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453 lines
14 KiB
C
453 lines
14 KiB
C
/* -----------------------------------------------------------------------------
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* Copyright (c) 2014 - 2019 ARM Ltd.
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*
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* This software is provided 'as-is', without any express or implied warranty.
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* In no event will the authors be held liable for any damages arising from
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* the use of this software. Permission is granted to anyone to use this
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* software for any purpose, including commercial applications, and to alter
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* it and redistribute it freely, subject to the following restrictions:
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*
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* 1. The origin of this software must not be misrepresented; you must not
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* claim that you wrote the original software. If you use this software in
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* a product, an acknowledgment in the product documentation would be
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* appreciated but is not required.
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*
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* 2. Altered source versions must be plainly marked as such, and must not be
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* misrepresented as being the original software.
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*
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* 3. This notice may not be removed or altered from any source distribution.
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*
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*
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* $Date: 2021-7-1
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* $Revision: V1.0.0
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*
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* Project: Flash Programming Functions for Puya PY32F030xx Flash
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* --------------------------------------------------------------------------- */
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/* History:
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* Version 1.0.0
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* Initial release
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*/
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#include "FlashOS.h" // FlashOS Structures
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#include "py32f0xx.h"
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typedef volatile unsigned char vu8;
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typedef unsigned char u8;
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typedef volatile unsigned short vu16;
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typedef unsigned short u16;
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typedef volatile unsigned long vu32;
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typedef unsigned long u32;
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#define M8(adr) (*((vu8 *) (adr)))
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#define M16(adr) (*((vu16 *) (adr)))
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#define M32(adr) (*((vu32 *) (adr)))
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//uint32_t gdw_HSI_FS;
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//#define USE_HSI_24MHZ
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////uiOffset = 0(4MHz), 1(8MHz), 2(16MHz), 3(22.12MHz), 4(24MHz)
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//void SetFlashParameter(uint32_t uiOffset)
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//{
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// FLASH->TS0 = ((M32(0x1FFF0F1C + uiOffset * 0x14) >> 0) & 0x000000FF);
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// FLASH->TS3 = ((M32(0x1FFF0F1C + uiOffset * 0x14) >> 8) & 0x000000FF);
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// FLASH->TS1 = ((M32(0x1FFF0F1C + uiOffset * 0x14) >> 16) & 0x000001FF);
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// FLASH->TS2P = ((M32(0x1FFF0F20 + uiOffset * 0x14) >> 0) & 0x000000FF);
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// FLASH->TPS3 = ((M32(0x1FFF0F20 + uiOffset * 0x14) >> 16) & 0x000007FF);
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// FLASH->PERTPE = ((M32(0x1FFF0F24 + uiOffset * 0x14) >> 0) & 0x0001FFFF);
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// FLASH->SMERTPE = ((M32(0x1FFF0F28 + uiOffset * 0x14) >> 0) & 0x0001FFFF);
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// FLASH->PRGTPE = ((M32(0x1FFF0F2C + uiOffset * 0x14) >> 0) & 0x0000FFFF);
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// FLASH->PRETPE = ((M32(0x1FFF0F2C + uiOffset * 0x14) >> 16) & 0x0000FFFF);
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//}
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//void InitRccAndFlashParam(void)
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//{
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//#ifdef USE_HSI_24MHZ
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// gdw_HSI_FS = READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS);
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// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_FS, RCC_ICSCR_HSI_FS_2);//HSI_24MHz
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// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F10)&RCC_ICSCR_HSI_TRIM);
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// while (RCC_CR_HSIRDY != READ_BIT(RCC->CR, RCC_CR_HSIRDY));
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// SetFlashParameter(4);
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//#else
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// uint32_t dwOffset;
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// switch (READ_BIT(RCC->ICSCR, RCC_ICSCR_HSI_FS))
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// {
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// default://4MHz
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// dwOffset = 0x00;
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// break;
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// case RCC_ICSCR_HSI_FS_0://8MHz
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// dwOffset = 0x01;
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// break;
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// case RCC_ICSCR_HSI_FS_1://16MHz
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// dwOffset = 0x02;
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// break;
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// case (RCC_ICSCR_HSI_FS_1|RCC_ICSCR_HSI_FS_0)://22.12MHz
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// dwOffset = 0x03;
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// break;
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// case RCC_ICSCR_HSI_FS_2://24MHz
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// dwOffset = 0x04;
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// break;
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// }
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// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F00 + dwOffset * 4)&RCC_ICSCR_HSI_TRIM);
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// WRITE_REG(FLASH->TS0, ((M32(0x1FFF0F1C + dwOffset * 0x14) >> 0) & 0x000000FF));
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// WRITE_REG(FLASH->TS1, ((M32(0x1FFF0F1C + dwOffset * 0x14) >> 8) & 0x000000FF));
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// WRITE_REG(FLASH->TS3, ((M32(0x1FFF0F1C + dwOffset * 0x14) >> 16) & 0x000001FF));
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// WRITE_REG(FLASH->TS2P, ((M32(0x1FFF0F20 + dwOffset * 0x14) >> 0) & 0x000000FF));
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// WRITE_REG(FLASH->TPS3, ((M32(0x1FFF0F20 + dwOffset * 0x14) >> 16) & 0x000007FF));
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// WRITE_REG(FLASH->PERTPE, ((M32(0x1FFF0F24 + dwOffset * 0x14) >> 0) & 0x0001FFFF));
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// WRITE_REG(FLASH->SMERTPE, ((M32(0x1FFF0F28 + dwOffset * 0x14) >> 0) & 0x0001FFFF));
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// WRITE_REG(FLASH->PRGTPE, ((M32(0x1FFF0F2C + dwOffset * 0x14) >> 0) & 0x0000FFFF));
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// WRITE_REG(FLASH->PRETPE, ((M32(0x1FFF0F2C + dwOffset * 0x14) >> 16) & 0x00000FFF));
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//#endif
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//}
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//void UnInitRccAndFlashParam(void)
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//{
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//#ifdef USE_HSI_24MHZ
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// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_FS, gdw_HSI_FS);
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// switch (gdw_HSI_FS)
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// {
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// case RCC_ICSCR_HSI_FS_2://24MHz
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// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F10)&RCC_ICSCR_HSI_TRIM);
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// break;
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// case (RCC_ICSCR_HSI_FS_1|RCC_ICSCR_HSI_FS_0)://22.12MHz
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// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F0C)&RCC_ICSCR_HSI_TRIM);
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// break;
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// case RCC_ICSCR_HSI_FS_1://16MHz
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// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F08)&RCC_ICSCR_HSI_TRIM);
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// break;
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// case RCC_ICSCR_HSI_FS_0://8MHz
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// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F04)&RCC_ICSCR_HSI_TRIM);
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// break;
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// default://4MHz
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// MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSI_TRIM, M32(0x1FFF0F00)&RCC_ICSCR_HSI_TRIM);
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// break;
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// }
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// while (RCC_CR_HSIRDY != READ_BIT(RCC->CR, RCC_CR_HSIRDY));
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//#endif
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//}
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/*
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* Initialize Flash Programming Functions
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* Parameter: adr: Device Base Address
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* clk: Clock Frequency (Hz)
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* fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify)
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* Return Value: 0 - OK, 1 - Failed
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*/
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#ifdef FLASH_MEM
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int Init(unsigned long adr, unsigned long clk, unsigned long fnc)
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{
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// InitRccAndFlashParam();
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FLASH->KEYR = FLASH_KEY1; // Unlock Flash
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FLASH->KEYR = FLASH_KEY2;
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FLASH->ACR = 0x00000000; // Zero Wait State, no Prefetch
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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if ((FLASH->OPTR & FLASH_OPTR_IWDG_SW) == 0x00) // Test if IWDG is running (IWDG in HW mode)
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{
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// Set IWDG time out to ~32.768 second
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IWDG->KR = 0x5555; // Enable write access to IWDG_PR and IWDG_RLR
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IWDG->PR = 0x06; // Set prescaler to 256
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IWDG->RLR = 0xFFF; // Set reload value to 4095
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}
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return (0);
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}
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#endif
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#ifdef FLASH_OPT
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int Init(unsigned long adr, unsigned long clk, unsigned long fnc)
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{
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InitRccAndFlashParam();
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FLASH->KEYR = FLASH_KEY1; // Unlock Flash
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FLASH->KEYR = FLASH_KEY2;
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FLASH->OPTKEYR = FLASH_OPTKEY1; // Unlock Option Bytes
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FLASH->OPTKEYR = FLASH_OPTKEY2;
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FLASH->ACR = 0x00000000; // Zero Wait State, no Prefetch
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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if ((FLASH->OPTR & 0x1000) == 0x00) // Test if IWDG is running (IWDG in HW mode)
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{
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// Set IWDG time out to ~32.768 second
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IWDG->KR = 0x5555; // Enable write access to IWDG_PR and IWDG_RLR
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IWDG->PR = 0x06; // Set prescaler to 256
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IWDG->RLR = 0xFFF; // Set reload value to 4095
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}
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return (0);
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}
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#endif
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/*
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* De-Initialize Flash Programming Functions
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* Parameter: fnc: Function Code (1 - Erase, 2 - Program, 3 - Verify)
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* Return Value: 0 - OK, 1 - Failed
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*/
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#ifdef FLASH_MEM
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int UnInit(unsigned long fnc)
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{
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// UnInitRccAndFlashParam();
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FLASH->CR |= FLASH_CR_LOCK; // Lock Flash
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return (0);
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}
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#endif
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#ifdef FLASH_OPT
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int UnInit(unsigned long fnc)
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{
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UnInitRccAndFlashParam();
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FLASH->CR |= FLASH_CR_LOCK; // Lock Flash
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FLASH->CR |= FLASH_CR_OPTLOCK; // Lock Option Bytes
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return (0);
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}
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#endif
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/*
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* Erase complete Flash Memory
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* Return Value: 0 - OK, 1 - Failed
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*/
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#ifdef FLASH_MEM
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int EraseChip(void)
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{
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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FLASH->CR |= FLASH_CR_MER; // Mass Erase Enabled
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FLASH->CR |= FLASH_CR_EOPIE;
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M32(0x08000000) = 0xFF;
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__asm("DSB");
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while (FLASH->SR & FLASH_SR_BSY)
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{
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IWDG->KR = 0xAAAA; // Reload IWDG
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}
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FLASH->CR &= ~FLASH_CR_MER; // Mass Erase Disabled
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FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE
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if (FLASH_SR_EOP != (FLASH->SR & FLASH_SR_EOP)) // Check for FLASH_SR_EOP
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{
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FLASH->SR |= FLASH_SR_EOP;
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return (1); // Failed
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}
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return (0); // Done
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}
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#endif
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#ifdef FLASH_OPT
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int EraseChip(void)
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{
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/* erase chip is not needed for
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- Flash Option bytes
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- Flash One Time Programmable bytes
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*/
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return (0); // Done
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}
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#endif
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/*
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* Erase Sector in Flash Memory
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* Parameter: adr: Sector Address
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* Return Value: 0 - OK, 1 - Failed
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*/
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#ifdef FLASH_MEM
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int EraseSector(unsigned long adr)
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{
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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FLASH->CR |= FLASH_CR_SER; // Sector Erase Enabled
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FLASH->CR |= FLASH_CR_EOPIE;
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M32(adr) = 0xFF; // Sector Address
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__asm("DSB");
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while (FLASH->SR & FLASH_SR_BSY)
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{
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IWDG->KR = 0xAAAA; // Reload IWDG
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}
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FLASH->CR &= ~FLASH_CR_SER; // Sector Erase Disabled
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FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE
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// if (FLASH_EOP != (FLASH->SR & FLASH_EOP)) { // Check for FLASH_SR_EOP
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// FLASH->SR |= FLASH_EOP;
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// return (1); // Failed
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// }
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return (0); // Done
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}
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#endif
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#ifdef FLASH_OPT
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int EraseSector(unsigned long adr)
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{
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/* erase sector is not needed for
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- Flash Option bytes
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- Flash One Time Programmable bytes
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*/
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return (0); // Done
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}
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#endif
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/*
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* Blank Check Checks if Memory is Blank
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* Parameter: adr: Block Start Address
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* sz: Block Size (in bytes)
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* pat: Block Pattern
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* Return Value: 0 - OK, 1 - Failed
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*/
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int BlankCheck(unsigned long adr, unsigned long sz, unsigned char pat)
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{
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return (1); // Always Force Erase
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}
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/*
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* Program Page in Flash Memory
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* Parameter: adr: Page Start Address
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* sz: Page Size
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* buf: Page Data
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* Return Value: 0 - OK, 1 - Failed
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*/
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#ifdef FLASH_MEM
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int ProgramPage(unsigned long adr, unsigned long sz, unsigned char *buf)
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{
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sz = (sz + 127) & ~127; // Adjust size for 32 Words
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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while (sz)
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{
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FLASH->CR |= FLASH_CR_PG; // Programming Enabled
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FLASH->CR |= FLASH_CR_EOPIE;
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for (u8 i = 0; i < 32; i++)
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{
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M32(adr + i * 4) = *((u32 *)(buf + i * 4)); // Program the first word of the Double Word
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if (i == 30)
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{
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FLASH->CR |= FLASH_CR_PGSTRT;
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}
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}
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__asm("DSB");
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while (FLASH->SR & FLASH_SR_BSY)
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{
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IWDG->KR = 0xAAAA; // Reload IWDG
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}
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FLASH->CR &= ~FLASH_CR_PG; // Programming Disabled
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FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE
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//Ϊ<><CEAA><EFBFBD>ܹ<EFBFBD>Program SRAM<41><4D><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>EOP<4F><50><EFBFBD><EFBFBD>
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// if (FLASH_EOP != (FLASH->SR & FLASH_EOP)) { // Check for FLASH_SR_EOP
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// FLASH->SR |= FLASH_EOP;
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// return (1); // Failed
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// }
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adr += 128; // Go to next Page
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buf += 128;
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sz -= 128;
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}
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return (0); // Done
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}
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#endif // PY32F030xx_64 || FLASH_OTP
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#ifdef FLASH_OPT
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int ProgramPage(unsigned long adr, unsigned long sz, unsigned char *buf)
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{
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u32 optr;
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u32 sdkr;
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u32 wrpr;
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optr = *((u32 *)(buf + 0x00));
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sdkr = *((u32 *)(buf + 0x04));
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wrpr = *((u32 *)(buf + 0x0C));
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FLASH->SR |= FLASH_SR_EOP; // Reset FLASH_EOP
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FLASH->OPTR = (optr & 0x0000FFFF); // Write OPTR values
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FLASH->SDKR = (sdkr & 0x0000FFFF); // Write SDKR values
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FLASH->WRPR = (wrpr & 0x0000FFFF); // Write WRPR values
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FLASH->CR |= FLASH_CR_OPTSTRT;
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FLASH->CR |= FLASH_CR_EOPIE;
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M32(0x40022080) = 0xFF;
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__asm("DSB");
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FLASH->CR &= ~FLASH_CR_OPTSTRT; // Programming Disabled
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FLASH->CR &= ~FLASH_CR_EOPIE; // Reset FLASH_EOPIE
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#ifdef FLASH_OPT_OBL_LAUNCH
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FLASH->CR |= FLASH_CR_OBL_LAUNCH;
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#endif
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return (0); // Done
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}
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#endif // FLASH_OPT
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/*
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* Verify Flash Contents
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* Parameter: adr: Start Address
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* sz: Size (in bytes)
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* buf: Data
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* Return Value: (adr+sz) - OK, Failed Address
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*/
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#ifdef FLASH_OPT
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unsigned long Verify(unsigned long adr, unsigned long sz, unsigned char *buf)
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{
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u32 optr;
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u32 sdkr;
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u32 wrpr;
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optr = *((u32 *)(buf + 0x00));
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sdkr = *((u32 *)(buf + 0x04));
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wrpr = *((u32 *)(buf + 0x0C));
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if (M32(adr + 0x00) != optr)
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{
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return (adr + 0x00);
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}
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if (M32(adr + 0x04) != sdkr)
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{
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return (adr + 0x04);
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}
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if (M32(adr + 0x0C) != wrpr)
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{
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return (adr + 0x0C);
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}
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return (adr + sz);
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}
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#endif // FLASH_OPT
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