mirror of
https://github.com/IcedRooibos/py32f0-template.git
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7954 lines
214 KiB
XML
7954 lines
214 KiB
XML
<?xml version="1.0" encoding="utf-8" standalone="no"?>
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<device schemaVersion="1.1"
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xmlns:xs="http://www.w3.org/2001/XMLSchema-instance" xs:noNamespaceSchemaLocation="CMSIS-SVD.xsd">
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<vendor>Puya</vendor>
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<vendorID>Puya</vendorID>
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<name>PY32F0xx_DFP</name>
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<!-- name of part-->
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<series>PY32F0</series>
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<version>1.0.0</version>
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<description>Arm 32-bit Cortex-M0+ Microcontroller based device, CPU clock up to 48 MHz.</description>
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<cpu>
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<!-- details about the cpu embedded in the device -->
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<name>CM0+</name>
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<revision>r0p1</revision>
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<endian>little</endian>
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<mpuPresent>false</mpuPresent>
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<fpuPresent>false</fpuPresent>
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<nvicPrioBits>4</nvicPrioBits>
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<vendorSystickConfig>false</vendorSystickConfig>
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</cpu>
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<addressUnitBits>8</addressUnitBits> <!-- byte addressable memory -->
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<width>32</width> <!-- bus width is 32 bits --> <!-- default settings implicitly inherited by subsequent sections -->
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<size>32</size> <!-- this is the default size (number of bits) of all peripherals and register that do not define "size" themselves -->
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<access>read-write</access> <!-- default access permission for all subsequent registers -->
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<resetValue>0x00000000</resetValue> <!-- by default all bits of the registers are initialized to 0 on reset -->
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<resetMask>0xFFFFFFFF</resetMask> <!-- by default all 32Bits of the registers are used -->
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<peripherals>
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<peripheral>
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<name>ADC</name>
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<description>Analog to Digital Converter</description>
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<groupName>ADC</groupName>
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<baseAddress>0x40012400</baseAddress>
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<addressBlock>
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<offset>0x0</offset>
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<size>0x400</size>
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<usage>registers</usage>
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</addressBlock>
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<interrupt>
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<name>ADC</name>
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<description>ADC Interrupt through EXTI Lines 17 and 18</description>
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<value>12</value>
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</interrupt>
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<registers>
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<register>
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<name>ISR</name>
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<displayName>ISR</displayName>
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<description>ADC interrupt and status register</description>
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<addressOffset>0x0</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>AWD</name>
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<description>ADC analog watchdog flag</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>OVR</name>
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<description>ADC group regular overrun
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flag</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOSEQ</name>
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<description>ADC group regular end of sequence
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conversions flag</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOC</name>
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<description>ADC group regular end of unitary
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conversion flag</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOSMP</name>
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<description>ADC group regular end of sampling
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flag</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>IER</name>
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<displayName>IER</displayName>
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<description>ADC interrupt enable register</description>
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<addressOffset>0x4</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>AWDIE</name>
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<description>ADC analog watchdog
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interrupt</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>OVRIE</name>
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<description>ADC group regular overrun
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interrupt</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOSEQIE</name>
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<description>ADC group regular end of sequence
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conversions interrupt</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOCIE</name>
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<description>ADC group regular end of unitary
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conversion interrupt</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EOSMPIE</name>
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<description>ADC group regular end of sampling
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interrupt</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CR</name>
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<displayName>CR</displayName>
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<description>ADC control register</description>
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<addressOffset>0x8</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>ADCAL</name>
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<description>ADC group regular conversion
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calibration</description>
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<bitOffset>31</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>VERBUFF_SEL</name>
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<description>desc VERBUFF_SEL</description>
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<bitOffset>6</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
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<field>
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<name>VREF_BUFFERE</name>
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<description>desc VREF_BUFFERE</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ADSTP</name>
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<description>ADC group regular conversion
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stop</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ADSTART</name>
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<description>ADC group regular conversion
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start</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>ADEN</name>
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<description>ADC enable</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CFGR1</name>
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<displayName>CFGR1</displayName>
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<description>ADC configuration register 1</description>
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<addressOffset>0xC</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>AWDCH</name>
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<description>ADC analog watchdog monitored channel
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selection</description>
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<bitOffset>26</bitOffset>
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<bitWidth>4</bitWidth>
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</field>
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<field>
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<name>AWDEN</name>
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<description>ADC analog watchdog enable on scope
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ADC group regular</description>
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<bitOffset>23</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>AWDSGL</name>
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<description>ADC analog watchdog monitoring a
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single channel or all channels</description>
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<bitOffset>22</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>DISCEN</name>
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<description>ADC group regular sequencer
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discontinuous mode</description>
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<bitOffset>16</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>WAIT</name>
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<description>Wait conversion mode</description>
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<bitOffset>14</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CONT</name>
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<description>ADC group regular continuous conversion
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mode</description>
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<bitOffset>13</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>OVRMOD</name>
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<description>ADC group regular overrun
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configuration</description>
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<bitOffset>12</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>EXTEN</name>
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<description>ADC group regular external trigger
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polarity</description>
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<bitOffset>10</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
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<field>
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<name>EXTSEL</name>
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<description>ADC group regular external trigger
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source</description>
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<bitOffset>6</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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<field>
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<name>ALIGN</name>
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<description>ADC data alignement</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>RESSEL</name>
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<description>ADC data resolution</description>
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<bitOffset>3</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
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<field>
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<name>SCANDIR</name>
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<description>Scan sequence direction</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CFGR2</name>
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<displayName>CFGR2</displayName>
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<description>ADC configuration register 2</description>
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<addressOffset>0x10</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>CKMODE</name>
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<description>ADC clock mode</description>
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<bitOffset>28</bitOffset>
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<bitWidth>4</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>SMPR</name>
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<displayName>SMPR</displayName>
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<description>ADC sampling time register</description>
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<addressOffset>0x14</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>SMP</name>
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<description>Sampling time selection</description>
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<bitOffset>0</bitOffset>
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<bitWidth>3</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>TR</name>
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<displayName>TR</displayName>
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<description>ADC analog watchdog 1 threshold register</description>
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<addressOffset>0x20</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x0FFF0000</resetValue>
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<fields>
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<field>
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<name>HT</name>
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<description>ADC analog watchdog threshold
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high</description>
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<bitOffset>16</bitOffset>
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<bitWidth>12</bitWidth>
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</field>
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<field>
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<name>LT</name>
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<description>ADC analog watchdog threshold
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low</description>
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<bitOffset>0</bitOffset>
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<bitWidth>12</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CHSELR</name>
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<displayName>CHSELR</displayName>
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<description>ADC group regular sequencer register</description>
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<addressOffset>0x28</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x0FFF0000</resetValue>
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<fields>
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<field>
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<name>CHSEL12</name>
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<description>Channel-12 selection</description>
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<bitOffset>12</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL11</name>
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<description>Channel-11 selection</description>
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<bitOffset>11</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL9</name>
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<description>Channel-9 selection</description>
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<bitOffset>9</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL8</name>
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<description>Channel-8 selection</description>
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<bitOffset>8</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL7</name>
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<description>Channel-7 selection</description>
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<bitOffset>7</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL6</name>
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<description>Channel-6 selection</description>
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<bitOffset>6</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL5</name>
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<description>Channel-5 selection</description>
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<bitOffset>5</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL4</name>
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<description>Channel-4 selection</description>
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<bitOffset>4</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL3</name>
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<description>Channel-3 selection</description>
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<bitOffset>3</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL2</name>
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<description>Channel-2 selection</description>
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<bitOffset>2</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL1</name>
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<description>Channel-1 selection</description>
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<bitOffset>1</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CHSEL0</name>
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<description>Channel-0 selection</description>
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<bitOffset>0</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>DR</name>
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<displayName>DR</displayName>
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<description>ADC group regular data register</description>
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<addressOffset>0x40</addressOffset>
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<size>0x20</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>DATA</name>
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<description>ADC group regular conversion
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data</description>
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<bitOffset>0</bitOffset>
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<bitWidth>16</bitWidth>
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</field>
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</fields>
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</register>
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<register>
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<name>CCSR</name>
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<displayName>CCSR</displayName>
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<description>ADC calibration configuration and status register</description>
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<addressOffset>0x44</addressOffset>
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<size>0x20</size>
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<access>read-write</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>CALON</name>
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<description>Calibration flag</description>
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<bitOffset>31</bitOffset>
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<bitWidth>1</bitWidth>
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<access>read-only</access>
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</field>
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<field>
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<name>CALFAIL</name>
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<description>Calibration fail flag</description>
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<bitOffset>30</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>OFFSUC</name>
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<description>desc OFFSUC</description>
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<bitOffset>29</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CALSET</name>
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<description>Calibration factor selection</description>
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<bitOffset>15</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CALBYP</name>
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<description>desc CALBYP</description>
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<bitOffset>14</bitOffset>
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<bitWidth>1</bitWidth>
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</field>
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<field>
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<name>CALSMP</name>
|
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<description>Calibration sample time selection</description>
|
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<bitOffset>12</bitOffset>
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<bitWidth>2</bitWidth>
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</field>
|
|
<field>
|
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<name>CALSEL</name>
|
|
<description>Calibration contents selection</description>
|
|
<bitOffset>11</bitOffset>
|
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<bitWidth>1</bitWidth>
|
|
</field>
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|
</fields>
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</register>
|
|
<register>
|
|
<name>CALRR1</name>
|
|
<displayName>CALRR1</displayName>
|
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<description>ADC calibration result register 1</description>
|
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<addressOffset>0x48</addressOffset>
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<size>0x20</size>
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<access>read-only</access>
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<resetValue>0x00000000</resetValue>
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<fields>
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<field>
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<name>CALBOUT</name>
|
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<description>offset result</description>
|
|
<bitOffset>16</bitOffset>
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<bitWidth>7</bitWidth>
|
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</field>
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|
<field>
|
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<name>CALC5OUT</name>
|
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<description>C5 result</description>
|
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<bitOffset>8</bitOffset>
|
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<bitWidth>8</bitWidth>
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</field>
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|
<field>
|
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<name>CALC4OUT</name>
|
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<description>C4 result</description>
|
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<bitOffset>0</bitOffset>
|
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<bitWidth>8</bitWidth>
|
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</field>
|
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</fields>
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</register>
|
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<register>
|
|
<name>CALRR2</name>
|
|
<displayName>CALRR2</displayName>
|
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<description>ADC calibration result register 2</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>0x20</size>
|
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<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALC3OUT</name>
|
|
<description>C3 result</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALC2OUT</name>
|
|
<description>C2 result</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALC1OUT</name>
|
|
<description>C1 result</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALC0OUT</name>
|
|
<description>C0 result</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALFIR1</name>
|
|
<displayName>CALFIR1</displayName>
|
|
<description>ADC calibration factor input register 1</description>
|
|
<addressOffset>0x50</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALBIO</name>
|
|
<description>Calibration offset factor input</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALC5IO</name>
|
|
<description>Calibration C5 factor input</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALC4IO</name>
|
|
<description>Calibration C4 factor input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CALFIR2</name>
|
|
<displayName>CALFIR2</displayName>
|
|
<description>ADC calibration factor input register 2</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CALC3IO</name>
|
|
<description>Calibration C3 factor input</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALC2IO</name>
|
|
<description>Calibration C2 factor input</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALC1IO</name>
|
|
<description>Calibration C1 factor input</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CALC0IO</name>
|
|
<description>Calibration C0 factor input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<displayName>CCR</displayName>
|
|
<description>ADC common configuration register</description>
|
|
<addressOffset>0x308</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TSEN</name>
|
|
<description>Temperature sensor enable</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VREFEN</name>
|
|
<description>VREFINT enable</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>RCC</name>
|
|
<description>Reset and clock control</description>
|
|
<groupName>RCC</groupName>
|
|
<baseAddress>0x40021000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>RCC</name>
|
|
<description>RCC global Interrupt</description>
|
|
<value>4</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Clock control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000100</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HSIDIV</name>
|
|
<description>HSI16 clock division
|
|
factor</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDY</name>
|
|
<description>HSI16 clock ready flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSION</name>
|
|
<description>HSI16 clock enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICSCR</name>
|
|
<displayName>ICSCR</displayName>
|
|
<description>Internal clock sources calibration
|
|
register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x10000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSI_STARTUP</name>
|
|
<description>LSI startup time </description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSI_TRIM</name>
|
|
<description>LSI clock trimming</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSI_FS</name>
|
|
<description>HSI frequency selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HSI_TRIM</name>
|
|
<description>HSI clock trimming</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR</name>
|
|
<displayName>CFGR</displayName>
|
|
<description>Clock configuration register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MCOPRE</name>
|
|
<description>Microcontroller clock output
|
|
prescaler</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MCOSEL</name>
|
|
<description>Microcontroller clock
|
|
output</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PPRE</name>
|
|
<description>APB prescaler</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>HPRE</name>
|
|
<description>AHB prescaler</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SWS</name>
|
|
<description>System clock switch status</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SW</name>
|
|
<description>System clock switch</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ECSCR</name>
|
|
<displayName>ECSCR</displayName>
|
|
<description>External clock source control register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSE_DRIVER</name>
|
|
<description>desc LSE_DRIVER</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIER</name>
|
|
<displayName>CIER</displayName>
|
|
<description>Clock interrupt enable
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HSIRDYIE</name>
|
|
<description>HSI ready interrupt enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDYIE</name>
|
|
<description>LSE ready interrupt enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSIRDYIE</name>
|
|
<description>LSI ready interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CIFR</name>
|
|
<displayName>CIFR</displayName>
|
|
<description>Clock interrupt flag register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSECSSF</name>
|
|
<description>LSE clock secure system interrupt flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDYF</name>
|
|
<description>HSI ready interrupt flag</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDYF</name>
|
|
<description>LSE ready interrupt flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSIRDYF</name>
|
|
<description>LSI ready interrupt flag</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CICR</name>
|
|
<displayName>CICR</displayName>
|
|
<description>Clock interrupt clear register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSECSSC</name>
|
|
<description>LSE clock secure system interrupt flag clear</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HSIRDYC</name>
|
|
<description>HSI ready interrupt clear</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDYC</name>
|
|
<description>LSE ready interrupt clear</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSIRDYC</name>
|
|
<description>LSI ready interrupt clear</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOPRSTR</name>
|
|
<displayName>IOPRSTR</displayName>
|
|
<description>GPIO reset register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GPIOCRST</name>
|
|
<description>I/O port C reset</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOBRST</name>
|
|
<description>I/O port B reset</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOARST</name>
|
|
<description>I/O port A reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBRSTR</name>
|
|
<displayName>AHBRSTR</displayName>
|
|
<description>AHB peripheral reset register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCRST</name>
|
|
<description>CRC reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLASHRST</name>
|
|
<description>FLASH reset</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMARST</name>
|
|
<description>DMA reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBRSTR1</name>
|
|
<displayName>APBRSTR1</displayName>
|
|
<description>APB peripheral reset register 1</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPTIMRST</name>
|
|
<description>Low Power Timer reset</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWRRST</name>
|
|
<description>Power interface reset</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBGRST</name>
|
|
<description>Debug support reset</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2CRST</name>
|
|
<description>I2C reset</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM6RST</name>
|
|
<description>TIM6 reset</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBRSTR2</name>
|
|
<displayName>APBRSTR2</displayName>
|
|
<description>APB peripheral reset register
|
|
2</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADCRST</name>
|
|
<description>ADC reset</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1RST</name>
|
|
<description>USART1 reset</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI1RST</name>
|
|
<description>SPI1 reset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM1RST</name>
|
|
<description>TIM1 timer reset</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSCFGRST</name>
|
|
<description>SYSCFG and COMP
|
|
reset</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IOPENR</name>
|
|
<displayName>IOPENR</displayName>
|
|
<description>GPIO clock enable register</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>GPIOCEN</name>
|
|
<description>I/O port C clock enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOBEN</name>
|
|
<description>I/O port B clock enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GPIOAEN</name>
|
|
<description>I/O port A clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AHBENR</name>
|
|
<displayName>AHBENR</displayName>
|
|
<description>AHB peripheral clock enable
|
|
register</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>CRC clock enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAMEN</name>
|
|
<description>SRAM memory interface clock enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLASHEN</name>
|
|
<description>Flash memory interface clock enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DMAEN</name>
|
|
<description>DMA interface clock enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBENR1</name>
|
|
<displayName>APBENR1</displayName>
|
|
<description>APB peripheral clock enable register
|
|
1</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPTIMEN</name>
|
|
<description>LPTIM clock enable</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWREN</name>
|
|
<description>Power interface clock
|
|
enable</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBGEN</name>
|
|
<description>Debug support clock enable</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2CEN</name>
|
|
<description>I2C clock enable</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM6EN</name>
|
|
<description>TIM6 clock enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APBENR2</name>
|
|
<displayName>APBENR2</displayName>
|
|
<description>APB peripheral clock enable register
|
|
2</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADCEN</name>
|
|
<description>ADC clock enable</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>USART1EN</name>
|
|
<description>USART1 clock enable</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SPI1EN</name>
|
|
<description>SPI1 clock enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TIM1EN</name>
|
|
<description>TIM1 timer clock enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SYSCFGEN</name>
|
|
<description>SYSCFG, COMP and VREFBUF clock
|
|
enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCIPR</name>
|
|
<displayName>CCIPR</displayName>
|
|
<description>Peripherals independent clock configuration
|
|
register</description>
|
|
<addressOffset>0x54</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LPTIM1SEL</name>
|
|
<description>LPTIM1 clock source
|
|
selection</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDCR</name>
|
|
<displayName>BDCR</displayName>
|
|
<description>RTC domain control register</description>
|
|
<addressOffset>0x5C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LSCOSEL</name>
|
|
<description>
|
|
Low-speed clock output
|
|
selection
|
|
</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSCOEN</name>
|
|
<description>
|
|
Low-speed clock output (LSCO)
|
|
enable
|
|
</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSECSSD</name>
|
|
<description>LSE CSS detect</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSECSSON</name>
|
|
<description>LSE CSS enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSEBYP</name>
|
|
<description>LSE oscillator bypass</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSERDY</name>
|
|
<description>LSE oscillator ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSEON</name>
|
|
<description>LSE oscillator enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CSR</name>
|
|
<displayName>CSR</displayName>
|
|
<description>Control/status register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IWDGRSTF</name>
|
|
<description>Independent window watchdog reset
|
|
flag</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SFTRSTF</name>
|
|
<description>Software reset flag</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PWRRSTF</name>
|
|
<description>BOR or POR/PDR flag</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINRSTF</name>
|
|
<description>Pin reset flag</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OBLRSTF</name>
|
|
<description>Option byte loader reset
|
|
flag</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RMVF</name>
|
|
<description>Remove reset flags</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PINRST_FLTDIS</name>
|
|
<description>desc PINRST_FLTDIS</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSIRDY</name>
|
|
<description>LSI oscillator ready</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LSION</name>
|
|
<description>LSI oscillator enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>PWR</name>
|
|
<description>Power control</description>
|
|
<groupName>PWR</groupName>
|
|
<baseAddress>0x40007000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>Power control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00030000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>HSION_CTRL</name>
|
|
<description>HSI open time control</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SRAM_RETV</name>
|
|
<description>SRAM retention voltage control</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LPR</name>
|
|
<description>Low-power run</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLS_SLPTIME</name>
|
|
<description>Flash wait time after wakeup from the stop mode</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MRRDY_TIME</name>
|
|
<description>Time selection wakeup from LP to VR</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>VOS</name>
|
|
<description>Voltage scaling range
|
|
selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBP</name>
|
|
<description>Disable backup domain write
|
|
protection</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAS_CR_SEL</name>
|
|
<description>MR Bias current selection</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BIAS_CR</name>
|
|
<description>MR Bias current</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>Power control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000500</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FLT_TIME</name>
|
|
<description>Digital filter time configuration</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FLTEN</name>
|
|
<description>Digital filter enable </description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOA</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x50000000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MODER</name>
|
|
<displayName>MODER</displayName>
|
|
<description>GPIO port mode register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xEBFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODE15</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE14</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE13</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE12</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE11</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE10</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE9</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE8</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE7</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE6</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE5</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE4</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE0</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTYPER</name>
|
|
<displayName>OTYPER</displayName>
|
|
<description>GPIO port output type register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OT15</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT14</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT13</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT12</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT11</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT10</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT9</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT8</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT7</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT6</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT5</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT4</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT3</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT2</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT1</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT0</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSPEEDR</name>
|
|
<displayName>OSPEEDR</displayName>
|
|
<description>GPIO port output speed
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0C000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSPEED15</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED14</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED13</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED12</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED11</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED10</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED9</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED8</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED7</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED6</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED5</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED4</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED3</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED2</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED1</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED0</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUPDR</name>
|
|
<displayName>PUPDR</displayName>
|
|
<description>GPIO port pull-up/pull-down
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x24000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUPD15</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD14</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD13</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD12</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD11</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD10</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD9</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD8</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD7</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD6</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD5</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD4</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD3</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD2</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD1</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD0</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<displayName>IDR</displayName>
|
|
<description>GPIO port input data register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID15</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID14</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID13</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID12</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID11</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID10</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID9</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID8</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID7</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID6</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID5</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID4</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID3</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID2</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODR</name>
|
|
<displayName>ODR</displayName>
|
|
<description>GPIO port output data register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OD15</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD14</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD13</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD12</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD11</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD10</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD9</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD8</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD7</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD6</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD5</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD4</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD3</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD2</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD1</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD0</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BSRR</name>
|
|
<displayName>BSRR</displayName>
|
|
<description>GPIO port bit set/reset
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>26</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS15</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS14</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS13</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS12</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS11</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS10</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS9</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS8</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS7</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS6</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS5</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS4</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS3</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS2</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS1</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS0</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCKR</name>
|
|
<displayName>LCKR</displayName>
|
|
<description>GPIO port configuration lock
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCKK</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK15</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK14</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK13</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK12</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK11</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK10</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK9</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK8</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK7</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK6</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK5</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK4</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK3</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK2</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK1</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK0</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRL</name>
|
|
<displayName>AFRL</displayName>
|
|
<description>GPIO alternate function low
|
|
register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFSEL7</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL6</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL5</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL4</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL3</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL2</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL1</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL0</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRH</name>
|
|
<displayName>AFRH</displayName>
|
|
<description>GPIO alternate function high
|
|
register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFSEL15</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL14</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL13</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL12</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL11</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL10</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL9</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL8</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<displayName>BRR</displayName>
|
|
<description>port bit reset register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR15</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR14</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR13</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR12</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR11</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR10</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR9</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>GPIOB</name>
|
|
<description>General-purpose I/Os</description>
|
|
<groupName>GPIO</groupName>
|
|
<baseAddress>0x50000400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>MODER</name>
|
|
<displayName>MODER</displayName>
|
|
<description>GPIO port mode register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>MODE8</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE7</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE6</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE5</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE4</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE3</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE2</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE1</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MODE0</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OTYPER</name>
|
|
<displayName>OTYPER</displayName>
|
|
<description>GPIO port output type register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OT8</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT7</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT6</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT5</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT4</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT3</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT2</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT1</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OT0</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OSPEEDR</name>
|
|
<displayName>OSPEEDR</displayName>
|
|
<description>GPIO port output speed
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OSPEED8</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED7</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED6</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED5</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED4</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED3</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED2</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED1</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OSPEED0</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PUPDR</name>
|
|
<displayName>PUPDR</displayName>
|
|
<description>GPIO port pull-up/pull-down
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PUPD8</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD7</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD6</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD5</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD4</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD3</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD2</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD1</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PUPD0</name>
|
|
<description>Port x configuration bits (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<displayName>IDR</displayName>
|
|
<description>GPIO port input data register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ID8</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID7</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID6</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID5</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID4</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID3</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID2</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID1</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ID0</name>
|
|
<description>Port input data (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ODR</name>
|
|
<displayName>ODR</displayName>
|
|
<description>GPIO port output data register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OD8</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD7</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD6</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD5</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD4</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD3</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD2</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD1</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OD0</name>
|
|
<description>Port output data (y =
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BSRR</name>
|
|
<displayName>BSRR</displayName>
|
|
<description>GPIO port bit set/reset
|
|
register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>23</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port x reset bit y (y =
|
|
0..15)</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS8</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS7</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS6</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS5</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS4</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS3</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS2</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS1</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BS0</name>
|
|
<description>Port x set bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>LCKR</name>
|
|
<displayName>LCKR</displayName>
|
|
<description>GPIO port configuration lock
|
|
register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LCKK</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK8</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK7</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK6</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK5</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK4</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK3</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK2</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK1</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LCK0</name>
|
|
<description>Port x lock bit y (y=
|
|
0..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRL</name>
|
|
<displayName>AFRL</displayName>
|
|
<description>GPIO alternate function low
|
|
register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFSEL7</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL6</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL5</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL4</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL3</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL2</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL1</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL0</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 0..7)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>AFRH</name>
|
|
<displayName>AFRH</displayName>
|
|
<description>GPIO alternate function high
|
|
register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>AFSEL15</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>28</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL14</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL13</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>20</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL12</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL11</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL10</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL9</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>AFSEL8</name>
|
|
<description>Alternate function selection for port x
|
|
bit y (y = 8..15)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<displayName>BRR</displayName>
|
|
<description>port bit reset register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BR8</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR7</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR6</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR5</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR4</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR3</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR2</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR1</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BR0</name>
|
|
<description>Port Reset bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral derivedFrom="GPIOB">
|
|
<name>GPIOC</name>
|
|
<baseAddress>0x50000800</baseAddress>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>EXTI</name>
|
|
<description>External interrupt/event
|
|
controller</description>
|
|
<groupName>EXTI</groupName>
|
|
<baseAddress>0x40021800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>EXTI0_1</name>
|
|
<description>EXTI Line 0 and 1 Interrupt</description>
|
|
<value>5</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI2_3</name>
|
|
<description>EXTI Line 2 and 3 Interrupt</description>
|
|
<value>6</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>EXTI4_15</name>
|
|
<description>EXTI Line 4 to 15 Interrupt</description>
|
|
<value>7</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>RTSR</name>
|
|
<displayName>RTSR</displayName>
|
|
<description>EXTI rising trigger selection
|
|
register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RT7</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT6</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT5</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT4</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT3</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT2</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT1</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RT0</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>FTSR</name>
|
|
<displayName>FTSR</displayName>
|
|
<description>EXTI falling trigger selection
|
|
register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>FT7</name>
|
|
<description>Falling trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT6</name>
|
|
<description>Falling trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT5</name>
|
|
<description>Falling trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT4</name>
|
|
<description>Falling trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT3</name>
|
|
<description>Falling trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT2</name>
|
|
<description>Falling trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT1</name>
|
|
<description>Falling trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FT0</name>
|
|
<description>Falling trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SWIER</name>
|
|
<displayName>SWIER</displayName>
|
|
<description>EXTI software interrupt event
|
|
register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWI7</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI6</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI5</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI4</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI3</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI2</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI1</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SWI0</name>
|
|
<description>Rising trigger event configuration bit
|
|
of Configurable Event input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<displayName>PR</displayName>
|
|
<description>EXTI pending
|
|
register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PR7</name>
|
|
<description>configurable event inputs x rising edge
|
|
Pending bit.</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR6</name>
|
|
<description>configurable event inputs x rising edge
|
|
Pending bit.</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR5</name>
|
|
<description>configurable event inputs x rising edge
|
|
Pending bit.</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR4</name>
|
|
<description>configurable event inputs x rising edge
|
|
Pending bit.</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR3</name>
|
|
<description>configurable event inputs x rising edge
|
|
Pending bit.</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR2</name>
|
|
<description>configurable event inputs x rising edge
|
|
Pending bit.</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR1</name>
|
|
<description>configurable event inputs x rising edge
|
|
Pending bit.</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PR0</name>
|
|
<description>configurable event inputs x rising edge
|
|
Pending bit.</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTICR1</name>
|
|
<displayName>EXTICR1</displayName>
|
|
<description>EXTI external interrupt selection
|
|
register</description>
|
|
<addressOffset>0x60</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI3</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI2</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI1</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI0</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EXTICR2</name>
|
|
<displayName>EXTICR2</displayName>
|
|
<description>EXTI external interrupt selection
|
|
register</description>
|
|
<addressOffset>0x64</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EXTI7</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI6</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI5</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EXTI4</name>
|
|
<description>GPIO port selection</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IMR</name>
|
|
<displayName>IMR</displayName>
|
|
<description>EXTI CPU wakeup with interrupt mask
|
|
register</description>
|
|
<addressOffset>0x80</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFF80000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IM29</name>
|
|
<description>CPU wakeup with interrupt mask on event
|
|
input</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM7</name>
|
|
<description>CPU wakeup with interrupt mask on event
|
|
input</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM6</name>
|
|
<description>CPU wakeup with interrupt mask on event
|
|
input</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM5</name>
|
|
<description>CPU wakeup with interrupt mask on event
|
|
input</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM4</name>
|
|
<description>CPU wakeup with interrupt mask on event
|
|
input</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM3</name>
|
|
<description>CPU wakeup with interrupt mask on event
|
|
input</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM2</name>
|
|
<description>CPU wakeup with interrupt mask on event
|
|
input</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM1</name>
|
|
<description>CPU wakeup with interrupt mask on event
|
|
input</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IM0</name>
|
|
<description>CPU wakeup with interrupt mask on event
|
|
input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EMR</name>
|
|
<displayName>EMR</displayName>
|
|
<description>EXTI CPU wakeup with event mask
|
|
register</description>
|
|
<addressOffset>0x84</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>EM29</name>
|
|
<description>CPU wakeup with event mask on event
|
|
input</description>
|
|
<bitOffset>29</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM7</name>
|
|
<description>CPU wakeup with event mask on event
|
|
input</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM6</name>
|
|
<description>CPU wakeup with event mask on event
|
|
input</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM5</name>
|
|
<description>CPU wakeup with event mask on event
|
|
input</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM4</name>
|
|
<description>CPU wakeup with event mask on event
|
|
input</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM3</name>
|
|
<description>CPU wakeup with event mask on event
|
|
input</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM2</name>
|
|
<description>CPU wakeup with event mask on event
|
|
input</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM1</name>
|
|
<description>CPU wakeup with event mask on event
|
|
input</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EM0</name>
|
|
<description>CPU wakeup with event mask on event
|
|
input</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>LPTIM1</name>
|
|
<description>Low power timer</description>
|
|
<groupName>LPTIM1</groupName>
|
|
<baseAddress>0x40007C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM6_LPTIM1_DAC</name>
|
|
<description>TIM6, LPTIM1, DAC global Interrupts</description>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ISR</name>
|
|
<displayName>ISR</displayName>
|
|
<description>Interrupt and Status Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARRM</name>
|
|
<description>Autoreload match</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARROK</name>
|
|
<description>Autoreload match update OK</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ICR</name>
|
|
<displayName>ICR</displayName>
|
|
<description>Interrupt Clear Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARRMCF</name>
|
|
<description>
|
|
Autoreload match Clear
|
|
Flag
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARROKCF</name>
|
|
<description>
|
|
Autoreload match update OK
|
|
Clear Flag
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IER</name>
|
|
<displayName>IER</displayName>
|
|
<description>Interrupt Enable Register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARRMIE</name>
|
|
<description>
|
|
Autoreload matchInterrupt
|
|
Enable
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ARROKIE</name>
|
|
<description>
|
|
Autoreload match update
|
|
OK Interrupt Enable
|
|
</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR</name>
|
|
<displayName>CFGR</displayName>
|
|
<description>Configuration Register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRELOAD</name>
|
|
<description>Registers update mode</description>
|
|
<bitOffset>22</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PRESC</name>
|
|
<description>Clock prescaler</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Control Register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RSTARE</name>
|
|
<description>Reset after read enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CNTSTRT</name>
|
|
<description>CNTSTRT</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SNGSTRT</name>
|
|
<description>LPTIM start in single mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENABLE</name>
|
|
<description>LPTIM Enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<displayName>ARR</displayName>
|
|
<description>Autoreload Register</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000001</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>Auto reload value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<displayName>CNT</displayName>
|
|
<description>Counter Register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>Counter value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>USART1</name>
|
|
<description>Universal synchronous asynchronous receiver
|
|
transmitter</description>
|
|
<groupName>USART</groupName>
|
|
<baseAddress>0x40013800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>USART1</name>
|
|
<description>USART1 global Interrupt</description>
|
|
<value>27</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x00C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ABRRQ</name>
|
|
<description>Automate baudrate detection requeset</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ABRE</name>
|
|
<description>Automate baudrate detection error flag</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ABRF</name>
|
|
<description>Automate baudrate detection flag</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CTS</name>
|
|
<description>CTS flag</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>Transmit data register
|
|
empty</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TC</name>
|
|
<description>Transmission complete</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>Read data register not
|
|
empty</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IDLE</name>
|
|
<description>IDLE line detected</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ORE</name>
|
|
<description>Overrun error</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>NE</name>
|
|
<description>Noise error flag</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FE</name>
|
|
<description>Framing error</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Parity error</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>Data register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>Data value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BRR</name>
|
|
<displayName>BRR</displayName>
|
|
<description>Baud rate register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DIV_Mantissa</name>
|
|
<description>mantissa of USARTDIV</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DIV_Fraction</name>
|
|
<description>fraction of USARTDIV</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>Control register 1</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>UE</name>
|
|
<description>USART enable</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>M</name>
|
|
<description>Word length</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WAKE</name>
|
|
<description>Wakeup method</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PCE</name>
|
|
<description>Parity control enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PS</name>
|
|
<description>Parity selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEIE</name>
|
|
<description>PE interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TXEIE</name>
|
|
<description>TXE interrupt enable</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TCIE</name>
|
|
<description>Transmission complete interrupt
|
|
enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RXNEIE</name>
|
|
<description>RXNE interrupt enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IDLEIE</name>
|
|
<description>IDLE interrupt enable</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TE</name>
|
|
<description>Transmitter enable</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RE</name>
|
|
<description>Receiver enable</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RWU</name>
|
|
<description>Receiver wakeup</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>Control register 2</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>STOP bits</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CLKEN</name>
|
|
<description>Clock enable</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>Clock polarity</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>Clock phase</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LBCL</name>
|
|
<description>Last bit clock pulse</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ADD</name>
|
|
<description>Address of the USART node</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR3</name>
|
|
<displayName>CR3</displayName>
|
|
<description>Control register 3</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ABRMOD</name>
|
|
<description>Auto baudrate mode</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ABREN</name>
|
|
<description>Auto baudrate enable</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OVER8</name>
|
|
<description>Oversampling mode</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSIE</name>
|
|
<description>CTS interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CTSE</name>
|
|
<description>CTS enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RTSE</name>
|
|
<description>RTS enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>HDSEL</name>
|
|
<description>Half-duplex selection</description>
|
|
<bitOffset>3</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IRLP</name>
|
|
<description>IrDA low-power</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IREN</name>
|
|
<description>IrDA mode enable</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>IWDG</name>
|
|
<description>Independent watchdog</description>
|
|
<groupName>IWDG</groupName>
|
|
<baseAddress>0x40003000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>KR</name>
|
|
<displayName>KR</displayName>
|
|
<description>Key register (IWDG_KR)</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Key value</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PR</name>
|
|
<displayName>PR</displayName>
|
|
<description>Prescaler register (IWDG_PR)</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PR</name>
|
|
<description>Prescaler divider</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RLR</name>
|
|
<displayName>RLR</displayName>
|
|
<description>Reload register (IWDG_RLR)</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000FFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RL</name>
|
|
<description>
|
|
Watchdog counter reload
|
|
value
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>Status register (IWDG_SR)</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RVU</name>
|
|
<description>
|
|
Watchdog counter reload value
|
|
update
|
|
</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PVU</name>
|
|
<description>
|
|
Watchdog prescaler value
|
|
update
|
|
</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM1</name>
|
|
<description>Advanced timer</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40012C00</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM1_BRK_UP_TRG_COM</name>
|
|
<description>TIM1 Break, Update, Trigger and Commutation Interrupt</description>
|
|
<value>13</value>
|
|
</interrupt>
|
|
<interrupt>
|
|
<name>TIM1_CC</name>
|
|
<description>TIM1 Capture Compare Interrupt</description>
|
|
<value>14</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>desc CEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>desc UDIS</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>desc URS</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>desc OPM</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>desc CMS</description>
|
|
<msb>6</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>desc ARPE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>desc CKD</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>desc CCDS</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>desc MMS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>desc TI1S</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMCR</name>
|
|
<description>desc SMCR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFF7</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>SMS</name>
|
|
<description>desc SMS</description>
|
|
<msb>2</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OCCS</name>
|
|
<description>desc OCCS</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TS</name>
|
|
<description>desc TS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSM</name>
|
|
<description>desc MSM</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETF</name>
|
|
<description>desc ETF</description>
|
|
<msb>11</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETPS</name>
|
|
<description>desc ETPS</description>
|
|
<msb>13</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ECE</name>
|
|
<description>desc ECE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ETP</name>
|
|
<description>desc ETP</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<description>desc DIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>desc UIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>desc CC1IE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>desc CC2IE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>desc CC3IE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>desc CC4IE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>desc TIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIE</name>
|
|
<description>desc BIE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1E5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>desc UIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>desc CC1IF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>desc CC2IF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>desc CC3IF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>desc CC4IF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>desc COMIF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>desc TIF</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>desc BIF</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>desc CC1OF</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>desc CC2OF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>desc CC3OF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>desc CC4OF</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IR</name>
|
|
<description>desc IC1IR</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IR</name>
|
|
<description>desc IC2IR</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IF</name>
|
|
<description>desc IC1IF</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IF</name>
|
|
<description>desc IC2IF</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<description>desc EGR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>desc UG</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/Compare 1 Generation</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>desc CC2G</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>desc CC3G</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>desc CC4G</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>COMG</name>
|
|
<description>desc COMG</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>desc TG</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BG</name>
|
|
<description>desc BG</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_OUTPUT</name>
|
|
<description>desc CCMR1:OUTPUT</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1FE</name>
|
|
<description>desc OC1FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1PE</name>
|
|
<description>desc OC1PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1M</name>
|
|
<description>desc OC1M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC1CE</name>
|
|
<description>desc OC1CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2FE</name>
|
|
<description>desc OC2FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2PE</name>
|
|
<description>desc OC2PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2M</name>
|
|
<description>desc OC2M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC2CE</name>
|
|
<description>desc OC2CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR1_INPUT</name>
|
|
<description>desc CCMR1:INPUT</description>
|
|
<alternateRegister>CCMR1_OUTPUT</alternateRegister>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1S</name>
|
|
<description>desc CC1S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1PSC</name>
|
|
<description>desc IC1PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1F</name>
|
|
<description>desc IC1F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2S</name>
|
|
<description>desc CC2S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2PSC</name>
|
|
<description>desc IC2PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2F</name>
|
|
<description>desc IC2F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_OUTPUT</name>
|
|
<description>desc CCMR2:OUTPUT</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>desc CC3S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3FE</name>
|
|
<description>desc OC3FE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3PE</name>
|
|
<description>desc OC3PE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3M</name>
|
|
<description>desc OC3M</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC3CE</name>
|
|
<description>desc OC3CE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>desc CC4S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4FE</name>
|
|
<description>desc OC4FE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4PE</name>
|
|
<description>desc OC4PE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4M</name>
|
|
<description>desc OC4M</description>
|
|
<msb>14</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OC4CE</name>
|
|
<description>desc OC4CE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCMR2_INPUT</name>
|
|
<description>desc CCMR2:INPUT</description>
|
|
<alternateRegister>CCMR2_OUTPUT</alternateRegister>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC3S</name>
|
|
<description>desc CC3S</description>
|
|
<msb>1</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3PSC</name>
|
|
<description>desc IC3PSC</description>
|
|
<msb>3</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3F</name>
|
|
<description>desc IC3F</description>
|
|
<msb>7</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4S</name>
|
|
<description>desc CC4S</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4PSC</name>
|
|
<description>desc IC4PSC</description>
|
|
<msb>11</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4F</name>
|
|
<description>desc IC4F</description>
|
|
<msb>15</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCER</name>
|
|
<description>desc CCER</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3333</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CC1E</name>
|
|
<description>desc CC1E</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1P</name>
|
|
<description>desc CC1P</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2E</name>
|
|
<description>desc CC2E</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2P</name>
|
|
<description>desc CC2P</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3E</name>
|
|
<description>desc CC3E</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3P</name>
|
|
<description>desc CC3P</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4E</name>
|
|
<description>desc CC4E</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4P</name>
|
|
<description>desc CC4P</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RCR</name>
|
|
<description>desc RCR</description>
|
|
<addressOffset>0x30</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>REP</name>
|
|
<description>desc REP</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<addressOffset>0x34</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR1</name>
|
|
<description>desc CCR1</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<addressOffset>0x38</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR2</name>
|
|
<description>desc CCR2</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR3</name>
|
|
<description>desc CCR3</description>
|
|
<addressOffset>0x3C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR3</name>
|
|
<description>desc CCR3</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR4</name>
|
|
<description>desc CCR4</description>
|
|
<addressOffset>0x40</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCR4</name>
|
|
<description>desc CCR4</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BDTR</name>
|
|
<description>desc BDTR</description>
|
|
<addressOffset>0x44</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DTG</name>
|
|
<description>desc DTG</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>desc LOCK</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSI</name>
|
|
<description>desc OSSI</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OSSR</name>
|
|
<description>desc OSSR</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BKE</name>
|
|
<description>desc BKE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BKP</name>
|
|
<description>desc BKP</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AOE</name>
|
|
<description>desc AOE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MOE</name>
|
|
<description>desc MOE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DCR</name>
|
|
<description>desc DCR</description>
|
|
<addressOffset>0x48</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1F1F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DBA</name>
|
|
<description>desc DBA</description>
|
|
<msb>4</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DBL</name>
|
|
<description>desc DBL</description>
|
|
<msb>12</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DMAR</name>
|
|
<description>desc DMAR</description>
|
|
<addressOffset>0x4C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>DMAB</name>
|
|
<description>desc DMAB</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>TIM6</name>
|
|
<description>desc TIM</description>
|
|
<groupName>TIM</groupName>
|
|
<baseAddress>0x40001000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>TIM6_LPTIM1_DAC</name>
|
|
<description>TIM6, LPTIM1, DAC global Interrupts</description>
|
|
<value>17</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x3FF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CEN</name>
|
|
<description>desc CEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDIS</name>
|
|
<description>desc UDIS</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>URS</name>
|
|
<description>desc URS</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OPM</name>
|
|
<description>desc OPM</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DIR</name>
|
|
<description>desc DIR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CMS</name>
|
|
<description>desc CMS</description>
|
|
<msb>6</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARPE</name>
|
|
<description>desc ARPE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKD</name>
|
|
<description>desc CKD</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xF8</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CCDS</name>
|
|
<description>desc CCDS</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MMS</name>
|
|
<description>desc MMS</description>
|
|
<msb>6</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TI1S</name>
|
|
<description>desc TI1S</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DIER</name>
|
|
<description>desc DIER</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIE</name>
|
|
<description>desc UIE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IE</name>
|
|
<description>desc CC1IE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IE</name>
|
|
<description>desc CC2IE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IE</name>
|
|
<description>desc CC3IE</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IE</name>
|
|
<description>desc CC4IE</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIE</name>
|
|
<description>desc TIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>UDE</name>
|
|
<description>desc UDE</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1DE</name>
|
|
<description>desc CC1DE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2DE</name>
|
|
<description>desc CC2DE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3DE</name>
|
|
<description>desc CC3DE</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4DE</name>
|
|
<description>desc CC4DE</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TDE</name>
|
|
<description>desc TDE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x1E5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UIF</name>
|
|
<description>desc UIF</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1IF</name>
|
|
<description>desc CC1IF</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2IF</name>
|
|
<description>desc CC2IF</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3IF</name>
|
|
<description>desc CC3IF</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4IF</name>
|
|
<description>desc CC4IF</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>COMIF</name>
|
|
<description>desc COMIF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TIF</name>
|
|
<description>desc TIF</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIF</name>
|
|
<description>desc BIF</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1OF</name>
|
|
<description>desc CC1OF</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2OF</name>
|
|
<description>desc CC2OF</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3OF</name>
|
|
<description>desc CC3OF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4OF</name>
|
|
<description>desc CC4OF</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IR</name>
|
|
<description>desc IC1IR</description>
|
|
<msb>16</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IR</name>
|
|
<description>desc IC2IR</description>
|
|
<msb>17</msb>
|
|
<lsb>17</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>18</msb>
|
|
<lsb>18</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IR</name>
|
|
<description>desc IC3IR</description>
|
|
<msb>19</msb>
|
|
<lsb>19</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC1IF</name>
|
|
<description>desc IC1IF</description>
|
|
<msb>20</msb>
|
|
<lsb>20</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC2IF</name>
|
|
<description>desc IC2IF</description>
|
|
<msb>21</msb>
|
|
<lsb>21</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC3IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>22</msb>
|
|
<lsb>22</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>IC4IF</name>
|
|
<description>desc IC3IF</description>
|
|
<msb>23</msb>
|
|
<lsb>23</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>EGR</name>
|
|
<description>desc EGR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0x5F</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>UG</name>
|
|
<description>desc UG</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC1G</name>
|
|
<description>Capture/Compare 1 Generation</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC2G</name>
|
|
<description>desc CC2G</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC3G</name>
|
|
<description>desc CC3G</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CC4G</name>
|
|
<description>desc CC4G</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TG</name>
|
|
<description>desc TG</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>write-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>CNT</name>
|
|
<description>desc CNT</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>PSC</name>
|
|
<description>desc PSC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFF</resetValue>
|
|
<resetMask>0xFFFF</resetMask>
|
|
<fields>
|
|
<field>
|
|
<name>ARR</name>
|
|
<description>desc ARR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SYSCFG</name>
|
|
<description>System configuration controller</description>
|
|
<groupName>SYSCFG</groupName>
|
|
<baseAddress>0x40010000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x30</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>CFGR1</name>
|
|
<displayName>CFGR1</displayName>
|
|
<description>SYSCFG configuration register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>I2C_PB6_FMP</name>
|
|
<description>desc I2C_PB6_FMP</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C_PB4_FMP</name>
|
|
<description>desc I2C_PB4_FMP</description>
|
|
<bitOffset>18</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C_PB3_FMP</name>
|
|
<description>desc I2C_PB3_FMP</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>I2C_PA2_FMP</name>
|
|
<description>desc I2C_PA2_FMP</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MEM_MODE</name>
|
|
<description>Memory mapping selection bits</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CFGR2</name>
|
|
<displayName>CFGR2</displayName>
|
|
<description>SYSCFG configuration register
|
|
2</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ETR_SRC_TIM1</name>
|
|
<description>TIM1 ETR source selection</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>2</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>LOCKUP_LOCK</name>
|
|
<description>Cortex-M0+ LOCKUP bit enable
|
|
bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>GPIO_ENS</name>
|
|
<description>desc GPIO_ENS</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PC_ENS</name>
|
|
<description>desc PC_ENS</description>
|
|
<msb>17</msb>
|
|
<lsb>16</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PB_ENS</name>
|
|
<description>desc PB_ENS</description>
|
|
<msb>15</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PA_ENS</name>
|
|
<description>desc PA_ENS</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>FLASH</name>
|
|
<description>Flash</description>
|
|
<groupName>Flash</groupName>
|
|
<baseAddress>0x40022000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>FLASH</name>
|
|
<description>FLASH global Interrupt</description>
|
|
<value>3</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>ACR</name>
|
|
<displayName>ACR</displayName>
|
|
<description>Access control register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000600</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LATENCY</name>
|
|
<description>Latency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>KEYR</name>
|
|
<displayName>KEYR</displayName>
|
|
<description>Flash key register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>KEY</name>
|
|
<description>Flash key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPTKEYR</name>
|
|
<displayName>OPTKEYR</displayName>
|
|
<description>Option byte key register</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>OPTKEY</name>
|
|
<description>Option byte key</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<displayName>SR</displayName>
|
|
<description>Status register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>Busy</description>
|
|
<bitOffset>16</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPTVERR</name>
|
|
<description>Option and Engineering bits loading
|
|
validity error</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WRPERR</name>
|
|
<description>Write protected error</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOP</name>
|
|
<description>End of operation</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Flash control register</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xC0000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>LOCK</name>
|
|
<description>FLASH_CR Lock</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPTLOCK</name>
|
|
<description>Options Lock</description>
|
|
<bitOffset>30</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OBL_LAUNCH</name>
|
|
<description>Force the option byte
|
|
loading</description>
|
|
<bitOffset>27</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>25</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>EOPIE</name>
|
|
<description>End of operation interrupt
|
|
enable</description>
|
|
<bitOffset>24</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PGTSTRT</name>
|
|
<description>Flash main memory program start</description>
|
|
<bitOffset>19</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>OPTSTRT</name>
|
|
<description>Option byte program start</description>
|
|
<bitOffset>17</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SER</name>
|
|
<description>Sector erase</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MER</name>
|
|
<description>Mass erase</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PER</name>
|
|
<description>Page erase</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PG</name>
|
|
<description>Programming</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OPTR</name>
|
|
<displayName>OPTR</displayName>
|
|
<description>Flash option register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x4F55B0AA</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>nBOOT1</name>
|
|
<description>Boot configuration</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NRST_MODE</name>
|
|
<description>NRST_MODE</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>WWDG_SW</name>
|
|
<description>Window watchdog selection</description>
|
|
<bitOffset>13</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>IWDG_SW</name>
|
|
<description>Independent watchdog
|
|
selection</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BORF_LEV</name>
|
|
<description>These bits contain the VDD supply level
|
|
threshold that activates the reset</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOREN</name>
|
|
<description>BOR reset Level</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>RDP</name>
|
|
<description>Read Protection </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SDKR</name>
|
|
<displayName>SDKR</displayName>
|
|
<description>Flash SDK address
|
|
register</description>
|
|
<addressOffset>0x24</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFE0001F</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SDK_END</name>
|
|
<description>SDK area end address</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SDK_STRT</name>
|
|
<description>SDK area start address</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>4</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>BTCR</name>
|
|
<displayName>SDKR</displayName>
|
|
<description>FLASH boot control register</description>
|
|
<addressOffset>0x28</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>BOOT0</name>
|
|
<description>desc BOOT0</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BOOT_SIZE</name>
|
|
<description>desc BOOT_SIZE</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>3</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>WRPR</name>
|
|
<displayName>WRPR</displayName>
|
|
<description>Flash WRP address
|
|
register</description>
|
|
<addressOffset>0x2C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>WRP</name>
|
|
<description>WRP address </description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>STCR</name>
|
|
<displayName>STCR</displayName>
|
|
<description>Flash sleep time config
|
|
register</description>
|
|
<addressOffset>0x90</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00006400</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SLEEP_TIME</name>
|
|
<description>FLash sleep time configuration(counter based on HSI_10M)</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>SLEEP_EN</name>
|
|
<description>FLash sleep enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TS0</name>
|
|
<displayName>TS0</displayName>
|
|
<description>Flash TS0
|
|
register</description>
|
|
<addressOffset>0x100</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000B4</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS0</name>
|
|
<description>FLash TS0 register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TS1</name>
|
|
<displayName>TS1</displayName>
|
|
<description>Flash TS1
|
|
register</description>
|
|
<addressOffset>0x104</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000001B0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS1</name>
|
|
<description>FLash TS1 register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>9</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TS2P</name>
|
|
<displayName>TS2P</displayName>
|
|
<description>Flash TS2P
|
|
register</description>
|
|
<addressOffset>0x108</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000B4</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS2P</name>
|
|
<description>FLash TS2P register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TPS3</name>
|
|
<displayName>TPS3</displayName>
|
|
<description>Flash TPS3
|
|
register</description>
|
|
<addressOffset>0x10C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000006C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TPS3</name>
|
|
<description>FLash TPS3 register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>11</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TS3</name>
|
|
<displayName>TS3</displayName>
|
|
<description>Flash TS3
|
|
register</description>
|
|
<addressOffset>0x110</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000000B4</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TS3</name>
|
|
<description>FLash TS3 register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PERTPE</name>
|
|
<displayName>PERTPE</displayName>
|
|
<description>Flash PERTPE
|
|
register</description>
|
|
<addressOffset>0x114</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000EA60</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PERTPE</name>
|
|
<description>FLash PERTPE register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SMERTPE</name>
|
|
<displayName>SMERTPE</displayName>
|
|
<description>Flash SMERTPE
|
|
register</description>
|
|
<addressOffset>0x118</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000FD20</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SMERTPE</name>
|
|
<description>FLash SMERTPE register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>17</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRGTPE</name>
|
|
<displayName>PRGTPE</displayName>
|
|
<description>Flash PRGTPE
|
|
register</description>
|
|
<addressOffset>0x11C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00008CA0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRGTPE</name>
|
|
<description>FLash PRGTPE register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>16</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>PRETPE</name>
|
|
<displayName>PRETPE</displayName>
|
|
<description>Flash PRETPE
|
|
register</description>
|
|
<addressOffset>0x120</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x000012C0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PRETPE</name>
|
|
<description>FLash PRETPE register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>13</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>CRC</name>
|
|
<description>CRC calculation unit</description>
|
|
<groupName>CRC</groupName>
|
|
<baseAddress>0x40023000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>Data register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0xFFFFFFFF</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>Data Register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>IDR</name>
|
|
<displayName>IDR</displayName>
|
|
<description>Independent Data register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>IDR</name>
|
|
<description>Independent Data register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Control register</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>write-only</access>
|
|
<resetValue>0x00000000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RESET</name>
|
|
<description>Reset bit</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>SPI1</name>
|
|
<description>Serial peripheral interface</description>
|
|
<groupName>SPI</groupName>
|
|
<baseAddress>0x40013000</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>SPI1</name>
|
|
<description>SPI1 global Interrupt</description>
|
|
<value>25</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<description>desc CR1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CPHA</name>
|
|
<description>desc CPHA</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CPOL</name>
|
|
<description>desc CPOL</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MSTR</name>
|
|
<description>desc MSTR</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BR</name>
|
|
<description>desc BR</description>
|
|
<msb>5</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SPE</name>
|
|
<description>desc SPE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LSBFIRST</name>
|
|
<description>desc LSBFIRST</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSI</name>
|
|
<description>desc SSI</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSM</name>
|
|
<description>desc SSM</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXONLY</name>
|
|
<description>desc RXONLY</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DDF</name>
|
|
<description>desc DDF</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCNEXT</name>
|
|
<description>desc CRCNEXT</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCEN</name>
|
|
<description>desc CRCEN</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIDIOE</name>
|
|
<description>desc BIDIOE</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BIDIMODE</name>
|
|
<description>desc BIDIMODE</description>
|
|
<msb>15</msb>
|
|
<lsb>15</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<description>desc CR2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXDMAEN</name>
|
|
<description>desc RXDMAEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXDMAEN</name>
|
|
<description>desc TXDMAEN</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>SSOE</name>
|
|
<description>desc SSOE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CLRTXFIFO</name>
|
|
<description>desc CLRTXFIFO</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ERRIE</name>
|
|
<description>desc ERRIE</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>RXNEIE</name>
|
|
<description>desc RXNEIE</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TXEIE</name>
|
|
<description>desc TXEIE</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>FRXTH</name>
|
|
<description>desc FRXTH</description>
|
|
<msb>12</msb>
|
|
<lsb>12</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LDMA_RX</name>
|
|
<description>desc LDMA_RX</description>
|
|
<msb>13</msb>
|
|
<lsb>13</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>LDMA_TX</name>
|
|
<description>desc LDMA_TX</description>
|
|
<msb>14</msb>
|
|
<lsb>14</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR</name>
|
|
<description>desc SR</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXNE</name>
|
|
<description>desc RXNE</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>TXE</name>
|
|
<description>desc TXE</description>
|
|
<msb>1</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CHSIDE</name>
|
|
<description>desc CHSIDE</description>
|
|
<msb>2</msb>
|
|
<lsb>2</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>UDR</name>
|
|
<description>desc UDR</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>CRCERR</name>
|
|
<description>desc CRCERR</description>
|
|
<msb>4</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MODF</name>
|
|
<description>desc MODF</description>
|
|
<msb>5</msb>
|
|
<lsb>5</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>desc OVR</description>
|
|
<msb>6</msb>
|
|
<lsb>6</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BSY</name>
|
|
<description>desc BSY</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FRLVL</name>
|
|
<description>desc FRLVL</description>
|
|
<msb>10</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>FTLVL</name>
|
|
<description>desc FTLVL</description>
|
|
<msb>12</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<description>desc DR</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>desc DR</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CRCPR</name>
|
|
<description>desc CRCPR</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x7</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CRCPOLY</name>
|
|
<description>desc CRCPOLY</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>RXCRCR</name>
|
|
<description>desc RXCRCR</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>RXCRC</name>
|
|
<description>desc RXCRC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TXCRCR</name>
|
|
<description>desc TXCRCR</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>32</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TXCRC</name>
|
|
<description>desc TXCRC</description>
|
|
<msb>15</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SCFGR</name>
|
|
<description>desc I2SCFGR</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>CHLEN</name>
|
|
<description>desc CHLEN</description>
|
|
<msb>0</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>DATLEN</name>
|
|
<description>desc DATLEN</description>
|
|
<msb>2</msb>
|
|
<lsb>1</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>CKPOL</name>
|
|
<description>desc CKPOL</description>
|
|
<msb>3</msb>
|
|
<lsb>3</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SSTD</name>
|
|
<description>desc I2SSTD</description>
|
|
<msb>5</msb>
|
|
<lsb>4</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>PCMSYNC</name>
|
|
<description>desc PCMSYNC</description>
|
|
<msb>7</msb>
|
|
<lsb>7</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SCFG</name>
|
|
<description>desc I2SCFG</description>
|
|
<msb>9</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SE</name>
|
|
<description>desc I2SE</description>
|
|
<msb>10</msb>
|
|
<lsb>10</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>I2SMOD</name>
|
|
<description>desc I2SMOD</description>
|
|
<msb>11</msb>
|
|
<lsb>11</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>I2SPR</name>
|
|
<description>desc I2SPR</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>32</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x2</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>I2SDIV</name>
|
|
<description>desc I2SDIV</description>
|
|
<msb>7</msb>
|
|
<lsb>0</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ODD</name>
|
|
<description>desc ODD</description>
|
|
<msb>8</msb>
|
|
<lsb>8</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>MCKOE</name>
|
|
<description>desc MCKOE</description>
|
|
<msb>9</msb>
|
|
<lsb>9</lsb>
|
|
<access>read-write</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>I2C</name>
|
|
<description>Inter integrated circuit</description>
|
|
<groupName>I2C</groupName>
|
|
<baseAddress>0x40005400</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<interrupt>
|
|
<name>I2C1</name>
|
|
<description>I2C1 global Interrupt</description>
|
|
<value>23</value>
|
|
</interrupt>
|
|
<registers>
|
|
<register>
|
|
<name>CR1</name>
|
|
<displayName>CR1</displayName>
|
|
<description>Control register 1</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>SWRST</name>
|
|
<description>Software reset</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>Packet error checking</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>POS</name>
|
|
<description>Acknowledge/PEC Position (for datareception)</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ACK</name>
|
|
<description>Acknowledge enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>STOP</name>
|
|
<description>Stop generation</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>START</name>
|
|
<description>Start generation</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>NOSTRETCH</name>
|
|
<description>Clock stretching disable (Slavemode)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENGC</name>
|
|
<description>General call enable</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ENPEC</name>
|
|
<description>PEC enable</description>
|
|
<bitOffset>5</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>PE</name>
|
|
<description>Peripheral enable</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR2</name>
|
|
<displayName>CR2</displayName>
|
|
<description>Control register 2</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ITBUFEN</name>
|
|
<description>Buffer interrupt enable</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITEVTEN</name>
|
|
<description>Event interrupt enable</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>ITERREN</name>
|
|
<description>Error interrupt enable</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>FREQ</name>
|
|
<description>Peripheral clock frequency</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>OAR1</name>
|
|
<displayName>OAR1</displayName>
|
|
<description>Own address register 1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>ADD</name>
|
|
<description>Interface address</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>7</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>DR</name>
|
|
<displayName>DR</displayName>
|
|
<description>Data register</description>
|
|
<addressOffset>0x10</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DR</name>
|
|
<description>8-bit data register</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR1</name>
|
|
<displayName>SR1</displayName>
|
|
<description>Status register 1</description>
|
|
<addressOffset>0x14</addressOffset>
|
|
<size>0x20</size>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PECERR</name>
|
|
<description>PEC Error in reception</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>OVR</name>
|
|
<description>Overrun/Underrun</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>AF</name>
|
|
<description>Acknowledge failure</description>
|
|
<bitOffset>10</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>ARLO</name>
|
|
<description>Arbitration lost (mastermode)</description>
|
|
<bitOffset>9</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>BERR</name>
|
|
<description>Bus error</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-write</access>
|
|
</field>
|
|
<field>
|
|
<name>TxE</name>
|
|
<description>Data register empty(transmitters)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>RxNE</name>
|
|
<description>Data register not empty(receivers)</description>
|
|
<bitOffset>6</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>STOPF</name>
|
|
<description>Stop detection (slavemode)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>BTF</name>
|
|
<description>Byte transfer finished</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>ADDR</name>
|
|
<description>Address sent (master mode)/matched(slave mode)</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
<field>
|
|
<name>SB</name>
|
|
<description>Start bit (Master mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
<access>read-only</access>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>SR2</name>
|
|
<displayName>SR2</displayName>
|
|
<description>Status register 2</description>
|
|
<addressOffset>0x18</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>PEC</name>
|
|
<description>acket error checkingregister</description>
|
|
<bitOffset>8</bitOffset>
|
|
<bitWidth>8</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUALF</name>
|
|
<description>Dual flag (Slave mode)</description>
|
|
<bitOffset>7</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>GENCALL</name>
|
|
<description>General call address (Slavemode)</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>TRA</name>
|
|
<description>Transmitter/receiver</description>
|
|
<bitOffset>2</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>BUSY</name>
|
|
<description>Bus busy</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>MSL</name>
|
|
<description>Master/slave</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CCR</name>
|
|
<displayName>CCR</displayName>
|
|
<description>Clock control register</description>
|
|
<addressOffset>0x1C</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0000</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>F_S</name>
|
|
<description>I2C master mode selection</description>
|
|
<bitOffset>15</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DUTY</name>
|
|
<description>Fast mode duty cycle</description>
|
|
<bitOffset>14</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>CCR</name>
|
|
<description>Clock control register in Fast/Standardmode (Master mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>12</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>TRISE</name>
|
|
<displayName>TRISE</displayName>
|
|
<description>TRISE register</description>
|
|
<addressOffset>0x20</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0002</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>TRISE</name>
|
|
<description>Maximum rise time in Fast/Standard mode(Master mode)</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>6</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
<peripheral>
|
|
<name>DBGMCU</name>
|
|
<description>Debug support</description>
|
|
<groupName>DBGMCU</groupName>
|
|
<baseAddress>0x40015800</baseAddress>
|
|
<addressBlock>
|
|
<offset>0x0</offset>
|
|
<size>0x400</size>
|
|
<usage>registers</usage>
|
|
</addressBlock>
|
|
<registers>
|
|
<register>
|
|
<name>IDCODE</name>
|
|
<displayName>IDCODE</displayName>
|
|
<description>MCU Device ID Code Register</description>
|
|
<addressOffset>0x0</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-only</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>REV_ID</name>
|
|
<description>REV_ID</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>32</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>CR</name>
|
|
<displayName>CR</displayName>
|
|
<description>Debug MCU Configuration Register</description>
|
|
<addressOffset>0x4</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_SLEEP</name>
|
|
<description>Debug Sleep Mode</description>
|
|
<bitOffset>0</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_STOP</name>
|
|
<description>Debug Stop Mode</description>
|
|
<bitOffset>1</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB_FZ1</name>
|
|
<displayName>APB_FZ1</displayName>
|
|
<description>APB Freeze Register1</description>
|
|
<addressOffset>0x8</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_TIM6_STOP</name>
|
|
<description>Debug TIM 6 stopped whenCore is halted</description>
|
|
<bitOffset>4</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_IWDG_STOP</name>
|
|
<description>Debug Independent Wachdog stopped whenCore is halted</description>
|
|
<bitOffset>12</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_I2C1_TIMEOUT</name>
|
|
<description>Debug I2C1 TIMEOUT stopped when Core ishalted</description>
|
|
<bitOffset>21</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
<field>
|
|
<name>DBG_LPTIM_STOP</name>
|
|
<description>Debug LPTIM stopped when Core ishalted</description>
|
|
<bitOffset>31</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
<register>
|
|
<name>APB_FZ2</name>
|
|
<displayName>APB_FZ2</displayName>
|
|
<description>APB Freeze Register2</description>
|
|
<addressOffset>0xC</addressOffset>
|
|
<size>0x20</size>
|
|
<access>read-write</access>
|
|
<resetValue>0x0</resetValue>
|
|
<fields>
|
|
<field>
|
|
<name>DBG_TIMER1_STOP</name>
|
|
<description>Debug Timer 1 stopped when Core ishalted</description>
|
|
<bitOffset>11</bitOffset>
|
|
<bitWidth>1</bitWidth>
|
|
</field>
|
|
</fields>
|
|
</register>
|
|
</registers>
|
|
</peripheral>
|
|
</peripherals>
|
|
</device>
|