mirror of
https://github.com/IcedRooibos/py32f0-template.git
synced 2025-10-29 08:52:04 -07:00
448 lines
12 KiB
C
448 lines
12 KiB
C
#include <stdio.h>
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#include "nrf24l01.h"
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#include "py32f0xx_bsp_printf.h"
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uint8_t RX_BUF[NRF24L01_PLOAD_WIDTH];
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uint8_t TX_BUF[NRF24L01_PLOAD_WIDTH];
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void NRF24L01_Init(void)
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{
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CSN(1);
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}
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/**
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* Read a 1-bit register
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*/
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uint8_t NRF24L01_Read_Reg(uint8_t reg)
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{
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uint8_t value;
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CSN(0);
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SPI_TxRxByte(reg);
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value = SPI_TxRxByte(NRF24L01_CMD_NOP);
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CSN(1);
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return value;
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}
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/**
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* Write a 1-byte register
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*/
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uint8_t NRF24L01_Write_Reg(uint8_t reg, uint8_t value)
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{
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uint8_t status;
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CSN(0);
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if (reg < NRF24L01_CMD_REGISTER_W)
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{
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// This is a register access
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status = SPI_TxRxByte(NRF24L01_CMD_REGISTER_W | (reg & NRF24L01_MASK_REG_MAP));
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SPI_TxRxByte(value);
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}
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else
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{
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// This is a single byte command or future command/register
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status = SPI_TxRxByte(reg);
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if ((reg != NRF24L01_CMD_FLUSH_TX)
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&& (reg != NRF24L01_CMD_FLUSH_RX)
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&& (reg != NRF24L01_CMD_REUSE_TX_PL)
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&& (reg != NRF24L01_CMD_NOP)) {
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// Send register value
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SPI_TxRxByte(value);
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}
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}
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CSN(1);
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return status;
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}
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/**
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* Read a multi-byte register
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* reg - register to read
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* buf - pointer to the buffer to write
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* len - number of bytes to read
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*/
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uint8_t NRF24L01_Read_To_Buf(uint8_t reg, uint8_t *buf, uint8_t len)
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{
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CSN(0);
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uint8_t status = SPI_TxRxByte(reg);
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while (len--)
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{
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*buf++ = SPI_TxRxByte(NRF24L01_CMD_NOP);
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}
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CSN(1);
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return status;
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}
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/**
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* Write a multi-byte register
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* reg - register to write
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* buf - pointer to the buffer with data
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* len - number of bytes to write
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*/
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uint8_t NRF24L01_Write_From_Buf(uint8_t reg, uint8_t *buf, uint8_t len)
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{
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CSN(0);
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uint8_t status = SPI_TxRxByte(reg);
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while (len--)
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{
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SPI_TxRxByte(*buf++);
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}
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CSN(1);
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return status;
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}
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uint8_t NRF24L01_Check(void)
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{
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uint8_t rxbuf[5];
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uint8_t i;
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uint8_t *ptr = (uint8_t *)NRF24L01_TEST_ADDR;
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// Write test TX address and read TX_ADDR register
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NRF24L01_Write_From_Buf(NRF24L01_CMD_REGISTER_W | NRF24L01_REG_TX_ADDR, ptr, 5);
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NRF24L01_Read_To_Buf(NRF24L01_CMD_REGISTER_R | NRF24L01_REG_TX_ADDR, rxbuf, 5);
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// Compare buffers, return error on first mismatch
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for (i = 0; i < 5; i++)
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{
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if (rxbuf[i] != *ptr++) return 1;
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}
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return 0;
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}
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/**
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* Flush the RX FIFO
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*/
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void NRF24L01_FlushRX(void)
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{
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NRF24L01_Write_Reg(NRF24L01_CMD_FLUSH_RX, NRF24L01_CMD_NOP);
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}
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/**
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* Flush the TX FIFO
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*/
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void NRF24L01_FlushTX(void)
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{
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NRF24L01_Write_Reg(NRF24L01_CMD_FLUSH_TX, NRF24L01_CMD_NOP);
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}
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/**
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* Clear IRQ bit of the STATUS register
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* reg - NRF24L01_FLAG_RX_DREADY
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* NRF24L01_FLAG_TX_DSENT
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* NRF24L01_FLAG_MAX_RT
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*/
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void NRF24L01_ClearIRQFlag(uint8_t reg) {
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NRF24L01_Write_Reg(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_STATUS, reg);
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}
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/**
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* Clear RX_DR, TX_DS and MAX_RT bits of the STATUS register
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*/
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void NRF24L01_ClearIRQFlags(void) {
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uint8_t reg;
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reg = NRF24L01_Read_Reg(NRF24L01_REG_STATUS);
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reg |= NRF24L01_MASK_STATUS_IRQ;
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NRF24L01_Write_Reg(NRF24L01_REG_STATUS, reg);
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}
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/**
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* Common configurations of RX and TX, internal function
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*/
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void _NRF24L01_Config(uint8_t *tx_addr)
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{
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// TX Address
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NRF24L01_Write_From_Buf(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_TX_ADDR, tx_addr, NRF24L01_ADDR_WIDTH);
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// RX P0 Payload Width
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NRF24L01_Write_Reg(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_RX_PW_P0, NRF24L01_PLOAD_WIDTH);
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// Enable Auto ACK
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NRF24L01_Write_Reg(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_EN_AA, 0x3f);
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// Enable RX channels
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NRF24L01_Write_Reg(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_EN_RXADDR, 0x3f);
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// RF channel: 2.400G + 0.001 * x
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NRF24L01_Write_Reg(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_RF_CH, 40);
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// 000+0+[0:1Mbps,1:2Mbps]+[00:-18dbm,01:-12dbm,10:-6dbm,11:0dbm]+[0:LNA_OFF,1:LNA_ON]
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// 01:1Mbps,-18dbm; 03:1Mbps,-12dbm; 05:1Mbps,-6dbm; 07:1Mbps,0dBm
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// 09:2Mbps,-18dbm; 0b:2Mbps,-12dbm; 0d:2Mbps,-6dbm; 0f:2Mbps,0dBm,
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NRF24L01_Write_Reg(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_RF_SETUP, 0x03);
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// 0A:delay=250us,count=10, 1A:delay=500us,count=10
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NRF24L01_Write_Reg(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_SETUP_RETR, 0x0a);
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}
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/**
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* Switch NRF24L01 to RX mode
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*/
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void NRF24L01_RX_Mode(uint8_t *rx_addr, uint8_t *tx_addr)
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{
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CE(0);
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_NRF24L01_Config(tx_addr);
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// RX Address of P0
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NRF24L01_Write_From_Buf(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_RX_ADDR_P0, rx_addr, NRF24L01_ADDR_WIDTH);
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/**
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REG 0x00:
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0)PRIM_RX 0:TX 1:RX
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1)PWR_UP 0:OFF 1:ON
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2)CRCO 0:8bit CRC 1:16bit CRC
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3)EN_CRC Enabled if any of EN_AA is high
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4)MASK_MAX_RT 0:IRQ low 1:NO IRQ
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5)MASK_TX_DS 0:IRQ low 1:NO IRQ
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6)MASK_RX_DR 0:IRQ low 1:NO IRQ
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7)Reserved 0
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*/
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NRF24L01_Write_Reg(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_CONFIG, 0x0f); //RX,PWR_UP,CRC16,EN_CRC
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CE(1);
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}
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/**
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* Switch NRF24L01 to TX mode
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*/
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void NRF24L01_TX_Mode(uint8_t *rx_addr, uint8_t *tx_addr)
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{
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CE(0);
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_NRF24L01_Config(tx_addr);
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// On the PTX the **TX_ADDR** must be the same as the **RX_ADDR_P0** and as the pipe address for the designated pipe
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// RX_ADDR_P0 will be used for receiving ACK
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NRF24L01_Write_From_Buf(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_RX_ADDR_P0, tx_addr, NRF24L01_ADDR_WIDTH);
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NRF24L01_Write_Reg(NRF24L01_CMD_REGISTER_W + NRF24L01_REG_CONFIG, 0x0e); //TX,PWR_UP,CRC16,EN_CRC
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CE(1);
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}
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/**
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* Hold till data received and written to rx_buf
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*/
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uint8_t NRF24L01_RxPacket(uint8_t *rx_buf)
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{
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uint8_t status, result = 0;
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while(IRQ);
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CE(0);
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status = NRF24L01_Read_Reg(NRF24L01_REG_STATUS);
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printf("Interrupted, status: %02X\r\n", status);
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if(status & NRF24L01_FLAG_RX_DREADY)
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{
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NRF24L01_Read_To_Buf(NRF24L01_CMD_RX_PLOAD_R, rx_buf, NRF24L01_PLOAD_WIDTH);
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for (int i = 0; i < 32; i++)
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{
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printf("%02X ", RX_BUF[i]);
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}
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result = 1;
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NRF24L01_ClearIRQFlag(NRF24L01_FLAG_RX_DREADY);
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}
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CE(1);
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return result;
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}
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/**
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* Send data in tx_buf and wait till data is sent or max re-tr reached
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*/
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uint8_t NRF24L01_TxPacket(uint8_t *tx_buf, uint8_t len)
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{
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uint8_t status = 0x00;
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CE(0);
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len = len > NRF24L01_PLOAD_WIDTH? NRF24L01_PLOAD_WIDTH : len;
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NRF24L01_Write_From_Buf(NRF24L01_CMD_TX_PLOAD_W, tx_buf, len);
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CE(1);
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while(IRQ != 0); // Waiting send finish
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CE(0);
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status = NRF24L01_Read_Reg(NRF24L01_REG_STATUS);
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printf("Interrupted, status: %02X\r\n", status);
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if(status & NRF24L01_FLAG_TX_DSENT)
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{
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printf("Data sent: ");
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for (uint8_t i = 0; i < len; i++) {
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printf("%02X ", tx_buf[i]);
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}
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printf("\r\n");
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NRF24L01_ClearIRQFlag(NRF24L01_FLAG_TX_DSENT);
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}
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else if(status & NRF24L01_FLAG_MAX_RT)
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{
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printf("Sending exceeds max retries\r\n");
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NRF24L01_FlushTX();
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NRF24L01_ClearIRQFlag(NRF24L01_FLAG_MAX_RT);
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}
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CE(1);
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return status;
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}
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/**
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* Dump nRF24L01 configuration
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*/
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void NRF24L01_DumpConfig(void) {
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uint8_t i,j;
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uint8_t aw;
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uint8_t buf[5];
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// CONFIG
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i = NRF24L01_Read_Reg(NRF24L01_REG_CONFIG);
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printf("[0x%02X] 0x%02X MASK:%02X CRC:%02X PWR:%s MODE:P%s\r\n",
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NRF24L01_REG_CONFIG,
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i,
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i >> 4,
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(i & 0x0c) >> 2,
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(i & 0x02) ? "ON" : "OFF",
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(i & 0x01) ? "RX" : "TX"
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);
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// EN_AA
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i = NRF24L01_Read_Reg(NRF24L01_REG_EN_AA);
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printf("[0x%02X] 0x%02X ENAA: ",NRF24L01_REG_EN_AA,i);
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for (j = 0; j < 6; j++) {
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printf("[P%1u%s]%s",j,
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(i & (1 << j)) ? "+" : "-",
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(j == 5) ? "\r\n" : " "
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);
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}
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// EN_RXADDR
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i = NRF24L01_Read_Reg(NRF24L01_REG_EN_RXADDR);
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printf("[0x%02X] 0x%02X EN_RXADDR: ",NRF24L01_REG_EN_RXADDR,i);
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for (j = 0; j < 6; j++) {
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printf("[P%1u%s]%s",j,
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(i & (1 << j)) ? "+" : "-",
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(j == 5) ? "\r\n" : " "
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);
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}
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// SETUP_AW
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i = NRF24L01_Read_Reg(NRF24L01_REG_SETUP_AW);
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aw = (i & 0x03) + 2;
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printf("[0x%02X] 0x%02X EN_RXADDR=%03X (address width = %u)\r\n",NRF24L01_REG_SETUP_AW,i,i & 0x03,aw);
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// SETUP_RETR
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i = NRF24L01_Read_Reg(NRF24L01_REG_SETUP_RETR);
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printf("[0x%02X] 0x%02X ARD=%04X ARC=%04X (retr.delay=%uus, count=%u)\r\n",
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NRF24L01_REG_SETUP_RETR,
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i,
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i >> 4,
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i & 0x0F,
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((i >> 4) * 250) + 250,
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i & 0x0F
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);
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// RF_CH
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i = NRF24L01_Read_Reg(NRF24L01_REG_RF_CH);
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printf("[0x%02X] 0x%02X (%.3uGHz)\r\n",NRF24L01_REG_RF_CH,i,2400 + i);
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// RF_SETUP
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i = NRF24L01_Read_Reg(NRF24L01_REG_RF_SETUP);
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printf("[0x%02X] 0x%02X CONT_WAVE:%s PLL_LOCK:%s DataRate=",
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NRF24L01_REG_RF_SETUP,
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i,
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(i & 0x80) ? "ON" : "OFF",
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(i & 0x80) ? "ON" : "OFF"
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);
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switch ((i & 0x28) >> 3) {
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case 0x00:
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printf("1M");
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break;
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case 0x01:
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printf("2M");
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break;
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case 0x04:
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printf("250k");
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break;
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default:
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printf("???");
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break;
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}
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printf("pbs RF_PWR=");
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switch ((i & 0x06) >> 1) {
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case 0x00:
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printf("-18");
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break;
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case 0x01:
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printf("-12");
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break;
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case 0x02:
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printf("-6");
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break;
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case 0x03:
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printf("0");
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break;
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default:
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printf("???");
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break;
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}
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printf("dBm\r\n");
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// STATUS
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i = NRF24L01_Read_Reg(NRF24L01_REG_STATUS);
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printf("[0x%02X] 0x%02X IRQ:%03X RX_PIPE:%u TX_FULL:%s\r\n",
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NRF24L01_REG_STATUS,
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i,
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(i & 0x70) >> 4,
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(i & 0x0E) >> 1,
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(i & 0x01) ? "YES" : "NO"
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);
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// OBSERVE_TX
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i = NRF24L01_Read_Reg(NRF24L01_REG_OBSERVE_TX);
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printf("[0x%02X] 0x%02X PLOS_CNT=%u ARC_CNT=%u\r\n",NRF24L01_REG_OBSERVE_TX,i,i >> 4,i & 0x0F);
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// RPD
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i = NRF24L01_Read_Reg(NRF24L01_REG_RPD);
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printf("[0x%02X] 0x%02X RPD=%s\r\n",NRF24L01_REG_RPD,i,(i & 0x01) ? "YES" : "NO");
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// RX_ADDR_P0
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NRF24L01_Read_To_Buf(NRF24L01_REG_RX_ADDR_P0,buf,aw);
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printf("[0x%02X] RX_ADDR_P0 \"",NRF24L01_REG_RX_ADDR_P0);
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for (i = 0; i < aw; i++) printf("%X ",buf[i]);
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printf("\"\r\n");
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// RX_ADDR_P1
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NRF24L01_Read_To_Buf(NRF24L01_REG_RX_ADDR_P1,buf,aw);
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printf("[0x%02X] RX_ADDR_P1 \"",NRF24L01_REG_RX_ADDR_P1);
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for (i = 0; i < aw; i++) printf("%X ",buf[i]);
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printf("\"\r\n");
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// RX_ADDR_P2
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printf("[0x%02X] RX_ADDR_P2 \"",NRF24L01_REG_RX_ADDR_P2);
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for (i = 0; i < aw - 1; i++) printf("%X ",buf[i]);
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i = NRF24L01_Read_Reg(NRF24L01_REG_RX_ADDR_P2);
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printf("%X\"\r\n",i);
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// RX_ADDR_P3
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printf("[0x%02X] RX_ADDR_P3 \"",NRF24L01_REG_RX_ADDR_P3);
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for (i = 0; i < aw - 1; i++) printf("%X ",buf[i]);
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i = NRF24L01_Read_Reg(NRF24L01_REG_RX_ADDR_P3);
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printf("%X\"\r\n",i);
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// RX_ADDR_P4
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printf("[0x%02X] RX_ADDR_P4 \"",NRF24L01_REG_RX_ADDR_P4);
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for (i = 0; i < aw - 1; i++) printf("%X ",buf[i]);
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i = NRF24L01_Read_Reg(NRF24L01_REG_RX_ADDR_P4);
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printf("%X\"\r\n",i);
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// RX_ADDR_P5
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printf("[0x%02X] RX_ADDR_P5 \"",NRF24L01_REG_RX_ADDR_P5);
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for (i = 0; i < aw - 1; i++) printf("%X ",buf[i]);
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i = NRF24L01_Read_Reg(NRF24L01_REG_RX_ADDR_P5);
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printf("%X\"\r\n",i);
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// TX_ADDR
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NRF24L01_Read_To_Buf(NRF24L01_REG_TX_ADDR,buf,aw);
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printf("[0x%02X] TX_ADDR \"",NRF24L01_REG_TX_ADDR);
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for (i = 0; i < aw; i++) printf("%X ",buf[i]);
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printf("\"\r\n");
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// RX_PW_P0
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i = NRF24L01_Read_Reg(NRF24L01_REG_RX_PW_P0);
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printf("[0x%02X] RX_PW_P0=%u\r\n",NRF24L01_REG_RX_PW_P0,i);
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// RX_PW_P1
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i = NRF24L01_Read_Reg(NRF24L01_REG_RX_PW_P1);
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printf("[0x%02X] RX_PW_P1=%u\r\n",NRF24L01_REG_RX_PW_P1,i);
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// RX_PW_P2
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i = NRF24L01_Read_Reg(NRF24L01_REG_RX_PW_P2);
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printf("[0x%02X] RX_PW_P2=%u\r\n",NRF24L01_REG_RX_PW_P2,i);
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// RX_PW_P3
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i = NRF24L01_Read_Reg(NRF24L01_REG_RX_PW_P3);
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printf("[0x%02X] RX_PW_P3=%u\r\n",NRF24L01_REG_RX_PW_P3,i);
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// RX_PW_P4
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i = NRF24L01_Read_Reg(NRF24L01_REG_RX_PW_P4);
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printf("[0x%02X] RX_PW_P4=%u\r\n",NRF24L01_REG_RX_PW_P4,i);
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// RX_PW_P5
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i = NRF24L01_Read_Reg(NRF24L01_REG_RX_PW_P5);
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printf("[0x%02X] RX_PW_P5=%u\r\n",NRF24L01_REG_RX_PW_P5,i);
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}
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