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227 lines
9.8 KiB
C
227 lines
9.8 KiB
C
#ifndef _NRF24L01_H
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#define _NRF24L01_H
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#include <main.h>
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// CE Pin & CSN Pin & IRQ Pin
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#define CSN_HIGH LL_GPIO_SetOutputPin(GPIOA, LL_GPIO_PIN_6)
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#define CSN_LOW LL_GPIO_ResetOutputPin(GPIOA, LL_GPIO_PIN_6)
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#define CE_HIGH LL_GPIO_SetOutputPin(GPIOA, LL_GPIO_PIN_5)
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#define CE_LOW LL_GPIO_ResetOutputPin(GPIOA, LL_GPIO_PIN_5)
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#define IRQ READ_BIT(GPIOA->IDR, LL_GPIO_PIN_4)
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// SPI(nRF24L01) commands
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#define NRF24L01_CMD_R_REGISTER 0x00 // Register read
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#define NRF24L01_CMD_W_REGISTER 0x20 // Register write
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/**
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* ACTIVATE. For NRF24L01 only, removed from NRF24L01+ product specs
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* - https://github.com/nRF24/RF24/issues/401
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*
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* This write command followed by data 0x73 activates the following features: R_RX_PL_WID, W_ACK_PAYLOAD, W_TX_PAYLOAD_NOACK.
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* A new ACTIVATE command with the same data deactivates them again. This is executable in power down or stand by modes only.
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*/
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#define NRF24L01_CMD_ACTIVATE 0x50 // (De)Activates R_RX_PL_WID, W_ACK_PAYLOAD, W_TX_PAYLOAD_NOACK features
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#define NRF24L01_CMD_R_RX_PL_WID 0x60 // Read RX-payload width for the top R_RX_PAYLOAD in the RX FIFO. Flush RX FIFO if the read value is larger than 32 bytes
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#define NRF24L01_CMD_R_RX_PAYLOAD 0x61 // Read RX payload
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#define NRF24L01_CMD_W_TX_PAYLOAD 0xA0 // Write TX payload
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#define NRF24L01_CMD_W_ACK_PAYLOAD 0xA8 // 1010 1PPP, Used in RX mode. Write Payload to be transmitted together with ACK packet on PIPE PPP. (PPP valid in the range from 000 to 101)
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#define NRF24L01_CMD_W_TX_PAYLOAD_NOACK 0xB0 // Used in TX mode. Disables AUTOACK on this specific packet
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#define NRF24L01_CMD_FLUSH_TX 0xE1 // Flush TX FIFO
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#define NRF24L01_CMD_FLUSH_RX 0xE2 // Flush RX FIFO
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#define NRF24L01_CMD_REUSE_TX_PL 0xE3 // Reuse TX payload
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#define NRF24L01_CMD_LOCK_UNLOCK 0x50 // Lock/unlock exclusive features
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#define NRF24L01_CMD_NOP 0xFF // No operation (used for reading status register)
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// SPI(nRF24L01) register address definitions
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#define NRF24L01_REG_CONFIG 0x00 // Configuration register
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#define NRF24L01_REG_EN_AA 0x01 // Enable "Auto acknowledgment"
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#define NRF24L01_REG_EN_RXADDR 0x02 // Enable RX addresses
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#define NRF24L01_REG_SETUP_AW 0x03 // Setup of address widths
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#define NRF24L01_REG_SETUP_RETR 0x04 // Setup of automatic re-transmit
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#define NRF24L01_REG_RF_CH 0x05 // RF channel
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#define NRF24L01_REG_RF_SETUP 0x06 // RF setup
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#define NRF24L01_REG_STATUS 0x07 // Status register
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#define NRF24L01_REG_OBSERVE_TX 0x08 // Transmit observe register
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#define NRF24L01_REG_RPD 0x09 // Received power detector
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#define NRF24L01_REG_RX_ADDR_P0 0x0A // Receive address data pipe 0
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#define NRF24L01_REG_RX_ADDR_P1 0x0B // Receive address data pipe 1
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#define NRF24L01_REG_RX_ADDR_P2 0x0C // Receive address data pipe 2
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#define NRF24L01_REG_RX_ADDR_P3 0x0D // Receive address data pipe 3
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#define NRF24L01_REG_RX_ADDR_P4 0x0E // Receive address data pipe 4
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#define NRF24L01_REG_RX_ADDR_P5 0x0F // Receive address data pipe 5
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#define NRF24L01_REG_TX_ADDR 0x10 // Transmit address
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#define NRF24L01_REG_RX_PW_P0 0x11 // Number of bytes in RX payload in data pipe 0
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#define NRF24L01_REG_RX_PW_P1 0x12 // Number of bytes in RX payload in data pipe 1
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#define NRF24L01_REG_RX_PW_P2 0x13 // Number of bytes in RX payload in data pipe 2
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#define NRF24L01_REG_RX_PW_P3 0x14 // Number of bytes in RX payload in data pipe 3
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#define NRF24L01_REG_RX_PW_P4 0x15 // Number of bytes in RX payload in data pipe 4
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#define NRF24L01_REG_RX_PW_P5 0x16 // Number of bytes in RX payload in data pipe 5
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#define NRF24L01_REG_FIFO_STATUS 0x17 // FIFO status register
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#define NRF24L01_REG_DYNPD 0x1C // Enable dynamic payload length
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#define NRF24L01_REG_FEATURE 0x1D // Feature register
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// Register bits definitions
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#define NRF24L01_CONFIG_PRIM_RX 0x01 // PRIM_RX bit in CONFIG register
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#define NRF24L01_CONFIG_PWR_UP 0x02 // PWR_UP bit in CONFIG register
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// Enable dynamic payload length on data pipes
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#define NRF24L01_DYNPD_DPL_P5 0x20
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#define NRF24L01_DYNPD_DPL_P4 0x10
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#define NRF24L01_DYNPD_DPL_P3 0x08
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#define NRF24L01_DYNPD_DPL_P2 0x04
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#define NRF24L01_DYNPD_DPL_P1 0x02
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#define NRF24L01_DYNPD_DPL_P0 0x01
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/**
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* EN_DYN_ACK - this bit enables the W_TX_PAYLOAD_NOACK command
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*
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* The PTX can set the NO_ACK flag bit in the Packet Control Field with this command: W_TX_PAYLOAD_NOACK
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* However, the function must first be enabled in the FEATURE register by setting the EN_DYN_ACK bit.
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* When you use this option the PTX goes directly to standby-I mode after transmitting the packet. The PRX
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* does not transmit an ACK packet when it receives the packet.
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*/
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#define NRF24L01_FEATURE_EN_DYN_ACK 0x01 // EN_DYN_ACK bit in FEATURE register
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/**
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* EN_ACK_PAY - Enables Payload with ACK
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* If ACK packet payload is activated, ACK packets have dynamic payload lengths and the Dynamic Payload
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* Length feature should be enabled for pipe 0 on the PTX and PRX. This is to ensure that they receive the
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* ACK packets with payloads. If the ACK payload is more than 15 byte in 2Mbps mode the ARD must be
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* 500µS or more, and if the ACK payload is more than 5 byte in 1Mbps mode the ARD must be 500µS or
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* more. In 250kbps mode (even when the payload is not in ACK) the ARD must be 500µS or more.
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*/
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#define NRF24L01_FEATURE_EN_ACK_PAY 0x02 // EN_ACK_PAY bit in FEATURE register
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#define NRF24L01_FEATURE_EN_DPL 0x04 // EN_DPL bit in FEATURE register, enables Dynamic Payload Length
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// Status Flags
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#define NRF24L01_FLAG_RX_DR 0x40 // RX_DR bit (data ready RX FIFO interrupt)
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#define NRF24L01_FLAG_TX_DS 0x20 // TX_DS bit (data sent TX FIFO interrupt)
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#define NRF24L01_FLAG_MAX_RT 0x10 // MAX_RT bit (maximum number of TX re-transmits interrupt)
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#define NRF24L01_FLAG_IT_BITS 0x70 // RX_DR|TX_DS|MAX_RT
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#define NRF24L01_FLAG_TX_FULL 0x01 // TX FIFO full flag. 1: TX FIFO full. 0: Available locations in TX FIFO
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// Register masks definitions
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#define NRF24L01_MASK_REG_MAP 0x1F // Mask bits[4:0] for CMD_RREG and CMD_WREG commands
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#define NRF24L01_MASK_CRC 0x0C // Mask for CRC bits [3:2] in CONFIG register
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#define NRF24L01_MASK_STATUS_IRQ 0x70 // Mask for all IRQ bits in STATUS register
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#define NRF24L01_MASK_RF_PWR 0x06 // Mask RF_PWR[2:1] bits in RF_SETUP register
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#define NRF24L01_MASK_RX_P_NO 0x0E // Mask RX_P_NO[3:1] bits in STATUS register
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#define NRF24L01_MASK_DATARATE 0x28 // Mask RD_DR_[5,3] bits in RF_SETUP register
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#define NRF24L01_MASK_EN_RX 0x3F // Mask ERX_P[5:0] bits in EN_RXADDR register
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#define NRF24L01_MASK_RX_PW 0x3F // Mask [5:0] bits in RX_PW_Px register
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#define NRF24L01_MASK_RETR_ARD 0xF0 // Mask for ARD[7:4] bits in SETUP_RETR register
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#define NRF24L01_MASK_RETR_ARC 0x0F // Mask for ARC[3:0] bits in SETUP_RETR register
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#define NRF24L01_MASK_RXFIFO 0x03 // Mask for RX FIFO status bits [1:0] in FIFO_STATUS register
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#define NRF24L01_MASK_TXFIFO 0x30 // Mask for TX FIFO status bits [5:4] in FIFO_STATUS register
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#define NRF24L01_MASK_PLOS_CNT 0xF0 // Mask for PLOS_CNT[7:4] bits in OBSERVE_TX register
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#define NRF24L01_MASK_ARC_CNT 0x0F // Mask for ARC_CNT[3:0] bits in OBSERVE_TX register
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// Register masks definitions
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#define NRF24L01_MASK_REG_MAP 0x1F // Mask bits[4:0] for CMD_RREG and CMD_WREG commands
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// RXFIFO status
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#define NRF24L01_RXFIFO_STATUS_DATA 0x00 // The RX FIFO contains data and available locations
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#define NRF24L01_RXFIFO_STATUS_EMPTY 0x01 // The RX FIFO is empty
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#define NRF24L01_RXFIFO_STATUS_FULL 0x02 // The RX FIFO is full
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#define NRF24L01_RXFIFO_STATUS_ERROR 0x03 // Impossible state: RX FIFO cannot be empty and full at the same time
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#define NRF24L01_ADDR_WIDTH 5 // RX/TX address width
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#define NRF24L01_PLOAD_WIDTH 32 // Payload width
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#define NRF24L01_TEST_ADDR "nRF24"
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void NRF24L01_Init(void);
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uint8_t NRF24L01_Check(void);
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/**
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* Dump nRF24L01+ configuration
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*/
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void NRF24L01_DumpConfig(void);
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/**
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* Read a 1-bit register
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*/
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uint8_t NRF24L01_Read_Reg(uint8_t reg);
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/**
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* Write a 1-byte register
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*/
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uint8_t NRF24L01_Write_Reg(uint8_t reg,uint8_t value);
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/**
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* Read a multi-byte register
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* reg - register to read
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* buf - pointer to the buffer to write
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* len - number of bytes to read
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*/
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uint8_t NRF24L01_Read_To_Buf(uint8_t reg,uint8_t *pBuf,uint8_t len);
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/**
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* Write a multi-byte register
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* reg - register to write
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* buf - pointer to the buffer with data
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* len - number of bytes to write
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*/
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uint8_t NRF24L01_Write_From_Buf(uint8_t reg, const uint8_t *pBuf,uint8_t len);
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void NRF24L01_SetEnableDynamicPayloads(uint8_t mode);
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void NRF24L01_SetEnableAckPayload(uint8_t mode);
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/**
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* Get status of the RX FIFO
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*/
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uint8_t NRF24L01_RXFIFO_GetStatus(void);
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/**
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* Read received data (no fifo status check, no status clear, just read)
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*/
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uint8_t NRF24L01_ReadPayload(uint8_t *pBuf, uint8_t *length, uint8_t dpl);
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/**
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* Send data in tx_buf and wait till data is sent or max re-tr reached
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*/
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uint8_t NRF24L01_TxPacket(uint8_t *tx_buf, uint8_t len);
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/**
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* Send data in FIFO without sync ack
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*/
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uint8_t NRF24L01_TxFast(const void *pBuf, uint8_t len);
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/**
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* Switch NRF24L01 to RX mode
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*/
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void NRF24L01_RX_Mode(uint8_t *rx_addr, uint8_t *tx_addr);
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/**
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* Switch NRF24L01 to TX mode
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*/
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void NRF24L01_TX_Mode(uint8_t *rx_addr, uint8_t *tx_addr);
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/**
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* Flush the RX FIFO
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*/
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void NRF24L01_FlushRX(void);
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/**
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* Flush the TX FIFO
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*/
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void NRF24L01_FlushTX(void);
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/**
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* Clear TX error flags
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*/
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void NRF24L01_ResetTX(void);
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/**
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* Clear IRQ bit of the STATUS register
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* reg - NRF24L01_FLAG_RX_DREADY, NRF24L01_FLAG_TX_DSENT, NRF24L01_FLAG_MAX_RT
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*/
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void NRF24L01_ClearIRQFlag(uint8_t reg);
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/**
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* Clear RX_DR, TX_DS and MAX_RT bits of the STATUS register
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*/
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void NRF24L01_ClearIRQFlags(void);
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#endif /*_NRF24L01_H*/
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